S71PL254/127/064/032J 256M/128/64/32 16/8/4/2M 4M/2M/1M/512K/256K S71PL S29PL - Datasheet Archive

 

Stacked Multi-Chip Product (MCP) Flash Memory and RAM 256M/128/64/32 Megabit (16/8/4/2M x 16-bit) CMOS 3.0 Volt-only Simultaneous

 

S71PL254/127/064/032J S71PL254/127/064/032J based MCPs Stacked Multi-Chip Product (MCP) Flash Memory and RAM 256M/128/64/32 256M/128/64/32 Megabit (16/8/4/2M 16/8/4/2M x 16-bit) CMOS 3.0 Volt-only Simultaneous Operation Page Mode Flash Memory and 64/32/16/8/4 Megabit (4M/2M/1M/512K/256K 4M/2M/1M/512K/256K x 16-bit) Static RAM/Pseudo Static RAM ADVANCE Distinctive Characteristics MCP Features Packages - 7 x 9 x 1.2mm 56 ball FBGA Power supply voltage of 2.7 to 3.1 volt - 8 x 11.6 x 1.2mm 64 ball FBGA High performance - 8 x 11.6 x 1.4mm 84 ball FBGA - 55 ns - 65 ns (65 ns Flash, 70ns pSRAM) Operating Temperature - ­25°C to +85°C - ­40°C to +85°C General Description The S71PL S71PL series is a product line of stacked Multi-Chip Product (MCP) packages and consists of: One or more S29PL S29PL (Simultaneous Read/Write) Flash memory die pSRAM or SRAM The 256Mb Flash memory consists of two S29PL127J S29PL127J devices. In this case, CE#f2 is used to access the second Flash and no extra address lines are required. The products covered by this document are listed in the table below: Flash Memory Density 32Mb 64Mb 128Mb 256Mb 4Mb 8Mb pSRAM Density S71PL032J40 S71PL032J40 S71PL032J80 S71PL032J80 S71PL064J80 S71PL064J80 16Mb S71PL032JA0 S71PL032JA0 S71PL064JA0 S71PL064JA0 S71PL127JA0 S71PL127JA0 S71PL064JB0 S71PL064JB0 S71PL127JB0 S71PL127JB0 S71PL254JB0 S71PL254JB0 S71PL127JC0 S71PL127JC0 S71PL254JC0 S71PL254JC0 32Mb 64Mb Flash Memory Density 32Mb SRAM Density (Note) 4Mb S71PL032J04 S71PL032J04 8Mb S71PL032J08 S71PL032J08 64Mb S71PL064J08 S71PL064J08 Note: Not recommended for new designs; use pSRAM based MCPs instead. Publication Number S71PL254/127/064/032J S71PL254/127/064/032J_00 Revision A Amendment 4 Issue Date July 16, 2004 P r e l i m i n a r y Product Selector Guide 32Mb Flash Memory Device-Model# Flash Access time (ns) (p)SRAM density (p)SRAM Access time (ns) pSRAM type Package S71PL032J04-0B S71PL032J04-0B 65 4M SRAM 70 SRAM2 TLC056 TLC056 S71PL032J04-0F S71PL032J04-0F 65 4M SRAM 70 SRAM3 TLC056 TLC056 S71PL032J08-0B S71PL032J08-0B 65 8M SRAM 70 SRAM2 TLC056 TLC056 S71PL032J40-07 S71PL032J40-07 65 4M pSRAM 70 pSRAM1 TLC056 TLC056 S71PL032J80-05 S71PL032J80-05 55 8M pSRAM 55 pSRAM1 TLC056 TLC056 S71PL032J80-07 S71PL032J80-07 65 8M pSRAM 70 pSRAM1 TLC056 TLC056 S71PL032JA0-0K S71PL032JA0-0K 65 16Mb pSRAM 70 pSRAM1 TLC056 TLC056 S71PL032JA0-0F S71PL032JA0-0F 65 16Mb pSRAM 70 pSRAM3 TLC056 TLC056 64Mb Flash Memory Device-Model# Flash Access time (ns) (p)SRAM density (p)SRAM Access time (ns) (p)SRAM type Package S71PL064J08-0B S71PL064J08-0B 65 8M SRAM 70 SRAM2 TLC056 TLC056 S71PL064J08-0U S71PL064J08-0U 65 8M SRAM 70 SRAM4 TLC056 TLC056 S71PL064J80-0K S71PL064J80-0K 65 8M pSRAM 70 pSRAM1 TLC056 TLC056 S71PL064JA0-05 S71PL064JA0-05 55 8M pSRAM 55 pSRAM1 TLC056 TLC056 S71PL064JA0-0K S71PL064JA0-0K 65 16M pSRAM 70 pSRAM1 TLC056 TLC056 S71PL064JA0-0P S71PL064JA0-0P 65 16M pSRAM 70 pSRAM7 TLC056 TLC056 S71PL064JB0-07 S71PL064JB0-07 65 32M pSRAM 70 pSRAM1 TLC056 TLC056 S71PL064JB0-0U S71PL064JB0-0U 65 32M pSRAM 70 pSRAM6 TLC056 TLC056 128Mb Flash Memory Device-Model# pSRAM density pSRAM Access time (ns) pSRAM type Package S71PL127JA0-9P S71PL127JA0-9P 65 16M pSRAM 70 pSRAM7 TLA064 TLA064 S71PL127JB0-97 S71PL127JB0-97 65 32M pSRAM 70 pSRAM1 TLA064 TLA064 S71PL127JB0-9Z S71PL127JB0-9Z 65 32M pSRAM 70 pSRAM7 TLA064 TLA064 S71PL127JB0-9U S71PL127JB0-9U 65 32M pSRAM 70 pSRAM6 TLA064 TLA064 S71PL127JC0-97 S71PL127JC0-97 65 64M pSRAM 70 pSRAM1 TLA064 TLA064 S71PL127JC0-9Z S71PL127JC0-9Z 65 64M pSRAM 70 pSRAM7 TLA064 TLA064 S71PL127JC0-9U S71PL127JC0-9U 2 Flash Access time (ns) 65 64M pSRAM 70 pSRAM6 TLA064 TLA064 S71PL254/127/064/032J S71PL254/127/064/032J based MCPs S71PL254/127/064/032J S71PL254/127/064/032J_00_A4 July 16, 2004 P r e l i m i n a r y 256Mb Flash Memory (2xS29PL127J) Device-Model# Flash Access time (ns) pSRAM density pSRAM Access time (ns) pSRAM type Package S71PL254JB0-T7 S71PL254JB0-T7 65 32M pSRAM 70 pSRAM1 FTA084 FTA084 S71PL254JB0-TB S71PL254JB0-TB 65 32M pSRAM 70 pSRAM2 FTA084 FTA084 S71PL254JB0-TU S71PL254JB0-TU 65 32M pSRAM 70 pSRAM6 FTA084 FTA084 S71PL254JC0-TB S71PL254JC0-TB 65 64M pSRAM 70 pSRAM2 FTA084 FTA084 S71PL254JC0-TU S71PL254JC0-TU 65 64M pSRAM 70 pSRAM6 FTA084 FTA084 S71PL254JC0-TZ S71PL254JC0-TZ 65 64M pSRAM 70 pSRAM7 FTA084 FTA084 July 16, 2004 S71PL254/127/064/032J S71PL254/127/064/032J_00_A4 S71PL254/127/064/032J S71PL254/127/064/032J based MCPs 3 A d v a n c e I n f o r m a t i o n S71PL254/127/064/032J S71PL254/127/064/032J based MCPs Distinctive Characteristics . . . . . . . . . . . . . . . . . . . 1 MCP Features . 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . 1 Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .2 32Mb Flash Memory .2 64Mb Flash Memory .2 128Mb Flash Memory .2 Connection Diagram (S71PL032J S71PL032J) Connection Diagram (S71PL064J S71PL064J) Connection Diagram (S71PL127J S71PL127J) Connection Diagram (S71PL254J S71PL254J) . . . . . . . . . . . . . .8 . . . . . . . . . . . . . .9 . . . . . . . . . . . . . 10 . . . . . . . . . . . . . 11 Special Handling Instructions For FBGA Package . 11 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 13 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 18 TLC056-56-ball Fine-Pitch Ball Grid Array (FBGA) 9 x 7mm Package . 18 TLA064-64-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6mm Package . 19 FTA084-84-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6mm . 20 S29PL127J/S29PL064J/S29PL032J S29PL127J/S29PL064J/S29PL032J for MCP General Description . . . . . . . . . . . . . . . . . . . . . . . 23 Simultaneous Read/Write Operation with Zero Latency .23 Page Mode Features .23 Standard Flash Memory Features .23 Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 25 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Simultaneous Read/Write Block Diagram . . . . . 27 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .29 Table 1. PL127J PL127J Device Bus Operations . 29 Requirements for Reading Array Data . 29 Random Read (Non-Page Read) . 29 Page Mode Read . 30 Table 2. Page Select . 30 Simultaneous Read/Write Operation . 30 Table 3. Bank Select . 30 Writing Commands/Command Sequences .31 Accelerated Program Operation .31 Autoselect Functions .31 Automatic Sleep Mode .32 RESET#: Hardware Reset Pin .32 Output Disable Mode .32 Table 4. PL127J PL127J Sector Architecture . 33 Table 5. PL064J PL064J Sector Architecture . 40 Table 6. PL032J PL032J Sector Architecture . 43 Table 7. SecSiTM Sector Addresses . 44 Autoselect Mode .45 Table 8. Autoselect Codes (High Voltage Method) . 45 Table 9. PL127J PL127J Boot Sector/Sector Block Addresses for Protection/Unprotection . 46 Table 10. PL064J PL064J Boot Sector/Sector Block Addresses for Protection/Unprotection . 47 July 16, 2004 S71PL254/127/064/032J S71PL254/127/064/032J_00A3 Table 11. PL032J PL032J Boot Sector/Sector Block Addresses for Protection/Unprotection . 48 Selecting a Sector Protection Mode .48 Table 12. Sector Protection Schemes . 49 Persistent Sector Protection . . . . . . . . . . . . . . . . 49 Persistent Protection Bit (PPB) .49 Persistent Protection Bit Lock (PPB Lock) .50 Persistent Sector Protection Mode Locking Bit . 51 Password Protection Mode . . . . . . . . . . . . . . . . . . 51 Password and Password Mode Locking Bit . 52 64-bit Password . 52 Write Protect (WP#) . 53 Persistent Protection Bit Lock . 53 High Voltage Sector Protection . 53 Figure 1. In-System Sector Protection/Sector Unprotection Algorithms. 54 Temporary Sector Unprotect . 55 Figure 2. Temporary Sector Unprotect Operation . 55 SecSiTM (Secured Silicon) Sector Flash Memory Region . 55 Factory-Locked Area (64 words) . 55 Customer-Lockable Area (64 words) . 56 SecSi Sector Protection Bits . 56 Figure 3. SecSi Sector Protect Verify . 57 Hardware Data Protection . 57 Low VCC Write Inhibit . 57 Write Pulse "Glitch" Protection . 57 Logical Inhibit . 57 Power-Up Write Inhibit . 57 Common Flash Memory Interface (CFI) . . . . . . 58 Table 13. CFI Query Identification String . 58 Table 14. System Interface String . 59 Table 15. Device Geometry Definition . 59 Table 16. Primary Vendor-Specific Extended Query . 60 Command Definitions . . . . . . . . . . . . . . . . . . . . . . 62 Reading Array Data .62 Reset Command .62 Autoselect Command Sequence . 63 Enter SecSiTM Sector/Exit SecSi Sector Command Sequence . 63 Word Program Command Sequence . 63 Unlock Bypass Command Sequence .64 Figure 4. Program Operation . 65 Chip Erase Command Sequence . 65 Sector Erase Command Sequence .66 Figure 5. Erase Operation . 67 Erase Suspend/Erase Resume Commands . 67 Password Program Command .68 Password Verify Command .68 Password Protection Mode Locking Bit Program Command .68 Persistent Sector Protection Mode Locking Bit Program Command .69 SecSi Sector Protection Bit Program Command .69 PPB Lock Bit Set Command .69 DYB Write Command .69 Password Unlock Command .69 PPB Program Command .70 All PPB Erase Command .70 DYB Write Command .70 PPB Lock Bit Set Command .70 Command . 71 Command Definitions Tables . 71 Table 17. Memory Array Command Definitions . 71 3 A d v a n c e Table 18. Sector Protection Command Definitions . 72 Write Operation Status . . . . . . . . . . . . . . . . . . . . 73 DQ7: Data# Polling .73 Figure 6. Data# Polling Algorithm. 74 DQ6: Toggle Bit I .75 Figure 7. Toggle Bit Algorithm. 76 DQ2: Toggle Bit II .76 Reading Toggle Bits DQ6/DQ2 .76 DQ5: Exceeded Timing Limits .77 DQ3: Sector Erase Timer .77 Table 19. Write Operation Status . 78 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . .79 Figure 8. Maximum Overshoot Waveforms. 79 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . .80 Industrial (I) Devices . 80 Extended (E) Devices . 80 Supply Voltages . 80 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 20. CMOS Compatible . 81 AC Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . .82 Test Conditions . 82 Figure 9. Test Setups. 82 Table 21. Test Specifications . 82 SWITCHING WAVEFORMS .83 Table 22. KEY TO SWITCHING WAVEFORMS . 83 Figure 10. Input Waveforms and Measurement Levels. 83 VCC RampRate .83 Read Operations . 84 Table 23. Read-Only Operations . 84 Figure 11. Read Operation Timings . 84 Figure 12. Page Read Operation Timings . 85 Reset . 85 Table 24. Hardware Reset (RESET#) . 85 Figure 13. Reset Timings. 86 Erase/Program Operations . 87 Table 25. Erase and Program Operations . 87 Timing Diagrams . 88 Figure 14. Program Operation Timings . 88 Figure 15. Accelerated Program Timing Diagram . 88 Figure 16. Chip/Sector Erase Operation Timings . 89 Figure 17. Back-to-back Read/Write Cycle Timings . 89 Figure 18. Data# Polling Timings (During Embedded Algorithms) . 90 Figure 19. Toggle Bit Timings (During Embedded Algorithms) . 90 Figure 20. DQ2 vs. DQ6 . 91 Protect/Unprotect . . . . . . . . . . . . . . . . . . . . . . . . 91 Table 26. Temporary Sector Unprotect . 91 Figure 21. Temporary Sector Unprotect Timing Diagram. 91 Figure 22. Sector/Sector Block Protect and Unprotect Timing Diagram. 92 Controlled Erase Operations .93 Table 27. Alternate CE# Controlled Erase and Program Operations . 93 Table 28. Alternate CE# Controlled Write (Erase/Program) Operation Timings . 94 Table 29. Erase And Programming Performance . 95 BGA Pin Capacitance . . . . . . . . . . . . . . . . . . . . . . 95 Type 2 pSRAM Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Product Information . . . . . . . . . . . . . . . . . . . . . . . 97 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 4 I n f o r m a t i o n Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . 98 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Power Up .99 Figure 23. Power Up 1 (CS1# Controlled) . 99 Figure 24. Power Up 2 (CS2 Controlled). 99 Functional Description . . . . . . . . . . . . . . . . . . . . . 99 Absolute Maximum Ratings . . . . . . . . . . . . . . . . 100 DC Recommended Operating Conditions . . . . . 100 Capacitance (Ta = 25°C, f = 1 MHz) . . . . . . . . . . 100 DC and Operating Characteristics . . . . . . . . . . . 100 Common . 100 16M pSRAM .101 32M pSRAM .101 64M pSRAM .102 AC Operating Conditions . . . . . . . . . . . . . . . . . . 102 Test Conditions (Test Load and Test Input/Output Reference) .102 Figure 25. Output Load . 102 ACC Characteristics (Ta = -40°C to 85°C, VCC = 2.7 to 3.1 V) .103 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 104 Read Timings .104 Figure 26. Timing Waveform of Read Cycle(1) . 104 Figure 27. Timing Waveform of Read Cycle(2) . 104 Figure 28. Timing Waveform of Read Cycle(2) . 104 Write Timings .105 Figure 29. Write Cycle #1 (WE# Controlled). Figure 30. Write Cycle #2 (CS1# Controlled) . Figure 31. Timing Waveform of Write Cycle(3) (CS2 Controlled) . Figure 32. Timing Waveform of Write Cycle(4) (UB#, LB# Controlled) . 105 105 106 106 pSRAM Type 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Absolute Maximum Ratings (see Note) . . . . . . . 108 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 108 Table 30. DC Recommended Operating Conditions . 108 Table 31. DC Characteristics (TA = -25°C to 85°C, VDD = 2.6 to 3.3V) . 109 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 109 Table 32. AC Characteristics and Operating Conditions (TA = -25°C to 85°C, VDD = 2.6 to 3.3V) . 109 Table 33. AC Test Conditions . 110 Figure 33. AC Test Loads . 110 Figure 34. State Diagram . 111 Table 34. Standby Mode Characteristics . 111 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 111 Figure 35. Read Cycle 1-Addressed Controlled . Figure 36. Read Cycle 2-CS1# Controlled. Figure 37. Write Cycle 1-WE# Controlled . Figure 38. Write Cycle 2-CS1# Controlled . Figure 39. Write Cycle3-UB#, LB# Controlled . Figure 40. Deep Power-down Mode . Figure 41. Power-up Mode . Figure 42. Abnormal Timing . 111 112 112 113 113 114 114 114 pSRAM Type 6 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 S71PL254/127/064/032J S71PL254/127/064/032J_00A3 July 16, 2004 A d v a n c e I n f o r m a t i o n Functional Description . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . DC Recommended Operating Conditions (Ta = -40°C to 85°C) . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics (Ta = -40°C to 85°C, VDD = 2.6 to 3.3 V) (See Note 3 to 4) . . . . . . . . . . . . . . Capacitance (Ta = 25°C, f = 1 MHz) . . . . . . . . . . AC Characteristics and Operating Conditions . 116 116 116 116 117 117 (Ta = -40°C to 85°C, VDD = 2.6 to 3.3 V) (See Note 5 to 11) . 117 AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . 118 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 119 Read Timings . 119 Figure 43. Read Cycle . 119 Figure 44. Page Read Cycle (8 Words Access) . 120 Write Timings . 121 Figure 45. Write Cycle #1 (WE# Controlled) (See Note 8) . 121 Figure 46. Write Cycle #2 (CE# Controlled) (See Note 8) . 122 Deep Power-down Timing . 122 Figure 47. Deep Power Down Timing. 122 Power-on Timing . 122 Figure 48. Power-on Timing. 122 Provisions of Address Skew . 123 Read . 123 Figure 49. Read . 123 Write . 123 Figure 50. Write . 123 pSRAM Type 7 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Functional Description . . . . . . . . . . . . . . . . . . . . . 126 Power Down (for 32M, 64M Only) . . . . . . . . . . . . 126 Power Down . 126 Power Down Program Sequence . 127 Address Key . 127 Absolute Maximum Ratings . . . . . . . . . . . . . . . . 128 Recommended Operating Conditions (See Warning Below) . . . . . . . . . . . . . . . . . . . . . . . . . 128 Package Capacitance . . . . . . . . . . . . . . . . . . . . . 128 DC Characteristics (Under Recommended Conditions Unless Otherwise Noted) . . . . . . . . . 129 AC Characteristics (Under Recommended Operating Conditions Unless Otherwise Noted) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Read Operation . 130 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 132 Write Operation . 132 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 133 Power Down Parameters .133 Other Timing Parameters .133 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 134 Figure 54. Read Timing #3 (LB#/UB# Byte Access) . 136 Figure 55. Read Timing #4 (Page Address Access after CE1# Control Access for 32M and 64M Only) . 136 Figure 56. Read Timing #5 (Random and Page Address Access for 32M and 64M Only) . 137 Write Timings . 137 Figure 57. Write Timing #1 (Basic Timing). Figure 58. Write Timing #2 (WE# Control). Figure 59. Write Timing #3-1 (WE#/LB#/UB# Byte Write Control) . Figure 60. Write Timing #3-2 (WE#/LB#/UB# Byte Write Control) . Figure 61. Write Timing #3-3 (WE#/LB#/UB# Byte Write Control) . Figure 62. Write Timing #3-4 (WE#/LB#/UB# Byte Write Control) . 137 138 138 139 139 140 Read/Write Timings .140 Figure 63. Read/Write Timing #1-1 (CE1# Control) . Figure 64. Read / Write Timing #1-2 (CE1#/WE#/OE# Control) . Figure 65. Read / Write Timing #2 (OE#, WE# Control) . Figure 66. Read / Write Timing #3 (OE#, WE#, LB#, UB# Control) . Figure 67. Power-up Timing #1 . Figure 68. Power-up Timing #2 . Figure 69. Power Down Entry and Exit Timing . Figure 70. Standby Entry Timing after Read or Write. Figure 71. Power Down Program Timing (for 32M/64M 32M/64M Only). 140 141 141 142 142 143 143 143 144 SRAM Common Features . . . . . . . . . . . . . . . . . . . . . . . . 146 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Functional Description . . . . . . . . . . . . . . . . . . . . . 147 4M Version F, 4M version G, 8M version C .147 Byte Mode .147 Functional Description . . . . . . . . . . . . . . . . . . . . . 148 8M Version D .148 X means don't care (must be low or high state). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings (4M Version F) . . . Absolute Maximum Ratings (4M Version G, 8M Version C, 8M Version D) . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 148 148 148 149 Recommended DC Operating Conditions (Note 1) .149 Capacitance (f=1MHz, TA=25°C) .149 DC Operating Characteristics .149 Common .149 DC Operating Characteristics .150 4M Version F .150 DC Operating Characteristics .150 4M Version G .150 DC Operating Characteristics .151 8M Version C .151 DC Operating Characteristics .151 8M Version D .151 AC Test Conditions . 134 AC Measurement Output Load Circuit . 134 AC Operating Conditions . . . . . . . . . . . . . . . . . . 152 Figure 51. AC Output Load Circuit. 134 Test Conditions .152 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 135 Figure 72. AC Output Load. 152 Read Timings .135 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 152 Figure 52. Read Timing #1 (Basic Timing) . 135 Figure 53. Read Timing #2 (OE# Address Access . 135 Read/Write Characteristics (VCC=2.7-3.3V) .152 Data Retention Characteristics (4M Version F) . 153 July 16, 2004 S71PL254/127/064/032J S71PL254/127/064/032J_00A3 5 A d v a n c e Data Retention Characteristics (4M Version G) . 154 Data Retention Characteristics (8M Version C) . 154 Data Retention Characteristics (8M Version D) . 154 Timing Diagrams . 154 Figure 73. Timing Waveform of Read Cycle(1) (Address Controlled, CS#1=OE#=VIL, CS2=WE#=VIH, UB# and/or LB#=VIL) . Figure 74. Timing Waveform of Read Cycle(2) (WE#=VIH, if BYTE# is Low, Ignore UB#/LB# Timing) . Figure 75. Timing Waveform of Write Cycle(1) (WE# controlled, if BYTE# is Low, Ignore UB#/LB# Timing) . Figure 76. Timing Waveform of Write Cycle(2) (CS# controlled, if BYTE# is Low, Ignore UB#/LB# Timing) . Figure 77. Timing Waveform of Write Cycle(3) (UB#, LB# controlled) . Figure 78. Data Retention Waveform . 154 155 155 156 156 157 pSRAM Type 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Functional Description . . . . . . . . . . . . . . . . . . . . . 96 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 96 DC Characteristics (4Mb pSRAM Asynchronous) . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 DC Characteristics (8Mb pSRAM Asynchronous) . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 DC Characteristics (16Mb pSRAM Asynchronous) . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 DC Characteristics (16Mb pSRAM Page Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 DC Characteristics (32Mb pSRAM Page Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 DC Characteristics (64Mb pSRAM Page Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Timing Test Conditions . . . . . . . . . . . . . . . . . . . 102 Output Load Circuit . 103 Figure 79. Output Load Circuit . 103 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . 103 AC Characteristics (4Mb pSRAM Page Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 AC Characteristics (8Mb pSRAM Asynchronous) . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 AC Characteristics (16Mb pSRAM Asynchronous) . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6 I n f o r m a t i o n AC Characteristics (16Mb pSRAM Page Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 AC Characteristics (32Mb pSRAM Page Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 AC Characteristics (64Mb pSRAM Page Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 115 Read Cycle .115 Figure 80. Timing of Read Cycle (CE# = OE# = VIL, WE# = ZZ# = VIH). 115 Figure 81. Timing Waveform of Read Cycle (WE# = ZZ# = VIH) . 116 Figure 82. Timing Waveform of Page Mode Read Cycle (WE# = ZZ# = VIH) . 117 Write Cycle .118 Figure 83. Timing Waveform of Write Cycle (WE# Control, ZZ# = VIH). 118 Figure 84. Timing Waveform of Write Cycle (CE# Control, ZZ# = VIH). 118 Figure 85. Timing Waveform of Page Mode Write Cycle (ZZ# = VIH) . 119 Power Savings Modes (For 16M Page Mode, 32M and 64M Only) . . . . . . . . . . . . . . . . . . . . . . . . 119 Partial Array Self Refresh (PAR) .119 Temperature Compensated Refresh (for 64Mb) .120 Deep Sleep Mode .120 Reduced Memory Size (for 32M and 16M) .120 Other Mode Register Settings (for 64M) .120 Figure 86. Mode Register . 121 Figure 87. Mode Register Update Timings (UB#, LB#, OE# are Don't Care). 121 Figure 88. Deep Sleep Mode - Entry/Exit Timings. 122 Mode Register Update and Deep Sleep Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Patterns for PASR (A4=1) (64M) . . . . . Deep ICC Characteristics (for 64Mb) . . . . . . . . . Address Patterns for PAR (A3= 0, A4=1) (32M) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Patterns for RMS (A3 = 1, A4 = 1) (32M) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low Power ICC Characteristics (32M) . . . . . . . . Address Patterns for PAR (A3= 0, A4=1) (16M) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Patterns for RMS (A3 = 1, A4 = 1) (16M) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low Power ICC Characteristics (16M) . . . . . . . . 123 123 124 124 124 125 125 125 125 S71PL254/127/064/032J S71PL254/127/064/032J_00A3 July 16, 2004 P r e l i m i n a r y MCP Block Diagram VCCf VCC CE#f1 WP#/ACC RESET# Flash-only Address Flash 1 Shared Address OE# WE# VSS RY/BY# Flash 2 (Note 2) CE#f2 (Note 1) VCCS DQ15 to DQ0 VCC pSRAM/SRAM IO15-IO0 IO15-IO0 CE#s CE# UB#s UB# LB#s LB# CE2 Notes: 1. For 1 Flash + pSRAM, CE#f1=CE#. For 2 Flash + pSRAM, CE#=CE#f1 and CE#f2 is the chip-enable for the second Flash. 2. For 256Mb only, Flash 1 = Flash 2 = S29PL127J S29PL127J. July 16, 2004 S71PL254/127/064/032J S71PL254/127/064/032J_00_A4 7 P r e l i m i n a r y Connection Diagram (S71PL032J S71PL032J) 56-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down) A2 A3 A4 A5 A6 Legend A7 A7 LB# WP/ACC WE# A8 A11 B1 B2 B3 B4 B5 B6 B7 B8 A3 A6 UB# RST#f CE2s A19 A12 A15 C1 C2 C3 C4 C5 C6 C7 C8 A2 A5 A18 RY/BY# A20 A9 A13 RFU D1 D2 D3 D6 D7 D8 A1 A4 A17 A10 A14 RFU E1 E2 E3 E6 E7 VSS DQ1 DQ6 RFU Flash only RAM only E8 A0 Shared (Note 1) A16 F1 F2 F3 F4 F5 F6 F7 F8 CE1#f OE# DQ9 DQ3 DQ4 DQ13 DQ15 RFU G1 G2 G3 G4 G5 G6 G7 G8 CE1#s DQ0 DQ10 VCCf VCCs DQ12 DQ7 VSS H2 H3 H4 H5 H6 H7 DQ8 DQ2 DQ11 RFU DQ5 DQ14 Reserved for Future Use Notes: 1. May be shared depending on density. - A19 is shared for the 16M pSRAM configuration. - A18 is shared for the 8M (p)SRAM and above configurations. 2. Connecting all Vcc and Vss balls to Vcc and Vss is recommended. MCP Shared Addresses S71PL032JA0 S71PL032JA0 A20 A19-A0 A19-A0 S71PL032J80 S71PL032J80 A20-A19 A20-A19 A18-A0 A18-A0 S71PL032J08 S71PL032J08 A20-A19 A20-A19 A18-A0 A18-A0 S71PL032J40 S71PL032J40 A20-A18 A20-A18 A17-A0 A17-A0 S71PL032J04 S71PL032J04 8 Flash-only Addresses A20-A18 A20-A18 A17-A0 A17-A0 S71PL254/127/064/032J S71PL254/127/064/032J_00_A4 July 16, 2004 P r e l i m i n a r y Connection Diagram (S71PL064J S71PL064J) 56-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down) A2 A3 A4 A5 A6 Legend A7 A7 LB# WP/ACC WE# A8 A11 B1 B2 B3 B4 B5 B6 B7 B8 A3 A6 UB# RST#f CE2s A19 A12 A15 C1 C2 C3 C4 C5 C6 C7 C8 A2 A5 A18 RY/BY# A20 A9 A13 A21 D1 D2 D3 D6 D7 D8 A1 A4 A17 A10 A14 RFU E1 E2 E3 E6 E7 E8 A0 VSS DQ1 DQ6 RFU Shared (Note 1) Flash only RAM only A16 F1 F2 F3 F4 F5 F6 F7 F8 CE1#f OE# DQ9 DQ3 DQ4 DQ13 DQ15 RFU G1 G2 G3 G4 G5 G6 G7 G8 CE1#s DQ0 DQ10 VCCf VCCs DQ12 DQ7 VSS H2 H3 H4 H5 H6 H7 DQ8 DQ2 DQ11 RFU DQ5 DQ14 Reserved for Future Use Notes: 1. May be shared depending on density. - A20 is shared for the 32M pSRAM configuration. - A19 is shared for the 16M pSRAM and above configurations. - A18 is shared for the 8M (p)SRAM and above configurations. 2. Connecting all Vcc and Vss balls to Vcc and Vss is recommended. MCP Flash-only Addresses Shared Addresses S71PL064JB0 S71PL064JB0 A21 A20-A0 A20-A0 S71PL064JA0 S71PL064JA0 A21-A20 A21-A20 A19-A0 A19-A0 S71PL064J80 S71PL064J80 A21-A19 A21-A19 A18-A0 A18-A0 S71PL064J08 S71PL064J08 A21-A19 A21-A19 A18-A0 A18-A0 July 16, 2004 S71PL254/127/064/032J S71PL254/127/064/032J_00_A4 9 P r e l i m i n a r y Connection Diagram (S71PL127J S71PL127J) 64-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down) A1 A10 NC NC B5 B6 RFU RFU C3 C4 C5 C6 C7 A7 LB# WP/ACC WE# A8 Legend C8 A11 D2 D3 D4 D5 D6 D7 D8 D9 A3 A6 UB# RST#f CE2s A19 A12 A15 E2 E3 E4 E5 E6 E7 E8 E9 A2 A5 A18 RY/BY# A20 A9 A13 A21 F2 F3 F4 F7 F8 F9 A1 A4 A17 A10 A14 A22 G2 G3 G4 G7 G8 G9 A0 VSS DQ1 DQ6 RFU A16 H2 H3 H4 H5 H6 H7 H8 H9 CE#f OE# DQ9 DQ3 DQ4 DQ13 DQ15 RFU J2 J3 J4 J5 J6 J7 J8 J9 CE1#s DQ0 DQ10 VCCf VCCs DQ12 DQ7 VSS K3 K4 K5 K6 K7 K8 DQ8 DQ2 DQ11 RFU DQ5 DQ14 L5 Flash only RAM only Reserved for Future Use L6 RFU* Shared (Note 1) RFU M1 M10 NC NC *See notes below Notes: 1. May be shared depending on density. - A21 is shared for the 64M pSRAM configuration. - A20 is shared for the 32M pSRAM and above configurations. 1. A19 is shared for the 16M pSRAM and above configurations. MCP Flash-only Addresses Shared Addresses S71PL127JC0 S71PL127JC0 A22 A21-A0 A21-A0 S71PL127JB0 S71PL127JB0 A22-A21 A22-A21 A20-A0 A20-A0 S71PL127JA0 S71PL127JA0 A22-A20 A22-A20 A19-A0 A19-A0 2. Connecting all Vcc & Vss balls to Vcc & Vss is recommended. 3. Ball L5 will be Vccf in the 84-ball density upgrades. Do not connect to Vss or any other signal. 10 S71PL254/127/064/032J S71PL254/127/064/032J_00_A4 July 16, 2004 P r e l i m i n a r y Connection Diagram (S71PL254J S71PL254J) 84-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down) A1 A10 NC NC B2 B3 B4 B5 B6 B7 B8 B9 RFU RFU RFU CE#F2 RFU RFU RFU RFU C2 C3 C4 C5 C6 C7 C8 C9 RFU A7 LB# WP/ACC WE# A8 A11 RFU D2 D3 D4 D5 D6 D7 D8 D9 A3 A6 UB# RST#f CE2s A19 A12 A15 E2 E3 E4 E5 E6 E7 E8 E9 A2 A5 A18 RY/BY# A20 A9 A13 A21 F2 F3 F4 H5 H6 F7 F8 F9 A1 A4 A17 RFU RFU A10 A14 A22 G2 G3 G4 H5 H6 G7 G8 G9 A0 VSS DQ1 RFU RFU DQ6 RFU A16 H2 H3 H4 H5 H6 H7 H8 OE# DQ9 DQ3 DQ4 DQ13 DQ15 J3 J4 J5 J6 J7 J8 DQ0 DQ10 VCCf VCCs DQ12 DQ7 VSS K2 K3 K4 K5 K6 K7 K8 K9 RFU DQ8 DQ2 DQ11 RFU DQ5 DQ14 RAM only J9 CE1#s Flash only RFU J2 Shared (Note 1) H9 CE#f1 Legend RFU L2 L3 L4 L5 L6 L7 L8 RFU RFU VCCf RFU RFU RFU 2nd Flash Only L9 RFU Reserved for Future Use RFU M1 M10 NC NC Notes: 1. May be shared depending on density. - A21 is shared for the 64M pSRAM configuration. - A20 is shared for the 32M pSRAM configuration. MCP Flash-only Addresses Shared Addresses S71PL254JC0 S71PL254JC0 A22 A21-A0 A21-A0 S71PL254JB0 S71PL254JB0 A22-A21 A22-A21 A20-A0 A20-A0 2. Connecting all Vcc & Vss balls to Vcc & Vss is recommended. Special Handling Instructions For FBGA Package Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised July 16, 2004 S71PL254/127/064/032J S71PL254/127/064/032J_00_A4 11 P r e l i m i n a r y if the package body is exposed to temperatures above 150°C for prolonged periods of time. Pin Description A21­A0 DQ15­DQ0 CE1#f CE#f2 CE1#ps CE2ps OE# WE# RY/BY# UB# LB# RESET# WP#/ACC VCCf = = = = = = = = = = = = = = VCCps VSS NC 22 Address Inputs (Common) 16 Data Inputs/Outputs (Common) Chip Enable 1 (Flash) Chip Enable 2 (Flash) Chip Enable 1 (pSRAM) Chip Enable 2 (pSRAM) Output Enable (Common) Write Enable (Common) Ready/Busy Output (Flash 1) Upper Byte Control (pSRAM) Lower Byte Control (pSRAM) Hardware Reset Pin, Active Low (Flash 1) Hardware Write Protect/Acceleration Pin (Flash) Flash 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) pSRAM Power Supply Device Ground (Common) Pin Not Connected Internally = = = Logic Symbol 22 A21­A0 16 CE1#f DQ15­DQ0 CE2#f CE1#ps CE2ps RY/BY# OE# WE# WP#/ACC RESET# UB# LB# 12 S71PL254/127/064/032J S71PL254/127/064/032J_00_A4 July 16, 2004 P r e l i m i n a r y Ordering Information The order number is formed by a valid combinations of the following: S71PL S71PL 127 J B0 BA W 9 Z 0 PACKING TYPE 0 = Tray 2 = 7" Tape and Reel 3 = 13" Tape and Reel 4 = 10" Tape and Reel MODEL NUMBER See the Valid Combinations table. PACKAGE MODIFIER 0 = 7 x 9mm, 1.2mm height, 56 balls (TLC056 TLC056) 9 = 8 x 11.6mm, 1.2mm height, 64 balls (TLA056 TLA056) T = 8 x 11.6mm, 1.4mm height, 84 balls (FTA084 FTA084) TEMPERATURE RANGE W = Wireless (-25°C to +85°C) I = Industrial (-40°C to +85°C) PACKAGE TYPE BA = Fine-pitch BGA Lead (Pb)-free compliant package BF = Fine-pitch BGA Lead (Pb)-free package pSRAM C0 = B0 = A0 = 80 = 40 = 08 = 04 = DENSITY 64Mb pSRAM 32Mb pSRAM 16Mb pSRAM 8Mb pSRAM 4Mb pSRAM 8Mb SRAM 4Mb SRAM PROCESS TECHNOLOGY J = 110 nm, Floating Gate Technology FLASH DENSITY 254 = 256Mb 127 = 128Mb 064 = 64Mb 032 = 32Mb PRODUCT FAMILY S71PL S71PL Multi-chip Product (MCP) 3.0-volt Simultaneous Read/Write, Page Mode Flash Memory and RAM July 16, 2004 S71PL254/127/064/032J S71PL254/127/064/032J_00_A4 13 P r e l i m i n a r y S71PL032J S71PL032J Valid Combinations Base Ordering Part Number Package & Temperature Package Modifier/ Model Number S71PL032J04 S71PL032J04 0B S71PL032J04 S71PL032J04 0F S71PL032J08 S71PL032J08 0B S71PL032J40 S71PL032J40 07 Packing Type Speed Options (ns) S71PL032J80 S71PL032J80 BAW 07 (p)SRAM Type/Access Time (ns) SRAM2 / 70 SRAM3 / 70 65 SRAM2 / 70 pSRAM1 / 70 0, 2, 3, 4 (Note 1) pSRAM1 / 70 S71PL032J80 S71PL032J80 05 (Note 3) 55 07 65 pSRAM1 / 70 S71PL032JA0 S71PL032JA0 0F 65 pSRAM3 / 70 S71PL032J04 S71PL032J04 0B SRAM2 / 70 S71PL032J04 S71PL032J04 0F SRAM3 / 70 S71PL032J08 S71PL032J08 0B S71PL032J40 S71PL032J40 07 (Note 2) pSRAM1 / 55 S71PL032JA0 S71PL032JA0 S71PL032J80 S71PL032J80 BFW 65 SRAM2 / 70 pSRAM1 / 70 0, 2, 3, 4 (Note 1) 07 (Note 2) pSRAM1 / 70 S71PL032J80 S71PL032J80 05 (Note 3) 55 pSRAM1 / 55 S71PL032JA0 S71PL032JA0 07 65 pSRAM1 / 70 S71PL032JA0 S71PL032JA0 0F 65 pSRAM3 / 70 S71PL032J04 S71PL032J04 0B S71PL032J04 S71PL032J04 0F S71PL032J08 S71PL032J08 0B S71PL032J40 S71PL032J40 07 S71PL032J80 S71PL032J80 BAI 07 SRAM2 / 70 SRAM3 / 70 65 SRAM2 / 70 pSRAM1 / 70 0, 2, 3, 4 (Note 1) pSRAM1 / 70 S71PL032J80 S71PL032J80 05 (Note 3) 55 07 65 pSRAM1 / 70 S71PL032JA0 S71PL032JA0 0F 65 pSRAM3 / 70 S71PL032J04 S71PL032J04 0B SRAM2 / 70 S71PL032J04 S71PL032J04 0F SRAM3 / 70 S71PL032J08 S71PL032J08 0B S71PL032J40 S71PL032J40 07 (Note 2) pSRAM1 / 55 S71PL032JA0 S71PL032JA0 S71PL032J80 S71PL032J80 BFI 07 65 SRAM2 / 70 pSRAM1 / 70 0, 2, 3, 4 (Note 1) pSRAM1 / 70 S71PL032J80 S71PL032J80 05 (Note 3) 55 07 65 pSRAM1 / 70 S71PL032JA0 S71PL032JA0 0F 65 (Note 2) pSRAM1 / 55 S71PL032JA0 S71PL032JA0 pSRAM3 / 70 Notes: 1. Type 0 is standard. Specify other options as required. 2. BGA package marking omits leading "S" and packing type designator from ordering part number. 3. Contact factory for availability. 14 Package Marking Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. S71PL254/127/064/032J S71PL254/127/064/032J_00_A4 July 16, 2004 P r e l i m i n a r y S71PL064J S71PL064J Valid Combinations Base Ordering Part Number Package & Temperatur e Package Modifier/ Model Number Packing Type Speed Options (ns) (p)SRAM Type/Access Time (ns) S71PL064J08 S71PL064J08 0B S71PL064J08 S71PL064J08 0U SRAM3 / 70 S71PL064J80 S71PL064J80 0K Package Marking pSRAM1 /70 S71PL064JA0 S71PL064JA0 S71PL064JA0 S71PL064JA0 SRAM1 / 70 07 BAW 0P 65 pSRAM1 / 70 pSRAM7 / 70 0, 2, 3, 4 (Note 1) 07 S71PL064JB0 S71PL064JB0 0U pSRAM6 / 70 S71PL064J80 S71PL064J80 05 (Note 3) S71PL064JA0 S71PL064JA0 05 (Note 3) (Note 2) pSRAM1 / 70 S71PL064JB0 S71PL064JB0 55 pSRAM1 / 55 pSRAM1 / 55 S71PL064J08 S71PL064J08 0B S71PL064J08 S71PL064J08 0U SRAM3 / 70 S71PL064J80 S71PL064J80 0K pSRAM1 /70 S71PL064JA0 S71PL064JA0 S71PL064JA0 S71PL064JA0 SRAM1 / 70 07 BFW 0P 65 0, 2, 3, 4 (Note 1) pSRAM1 / 70 pSRAM7 / 70 S71PL064JB0 S71PL064JB0 07 pSRAM1 / 70 S71PL064JB0 S71PL064JB0 0U pSRAM6 / 70 S71PL064J80 S71PL064J80 05 (Note 3) S71PL064JA0 S71PL064JA0 05 (Note 3) S71PL064J08 S71PL064J08 0B S71PL064J08 S71PL064J08 0U SRAM3 / 70 S71PL064J80 S71PL064J80 0K (Note 2) pSRAM1 /70 S71PL064JA0 S71PL064JA0 S71PL064JA0 S71PL064JA0 BAI 07 55 pSRAM1 / 55 pSRAM1 / 55 SRAM1 / 70 65 0, 2, 3, 4 (Note 1) pSRAM1 / 70 0P pSRAM7 / 70 S71PL064JB0 S71PL064JB0 0U pSRAM6 / 70 S71PL064J80 S71PL064J80 05 (Note 3) S71PL064JA0 S71PL064JA0 05 (Note 3) S71PL064J08 S71PL064J08 0B S71PL064J08 S71PL064J08 0U SRAM3 / 70 S71PL064J80 S71PL064J80 0K (Note 2) pSRAM1 /70 S71PL064JA0 S71PL064JA0 S71PL064JA0 S71PL064JA0 BFI 07 0P S71PL064JB0 S71PL064JB0 05 (Note 3) S71PL064JA0 S71PL064JA0 05 (Note 3) Notes: 1. Type 0 is standard. Specify other options as required. 2. BGA package marking omits leading "S" and packing type designator from ordering part number. 3. Contact factory for availability. July 16, 2004 S71PL254/127/064/032J S71PL254/127/064/032J_00_A4 pSRAM1 / 55 pSRAM1 / 55 SRAM1 / 70 65 0, 2, 3, 4 (Note 1) pSRAM1 / 70 pSRAM7 / 70 0U S71PL064J80 S71PL064J80 55 (Note 2) pSRAM6 / 70 55 pSRAM1 / 55 pSRAM1 / 55 Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. 15 P r e l i m i n a r y S71PL127J S71PL127J Valid Combinations Base Ordering Part Number Package & Temperature Package Modifier/Model Number Packing Type Speed Options (ns) (p)SRAM Type/Access Time (ns) S71PL127JA0 S71PL127JA0 9P pSRAM7 / 70 S71PL127JB0 S71PL127JB0 97 pSRAM1 / 70 S71PL127JB0 S71PL127JB0 9Z S71PL127JB0 S71PL127JB0 BAW 9U 0, 2, 3, 4 (Note 1) pSRAM7 / 70 65 pSRAM6 /70 97 S71PL127JC0 S71PL127JC0 (Note 2) pSRAM1 /70 S71PL127JC0 S71PL127JC0 9Z pSRAM7 / 70 S71PL127JC0 S71PL127JC0 9U pSRAM6 / 70 S71PL127JA0 S71PL127JA0 9P pSRAM7 / 70 S71PL127JB0 S71PL127JB0 97 pSRAM1 / 70 S71PL127JB0 S71PL127JB0 S71PL127JB0 S71PL127JB0 9Z BFW 9U pSRAM7 / 70 0, 2, 3, 4 65 pSRAM6 / 70 97 S71PL127JC0 S71PL127JC0 (Note 2) pSRAM1 /70 S71PL127JC0 S71PL127JC0 9Z pSRAM7 / 70 S71PL127JC0 S71PL127JC0 9U pSRAM6 / 70 S71PL127JA0 S71PL127JA0 9P pSRAM7 / 70 S71PL127JB0 S71PL127JB0 97 pSRAM1 / 70 S71PL127JB0 S71PL127JB0 9Z S71PL127JB0 S71PL127JB0 BAI S71PL127JC0 S71PL127JC0 9U pSRAM7 / 70 0, 2, 3, 4 (Note 1) 65 pSRAM6 / 70 97 (Note 2) pSRAM1 /70 S71PL127JC0 S71PL127JC0 9Z pSRAM7 / 70 S71PL127JC0 S71PL127JC0 9U pSRAM6 / 70 S71PL127JA0 S71PL127JA0 9P pSRAM7 / 70 S71PL127JB0 S71PL127JB0 97 pSRAM1 / 70 S71PL127JB0 S71PL127JB0 9Z S71PL127JB0 S71PL127JB0 BFI 9U pSRAM7 / 70 0, 2, 3, 4 (Note 1) 65 pSRAM6 / 70 S71PL127JC0 S71PL127JC0 97 9Z pSRAM7 / 70 S71PL127JC0 S71PL127JC0 9U (Note 2) pSRAM1 /70 S71PL127JC0 S71PL127JC0 pSRAM6 / 70 Notes: 1. Type 0 is standard. Specify other options as required. 2. BGA package marking omits leading "S" and packing type designator from ordering part number. 16 Package Marking Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. S71PL254/127/064/032J S71PL254/127/064/032J_00_A4 July 16, 2004 P r e l i m i n a r y S71PL254J S71PL254J Valid Combinations Base Ordering Part Number Package & Temperature Model Number Packing Type Speed Options (ns) (p)SRAM Type/Access Time (ns) S71PL254JB0 S71PL254JB0 T7 S71PL254JB0 S71PL254JB0 TB pSRAM2 /70 S71PL254JB0 S71PL254JB0 TU pSRAM6 / 70 Package Marking S71PL254JC0 S71PL254JC0 BAW TB pSRAM1 / 70 0, 2, 3, 4 (Note 1) 65 pSRAM2 / 70 S71PL254JC0 S71PL254JC0 TU pSRAM6 /70 S71PL254JC0 S71PL254JC0 TZ pSRAM7 / 70 S71PL254JB0 S71PL254JB0 T7 pSRAM1 / 70 S71PL254JB0 S71PL254JB0 TB pSRAM2 /70 TU pSRAM6 / 70 (Note 2) S71PL254JB0 S71PL254JB0 BFW 0, 2, 3, 4 (Note 1) 65 pSRAM2 / 70 S71PL254JC0 S71PL254JC0 TB S71PL254JC0 S71PL254JC0 TU pSRAM6 / 70 S71PL254JC0 S71PL254JC0 TZ pSRAM7 / 70 S71PL254JB0 S71PL254JB0 T7 pSRAM1 / 70 S71PL254JB0 S71PL254JB0 TB pSRAM2 /70 S71PL254JB0 S71PL254JB0 TU pSRAM6 / 70 (Note 2) S71PL254JC0 S71PL254JC0 BAI TB 0, 2, 3, 4 (Note 1) 65 pSRAM2 / 70 S71PL254JC0 S71PL254JC0 TU pSRAM6 / 70 S71PL254JC0 S71PL254JC0 TZ pSRAM7 / 70 S71PL254JB0 S71PL254JB0 T7 pSRAM1 / 70 S71PL254JB0 S71PL254JB0 TB pSRAM2 /70 S71PL254JB0 S71PL254JB0 TU pSRAM6 / 70 (Note 2) S71PL254JC0 S71PL254JC0 BFI TB 0, 2, 3, 4 (Note 1) 65 pSRAM2 / 70 S71PL254JC0 S71PL254JC0 TU pSRAM6 / 70 S71PL254JC0 S71PL254JC0 TZ (Note 2) pSRAM7 / 70 Notes: 1. Type 0 is standard. Specify other options as required. 2. BGA package marking omits leading "S" and packing type designator from ordering part number. July 16, 2004 S71PL254/127/064/032J S71PL254/127/064/032J_00_A4 Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. 17 P r e l i m i n a r y Physical Dimensions TLC056-56-ball Fine-Pitch Ball Grid Array (FBGA) 9 x 7mm Package D1 A D eD 0.15 C (2X) 8 7 SE 7 6 5 E E1 4 3 eE 2 1 H INDEX MARK PIN A1 CORNER B 10 TOP VIEW G F E D C B A PIN A1 CORNER 7 SD 0.15 C (2X) BOTTOM VIEW 0.20 C A A2 A1 C 56X 0.08 C SIDE VIEW 6 b 0.15 M C A B 0.08 M C NOTES: PACKAGE TLC 056 JEDEC N/A DxE 9.00 mm x 7.00 mm PACKAGE 1. 2. MIN NOM MAX A - - 1.20 A1 0.20 - - A2 0.81 - 0.97 NOTE PROFILE ALL DIMENSIONS ARE IN MILLIMETERS. 3. SYMBOL DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994 5M-1994. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 SPP-010. 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. BALL HEIGHT SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. BODY THICKNESS D 9.00 BSC. BODY SIZE E 7.00 BSC. BODY SIZE D1 5.60 BSC. MATRIX FOOTPRINT E1 5.60 BSC. MATRIX FOOTPRINT MD 8 MATRIX SIZE D DIRECTION ME 8 MATRIX SIZE E DIRECTION n b 56 0.35 0.40 n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. 6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. BALL COUNT 0.45 WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. BALL DIAMETER eE 0.80 BSC. 0.80 BSC BALL PITCH SD / SE 0.40 BSC. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 BALL PITCH eD SOLDER BALL PLACEMENT A1,A8,D4,D5,E4,E5,H1,H8 DEPOPULATED SOLDER BALLS 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 9. N/A 10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 3348 \ 16-038.22a 18 S71PL254/127/064/032J S71PL254/127/064/032J_00_A4 July 16, 2004 P r e l i m i n a r y TLA064-64-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6mm Package D1 A D eD 0.15 C 10 (2X) 9 8 SE 7 7 6 E E1 5 4 eE 3 2 1 M INDEX MARK PIN A1 CORNER B 10 TOP VIEW L K J H G F E D C B A PIN A1 CORNER 7 SD 0.15 C (2X) BOTTOM VIEW A A2 0.20 C A1 C SIDE VIEW 6 0.08 C b 64X 0.15 0.08 M C A B M C NOTES: PACKAGE TLA 064 JEDEC N/A DxE 11.60 mm x 8.00 mm PACKAGE 1. SYMBOL MIN NOM A - - 1.20 A1 0.17 - - A2 0.81 - 0.97 2. NOTE PROFILE ALL DIMENSIONS ARE IN MILLIMETERS. 3. MAX DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994 5M-1994. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 SPP-010. 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. BALL HEIGHT SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. BODY THICKNESS D 11.60 BSC. BODY SIZE E 8.00 BSC. BODY SIZE D1 8.80 BSC. MATRIX FOOTPRINT E1 7.20 BSC. MATRIX FOOTPRINT MD 12 MATRIX SIZE D DIRECTION ME 10 MATRIX SIZE E DIRECTION n 64 b eE 0.35 0.40 n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. 6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. BALL COUNT 0.45 0.80 BSC. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. BALL DIAMETER WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 BALL PITCH eD 0.80 BSC BALL PITCH SD / SE 0.40 BSC. SOLDER BALL PLACEMENT A2,A3,A4,A5,A6,A7,A8,A9 DEPOPULATED SOLDER BALLS B1,B2,B3,B4,B7,B8,B9,B10 C1,C2,C9,C10,D1,D10,E1,E10, F1,F5,F6,F10,G1,G5,G6,G10 H1,H10,J1,J10,K1,K2,K9,K10 L1,L2,L3,L4,L7,L8,L9,L10 M2,M3,M4,M5,M6,M7,M8,M9 July 16, 2004 S71PL254/127/064/032J S71PL254/127/064/032J_00_A4 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 9. N/A 10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 3352 \ 16-038.22a 19 P r e l i m i n a r y FTA084-84-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6mm D1 A D eD 0.15 C 10 (2X) 9 SE 7 8 7 6 E E1 5 4 eE 3 2 1 M L K J INDEX MARK PIN A1 CORNER B 10 TOP VIEW H G F E D C B A PIN A1 CORNER 7 SD 0.15 C (2X) BOTTOM VIEW 0.20 C A A2 A1 C 84X 0.08 C SIDE VIEW 6 b 0.15 M C A B 0.08 M C NOTES: PACKAGE FTA 084 JEDEC N/A DxE 11.60 mm x 8.00 mm PACKAGE 1. SYMBOL MIN NOM MAX A - - 1.40 A1 0.17 - - A2 1.02 - 1.17 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. NOTE DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994 5M-1994. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 SPP-010. 4. PROFILE e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. BALL HEIGHT SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. BODY THICKNESS D 11.60 BSC. BODY SIZE E 8.00 BSC. BODY SIZE D1 8.80 BSC. MATRIX FOOTPRINT E1 7.20 BSC. MATRIX FOOTPRINT MD 12 MATRIX SIZE D DIRECTION ME 10 MATRIX SIZE E DIRECTION n b 84 0.35 0.40 n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. 6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. BALL COUNT 0.45 WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. BALL DIAMETER eE 0.80 BSC. 0.80 BSC BALL PITCH SD / SE 0.40 BSC. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 BALL PITCH eD SOLDER BALL PLACEMENT A2,A3,A4,A5,A6,A7,A8,A9 DEPOPULATED SOLDER BALLS B1,B10,C1,C10,D1,D10,E1,E10 F1,F10,G1,G10,H1,H10 J1,J10,K1,K10,L1,L10 M2,M3,M4,M5,M6,M7,M8,M9 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 9. N/A 10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 3388 \ 16-038.21a 20 S71PL254/127/064/032J S71PL254/127/064/032J_00_A4 July 16, 2004 S29PL127J/S29PL064J/S29PL032J S29PL127J/S29PL064J/S29PL032J for MCP 128/128/64/32 Megabit (8/4/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory with Enhanced VersatileIOTM Control PRELIMINARY Distinctive Characteristics ARCHITECTURAL ADVANTAGES PERFORMANCE CHARACTERISTICS 128/64/32Mbit Page Mode devices - Page size of 8 words: Fast page read access from random locations within the page High Performance - Page access times as fast as 20 ns - Random access times as fast as 55 ns Single power supply operation - Full Voltage range: 2.7 to 3.6 volt read, erase, and program operations for battery-powered applications Power consumption (typical values at 10 MHz) - 45 mA active read current - 17 mA program/erase current - 0.2 µA typical standby mode current Simultaneous Read/Write Operation - Data can be continuously read from one bank while executing erase/program functions in another bank - Zero latency switching from write to read operations FlexBank Architecture (PL127J/PL064J/PL032J PL127J/PL064J/PL032J) - 4 separate banks, with up to two simultaneous operations per device - Bank A: PL127J PL127J -16Mbit (4 Kw x 8 and 32 Kw x 31) PL064J PL064J - 8Mbit (4 Kw x 8 and 32 Kw x 15) PL032J PL032J - 4Mbit (4 Kw x 8 and 32 Kw x 7) SOFTWARE FEATURES Software command-set compatible with JEDEC 42.4 standard - Backward compatible with Am29F, Am29LV, Am29DL, and AM29PDL AM29PDL families and MBM29QM/RM MBM29QM/RM, MBM29LV MBM29LV, MBM29DL MBM29DL, MBM29PDL MBM29PDL families CFI (Common Flash Interface) compliant - Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices - Bank B: PL127J PL127J - 48Mbit (32 Kw x 96) PL064J PL064J - 24Mbit (32 Kw x 48) PL032J PL032J - 12 Mbit (32 Kw x 24) Erase Suspend / Erase Resume - Suspends an erase operation to allow read or program operations in other sectors of same bank - Bank C: PL127J PL127J - 48Mbit (32 Kw x 96) PL064J PL064J - 24Mbit (32 Kw x 48) PL032J PL032J - 12 Mbit (32 Kw x 24) Unlock Bypass Program command - Reduces overall programming time when issuing multiple program command sequences - Bank D: PL127J PL127J -16Mbit (4 Kw x 8 and 32 Kw x 31) PL064J PL064J - 8Mbit (4 Kw x 8 and 32 Kw x 15) PL032J PL032J - 4Mbit (4 Kw x 8 and 32 Kw x 7) Enhanced VersatileI/OTM (VIO) Control - Output voltage generated and input voltages tolerated on all control inputs and I/Os is determined by the voltage on the VIO pin - VIO options at 1.8 V and 3 V I/O for PL127J PL127J devices - 3V VIO for PL064J PL064J and PL032J PL032J devices SecSiTM (Secured Silicon) Sector region - Up to 128 words accessible through a command sequence - Up to 64 factory-locked words - Up to 64 customer-lockable words Both top and bottom boot blocks in one device Manufactured on 110 nm process technology Data Retention: 20 years typical Cycling Endurance: 1 million cycles per sector typical Publication Number S29PL127 S29PL127_064_032J_00_ Revision A Amendment 1 Issue Date May 21, 2004 P r e l i m i n a r y HARDWARE FEATURES Ready/Busy# pin (RY/BY#) - Provides a hardware method of detecting program or erase cycle completion Hardware reset pin (RESET#) - Hardware method to reset the device to reading array data WP#/ ACC (Write Protect/Acceleration) input - At VIL, hardware level protection for the first and last two 4K word sectors. - At VIH, allows removal of sector protection - At VHH, provides accelerated programming in a factory setting Persistent Sector Protection - A command sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector - Sectors can be locked and unlocked in-system at VCC level Password Sector Protection - A sophisticated sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector using a user-defined 64-bit password 22 S29PL127J/S29PL064J/S29PL032J S29PL127J/S29PL064J/S29PL032J for MCP S29PL127 S29PL127_064_032J_00_A1 May 21, 2004 P r e l i m i n a r y General Description The PL127J/PL064J/PL032J PL127J/PL064J/PL032J is a 128/128/64/32Mbit, 3.0 volt-only Page Mode and Simultaneous Read/Write Flash memory device organized as 8/8/4/2 Mwords. The word-wide data (x16) appears on DQ15-DQ0 DQ15-DQ0. This device can be programmed in-system or in standard EPROM programmers. A 12.0 V VPP is not required for write or erase operations. The device offers fast page access times of 20 to 30 ns, with corresponding random access times of 55 to 70 ns, respectively, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. Simultaneous Read/Write Operation with Zero Latency The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into 4 banks, which can be considered to be four separate memory arrays as far as certain operations are concerned. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from another bank with zero latency (with two simultaneous operations operating at any one time). This releases the system from waiting for the completion of a program or erase operation, greatly improving system performance. The device can be organized in both top and bottom sector configurations. The banks are organized as follows: Bank PL127J PL127J Sectors PL064J PL064J Sectors PL032J PL032J Sectors A 16Mbit (4 Kw x 8 and 32 Kw x 31) 8Mbit (4 Kw x 8 and 32 Kw x 15) 4Mbit (4 Kw x 8 and 32 Kw x 7) B 48Mbit (32 Kw x 96) 24Mbit (32 Kw x 48) 12 Mbit (32 Kw x 24) C 48Mbit (32 Kw x 96) 24Mbit (32 Kw x 48) 12 Mbit (32 Kw x 24) D 16Mbit (4 Kw x 8 and 32 Kw x 31) 8Mbit (4 Kw x 8 and 32 Kw x 15) 4Mbit (4 Kw x 8 and 32 Kw x 7) Page Mode Features The page size is 8 words. After initial page access is accomplished, the page mode operation provides fast read access speed of random locations within that page. Standard Flash Memory Features The device requires a single 3.0 volt power supply (2.7 V to 3.6 V) for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC 42.4 singlepower-supply Flash standard. Commands are written to the command register using standard microprocessor write timing. Register contents serve as inputs to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. May 21, 2004 S29PL127 S29PL127_064_032J_00_A1 S29PL127J/S29PL064J/S29PL032J S29PL127J/S29PL064J/S29PL032J for MCP 23 P r e l i m i n a r y Device programming occurs by executing the program command sequence. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. The host system can detect whether a program or erase operation is complete by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. If a read is needed from the SecSi Sector area (One Time Program area) after an erase suspend, then the user must use the proper command sequence to enter and exit this region. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. The device electrically erases all bits within a sector simultaneously via FowlerNordheim tunneling. The data is programmed using hot electron injection. 24 S29PL127J/S29PL064J/S29PL032J S29PL127J/S29PL064J/S29PL032J for MCP S29PL127 S29PL127_064_032J_00_A1 May 21, 2004 P r e l i m i n a r y Product Selector Guide Part Number S29PL032J/S29PL064J/S29PL127J/064J/032J S29PL032J/S29PL064J/S29PL127J/064J/032J VCC,VIO = 2.7­3.6 V Speed Option 55 (Note) 60 65 VCC = 2.7­3.6 V, VIO = 1.65­1.95 V (PL127J PL127J only) Max Access Time, ns (tACC) Max CE# Access, ns (tCE) Max Page Access, ns (tPACC) Max OE# Access, ns (tOE) 70 65 70 55 (Note) 60 65 65 70 70 20 (Note) 25 25 30 30 30 Note: Contact factory for availability May 21, 2004 S29PL127 S29PL127_064_032J_00_A1 S29PL127J/S29PL064J/S29PL032J S29PL127J/S29PL064J/S29PL032J for MCP 25 P r e l i m i n a r y Block Diagram DQ15­DQ0 RY/BY# (See Note) VCC VSS Sector Switches VIO RESET# Input/Output Buffers Erase Voltage Generator WE# State Control Command Register PGM Voltage Generator Chip Enable Output Enable Logic CE# OE# Y-Decoder Y-Gating Timer Address Latch VCC Detector Data Latch Amax­A3 X-Decoder Cell Matrix A2­A0 Notes: 1. RY/BY# is an open drain output. 2. Amax = A22 (PL127J PL127J), A21 (PL064J PL064J), A20 (PL032J PL032J) 26 S29PL127J/S29PL064J/S29PL032J S29PL127J/S29PL064J/S29PL032J for MCP S29PL127 S29PL127_064_032J_00_A1 May 21, 2004 P r e l i m i n a r y Simultaneous Read/Write Block Diagram VCC VSS OE# Mux Bank A Bank B X-Decoder Amax­A0 Status DQ15­DQ0 Control Mux DQ15­DQ0 CE# WP#/ACC STATE CONTROL & COMMAND REGISTER X-Decoder A22­A0 DQ0­DQ15 Bank C Address Bank C X-Decoder Amax­A0 Bank D Address Y-gate RESET# WE# DQ15­DQ0 Bank B Address DQ15­DQ0 RY/BY# DQ15­DQ0 A22­A0 X-Decoder Y-gate Bank A Address Amax­A0 Bank D Mux Note: Amax = A22 (PL127J PL127J), A21 (PL064J PL064J), A20 (PL032J PL032J) Note: Pinout shown for PL127J PL127J. May 21, 2004 S29PL127 S29PL127_064_032J_00_A1 S29PL127J/S29PL064J/S29PL032J S29PL127J/S29PL064J/S29PL032J for MCP 27 P r e l i m i n a r y Pin Description Amax­A0 DQ15­DQ0 CE# OE# WE# VSS NC RY/BY# = = = = = = = = WP#/ACC = VIO = VCC = RESET# CE#1 Address bus 16-bit data inputs/outputs/float Chip Enable Inputs Output Enable Input Write Enable Device Ground Pin Not Connected Internally Ready/Busy output and open drain. When RY/BY#= VIH, the device is ready to accept read operations and commands. When RY/BY#= VOL, the device is either executing an embedded algorithm or the device is executing a hardware reset operation. Write Protect/Acceleration Input. When WP#/ACC= VIL, the highest and lowest two 4K-word sectors are write protected regardless of other sector protection configurations. When WP#/ ACC= VIH, these sector are unprotected unless the DYB or PPB is programmed. When WP#/ACC= 12V, program and erase operations are accelerated. Input/Output Buffer Power Supply (1.65 V to 1.95 V (for PL127J PL127J) or 2.7 V to 3.6 V (for all PLxxxJ devices) Chip Power Supply (2.7 V to 3.6 V or 2.7 to 3.3 V) Hardware Reset Pin Chip Enable Inputs = = Notes: 1. Amax = A22 (PL127J PL127J), A21 (PL064J PL064J), A20 (PL032J PL032J) Logic Symbol max+1 Amax­A0 16 DQ15­DQ0 CE# OE# WE# WP#/ACC RESET# RY/BY# VIO (VCCQ) 28 S29PL127J/S29PL064J/S29PL032J S29PL127J/S29PL064J/S29PL032J for MCP S29PL127 S29PL127_064_032J_00_A1 May 21, 2004 P r e l i m i n a r y Device Bus Operations This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. Table 1. PL127J PL127J Device Bus Operations CE# OE# WE# RESET# WP#/ACC Addresses (Amax­A0) DQ15­ DQ0 Read L L H H X AIN DOUT Write L H L H X (Note 2) AIN DIN VIO± 0.3 V X X VIO ± 0.3 V X (Note 2) X High-Z Output Disable L H H H X X High-Z Reset X X X L X X High-Z Temporary Sector Unprotect (High Voltage) X X X VID X AIN DIN Operation Standby Legend: L= Logic Low = VIL, H = Logic High = VIH, VID = 11.5-12.5 V, VHH = 8.5-9.5 V, X = Don't Care, SA = Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the High Voltage Sector Protection section. 2. WP#/ACC must be high when writing to upper two and lower two sectors. Requirements for Reading Array Data To read array data from the outputs, the system must drive the OE# and appropriate CE# pins. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for read access until the command register contents are altered. Refer to Table 23 for timing specifications and to Figure 11 for the timing diagram. ICC1 in the DC Characteristics table represents the active current specification for reading array data. Random Read (Non-Page Read) Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from the stable addresses and stable CE# to valid data at the output inputs. The output enable May 21, 2004 S29PL127 S29PL127_064_032J_00_A1 S29PL127J/S29PL064J/S29PL032J S29PL127J/S29PL064J/S29PL032J for MCP 29 P r e l i m i n a r y access time is the delay from the falling edge of the OE# to valid data at the output inputs (assuming the addresses have been stable for at least tACC­tOE time). Page Mode Read The device is capable of fast page mode read and is compatible with the page mode Mask ROM read operation. This mode provides faster read access speed for random locations within a page. Address bits Amax­A3 select an 8 word page, and address bits A2­A0 select a specific word within that page. This is an asynchronous operation with the microprocessor supplying the specific word location. The random or initial page access is tACC or tCE and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to tPACC. Fast page mode accesses are obtained by keeping Amax­A3 constant and changing A2­A0 to select the specific word within that page. Table 2. Page Select Word A2 A1 A0 Word 0 0 0 0 Word 1 0 0 1 Word 2 0 1 0 Word 3 0 1 1 Word 4 1 0 0 Word 5 1 0 1 Word 6 1 1 0 Word 7 1 1 1 Simultaneous Read/Write Operation In addition to the conventional features (read, program, erase-suspend read, and erase-suspend program), the device is capable of reading data from one bank of memory while a program or erase operation is in progress in another bank of memory (simultaneous operation). The bank can be selected by bank addresses (PL127J PL127J: A22­A20, L064J L064J: A21­A19, PL032J PL032J: A20­A18) with zero latency. The simultaneous operation can execute multi-function mode in the same bank. Table 3. Bank Select Bank Bank A 000 Bank B 001, 010, 011 Bank C 100, 101, 110 Bank D 30 PL127J PL127J: A22­A20 PL064J PL064J: A21­A19 PL032J PL032J: A20­A18 111 S29PL127J/S29PL064J/S29PL032J S29PL127J/S29PL064J/S29PL032J for MCP S29PL127 S29PL127_064_032J_00_A1 May 21, 2004 P r e l i m i n a r y Writing Commands/Command Sequences To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. The device features an Unlock Bypass mode to facilitate faster programming. Once a bank enters the Unlock Bypass mode, only two write cycles are required to program a word, instead of four. The "Word Program Command Sequence" section has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sectors, or the entire device. Table 4 indicates the set of address space that each sector occupies. A "bank address" is the set of address bits required to uniquely select a bank. Similarly, a "sector address" refers to the address bits required to uniquely select a sector. The "Command Definitions" section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. ICC2 in the DC Characteristics table represents the active current specification for the write mode. See the timing specification tables and timing diagrams in the Reset for write operations. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This function is primarily intended to allow faster manufacturing throughput at the factory. If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the WP#/ACC pin returns the device to normal operation. Note that VHH must not be asserted on WP#/ACC for operations other than accelerated programming, or device damage may result. In addition, the WP#/ACC pin should be raised to VCC when not in use. That is, the WP#/ACC pin should not be left floating or unconnected; inconsistent behavior of the device may result. Autoselect Functions If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ15­DQ0. Standard read cycle timings apply in this mode. Refer to the SecSiTM Sector Addresses and Autoselect Command Sequence for more information. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VIO ± 0.3 V. (Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VIO ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device May 21, 2004 S29PL127 S29PL127_064_032J_00_A1 S29PL127J/S29PL064J/S29PL032J S29PL127J/S29PL064J/S29PL032J for MCP 31 P r e l i m i n a r y requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. ICC3 in "DC Characteristics" represents the CMOS standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. Note that during automatic sleep mode, OE# must be at VIH before the device reduces current to the stated sleep mode specification. ICC5 in "DC Characteristics" represents the automatic sleep mode current specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a "0" (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/ BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is "1"), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH. Refer to the AC Characteristic tables for RESET# parameters and to 13 for the timing diagram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins (except for RY/BY#) are placed in the highest Impedance state 32 S29PL127J/S29PL064J/S29PL032J S29PL127J/S29PL064J/S29PL032J for MCP S29PL127 S29PL127_064_032J_00_A1 May 21, 2004 P r e l i m i n a r y Table 4. Sector Sector Address (A22-A12 A22-A12) Sector Size (Kwords) Address Range (x16) SA0 00000000000 4 000000h­000FFFh SA1 00000000001 4 001000h­001FFFh SA2 00000000010 4 002000h­002FFFh SA3 00000000011 4 003000h­003FFFh SA4 00000000100 4 004000h­004FFFh SA5 00000000101 4 005000h­005FFFh SA6 00000000110 4 006000h­006FFFh SA7 00000000111 4 007000h­007FFFh SA8 00000001XXX 00000001XXX 32 008000h­00FFFFh SA9 00000010XXX 00000010XXX 32 010000h­017FFFh SA10 00000011XXX 00000011XXX 32 018000h­01FFFFh SA11 00000100XXX 00000100XXX 32 020000h­027FFFh SA12 00000101XXX 00000101XXX 32 028000h­02FFFFh SA13 00000110XXX 00000110XXX 32 030000h­037FFFh SA14 00000111XXX 00000111XXX 32 038000h­03FFFFh SA15 00001000XXX 00001000XXX 32 040000h­047FFFh SA16 00001001XXX 00001001XXX 32 048000h­04FFFFh SA17 00001010XXX 00001010XXX 32 050000h­057FFFh SA18 00001011XXX 00001011XXX 32 058000h­05FFFFh SA19 00001100XXX 00001100XXX 32 060000h­067FFFh SA20 00001101XXX 00001101XXX 32 068000h­06FFFFh SA21 00001110XXX 00001110XXX 32 070000h­077FFFh SA22 00001111XXX 00001111XXX 32 078000h­07FFFFh SA23 00010000XXX 00010000XXX 32 080000h­087FFFh SA24 00010001XXX 00010001XXX 32 088000h­08FFFFh SA25 00010010XXX 00010010XXX 32 090000h­097FFFh SA26 00010011XXX 00010011XXX 32 098000h­09FFFFh SA27 00010100XXX 00010100XXX 32 0A0000h­0A7FFFh SA28 00010101XXX 00010101XXX 32 0A8000h­0AFFFFh SA29 00010110XXX 00010110XXX 32 0B0000h­0B7FFFh SA30 00010111XXX 00010111XXX 32 0B8000h­0BFFFFh SA31 00011000XXX 00011000XXX 32 0C0000h­0C7FFFh SA32 00011001XXX 00011001XXX 32 0C8000h­0CFFFFh SA33 00011010XXX 00011010XXX 32 0D0000h­0D7FFFh SA34 00011011XXX 00011011XXX 32 0D8000h­0DFFFFh SA35 00011100XXX 00011100XXX 32 0E0000h­0E7FFFh SA36 00011101XXX 00011101XXX 32 0E8000h­0EFFFFh SA37 00011110XXX 00011110XXX 32 0F0000h­0F7FFFh SA38 Bank A Bank PL127J PL127J Sector Architecture 00011111XXX 00011111XXX 32 0F8000h­0FFFFFh May 21, 2004 S29PL127 S29PL127_064_032J_00_A1 S29PL127J/S29PL064J/S29PL032J S29PL127J/S29PL064J/S29PL032J for MCP 33 P r e l i m i n a r y Table 4. Sector Address (A22-A12 A22-A12) Sector Size (Kwords) Address Range (x16) 00100000XXX 00100000XXX 32 100000h­107FFFh SA40 00100001XXX 00100001XXX 32 108000h­10FFFFh SA41 00100010XXX 00100010XXX 32 110000h­117FFFh SA42 00100011XXX 00100011XXX 32 118000h­11FFFFh SA43 00100100XXX 00100100XXX 32 120000h­127FFFh SA44 00100101XXX 00100101XXX 32 128000h­12FFFFh SA45 00100110XXX 00100110XXX 32 130000h­137FFFh SA46 00100111XXX 00100111XXX 32 138000h­13FFFFh SA47 00101000XXX 00101000XXX 32 140000h­147FFFh SA48 00101001XXX 00101001XXX 32 148000h­14FFFFh SA49 00101010XXX 00101010XXX 32 150000h­157FFFh SA50 00101011XXX 00101011XXX 32 158000h­15FFFFh SA51 00101100XXX 00101100XXX 32 160000h­167FFFh SA52 00101101XXX 00101101XXX 32 168000h­16FFFFh SA53 00101110XXX 00101110XXX 32 170000h­177FFFh SA54 00101111XXX 00101111XXX 32 178000h­17FFFFh SA55 00110000XXX 00110000XXX 32 180000h­187FFFh SA56 00110001XXX 00110001XXX 32 188000h­18FFFFh SA57 00110010XXX 00110010XXX 32 190000h­197FFFh SA58 00110011XXX 00110011XXX 32 198000h­19FFFFh SA59 00110100XXX 00110100XXX 32 1A0000h­1A7FFFh SA60 00110101XXX 00110101XXX 32 1A8000h­1AFFFFh SA61 00110110XXX 00110110XXX 32 1B0000h­1B7FFFh SA62 00110111XXX 00110111XXX 32 1B8000h­1BFFFFh SA63 00111000XXX 00111000XXX 32 1C0000h­1C7FFFh SA64 00111001XXX 00111001XXX 32 1C8000h­1CFFFFh SA65 00111010XXX 00111010XXX 32 1D0000h­1D7FFFh SA66 00111011XXX 00111011XXX 32 1D8000h­1DFFFFh SA67 00111100XXX 00111100XXX 32 1E0000h­1E7FFFh SA68 00111101XXX 00111101XXX 32 1E8000h­1EFFFFh SA69 00111110XXX 00111110XXX 32 1F0000h­1F7FFFh SA70 00111111XXX 00111111XXX 32 1F8000h­1FFFFFh SA71 01000000XXX 01000000XXX 32 200000h­207FFFh SA72 01000001XXX 01000001XXX 32 208000h­20FFFFh SA73 01000010XXX 01000010XXX 32 210000h­217FFFh SA74 01000011XXX 01000011XXX 32 218000h­21FFFFh SA75 01000100XXX 01000100XXX 32 220000h­227FFFh SA76 01000101XXX 01000101XXX 32 228000h­22FFFFh SA77 01000110XXX 01000110XXX 32 230000h­237FFFh SA78 34 Sector SA39 Bank B Bank PL127J PL127J Sector Architecture (Continued) 01000111XXX 01000111XXX 32 238000h­23FFFFh S29PL127J/S29PL064J/S29PL032J S29PL127J/S29PL064J/S29PL032J for MCP S29PL127 S29PL127_064_032J_00_A1 May 21, 2004 P r e l i m i n a r y Table 4. Sector Sector Address (A22-A12 A22-A12) Sector Size (Kwords) Address Range (x16) SA79 01001000XXX 01001000XXX 32 240000h­247FFFh SA80 01001001XXX 01001001XXX 32 248000h­24FFFFh SA81 01001010XXX 01001010XXX 32 250000h­257FFFh SA82 01001011XXX 01001011XXX 32 258000h­25FFFFh SA83 01001100XXX 01001100XXX 32 260000h­267FFFh SA84 01001101XXX 01001101XXX 32 268000h­26FFFFh SA85 01001110XXX 01001110XXX 32 270000h­277FFFh SA86 01001111XXX 01001111XXX 32 278000h­27FFFFh SA87 01010000XXX 01010000XXX 32 280000h­287FFFh SA88 01010001XXX 01010001XXX 32 288000h­28FFFFh SA89 01010010XXX 01010010XXX 32 290000h­297FFFh SA90 01010011XXX 01010011XXX 32 298000h­29FFFFh SA91 01010100XXX 01010100XXX 32 2A0000h­2A7FFFh SA92 01010101XXX 01010101XXX 32 2A8000h­2AFFFFh SA93 01010110XXX 01010110XXX 32 2B0000h­2B7FFFh SA94 01010111XXX 01010111XXX 32 2B8000h­2BFFFFh SA95 01011000XXX 01011000XXX 32 2C0000h­2C7FFFh SA96 01011001XXX 01011001XXX 32 2C8000h­2CFFFFh SA97 01011010XXX 01011010XXX 32 2D0000h­2D7FFFh SA98 01011011XXX 01011011XXX 32 2D8000h­2DFFFFh SA99 01011100XXX 01011100XXX 32 2E0000h­2E7FFFh SA100 SA100 01011101XXX 01011101XXX 32 2E8000h­2EFFFFh SA101 SA101 01011110XXX 01011110XXX 32 2F0000h­2F7FFFh SA102 SA102 01011111XXX 01011111XXX 32 2F8000h­2FFFFFh SA103 SA103 01100000XXX 01100000XXX 32 300000h­307FFFh SA104 SA104 01100001XXX 01100001XXX 32 308000h­30FFFFh SA105 SA105 01100010XXX 01100010XXX 32 310000h­317FFFh SA106 SA106 01100011XXX 01100011XXX 32 318000h­31FFFFh SA107 SA107 01100100XXX 01100100XXX 32 320000h­327FFFh SA108 SA108 01100101XXX 01100101XXX 32 328000h­32FFFFh SA109 SA109 01100110XXX 01100110XXX 32 330000h­337FFFh SA110 SA110 01100111XXX 01100111XXX 32 338000h­33FFFFh SA111 SA111 01101000XXX 01101000XXX 32 340000h­347FFFh SA112 SA112 01101001XXX 01101001XXX 32 348000h­34FFFFh SA113 SA113 01101010XXX 01101010XXX 32 350000h­357FFFh SA114 SA114 01101011XXX 01101011XXX 32 358000h­35FFFFh SA115 SA115 01101100XXX 01101100XXX 32 360000h­367FFFh SA116 SA116 01101101XXX 01101101XXX 32 368000h­36FFFFh SA117 SA117 01101110XXX 01101110XXX 32 370000h­377FFFh SA118 SA118 Bank B Bank PL127J PL127J Sector Architecture (Continued) 01101111XXX 01101111XXX 32 378000h­37FFFFh May 21, 2004 S29PL127 S29PL127_064_032J_00_A1 S29PL127J/S29PL064J/S29PL032J S29PL127J/S29PL064J/S29PL032J for MCP 35 P r e l i m i n a r y Table 4. Sector Size (Kwords) Address Range (x16) 01110000XXX 01110000XXX 32 380000h­387FFFh 01110001XXX 01110001XXX 32 388000h­38FFFFh SA121 SA121 01110010XXX 01110010XXX 32 390000h­397FFFh SA122 SA122 01110011XXX 01110011XXX 32 398000h­39FFFFh SA123 SA123 01110100XXX 01110100XXX 32 3A0000h­3A7FFFh SA124 SA124 01110101XXX 01110101XXX 32 3A8000h­3AFFFFh SA125 SA125 01110110XXX 01110110XXX 32 3B0000h­3B7FFFh SA126 SA126 01110111XXX 01110111XXX 32 3B8000h­3BFFFFh SA127 SA127 01111000XXX 01111000XXX 32 3C0000h­3C7FFFh SA128 SA128 01111001XXX 01111001XXX 32 3C8000h­3CFFFFh SA129 SA129 01111010XXX 01111010XXX 32 3D0000h­3D7FFFh SA130 SA130 01111011XXX 01111011XXX 32 3D8000h­3DFFFFh SA131 SA131 01111100XXX 01111100XXX 32 3E0000h­3E7FFFh SA132 SA132 01111101XXX 01111101XXX 32 3E8000h­3EFFFFh SA133 SA133 01111110XXX 01111110XXX 32 3F0000h­3F7FFFh SA134 SA134 01111111XXX 01111111XXX 32 3F8000h­3FFFFFh SA135 SA135 10000000XXX 10000000XXX 32 400000h­407FFFh SA136 SA136 10000001XXX 10000001XXX 32 408000h­40FFFFh SA137 SA137 10000010XXX 10000010XXX 32 410000h­417FFFh SA138 SA138 10000011XXX 10000011XXX 32 418000h­41FFFFh SA139 SA139 10000100XXX 10000100XXX 32 420000h­427FFFh SA140 SA140 10000101XXX 10000101XXX 32 428000h­42FFFFh SA141 SA141 10000110XXX 10000110XXX 32 430000h­437FFFh SA142 SA142 10000111XXX 10000111XXX 32 438000h­43FFFFh SA143 SA143 10001000XXX 10001000XXX 32 440000h­447FFFh SA144 SA144 10001001XXX 10001001XXX 32 448000h­44FFFFh SA145 SA145 10001010XXX 10001010XXX 32 450000h­457FFFh SA146 SA146 10001011XXX 10001011XXX 32 458000h­45FFFFh SA147 SA147 10001100XXX 10001100XXX 32 460000h­467FFFh SA148 SA148 10001101XXX 10001101XXX 32 468000h­46FFFFh SA149 SA149 10001110XXX 10001110XXX 32 470000h­477FFFh SA150 SA150 10001111XXX 10001111XXX 32 478000h­47FFFFh SA151 SA151 10010000XXX 10010000XXX 32 480000h­487FFFh SA152 SA152 10010001XXX 10010001XXX 32 488000h­48FFFFh SA153 SA153 10010010XXX 10010010XXX 32 490000h­497FFFh SA154 SA154 10010011XXX 10010011XXX 32 498000h­49FFFFh SA155 SA155 10010100XXX 10010100XXX 32 4A0000h­4A7FFFh SA156 SA156 10010101XXX 10010101XXX 32 4A8000h­4AFFFFh SA157 SA157 10010110XXX 10010110XXX 32 4B0000h­4B7FFFh SA158 SA158 Bank C Sector Address (A22-A12 A22-A12) SA120 SA120 36 Sector SA119 SA119 Bank B Bank PL127J PL127J Sector Architecture (Continued) 10010111XXX 10010111XXX 32 4B8000h­4BFFFFh S29PL127J/S29PL064J/S29PL032J S29PL127J/S29PL064J/S29PL032J for MCP S29PL127 S29PL127_064_032J_00_A1 May 21, 2004 P r e l i m i n a r y Table 4. Sector Sector Address (A22-A12 A22-A12) Sector Size (Kwords) Address Range (x16) SA159 SA159 10011000XXX 10011000XXX 32 4C0000h­4C7FFFh SA160 SA160 10011001XXX 10011001XXX 32 4C8000h­4CFFFFh SA161 SA161 10011010XXX 10011010XXX 32 4D0000h­4D7FFFh SA162 SA162 10011011XXX 10011011XXX 32 4D8000h­4DFFFFh SA163 SA163 10011100XXX 10011100XXX 32 4E0000h­4E7FFFh SA164 SA164 10011101XXX 10011101XXX 32 4E8000h­4EFFFFh SA165 SA165 10011110XXX 10011110XXX 32 4F0000h­4F7FFFh SA166 SA166 10011111XXX 10011111XXX 32 4F8000h­4FFFFFh SA167 SA167 10100000XXX 10100000XXX 32 500000h­507FFFh SA168 SA168 10100001XXX 10100001XXX 32 508000h­50FFFFh SA169 SA169 10100010XXX 10100010XXX 32 510000h­517FFFh SA170 SA170 10100011XXX 10100011XXX 32 518000h­51FFFFh SA171 SA171 10100100XXX 10100100XXX 32 520000h­527FFFh SA172 SA172 10100101XXX 10100101XXX 32 528000h­52FFFFh SA173 SA173 10100110XXX 10100110XXX 32 530000h­537FFFh SA174 SA174 10100111XXX 10100111XXX 32 538000h­53FFFFh SA175 SA175 10101000XXX 10101000XXX 32 540000h­547FFFh SA176 SA176 10101001XXX 10101001XXX 32 548000h­54FFFFh SA177 SA177 10101010XXX 10101010XXX 32 550000h­557FFFh SA178 SA178 10101011XXX 10101011XXX 32 558000h­15FFFFh SA179 SA179 10101100XXX 10101100XXX 32 560000h­567FFFh SA180 SA180 10101101XXX 10101101XXX 32 568000h­56FFFFh SA181 SA181 10101110XXX 10101110XXX 32 570000h­577FFFh SA182 SA182 10101111XXX 10101111XXX 32 578000h­57FFFFh SA183 SA183 10110000XXX 10110000XXX 32 580000h­587FFFh SA184 SA184 10110001XXX 10110001XXX 32 588000h­58FFFFh SA185 SA185 10110010XXX 10110010XXX 32 590000h­597FFFh SA186 SA186 10110011XXX 10110011XXX 32 598000h­59FFFFh SA187 SA187 10110100XXX 10110100XXX 32 5A0000h­5A7FFFh SA188 SA188 10110101XXX 10110101XXX 32 5A8000h­5AFFFFh SA189 SA189 10110110XXX 10110110XXX 32 5B0000h­5B7FFFh SA190 SA190 10110111XXX 10110111XXX 32 5B8000h­5BFFFFh SA191 SA191 10111000XXX 10111000XXX 32 5C0000h­5C7FFFh SA192 SA192 10111001XXX 10111001XXX 32 5C8000h­5CFFFFh SA193 SA193 10111010XXX 10111010XXX 32 5D0000h­5D7FFFh SA194 SA194 10111011XXX 10111011XXX 32 5D8000h­5DFFFFh SA195 SA195 10111100XXX 10111100XXX 32 5E0000h­5E7FFFh SA196 SA196 10111101XXX 10111101XXX 32 5E8000h­5EFFFFh SA197 SA197 10111110XXX 10111110XXX 32 5F0000h­5F7FFFh SA198 SA198 Bank C Bank PL127J PL127J Sector Architecture (Continued) 10111111XXX 10111111XXX 32 5F8000h­5FFFFFh May 21, 2004 S29PL127 S29PL127_064_032J_00_A1 S29PL127J/S29PL064J/S29PL032J S29PL127J/S29PL064J/S29PL032J for MCP 37 P r e l i m i n a r y Table 4. Sector Address (A22-A12 A22-A12) Sector Size (Kwords) Address Range (x16) 11000000XXX 11000000XXX 32 600000h­607FFFh SA200 SA200 11000001XXX 11000001XXX 32 608000h­60FFFFh SA201 SA201 11000010XXX 11000010XXX 32 610000h­617FFFh SA202 SA202 11000011XXX 11000011XXX 32 618000h­61FFFFh SA203 SA203 11000100XXX 11000100XXX 32 620000h­627FFFh SA204 SA204 11000101XXX 11000101XXX 32 628000h­62FFFFh SA205 SA205 11000110XXX 11000110XXX 32 630000h­637FFFh SA206 SA206 11000111XXX 11000111XXX 32 638000h­63FFFFh SA207 SA207 11001000XXX 11001000XXX 32 640000h­647FFFh SA208 SA208 11001001XXX 11001001XXX 32 648000h­64FFFFh SA209 SA209 11001010XXX 11001010XXX 32 650000h­657FFFh SA210 SA210 11001011XXX 11001011XXX 32 658000h­65FFFFh SA211 SA211 11001100XXX 11001100XXX 32 660000h­667FFFh SA212 SA212 11001101XXX 11001101XXX 32 668000h­66FFFFh SA213 SA213 11001110XXX 11001110XXX 32 670000h­677FFFh SA214 SA214 11001111XXX 11001111XXX 32 678000h­67FFFFh SA215 SA215 11010000XXX 11010000XXX 32 680000h­687FFFh SA216 SA216 11010001XXX 11010001XXX 32 688000h­68FFFFh SA217 SA217 11010010XXX 11010010XXX 32 690000h­697FFFh SA218 SA218 11010011XXX 11010011XXX 32 698000h­69FFFFh SA219 SA219 11010100XXX 11010100XXX 32 6A0000h­6A7FFFh SA220 SA220 11010101XXX 11010101XXX 32 6A8000h­6AFFFFh SA221 SA221 11010110XXX 11010110XXX 32 6B0000h­6B7FFFh SA222 SA222 11010111XXX 11010111XXX 32 6B8000h­6BFFFFh SA223 SA223 11011000XXX 11011000XXX 32 6C0000h­6C7FFFh SA224 SA224 11011001XXX 11011001XXX 32 6C8000h­6CFFFFh SA225 SA225 11011010XXX 11011010XXX 32 6D0000h­6D7FFFh SA226 SA226 11011011XXX 11011011XXX 32 6D8000h­6DFFFFh SA227 SA227 11011100XXX 11011100XXX 32 6E0000h­6E7FFFh SA228 SA228 11011101XXX 11011101XXX 3