S3C8444 00000101B 00000111B 00000110B 00000001B 00001111B 00000011B 1A47H 0002H - Datasheet Archive

 

6 SAM8 INSTRUCTION SET SAM8 INSTRUCTION SET OVERVIEW The SAM8 instruction set is designed to support the large register file of

 

S3C8444 S3C8444 6 SAM8 INSTRUCTION SET SAM8 INSTRUCTION SET OVERVIEW The SAM8 instruction set is designed to support the large register file of S3C8-series microcontrollers. It includes a full complement of 8-bit arithmetic and logic operations, including multiply and divide. There are 78 instructions. No special I/O instructions are necessary because I/O control and data registers are mapped directly into the register file. Decimal adjustment is included in binary-coded decimal (BCD) operations. 16-bit word data can be incremented and decremented. Flexible instructions for bit addressing, rotate, and shift operations complete the powerful data manipulation capabilities of the SAM8 instruction set. DATA TYPES The SAM8 CPU performs operations on bits, bytes, BCD digits, and two-byte words. Bits in the register file can be set, cleared, complemented, and tested. Bits within a byte are numbered from 7 to 0, where bit 0 is the least significant (right-most) bit. REGISTER ADDRESSING To access an individual register, an 8-bit address in the range 0-255 or the 4-bit address of a working register is specified. Paired registers can be used to construct 16-bit data or 16-bit program memory or data memory addresses. For detailed information about register addressing, please refer to Section 2, "Address Spaces." ADDRESSING MODES There are seven addressing modes: Register (R), Indirect Register (IR), Indexed (X), Direct (DA), Relative (RA), Immediate (IM), and Indirect (IA). For detailed descriptions of these addressing modes, please refer to Section 3, "Addressing Modes." 6­1 SAM8 INSTRUCTION SET S3C8444 S3C8444 Table 6­1. Instruction Group Summary Mnemonic Operands Instruction dst dst,src dst,src dst,src dst,src dst,src dst,src dst,src dst,src dst,src dst,src dst,src dst,src dst,src dst dst,src dst,src src dst,src dst,src Clear Load Load bit Load external data memory Load program memory Load external data memory and decrement Load program memory and decrement Load external data memory and increment Load program memory and increment Load external data memory with pre-decrement Load program memory with pre-decrement Load external data memory with pre-increment Load program memory with pre-increment Load word Pop from stack Pop user stack (decrementing) Pop user stack (incrementing) Push to stack Push user stack (decrementing) Push user stack (incrementing) Load Instructions CLR LD LDB LDE LDC LDED LDCD LDEI LDCI LDEPD LDCPD LDEPI LDCPI LDW POP POPUD POPUI PUSH PUSHUD PUSHUI 6­2 S3C8444 S3C8444 SAM8 INSTRUCTION SET Table 6­1. Instruction Group Summary (Continued) Mnemonic Operands Instruction Arithmetic Instructions ADC ADD CP DA DEC DECW DIV INC INCW MULT SBC SUB dst,src dst,src dst,src dst dst dst dst,src dst dst dst,src dst,src dst,src Add with carry Add Compare Decimal adjust Decrement Decrement word Divide Increment Increment word Multiply Subtract with carry Subtract dst,src dst dst,src dst,src Logical AND Complement Logical OR Logical exclusive OR Logic Instructions AND COM OR XOR 6­3 SAM8 INSTRUCTION SET S3C8444 S3C8444 Table 6­1. Instruction Group Summary (Continued) Mnemonic Operands Instruction Program Control Instructions BTJRF BTJRT CALL CPIJE CPIJNE DJNZ ENTER EXIT IRET JP JP JR NEXT RET WFI dst,src dst,src dst dst,src dst,src r,dst cc,dst dst cc,dst Bit test and jump relative on false Bit test and jump relative on true Call procedure Compare, increment and jump on equal Compare, increment and jump on non-equal Decrement register and jump on non-zero Enter Exit Interrupt return Jump on condition code Jump unconditional Jump relative on condition code Next Return Wait for interrupt Bit Manipulation Instructions BAND BCP BITC BITR BITS BOR BXOR TCM TM 6­4 dst,src dst,src dst dst dst dst,src dst,src dst,src dst,src Bit AND Bit compare Bit complement Bit reset Bit set Bit OR Bit XOR Test complement under mask Test under mask S3C8444 S3C8444 SAM8 INSTRUCTION SET Table 6­1. Instruction Group Summary (Concluded) Mnemonic Operands Instruction Rotate and Shift Instructions RL RLC RR RRC SRA SWAP dst dst dst dst dst dst Rotate left Rotate left through carry Rotate right Rotate right through carry Shift right arithmetic Swap nibbles CPU Control Instructions CCF DI EI IDLE NOP RCF SB0 SB1 SCF SRP SRP0 SRP1 STOP src src src Complement carry flag Disable interrupts Enable interrupts Enter Idle mode No operation Reset carry flag Set bank 0 Set bank 1 Set carry flag Set register pointers Set register pointer 0 Set register pointer 1 Enter Stop mode 6­5 SAM8 INSTRUCTION SET S3C8444 S3C8444 FLAGS REGISTER (FLAGS) The flags register FLAGS contains eight bits that describe the current status of CPU operations. Four of these bits, FLAGS.4 ­ FLAGS.7, can be tested and used with conditional jump instructions; two others FLAGS.2 and FLAGS.3 are used for BCD arithmetic. The FLAGS register also contains a bit to indicate the status of fast interrupt processing (FLAGS.1) and a bank address status bit (FLAGS.0) to indicate whether bank 0 or bank 1 is being addressed. FLAGS is located in the system control register area of set 1 (D5H). FLAGS register can be set or reset by instructions as long as its outcome does not affect the flags, such as, Load instruction. Logical and Arithmetic instructions such as, AND, OR, XOR, ADD, and SUB can affect the Flags register. For example, the AND instruction updates the Zero, Sign and Overflow flags based on the outcome of the AND instruction. If the AND instruction uses the Flags register as the destination, then simultaneously, two write will occur to the Flags register producing an unpredictable result. SYSTEM FLAGS REGISTER (FLAGS) D5H, Set 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 Carry flag (C) Bank address status flag (BA) Zero flag (Z) Fast interrupt status flag (FIS) Sign flag (S) Overflow flag (V) Half-carry flag (H) Decimal adjust flag (D) Figure 6­1. System Flags Register (FLAGS) 6­6 LSB S3C8444 S3C8444 SAM8 INSTRUCTION SET FLAG DESCRIPTIONS Bank Address Flag (FLAGS.0, BA) The BA flag indicates which register bank is in the set 1 area of the internal register file is currently selected, bank 0 or bank 1. The BA flag is cleared to "0" (select bank 0) when you execute the SB0 instruction and is set to "1" (select bank 1) when you execute the SB1 instruction. Fast Interrupt Status Flag (FLAGS.1, FIS) The FIS bit is set during a fast interrupt cycle and reset during the IRET following interrupt servicing. When set, it inhibits all interrupts and causes the fast interrupt return to be executed when the IRET instruction is executed. Half-Carry Flag (FLAGS.2, H) The H bit is set to "1" whenever an addition generates a carry-out of bit 3, or when a subtraction borrows out of bit 4. It is used by the Decimal Adjust (DA) instruction to convert the binary result of a previous addition or subtraction into the correct decimal (BCD) result. The H flag is seldom accessed directly by a program. Decimal Adjust Flag (FLAGS.3, D) The DA bit is used to specify what type of instruction was executed last during BCD operations, so that a subsequent decimal adjust operation can execute correctly. The DA bit is not usually accessed by programmers, and cannot be used as a test condition. Overflow Flag (FLAGS.4, V) The V flag is set to "1" when the result of a two's-complement operation is greater than + 127 or less than ­ 128. It is also cleared to "0" following logic operations. Sign Flag (FLAGS.5, S) Following arithmetic, logic, rotate, or shift operations, the sign bit identifies the state of the MSB of the result. A logic zero indicates a positive number and a logic one indicates a negative number. Zero Flag (FLAGS.6, Z) For arithmetic and logic operations, the Z flag is set to "1" if the result of the operation is zero. For operations that test register bits, and for shift and rotate operations, the Z flag is set to "1" if the result is logic zero. Carry Flag (FLAGS.7, C) The C flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to the bit 7 position (MSB). After rotate and shift operations, it contains the last value shifted out of the specified register. Program instructions can set, clear, or complement the carry flag. 6­7 SAM8 INSTRUCTION SET S3C8444 S3C8444 INSTRUCTION SET NOTATION Table 6­2. Flag Notation Conventions Flag Description C Carry flag Z Zero flag S Sign flag V Overflow flag D Decimal-adjust flag H Half-carry flag 0 Cleared to logic zero 1 Set to logic one * Set or cleared according to operation ­ Value is unaffected x Value is undefined Table 6­3. Instruction Set Symbols Symbol Description dst Destination operand src Source operand @ Indirect register address prefix PC Program counter IP Instruction pointer FLAGS RP Flags register (D5H) Register pointer # Immediate operand or register address prefix H Hexadecimal number suffix D Decimal number suffix B Binary number suffix opc 6­8 Opcode S3C8444 S3C8444 SAM8 INSTRUCTION SET Table 6­4. Instruction Notation Conventions Notation Description Actual Operand Range cc Condition code See list of condition codes in Table 6­6. r Working register only Rn (n = 0­15) rb Bit (b) of working register Rn.b (n = 0­15, b = 0­7) r0 Bit 0 (LSB) of working register Rn (n = 0­15) rr Working register pair RRp (p = 0, 2, 4, ., 14) R Register or working register reg or Rn (reg = 0­255, n = 0­15) Rb Bit 'b' of register or working register reg.b (reg = 0­255, b = 0­7) RR Register pair or working register pair reg or RRp (reg = 0­254, even number only, where p = 0, 2, ., 14) IA Indirect addressing mode addr (addr = 0­254, even number only) Ir Indirect working register only @Rn (n = 0­15) IR Indirect register or indirect working register @Rn or @reg (reg = 0­255, n = 0­15) Irr Indirect working register pair only @RRp (p = 0, 2, ., 14) IRR Indirect register pair or indirect working register pair @RRp or @reg (reg = 0­254, even only, where p = 0, 2, ., 14) X Indexed addressing mode #reg[Rn] (reg = 0­255, n = 0­15) XS Indexed (short offset) addressing mode #addr[RRp] (addr = range ­128 to +127, where p = 0, 2, ., 14) XL Indexed (long offset) addressing mode #addr [RRp] (addr = range 0­65535, where p = 0, 2, ., 14) DA Direct addressing mode addr (addr = range 0­65535) RA Relative addressing mode addr (addr = number in the range +127 to ­128 that is an offset relative to the address of the next instruction) IM Immediate addressing mode #data (data = 0­255) IML Immediate (long) addressing mode #data (data = range 0­65535) 6­9 SAM8 INSTRUCTION SET S3C8444 S3C8444 Table 6­5. Opcode Quick Reference OPCODE MAP LOWER NIBBLE (HEX) - 0 1 2 3 4 5 6 7 U 0 DEC R1 DEC IR1 ADD r1,r2 ADD r1,Ir2 ADD R2,R1 ADD IR2,R1 ADD R1,IM BOR r0­Rb P 1 RLC R1 RLC IR1 ADC r1,r2 ADC r1,Ir2 ADC R2,R1 ADC IR2,R1 ADC R1,IM BCP r1.b, R2 P 2 INC R1 INC IR1 SUB r1,r2 SUB r1,Ir2 SUB R2,R1 SUB IR2,R1 SUB R1,IM BXOR r0­Rb E 3 JP IRR1 SRP/0/1 IM SBC r1,r2 SBC r1,Ir2 SBC R2,R1 SBC IR2,R1 SBC R1,IM BTJR r2.b, RA R 4 DA R1 DA IR1 OR r1,r2 OR r1,Ir2 OR R2,R1 OR IR2,R1 OR R1,IM LDB r0­Rb 5 POP R1 POP IR1 AND r1,r2 AND r1,Ir2 AND R2,R1 AND IR2,R1 AND R1,IM BITC r1.b N 6 COM R1 COM IR1 TCM r1,r2 TCM r1,Ir2 TCM R2,R1 TCM IR2,R1 TCM R1,IM BAND r0­Rb I 7 PUSH R2 PUSH IR2 TM r1,r2 TM r1,Ir2 TM R2,R1 TM IR2,R1 TM R1,IM BIT r1.b B 8 DECW RR1 DECW IR1 PUSHUD IR1,R2 PUSHUI IR1,R2 MULT R2,RR1 MULT IR2,RR1 MULT IM,RR1 LD r1, x, r2 B 9 RL R1 RL IR1 POPUD IR2,R1 POPUI IR2,R1 DIV R2,RR1 DIV IR2,RR1 DIV IM,RR1 LD r2, x, r1 L A INCW RR1 INCW IR1 CP r1,r2 CP r1,Ir2 CP R2,R1 CP IR2,R1 CP R1,IM LDC r1, Irr2, xL E B CLR R1 CLR IR1 XOR r1,r2 XOR r1,Ir2 XOR R2,R1 XOR IR2,R1 XOR R1,IM LDC r2, Irr2, xL C RRC R1 RRC IR1 CPIJE Ir,r2,RA LDC r1,Irr2 LDW RR2,RR1 LDW IR2,RR1 LDW RR1,IML LD r1, Ir2 H D SRA R1 SRA IR1 CPIJNE Irr,r2,RA LDC r2,Irr1 CALL IA1 LD IR1,IM LD Ir1, r2 E E RR R1 RR IR1 LDCD r1,Irr2 LDCI r1,Irr2 LD R2,R1 LD R2,IR1 LD R1,IM LDC r1, Irr2, xs X F SWAP R1 SWAP IR1 LDCPD r2,Irr1 LDCPI r2,Irr1 CALL IRR1 LD IR2,R1 CALL DA1 LDC r2, Irr1, xs 6­10 S3C8444 S3C8444 SAM8 INSTRUCTION SET Table 6­5. Opcode Quick Reference (Continued) OPCODE MAP LOWER NIBBLE (HEX) - 8 9 A B C D E F U 0 LD r1,R2 LD r2,R1 DJNZ r1,RA JR cc,RA LD r1,IM JP cc,DA INC r1 NEXT P 1 ENTER P 2 EXIT E 3 WFI R 4 SB0 5 SB1 N 6 IDLE I 7 B 8 DI B 9 EI L A RET E B IRET C RCF H D E F E X STOP SCF CCF LD r1,R2 LD r2,R1 DJNZ r1,RA JR cc,RA LD r1,IM JP cc,DA INC r1 NOP 6­11 SAM8 INSTRUCTION SET S3C8444 S3C8444 CONDITION CODES The opcode of a conditional jump always contains a 4-bit field called the condition code (cc). This specifies under which conditions it is to execute the jump. For example, a conditional jump with the condition code for "equal" after a compare operation only jumps if the two operands are equal. Condition codes are listed in Table 6­6. The carry (C), zero (Z), sign (S), and overflow (V) flags are used to control the operation of conditional jump instructions. Table 6­6. Condition Codes Binary Mnemonic Description Flags Set 0000 F Always false ­ 1000 T Always true ­ 0111 * C Carry C=1 1111 * NC No carry C=0 0110 * Z Zero Z=1 1110 * NZ Not zero Z=0 1101 PL Plus S=0 0101 MI Minus S=1 0100 OV Overflow V=1 1100 NOV No overflow V=0 0110 * EQ Equal Z=1 1110 * NE Not equal Z=0 1001 GE Greater than or equal (S XOR V) = 0 0001 LT Less than (S XOR V) = 1 1010 GT Greater than (Z OR (S XOR V) = 0 0010 LE Less than or equal (Z OR (S XOR V) = 1 1111 * UGE Unsigned greater than or equal C=0 0111 * ULT Unsigned less than C=1 1011 UGT Unsigned greater than (C = 0 AND Z = 0) = 1 0011 ULE Unsigned less than or equal (C OR Z) = 1 NOTES: 1. Asterisks (*) indicate condition codes that are related to two different mnemonics but which test the same flag. For example, Z and EQ are both true if the zero flag (Z) is set, but after an ADD instruction, Z would probably be used; after a CP instruction, however, EQ would probably be used. 2. For operations involving unsigned numbers, the special condition codes UGE, ULT, UGT, and ULE must be used. 6­12 S3C8444 S3C8444 SAM8 INSTRUCTION SET INSTRUCTION DESCRIPTIONS This section contains detailed information and programming examples for each instruction in the SAM8 instruction set. Information is arranged in a consistent format for improved readability and for fast referencing. The following information is included in each instruction description: - Instruction name (mnemonic) - Full instruction name - Source/destination format of the instruction operand - Shorthand notation of the instruction's operation - Textual description of the instruction's effect - Specific flag settings affected by the instruction - Detailed description of the instruction's format, execution time, and addressing mode(s) - Programming example(s) explaining how to use the instruction 6­13 SAM8 INSTRUCTION SET S3C8444 S3C8444 ADC - Add With Carry ADC dst,src Operation: dst dst + src + c The source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Twoscomplement addition is performed. In multiple precision arithmetic, this instruction permits the carry from the addition of low-order operands to be carried into the addition of high-order operands. Flags: C: Z: S: V: Set if there is a carry from the most significant bit of the result; cleared otherwise. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurs, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise. D: Always cleared to "0". H: Set if there is a carry from the most significant bit of the low-order four bits of the result; cleared otherwise. Format: Bytes 2 dst | src Opcode (Hex) 6 12 r r 13 Opcode Cycles Addr Mode dst src r lr NOTE: In the second byte of the two-byte instruction format, the destination and source addresses are each four bits long. Opcode Examples: dst dst src 3 3 10 10 14 R R 15 Opcode src R IR 16 R IM Given: R1 = 10H, R2 = 03H, C flag = "1", register 01H = 20H, register 02H = 03H, and register 03H = 0AH: ADC ADC ADC ADC ADC R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#11H R1 = 14H, R2 = 03H R1 = 1BH, R2 = 03H Register 01H = 24H, register 02H = 03H Register 01H = 2BH, register 02H = 03H Register 01H = 32H In the first example, destination register R1 contains the value 10H, the carry flag is set to "1", and the source working register R2 contains the value 03H. The statement "ADC R1,R2" adds 03H and the carry flag value ("1") to the destination value 10H, leaving 14H in register R1. 6­14 S3C8444 S3C8444 SAM8 INSTRUCTION SET ADD - Add ADD dst,src Operation: dst dst + src The source operand is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Twos-complement addition is performed. Flags: C: Z: S: V: Set if there is a carry from the most significant bit of the result; cleared otherwise. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise. D: Always cleared to "0". H: Set if a carry from the low-order nibble occurred. Format: Bytes 2 dst | src Opcode (Hex) 6 02 r r 03 Opcode Cycles Addr Mode dst src r lr NOTE: In the second byte of the two-byte instruction format, the destination and source addresses are each four bits long. Opcode Examples: dst dst src 3 3 10 10 04 R R 05 Opcode src R IR 06 R IM Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH: ADD ADD ADD ADD ADD R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#25H R1 = 15H, R2 = 03H R1 = 1CH, R2 = 03H Register 01H = 24H, register 02H = 03H Register 01H = 2BH, register 02H = 03H Register 01H = 46H In the first example, destination working register R1 contains 12H and the source working register R2 contains 03H. The statement "ADD R1,R2" adds 03H to 12H, leaving the value 15H in register R1. 6­15 SAM8 INSTRUCTION SET S3C8444 S3C8444 AND - Logical And AND dst,src Operation: dst dst AND src The source operand is logically ANDed with the destination operand. The result is stored in the destination. The AND operation results in a "1" bit being stored whenever the corresponding bits in the two operands are both logic ones; otherwise a "0" bit value is stored. The contents of the source are unaffected. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Always cleared to "0". Unaffected. Unaffected. Format: Bytes 2 dst | src Opcode (Hex) 6 52 r r 53 Opcode Cycles Addr Mode dst src r lr NOTE: In the second byte of the two-byte instruction format, the destination and source addresses are each four bits long. Opcode Examples: dst dst src 3 3 10 10 54 R R 55 Opcode src R IR 56 R IM Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH: AND AND AND AND AND R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#25H R1 = 02H, R2 = 03H R1 = 02H, R2 = 03H Register 01H = 01H, register 02H = 03H Register 01H = 00H, register 02H = 03H Register 01H = 21H In the first example, destination working register R1 contains the value 12H and the source working register R2 contains 03H. The statement "AND R1,R2" logically ANDs the source operand value 03H with the destination operand value (12H), leaving the value 02H in register R1. 6­16 S3C8444 S3C8444 SAM8 INSTRUCTION SET BAND - Bit And BAND dst,src.b BAND dst.b,src Operation: dst(0) dst(0) AND src(b) or dst(b) dst(b) AND src(0) The specified bit of the source (or the destination) is logically ANDed with the zero bit (LSB) of the destination (or source). The resultant bit is stored in the specified bit of the destination. No other bits of the destination are affected. The source is unaffected. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Cleared to "0". Undefined. Unaffected. Unaffected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst src Opcode dst | b | 0 src 3 10 67 r0 Rb Opcode src | b | 1 dst 3 10 67 Rb r0 NOTE: In the second byte of the 3-byte instruction formats, the destination (or source) address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length. Examples: Given: R1 = 07H and register 01H = 05H: BAND BAND R1,01H.1 01H.1,R1 R1 = 06H, register 01H = 05H Register 01H = 05H, R1 = 07H In the first example, source register 01H contains the value 05H (00000101B 00000101B) and destination working register R1 contains 07H (00000111B 00000111B). The statement "BAND R1,01H.1" ANDs the bit 1 value of the source register ("0") with the bit 0 value of register R1 (destination), leaving the value 06H (00000110B 00000110B) in register R1. 6­17 SAM8 INSTRUCTION SET S3C8444 S3C8444 BCP - Bit Compare BCP dst,src.b Operation: dst(0) ­ src(b) The specified bit of the source is compared to (subtracted from) bit zero (LSB) of the destination. The zero flag is set if the bits are the same; otherwise it is cleared. The contents of both operands are unaffected by the comparison. Flags: C: Z: S: V: D: H: Unaffected. Set if the two bits are the same; cleared otherwise. Cleared to "0". Undefined. Unaffected. Unaffected. Format: Bytes Opcode dst | b | 0 Opcode (Hex) 3 src Cycles 10 17 Addr Mode dst src r0 Rb NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length. Example: Given: R1 = 07H and register 01H = 01H: BCP R1,01H.1 R1 = 07H, register 01H = 01H If destination working register R1 contains the value 07H (00000111B 00000111B) and the source register 01H contains the value 01H (00000001B 00000001B), the statement "BCP R1,01H.1" compares bit one of the source register (01H) and bit zero of the destination register (R1). Because the bit values are not identical, the zero flag bit (Z) is cleared in the FLAGS register (0D5H). 6­18 S3C8444 S3C8444 SAM8 INSTRUCTION SET BITC - Bit Complement BITC dst.b Operation: dst(b) NOT dst(b) This instruction complements the specified bit within the destination without affecting any other bits in the destination. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Cleared to "0". Undefined. Unaffected. Unaffected. Format: Bytes Opcode Opcode (Hex) Addr Mode dst 2 dst | b | 0 Cycles 8 57 rb NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length. Example: Given: R1 = 07H BITC R1.1 R1 = 05H If working register R1 contains the value 07H (00000111B 00000111B), the statement "BITC R1.1" complements bit one of the destination and leaves the value 05H (00000101B 00000101B) in register R1. Because the result of the complement is not "0", the zero flag (Z) in the FLAGS register (0D5H) is cleared. 6­19 SAM8 INSTRUCTION SET S3C8444 S3C8444 BITR - Bit Reset BITR dst.b Operation: dst(b) 0 The BITR instruction clears the specified bit within the destination without affecting any other bits in the destination. Flags: No flags are affected. Format: Bytes Opcode Opcode (Hex) Addr Mode dst 2 dst | b | 0 Cycles 8 77 rb NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length. Example: Given: R1 = 07H: BITR R1.1 R1 = 05H If the value of working register R1 is 07H (00000111B 00000111B), the statement "BITR R1.1" clears bit one of the destination register R1, leaving the value 05H (00000101B 00000101B). 6­20 S3C8444 S3C8444 SAM8 INSTRUCTION SET BITS - Bit Set BITS dst.b Operation: dst(b) 1 The BITS instruction sets the specified bit within the destination without affecting any other bits in the destination. Flags: No flags are affected. Format: Bytes Opcode Opcode (Hex) Addr Mode dst 2 dst | b | 1 Cycles 8 77 rb NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length. Example: Given: R1 = 07H: BITS R1.3 R1 = 0FH If working register R1 contains the value 07H (00000111B 00000111B), the statement "BITS R1.3" sets bit three of the destination register R1 to "1", leaving the value 0FH (00001111B 00001111B). 6­21 SAM8 INSTRUCTION SET S3C8444 S3C8444 BOR - Bit OR BOR dst,src.b BOR dst.b,src Operation: dst(0) dst(0) OR src(b) or dst(b) dst(b) OR src(0) The specified bit of the source (or the destination) is logically ORed with bit zero (LSB) of the destination (or the source). The resultant bit is stored in the specified bit of the destination. No other bits of the destination are affected. The source is unaffected. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Cleared to "0". Undefined. Unaffected. Unaffected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst src Opcode dst | b | 0 src 3 10 07 r0 Rb Opcode src | b | 1 dst 3 10 07 Rb r0 NOTE: In the second byte of the 3-byte instruction formats, the destination (or source) address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit. Examples: Given: R1 = 07H and register 01H = 03H: BOR BOR R1, 01H.1 01H.2, R1 R1 = 07H, register 01H = 03H Register 01H = 07H, R1 = 07H In the first example, destination working register R1 contains the value 07H (00000111B 00000111B) and source register 01H the value 03H (00000011B 00000011B). The statement "BOR R1,01H.1" logically ORs bit one of register 01H (source) with bit zero of R1 (destination). This leaves the same value (07H) in working register R1. In the second example, destination register 01H contains the value 03H (00000011B 00000011B) and the source working register R1 the value 07H (00000111B 00000111B). The statement "BOR 01H.2,R1" logically ORs bit two of register 01H (destination) with bit zero of R1 (source). This leaves the value 07H in register 01H. 6­22 S3C8444 S3C8444 SAM8 INSTRUCTION SET BTJRF - Bit Test, Jump Relative on False BTJRF dst,src.b Operation: If src(b) is a "0", then PC PC + dst The specified bit within the source operand is tested. If it is a "0", the relative address is added to the program counter and control passes to the statement whose address is now in the PC; otherwise, the instruction following the BTJRF instruction is executed. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) 3 16/18 (2) 37 (1) Opcode src | b | 0 dst Addr Mode dst src RA rb NOTES: 1. In the second byte of the instruction format, the source address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length. 2. Execution time takes 18 cycles if the jump is taken or 16 cycles if it is not taken. Example: Given: R1 = 07H: BTJRF SKIP,R1.3 PC jumps to SKIP location If working register R1 contains the value 07H (00000111B 00000111B), the statement "BTJRF SKIP,R1.3" tests bit 3. Because it is "0", the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP. (Remember that the memory location must be within the allowed range of + 127 to ­ 128.) 6­23 SAM8 INSTRUCTION SET S3C8444 S3C8444 BTJRT - Bit Test, Jump Relative on True BTJRT dst,src.b Operation: If src(b) is a "1", then PC PC + dst The specified bit within the source operand is tested. If it is a "1", the relative address is added to the program counter and control passes to the statement whose address is now in the PC; otherwise, the instruction following the BTJRT instruction is executed. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) 3 16/18 (2) 37 (1) Opcode src | b | 1 dst Addr Mode dst src RA rb NOTES: 1. In the second byte of the instruction format, the source address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length. 2. Execution time takes 18 cycles if the jump is taken or 16 cycles if it is not taken. Example: Given: R1 = 07H: BTJRT SKIP,R1.1 If working register R1 contains the value 07H (00000111B 00000111B), the statement "BTJRT SKIP,R1.1" tests bit one in the source register (R1). Because it is a "1", the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP. (Remember that the memory location must be within the allowed range of + 127 to ­ 128.) 6­24 S3C8444 S3C8444 SAM8 INSTRUCTION SET BXOR - Bit XOR BXOR dst,src.b BXOR dst.b,src Operation: dst(0) dst(0) XOR src(b) or dst(b) dst(b) XOR src(0) The specified bit of the source (or the destination) is logically exclusive-ORed with bit zero (LSB) of the destination (or source). The result bit is stored in the specified bit of the destination. No other bits of the destination are affected. The source is unaffected. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Cleared to "0". Undefined. Unaffected. Unaffected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst src Opcode dst | b | 0 src 3 10 27 r0 Rb Opcode src | b | 1 dst 3 10 27 Rb r0 NOTE: In the second byte of the 3-byte instruction formats, the destination (or source) address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length. Examples: Given: R1 = 07H (00000111B 00000111B) and register 01H = 03H (00000011B 00000011B): BXOR BXOR R1,01H.1 01H.2,R1 R1 = 06H, register 01H = 03H Register 01H = 07H, R1 = 07H In the first example, destination working register R1 has the value 07H (00000111B 00000111B) and source register 01H has the value 03H (00000011B 00000011B). The statement "BXOR R1,01H.1" exclusive-ORs bit one of register 01H (source) with bit zero of R1 (destination). The result bit value is stored in bit zero of R1, changing its value from 07H to 06H. The value of source register 01H is unaffected. 6­25 SAM8 INSTRUCTION SET S3C8444 S3C8444 CALL - Call Procedure CALL dst Operation: SP @SP SP @SP PC SP ­ 1 PCL SP ­1 PCH dst The current contents of the program counter are pushed onto the top of the stack. The program counter value used is the address of the first instruction following the CALL instruction. The specified destination address is then loaded into the program counter and points to the first instruction of a procedure. At the end of the procedure the return instruction (RET) can be used to return to the original program flow. RET pops the top of the stack back into the program counter. Flags: No flags are affected. Format: Bytes Opcode 3 dst Cycles 18 Opcode (Hex) F6 Addr Mode dst DA Opcode 2 18 F4 IRR Opcode Examples: dst dst 2 20 D4 IA Given: R0 = 35H, R1 = 21H, PC = 1A47H 1A47H, and SP = 0002H 0002H: CALL 3521H 3521H CALL @RR0 CALL #40H SP = 0000H 0000H (Memory locations 0000H 0000H = 1AH, 0001H 0001H = 4AH, where 4AH is the address that follows the instruction.) SP = 0000H 0000H (Memory locations 0000H 0000H = 1AH, 0001H 0001H = 49H) SP = 0000H 0000H (Memory locations 0000H 0000H = 1AH, 0001H 0001H = 49H) In the first example, if the program counter value is 1A47H 1A47H and the stack pointer contains the value 0002H 0002H, the statement "CALL 3521H 3521H" pushes the current PC value onto the top of the stack. The stack pointer now points to memory location 0000H 0000H. The PC is then loaded with the value 3521H 3521H, the address of the first instruction in the program sequence to be executed. If the contents of the program counter and stack pointer are the same as in the first example, the statement "CALL @RR0" produces the same result except that the 49H is stored in stack location 0001H 0001H (since the two-byte instruction format was used). The PC is then loaded with the value 3521H 3521H, the address of the first instruction in the program sequence to be executed. Assuming that the contents of the program counter and stack pointer are the same as in the first example, if program address 0040H 0040H contains 35H and program address 0041H 0041H contains 21H, the statement "CALL #40H" produces the same result as in the second example. 6­26 S3C8444 S3C8444 SAM8 INSTRUCTION SET CCF - Complement Carry Flag CCF Operation: C NOT C The carry flag (C) is complemented. If C = "1", it is changed to C = "0"; if C = "0", it is changed to C = "1". Flags: C: Complemented. No other flags are affected. Format: Bytes Opcode Example: Cycles Opcode (Hex) 1 6 EF Given: The carry flag = "0": CCF If the carry flag = "0", the CCF instruction complements it in the FLAGS register (0D5H), changing its value from logic zero to logic one. 6­27 SAM8 INSTRUCTION SET S3C8444 S3C8444 CLR - Clear CLR dst Operation: dst "0" The destination location is cleared to "0". Flags: No flags are affected. Format: Bytes Examples: Addr Mode dst 2 dst Opcode (Hex) 6 B0 R B1 Opcode Cycles IR Given: Register 00H = 4FH, register 01H = 02H, and register 02H = 5EH: CLR CLR 00H @01H Register 00H = 00H Register 01H = 02H, register 02H = 00H In Register (R) addressing mode, the statement "CLR 00H" clears the destination register 00H value to 00H. In the second example, the statement "CLR @01H" uses Indirect Register (IR) addressing mode to clear the 02H register value to 00H. 6­28 S3C8444 S3C8444 SAM8 INSTRUCTION SET COM - Complement COM dst Operation: dst NOT dst The contents of the destination location are complemented (ones complement); all "1" bits are changed to "0", and vice-versa. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Always reset to "0". Unaffected. Unaffected. Format: Bytes Examples: Addr Mode dst 2 dst Opcode (Hex) 6 60 R 61 Opcode Cycles IR Given: R1 = 07H and register 07H = 0F1H: COM COM R1 @R1 R1 = 0F8H R1 = 07H, register 07H = 0EH In the first example, destination working register R1 contains the value 07H (00000111B 00000111B). The statement "COM R1" complements all the bits in R1: all "1s" are changed to "0s", and viceversa, leaving the value 0F8H (11111000B 11111000B). In the second example, Indirect Register (IR) addressing mode is used to complement the value of destination register 07H (11110001B 11110001B), leaving the new value 0EH (00001110B 00001110B). 6­29 SAM8 INSTRUCTION SET S3C8444 S3C8444 CP - Compare CP dst,src Operation: dst ­ src The source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. The contents of both operands are unaffected by the comparison. Flags: C: Z: S: V: D: H: Set if a "borrow" occurred (src > dst); cleared otherwise. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred; cleared otherwise. Unaffected. Unaffected. Format: Bytes Opcode 2 dst | src Cycles 6 Opcode (Hex) A2 A3 Addr Mode dst src r r r lr NOTE: In the second byte of the two-byte instruction format, the destination and source addresses are each four bits long. Opcode dst 3 10 A4 A5 R R R IR Opcode Examples: src dst src 3 10 A6 R IM 1. Given: R1 = 02H and R2 = 03H: CP R1,R2 Set the C and S flags Destination working register R1 contains the value 02H and source register R2 contains the value 03H. The statement "CP R1,R2" subtracts the R2 value (source/subtrahend) from the R1 value (destination/minuend). Because a "borrow" occurs and the difference is negative, C and S = "1". 2. Given: R1 = 05H and R2 = 0AH: SKIP CP JP INC LD R1, R2 UGE,SKIP R1 R3,R1 In this example, destination working register R1 contains the value 05H which is less than the contents of the source working register R2 (0AH). The statement "CP R1,R2" generates C = "1" and the JP instruction does not jump to the SKIP location. After the statement "LD R3,R1" executes, the value 06H is left in working register R3. 6­30 S3C8444 S3C8444 SAM8 INSTRUCTION SET CPIJE - Compare, Increment, And Jump on Equal CPIJE dst,src,RA Operation: If dst ­ src = "0", PC PC + RA Ir Ir + 1 The source operand is compared to (subtracted from) the destination operand. If the result is "0", the relative address is added to the program counter and control passes to the statement whose address is now in the program counter; otherwise the instruction following the CPIJE instruction is executed. In either case the source pointer is incremented by one before the next instruction. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) 3 16/18 (2) C2 (1) Opcode src dst RA Addr Mode dst src r Ir NOTES: 1. In the second byte of the instruction format, the source and destination addresses are each four bits. 2. Execution time takes 18 cycles if the jump is taken or 16 cycles if it is not taken. Example: Given: R1 = 02H, R2 = 03H, and register 03H = 02H: CPIJE R1,@R2,SKIP R2 = 04H, PC jumps to SKIP location In this example, working register R1 contains the value 02H, working register R2 the value 03H, and register 03 contains 02H. The statement "CPIJE R1,@R2,SKIP" compares the @R2 value 02H (00000010B 00000010B) to 02H (00000010B 00000010B). Because the result of the comparison is equal, the relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP. The source register (R2) is incremented by one, leaving a value of 04H. (Remember that the memory location must be within the allowed range of + 127 to ­ 128.) 6­31 SAM8 INSTRUCTION SET S3C8444 S3C8444 CPIJNE - Compare, Increment, And Jump on Non-Equal CPIJNE dst,src,RA Operation: If dst ­ src _ "0", PC PC + RA Ir Ir + 1 The source operand is compared to (subtracted from) the destination operand. If the result is not "0", the relative address is added to the program counter and control passes to the statement whose address is now in the program counter; otherwise the instruction following the CPIJNE instruction is executed. In either case the source pointer is incremented by one before the next instruction. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) 3 16/18 (2) D2 (1) Opcode src dst RA Addr Mode dst src r Ir NOTES: 1. In the second byte of the instruction format, the source and destination addresses are each four bits. 2. Execution time takes 18 cycles if the jump is taken or 16 cycles if it is not taken. Example: Given: R1 = 02H, R2 = 03H, and register 03H = 04H: CPIJNE R1,@R2,SKIP R2 = 04H, PC jumps to SKIP location Working register R1 contains the value 02H, working register R2 (the source pointer) the value 03H, and general register 03 the value 04H. The statement "CPIJNE R1,@R2,SKIP" subtracts 04H (00000100B 00000100B) from 02H (00000010B 00000010B). Because the result of the comparison is non-equal, the relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP. The source pointer register (R2) is also incremented by one, leaving a value of 04H. (Remember that the memory location must be within the allowed range of + 127 to ­ 128.) 6­32 S3C8444 S3C8444 SAM8 INSTRUCTION SET DA - Decimal Adjust DA dst Operation: dst DA dst The destination operand is adjusted to form two 4-bit BCD digits following an addition or subtraction operation. For addition (ADD, ADC) or subtraction (SUB, SBC), the following table indicates the operation performed. (The operation is undefined if the destination operand was not the result of a valid addition or subtraction of BCD digits): Instruction Carry Before DA Flags: C: Z: S: V: D: H: Bits 0­3 Value (Hex) Number Added to Byte Carry After DA 0­9 0­8 0­9 A­F 9­F A­F 0­2 0­2 0­3 0 0 1 0 0 1 0 0 1 0­9 A­F 0­3 0­9 A­F 0­3 0­9 A­F 0­3 00 06 06 60 66 66 60 66 66 0 0 0 1 1 1 1 1 1 0 0 1 1 SUB SBC H Flag Before DA 0 0 0 0 0 0 1 1 1 ADD ADC Bits 4­7 Value (Hex) 0­9 0­8 7­F 6­F 0 1 0 1 0­9 6­F 0­9 6­F = = = = 0 0 1 1 00 FA A0 9A ­ 00 ­ 06 ­ 60 ­ 66 Set if there was a carry from the most significant bit; cleared otherwise (see table). Set if result is "0"; cleared otherwise. Set if result bit 7 is set; cleared otherwise. Undefined. Unaffected. Unaffected. Format: Bytes Opcode dst Cycles Opcode (Hex) Addr Mode dst 2 6 40 R 41 IR 6­33 SAM8 INSTRUCTION SET S3C8444 S3C8444 DA - Decimal Adjust DA (Continued) Example: Given: Working register R0 contains the value 15 (BCD), working register R1 contains 27 (BCD), and address 27H contains 46 (BCD): ADD DA R1,R0 R1 C "0", H "0", Bits 4­7 = 3, bits 0­3 = C, R1 3CH R1 3CH + 06 ; ; If addition is performed using the BCD values 15 and 27, the result should be 42. The sum is incorrect, however, when the binary representations are added in the destination location using standard binary arithmetic: 0001 + 0010 0011 0101 0111 1100 = 15 27 3CH The DA instruction adjusts this result so that the correct BCD representation is obtained: 0011 + 0000 0100 1100 0110 0010 = 42 Assuming the same values given above, the statements SUB DA 27H,R0 @R1 ; ; C "0", H "0", Bits 4­7 = 3, bits 0­3 = 1 @R1 31­0 leave the value 31 (BCD) in address 27H (@R1). 6­34 S3C8444 S3C8444 SAM8 INSTRUCTION SET DEC - Decrement DEC dst Operation: dst dst ­ 1 The contents of the destination operand are decremented by one. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Set if result is negative; cleared otherwise. Set if arithmetic overflow occurred, that is, dst value is #80H (-128); cleared otherwise. Unaffected. Unaffected. Format: Bytes Examples: Addr Mode dst 2 dst Opcode (Hex) 6 00 R 01 Opcode Cycles IR Given: R1 = 03H and register 03H = 10H: DEC DEC R1 @R1 R1 = 02H Register 03H = 0FH In the first example, if working register R1 contains the value 03H, the statement "DEC R1" decrements the hexadecimal value by one, leaving the value 02H. In the second example, the statement "DEC @R1" decrements the value 10H contained in the destination register 03H by one, leaving the value 0FH. 6­35 SAM8 INSTRUCTION SET S3C8444 S3C8444 DECW - Decrement Word DECW dst Operation: dst dst ­ 1 The contents of the destination location (which must be an even address) and the operand following that location are treated as a single 16-bit value which is decremented by one. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred, that is, dst value is #8000H 8000H (-32768); cleared otherwise. Unaffected. Unaffected. Format: Bytes Examples: Addr Mode dst 2 dst Opcode (Hex) 10 80 RR 81 Opcode Cycles IR Given: R0 = 12H, R1 = 34H, R2 = 30H, register 30H = 0FH, and register 31H = 21H: DECW DECW RR0 @R2 R0 = 12H, R1 = 33H Register 30H = 0FH, register 31H = 20H In the first example, destination register R0 contains the value 12H and register R1 the value 34H. The statement "DECW RR0" addresses R0 and the following operand R1 as a 16-bit word and decrements the value of R1 by one, leaving the value 33H. 6­36 S3C8444 S3C8444 SAM8 INSTRUCTION SET DI - Disable Interrupts DI Operation: SYM (0) 0 Bit zero of the system mode control register SYM (0DEH) is cleared to "0", disabling all interrupt processing. Interrupt requests can still set their respective interrupt pending bits, but the CPU will not directly service them. Flags: No flags are affected. Format: Bytes Opcode Example: Cycles Opcode (Hex) 1 6 8F Given: SYM (0DEH) = 01H: DI If the value of the SYM register is 01H, the statement "DI" leaves the new value 00H in the register, clearing bit zero (LSB) and disabling all interrupts. 6­37 SAM8 INSTRUCTION SET S3C8444 S3C8444 DIV - Divide (Unsigned) DIV dst,src Operation: dst ÷ src dst (UPPER) REMAINDER dst (LOWER) QUOTIENT The destination operand (16 bits) is divided by the source operand (8 bits). The quotient (8 bits) is stored in the lower half of the destination. The remainder (8 bits) is stored in the upper half of the destination. When the quotient is 28, the numbers stored in the upper and lower halves of the destination for quotient and remainder are incorrect. Both operands are treated as unsigned integers. Flags: C: Z: S: V: D: H: Set if the V flag is set and quotient is between 28 and 29 ­1; cleared otherwise. Set if divisor or quotient = "0"; cleared otherwise. Set if MSB of quotient = "1"; cleared otherwise. Set if quotient is 28 or if divisor = "0"; cleared otherwise. Unaffected. Unaffected. Format: Bytes 3 dst * Example: 28/12* 94 RR R 95 RR IR 28/12* src Opcode (Hex) 28/12* Opcode Cycles Addr Mode dst src 96 RR IM Execution takes 12 cycles if the divide-by-zero is attempted; otherwise 28 cycles. Given: R0 = 10H, R1 = 03H, R2 = 40H, register 40H = 80H: DIV DIV DIV RR0,R2 RR0,@R2 RR0,#20H R0 = 03H, R1 = 40H R0 = 03H, R1 = 20H R0 = 03H, R1 = 80H In the first example, destination working register pair RR0 contains the values 10H (R0) and 03H (R1), and register R2 contains the value 40H. The statement "DIV RR0,R2" divides the 16-bit RR0 value by the 8-bit value of the R2 (source) register. After the DIV instruction, R0 contains the value 03H and R1 contains 40H. The 8-bit remainder is stored in the upper half of the destination register RR0 (R0) and the quotient in the lower half (R1). 6­38 S3C8444 S3C8444 SAM8 INSTRUCTION SET DJNZ - Decrement and Jump if Non-Zero DJNZ r,dst Operation: r r ­ 1 If r _ 0, PC PC + dst The working register being used as a counter is decremented. If the contents of the register are not logic zero after decrementing, the relative address is added to the program counter and control passes to the statement whose address is now in the PC. The range of the relative address is +127 to ­128, and the original value of the PC is taken to be the address of the instruction byte following the DJNZ statement. Flags: No flags are affected. Format: Bytes r| Opcode dst 2 Cycles 12 (jump taken) 10 (no jump) Opcode (Hex) Addr Mode dst rA RA r = 0 to F NOTE: In the first byte of the two-byte instruction format, the working register address 'r' is 4 bits and the opcode is 4 bits in length. Example: Given: R1 = 02H and LOOP is the label of a relative address: DJNZ R1,LOOP DJNZ is typically used to control a "loop" of instructions. In many cases, a label is used as the destination operand instead of a numeric relative address value. In the example, working register R1 contains the value 02H, and LOOP is the label for a relative address. The statement "DJNZ R1, LOOP" decrements register R1 by one, leaving the value 01H. Because the contents of R1 after the decrement are non-zero, the jump is taken to the relative address specified by the LOOP label. The working register being used as a counter must usually be a register in page 0, locations 00H­CFH only. (If another page were to be used, the counter would enter an infinite loop.) For I/O port applications, related peripheral control registers will have undefined results. 6­39 SAM8 INSTRUCTION SET S3C8444 S3C8444 EI - Enable Interrupts EI Operation: SYM (0) 1 Bit zero (LSB) of the system mode register SYM (0DEH) is set to "1". This allows any interrupts to be serviced when they occur (assuming they have highest priority) or, if their respective interrupt pending bit was previously enabled by its interrupt, then its interrupt can also be serviced. Flags: No flags are affected. Format: Bytes Opcode Example: Cycles Opcode (Hex) 1 6 9F Given: SYM (0DEH) = 00H: EI If the SYM register at location 0DEH contains the value 00H, that is, if interrupts are currently disabled, the statement "EI" sets the SYM register to 01H, enabling all interrupts. (Bit zero of the SYM register is the enable bit for global interrupt processing.) 6­40 S3C8444 S3C8444 SAM8 INSTRUCTION SET ENTER - Enter ENTER SP SP ­ 2 @SP IP IP PC PC @IP IP Operation: IP + 2 This instruction is useful for the implementation of threaded-code languages. The contents of the instruction pointer are pushed onto the stack. The value in the program counter is then transferred to the instruction pointer. The program memory word pointed to by the instruction pointer is loaded into the program counter. The instruction pointer is then incremented by two. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) 1 20 1F Opcode Example: The diagram below shows one example of how an ENTER statement is used. The example diagrams for the ENTER, EXIT, and NEXT instructions illustrate how these instructions can be used together in a program. BEFORE ADDR IP PC AFTER ADDR DATA 0050 0040 SP 0022 22 DATA STACK IP ADDR 40 41 42 43 DATA ENTER ADDR H ADDR L ADDR H MEMORY 1F 01 10 PC DATA 0043 0110 SP 0020 20 IPH 00 21 IPL 50 22 DATA ADDR 40 41 42 43 DATA ENTER ADDR H ADDR L ADDR H 110 ROUTINE MEMORY STACK 6­41 SAM8 INSTRUCTION SET S3C8444 S3C8444 EXIT - Exit EXIT IP @SP SP SP + 2 PC @IP IP Operation: IP + 2 This instruction is useful for the implementation of threaded-code languages. The stack is popped and the instruction pointer is loaded. The program memory word pointed to by the instruction pointer is loaded into the program counter. The instruction pointer is then incremented by two. Flags: No flags are affected. Format: Bytes Example: Opcode (Hex) 1 Opcode Cycles 22 2F The diagram below shows one example of how an EXIT statement is used. Example diagrams for the ENTER, EXIT, and NEXT instructions illustrate how these instructions can be used together in a program. BEFORE ADDR AFTER DATA IP 0050 PC 0140 ADDR IP IPH 00 IPL 50 DATA STACK 6­42 0052 PC 0060 SP ADDR 0022 DATA 50 PCL OLD 51 PCH 60 00 SP 0020 20 21 22 DATA 140 EXIT ADDR 60 DATA MAIN 2F 22 DATA MEMORY MEMORY STACK S3C8444 S3C8444 SAM8 INSTRUCTION SET IDLE - Idle Operation IDLE Operation: The IDLE instruction halts the CPU clock while allowing the system clock to continue oscillation. Idle mode is released by an interrupt request (IRQ) or an external reset operation. Flags: No flags are affected. Format: Bytes Opcode Example: Cycles Opcode (Hex) 1 3 6F Addr Mode dst src ­ ­ The instruction IDLE stops the CPU clock while allowing system clock oscillation to continue. 6­43 SAM8 INSTRUCTION SET S3C8444 S3C8444 INC - Increment INC dst Operation: dst dst + 1 The contents of the destination operand are incremented by one. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred, that is, dst is #7FH (127); cleared otherwise. Unaffected. Unaffected. Format: Bytes Opcode (Hex) Addr Mode dst 1 dst | Opcode Cycles 6 rE r r = 0 to F NOTE: In the first byte of the one-byte instruction format, the destination (dst) address value is 4 bits and the opcode is 4 bits in length. Opcode 2 6 20 R 21 Examples: dst IR Given: R0 = 1BH, register 00H = 0CH, and register 1BH = 0FH: INC INC INC R0 00H @R0 R0 = 1CH Register 00H = 0DH R0 = 1BH, register 01H = 10H In the first example, if destination working register R0 contains the value 1BH, the statement "INC R0" leaves the value 1CH in that same register. The next example shows the effect of an INC instruction on register 00H if it contains the value 0CH. In the third example, INC is used in Indirect Register (IR) addressing mode to increment the value of register 1BH from 0FH to 10H. 6­44 S3C8444 S3C8444 SAM8 INSTRUCTION SET INCW - Increment Word INCW dst Operation: dst dst + 1 The contents of the destination (which must be an even address) and the byte following that location are treated as a single 16-bit value which is incremented by one. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred, that is, dst is #7FFFH (32768); cleared otherwise. Unaffected. Unaffected. Format: Bytes Examples: Addr Mode dst 2 dst Opcode (Hex) 10 A0 RR A1 Opcode Cycles IR Given: R0 = 1AH, R1 = 02H, register 02H = 0FH, and register 03H = 0FFH: INCW INCW RR0 @R1 R0 = 1AH, R1 = 03H Register 02H = 10H, register 03H = 00H In the first example, the working register pair RR0 contains the value 1AH in register R0 and 02H in register R1. The statement "INCW RR0" increments the 16-bit destination by one, leaving the value 03H in register R1. In the second example, the statement "INCW @R1" uses Indirect Register (IR) addressing mode to increment the contents of general register 03H from 0FFH to 00H and register 02H from 0FH to 10H. 6­45 SAM8 INSTRUCTION SET S3C8444 S3C8444 IRET - Interrupt Return IRET IRET (Normal) IRET (Fast) Operation: FLAGS @SP PC IP SP SP + 1 FLAGS FLAGS' PC @SP FIS 0 SP SP + 2 SYM(0) 1 This instruction is used at the end of an interrupt service routine. It restores the flag register and the program counter. It also re-enables global interrupts. A "normal IRET" is executed only if the fast interrupt status bit (FIS, bit one of the FLAGS register, 0D5H) is cleared (= "0"). If a fast interrupt occurred, IRET clears the FIS bit that was set at the beginning of the service routine. Flags: All flags are restored to their original settings (that is, the settings before the interrupt occurred). Format: IRET (Normal) Cycles Opcode (Hex) Opcode 1 16 BF IRET (Fast) Bytes Cycles Opcode (Hex) Opcode Example: Bytes 1 6 BF In the figure below, the instruction pointer is initially loaded with 100H in the main program before interrupts are enabled. When an interrupt occurs, the program counter and instruction pointer are swapped. This causes the PC to jump to address 100H and the IP to keep the return address. The last instruction in the service routine normally is a jump to IRET at address FFH. This causes the instruction pointer to be loaded with 100H "again" and the program counter to jump back to the main program. Now, the next interrupt can occur and the IP is still correct at 100H. Note that in the fast interrupt example above, if the last instruction is not a jump to IRET, care must be taken with the order of the last two instructions. The instruction IRET cannot be immediately proceeded by a clearing of interrupt status (such as a reset of the interrupt pending register, IPR). 6­46 S3C8444 S3C8444 SAM8 INSTRUCTION SET JP - Jump JP cc,dst (Conditional) JP dst (Unconditional) Operation: If cc is true, PC dst The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code (cc) is true; otherwise, the instruction following the JP instruction is executed. (See list of condition codes.) The unconditional JP simply replaces the contents of the program counter with the contents of the specified register pair. Control then passes to the statement addresses by the program counter. Flags: No flags are affected. Format: (1) Bytes Cycles Opcode (Hex) Addr Mode dst 3 10/12 (3) ccD DA (2) cc | Opcode dst cc = 0 to F Opcode dst 2 10 30 IRR NOTES: 1. The 3-byte format is used for a conditional jump and the 2-byte format for an unconditional jump. 2. In the first byte of the three-byte instruction format (conditional jump), the condition code and the opcode are each four bits long. 3. For a conditional jump, execution takes 12 cycles if the jump is taken or 10 cycles if it is not taken. Examples: Given: The carry flag (C) = "1", register 00 = 01H, and register 01 = 20H: JP JP C,LABEL_W @00H LABEL_W = 1000H 1000H, PC = 1000H 1000H PC = 0120H 0120H The first example shows a conditional JP. If the carry flag is set to "1", the statement "JP C,LABEL_W" replaces the contents of the program counter with the value 1000H 1000H and transfers control to that location. Had the carry flag not been set, control would have passed to the statement following the JP instruction. The second example shows an unconditional JP. The statement "JP @00" replaces the contents of the program counter with the contents of the register pair 00H and 01H, leaving the value 0120H 0120H. 6­47 SAM8 INSTRUCTION SET S3C8444 S3C8444 JR - Jump Relative JR cc,dst Operation: If cc is true, PC PC + dst If the condition specified by the condition code (cc) is true, the relative address is added to the program counter and control passes to the statement whose address is now in the program counter; otherwise, the instruction following the JR instruction is executed. (See list of condition codes). The range of the relative address is +127, ­128, and the original value of the program counter is taken to be the address of the first instruction byte following the JR statement. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst 2 10/12 (2) ccB RA (1) cc | Opcode dst cc = 0 to F NOTES: 1. In the first byte of the two-byte instruction format, the condition code and the opcode are each four bits. 2. Instruction execution takes 12 cycles if the jump is taken or 10 cycles if it is not taken. Example: Given: The carry flag = "1" and LABEL_X = 1FF7H: JR C,LABEL_X PC = 1FF7H If the carry flag is set (that is, if the condition code is true), the statement "JR C,LABEL_X" will pass control to the statement whose address is now in the PC. Otherwise, the program instruction following the JR would be executed. 6­48 S3C8444 S3C8444 SAM8 INSTRUCTION SET LD - Load LD dst,src Operation: dst src The contents of the source are loaded into the destination. The source's contents are unaffected. Flags: No flags are affected. Format: Bytes src | Opcode 2 src dst Opcode (Hex) 6 rC r IM 6 dst | Opcode Cycles r8 r R 6 r9 R r 2 Addr Mode dst src r = 0 to F Opcode dst src 3 3 r lr D7 Ir r 10 E4 R R E5 R IR 10 E6 R IM 10 Opcode dst C7 10 src 2 6 6 Opcode dst | src D6 IR IM Opcode src dst 3 10 F5 IR R Opcode dst | src x 3 10 87 r x [r] Opcode src | dst x 3 10 97 x [r] r 6­49 SAM8 INSTRUCTION SET S3C8444 S3C8444 LD - Load LD (Continued) Examples: Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H, register 02H = 02H, LOOP = 30H, and register 3AH = 0FFH: LD R0 = 10H LD R0,01H R0 = 20H, register 01H = 20H LD 01H,R0 Register 01H = 01H, R0 = 01H LD R1,@R0 R1 = 20H, R0 = 01H LD @R0,R1 R0 = 01H, R1 = 0AH, register 01H = 0AH LD 00H,01H Register 00H = 20H, register 01H = 20H LD 02H,@00H Register 02H = 20H, register 00H = 01H LD 00H,#0AH Register 00H = 0AH LD @00H,#10H LD @00H,02H LD R0,#LOOP[R1] R0 = 0FFH, R1 = 0AH LD 6­50 R0,#10H #LOOP[R0],R1 Register 31H = 0AH, R0 = 01H, R1 = 0AH Register 00H = 01H, register 01H = 10H Register 00H = 01H, register 01H = 02, register 02H = 02H S3C8444 S3C8444 SAM8 INSTRUCTION SET LDB - Load Bit LDB dst,src.b LDB dst.b,src Operation: dst(0) src(b) or dst(b) src(0) The specified bit of the source is loaded into bit zero (LSB) of the destination, or bit zero of the source is loaded into the specified bit of the destination. No other bits of the destination are affected. The source is unaffected. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst src Opcode dst | b | 0 src 3 10 47 r0 Rb Opcode src | b | 1 dst 3 10 47 Rb r0 NOTE: In the second byte of the instruction formats, the destination (or source) address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length. Examples: Given: R0 = 06H and general register 00H = 05H: LDB LDB R0,00H.2 00H.0,R0 R0 = 07H, register 00H = 05H R0 = 06H, register 00H = 04H In the first example, destination working register R0 contains the value 06H and the source general register 00H the value 05H. The statement "LD R0,00H.2" loads the bit two value of the 00H register into bit zero of the R0 register, leaving the value 07H in register R0. In the second example, 00H is the destination register. The statement "LD 00H.0,R0" loads bit zero of register R0 to the specified bit (bit zero) of the destination register, leaving 04H in register 00H. 6­51 SAM8 INSTRUCTION SET S3C8444 S3C8444 LDC/LDE - Load Memory LDC/LDE dst,src Operation: dst src This instruction loads a byte from program or data memory into a working register or vice-versa. The source values are unaffected. LDC refers to program memory and LDE to data memory. The assembler makes Irr or rr values an even number for program memory and odd an odd number for data memory. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst src 1. Opcode dst | src 2 12 C3 r Irr 2. Opcode src | dst 2 12 D3 Irr r 3. Opcode dst | src XS 3 18 E7 r XS [rr] 4. Opcode src | dst XS 3 18 F7 XS [rr] r 5. Opcode dst | src XLL XLH 4 20 A7 r XL [rr] 6. Opcode src | dst XLL XLH 4 20 B7 XL [rr] r 7. Opcode dst | 0000 DAL DAH 4 20 A7 r DA 8. Opcode src | 0000 DAL DAH 4 20 B7 DA r 9. Opcode dst | 0001 DAL DAH 4 20 A7 r DA 10. Opcode src | 0001 DAL DAH 4 20 B7 DA r NOTES: 1. The source (src) or working register pair [rr] for formats 5 and 6 cannot use register pair 0­1. 2. For formats 3 and 4, the destination address 'XS [rr]' and the source address 'XS [rr]' are each one byte. 3. For formats 5 and 6, the destination address 'XL [rr] and the source address 'XL [rr]' are each two bytes. 4. The DA and r source values for formats 7 and 8 are used to address program memory; the second set of values, used in formats 9 and 10, are used to address data memory. 6­52 S3C8444 S3C8444 SAM8 INSTRUCTION SET LDC/LDE - Load Memory LDC/LDE (Continued) Examples: Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H; Program memory locations 0103H 0103H = 4FH, 0104H 0104H = 1A, 0105H 0105H = 6DH, and 1104H 1104H = 88H. External data memory locations 0103H 0103H = 5FH, 0104H 0104H = 2AH, 0105H 0105H = 7DH, and 1104H 1104H = 98H: LDC R0,@RR2 ; R0 contents of program memory location 0104H 0104H ; R0 = 1AH, R2 = 01H, R3 = 04H LDE R0,@RR2 ; R0 contents of external data memory location 0104H 0104H ; R0 = 2AH, R2 = 01H, R3 = 04H LDC * @RR2,R0 ; 11H (contents of R0) is loaded into program memory ; location 0104H 0104H (RR2), ; working registers R0, R2, R3 no change LDE @RR2,R0 ; 11H (contents of R0) is loaded into external data memory ; location 0104H 0104H (RR2), ; working registers R0, R2, R3 no change LDC R0,#01H[RR2] ; R0 contents of program memory location 0105H 0105H ; (01H + RR2), ; R0 = 6DH, R2 = 01H, R3 = 04H LDE R0,#01H[RR2] ; R0 contents of external data memory location 0105H 0105H ; (01H + RR2), R0 = 7DH, R2 = 01H, R3 = 04H LDC * #01H[RR2],R0 ; 11H (contents of R0) is loaded into program memory location ; 0105H 0105H (01H + 0104H 0104H) LDE #01H[RR2],R0 ; 11H (contents of R0) is loaded into external data memory ; location 0105H 0105H (01H + 0104H 0104H) LDC R0,#1000H 1000H[RR2] ; R0 contents of program memory location 1104H 1104H ; (1000H 1000H + 0104H 0104H), R0 = 88H, R2 = 01H, R3 = 04H LDE R0,#1000H 1000H[RR2] ; R0 contents of external data memory location 1104H 1104H ; (1000H 1000H + 0104H 0104H), R0 = 98H, R2 = 01H, R3 = 04H LDC R0,1104H 1104H ; R0 contents of program memory location 1104H 1104H, R0 = 88H LDE R0,1104H 1104H ; R0 contents of external data memory location 1104H 1104H, ; R0 = 98H LDC * 1105H 1105H,R0 ; 11H (contents of R0) is loaded into program memory location ; 1105H 1105H, (1105H 1105H) 11H LDE 1105H 1105H,R0 ; 11H (contents of R0) is loaded into external data memory ; location 1105H 1105H, (1105H 1105H) 11H * These instructions are not supported by mask ROM type devices. 6­53 SAM8 INSTRUCTION SET S3C8444 S3C8444 LDCD/LDED - Load Memory and Decrement LDCD/LDED dst,src Operation: dst src rr rr ­ 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The contents of the source location are loaded into the destination location. The memory address is then decremented. The contents of the source are unaffected. LDCD references program memory and LDED references external data memory. The assembler makes 'Irr' an even number for program memory and an odd number for data memory. Flags: No flags are affected. Format: Bytes Opcode dst | src Cycles Opcode (Hex) 2 16 E2 Addr Mode dst src r Irr NOTE: In the second byte of the two-byte instruction format, the destination and source addresses are each four bits long. Examples: Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory location 1033H 1033H = 0CDH, and external data memory location 1033H 1033H = 0DDH: LDCD ; 0CDH (contents of program memory location 1033H 1033H) is loaded ; into R8 and RR6 is decremented by one ; R8 = 0CDH, R6 = 10H, R7 = 32H (RR6 RR6 ­ 1) LDED 6­54 R8,@RR6 R8,@RR6 ; 0DDH (contents of data memory location 1033H 1033H) is loaded ; into R8 and RR6 is decremented by one (RR6 RR6 ­ 1) ; R8 = 0DDH, R6 = 10H, R7 = 32H S3C8444 S3C8444 SAM8 INSTRUCTION SET LDCI/LDEI - Load Memory and Increment LDCI/LDEI dst,src Operation: dst src rr rr + 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The contents of the source location are loaded into the destination location. The memory address is then incremented automatically. The contents of the source are unaffected. LDCI refers to program memory and LDEI refers to external data memory. The assembler makes 'Irr' even for program memory and odd for data memory. Flags: No flags are affected. Format: Bytes Opcode dst | src Cycles Opcode (Hex) 2 16 E3 Addr Mode dst src r Irr NOTE: In the second byte of the two-byte instruction format, the destination and source addresses are each four bits. Example: Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory locations 1033H 1033H = 0CDH and 1034H 1034H = 0C5H; external data memory locations 1033H 1033H = 0DDH and 1034H 1034H = 0D5H: LDCI R8,@RR6 ; 0CDH (contents of program memory location 1033H 1033H) is loaded ; into R8 and RR6 is incremented by one (RR6 RR6 + 1) ; R8 = 0CDH, R6 = 10H, R7 = 34H LDEI R8,@RR6 ; 0DDH (contents of data memory location 1033H 1033H) is loaded ; into R8 and RR6 is incremented by one (RR6 RR6 + 1) ; R8 = 0DDH, R6 = 10H, R7 = 34H 6­55 SAM8 INSTRUCTION SET S3C8444 S3C8444 LDCPD/LDEPD - Load Memory with Pre-Decrement LDCPD/ LDEPD dst,src Operation: rr rr ­ 1 dst src These instructions are used for block transfers of data from program or data memory from the register file. The address of the memory location is specified by a working register pair and is first decremented. The contents of the source location are then loaded into the destination location. The contents of the source are unaffected. LDCPD refers to program memory and LDEPD refers to external data memory. The assembler makes 'Irr' an even number for program memory and an odd number for external data memory. Flags: No flags are affected. Format: Bytes Opcode Opcode (Hex) 2 src | dst Cycles 16 F2 Addr Mode dst src Irr r NOTE: In the second byte of the two-byte instruction format, the source and destination addresses are each four bits. Examples: Given: R0 = 77H, R6 = 30H, and R7 = 00H: (RR6 RR6 ­ 1) 77H (contents of R0) is loaded into program memory location 2FFFH (3000H 3000H ­ 1H) R0 = 77H, R6 = 2FH, R7 = 0FFH LDCPD @RR6,R0 ; ; ; ; LDEPD @RR6,R0 ; (RR6 RR6 ­ 1) ; 77H (contents of R0) is loaded into external data memory location 2FFFH (3000H 3000H ­ 1H) ; R0 = 77H, R6 = 2FH, R7 = 0FFH ; 6­56 S3C8444 S3C8444 SAM8 INSTRUCTION SET LDCPI/LDEPI - Load Memory with Pre-Increment LDCPI/ LDEPI dst,src Operation: rr rr + 1 dst src These instructions are used for block transfers of data from program or data memory from the register file. The address of the memory location is specified by a working register pair and is first incremented. The contents of the source location are loaded into the destination location. The contents of the source are unaffected. LDCPI refers to program memory and LDEPI refers to external data memory. The assembler makes 'Irr' an even number for program memory and an odd number for data memory. Flags: No flags are affected. Format: Bytes Opcode Cycles Opcode (Hex) 2 16 F3 src | dst Addr Mode dst src Irr r NOTE: In the second byte of the two-byte instruction format, the source and destination addresses are each four bits long. Examples: Given: R0 = 7FH, R6 = 21H, and R7 = 0FFH: LDCPI @RR6,R0 ; ; ; ; (RR6 RR6 + 1) 7FH (contents of R0) is loaded into program memory location 2200H 2200H (21FFH 21FFH + 1H) R0 = 7FH, R6 = 22H, R7 = 00H LDEPI @RR6,R0 ; ; ; ; (RR6 RR6 + 1) 7FH (contents of R0) is loaded into external data memory location 2200H 2200H (21FFH 21FFH + 1H) R0 = 7FH, R6 = 22H, R7 = 00H 6­57 SAM8 INSTRUCTION SET S3C8444 S3C8444 LDW - Load Word LDW dst,src Operation: dst src The contents of the source (a word) are loaded into the destination. The contents of the source are unaffected. Flags: No flags are affected. Format: Bytes Opcode Examples: src dst 3 dst src Opcode (Hex) 10 C4 RR RR 10 Opcode Cycles C5 RR IR 12 C6 RR IML 4 Addr Mode dst src Given: R4 = 06H, R5 = 1CH, R6 = 05H, R7 = 02H, register 00H = 1AH, register 01H = 02H, register 02H = 03H, and register 03H = 0FH: LDW RR6,RR4 R6 = 06H, R7 = 1CH, R4 = 06H, R5 = 1CH LDW 00H,02H Register 00H = 03H, register 01H = 0FH, register 02H = 03H, register 03H = 0FH LDW RR2,@R7 R2 = 03H, R3 = 0FH, LDW 04H,@01H Register 04H = 03H, register 05H = 0FH LDW RR6,#1234H 1234H R6 = 12H, R7 = 34H LDW 02H,#0FEDH Register 02H = 0FH, register 03H = 0EDH In the second example, the statement "LDW 00H,02H" loads the contents of the source word 02H, 03H into the destination word 00H, 01H. This leaves the value 03H in general register 00H and the value 0FH in register 01H. The other examples show how LDW is used together with various addressing modes and formats. 6­58 S3C8444 S3C8444 SAM8 INSTRUCTION SET MULT - Multiply (Unsigned) MULT dst,src Operation: dst dst × src The 8-bit destination operand (even register of the register pair) is multiplied by the source operand (8 bits) and the product (16 bits) is stored in the register pair specified by the destination address. Both operands are treated as unsigned integers. Flags: C: Z: S: V: D: H: Set if result is > 255; cleared otherwise. Set if the result is "0"; cleared otherwise. Set if MSB of the result is a "1"; cleared otherwise. Cleared. Unaffected. Unaffected. Format: Bytes Examples: src dst Opcode (Hex) 3 24 84 RR R 24 24 Opcode Cycles Addr Mode dst src 85 86 RR RR IR IM Given: Register 00H = 20H, register 01H = 03H, register 02H = 09H, register 03H = 06H: MULT MULT MULT 00H, 02H 00H, @01H 00H, #30H Register 00H = 01H, register 01H = 20H, register 02H = 09H Register 00H = 00H, register 01H = 0C0H Register 00H = 06H, register 01H = 00H In the first example, the statement "MULT 00H,02H" multiplies the 8-bit destination operand (in the register 00H of the register pair 00H, 01H) by the source register 02H operand (09H). The 16bit product, 0120H 0120H, is stored in the register pair 00H, 01H. 6­59 SAM8 INSTRUCTION SET S3C8444 S3C8444 NEXT - Next NEXT Operation: PC @IP IP IP + 2 The NEXT instruction is useful for the implementation of threaded-code languages. The program memory word pointed to by the instruction pointer is loaded into the program counter. The instruction pointer is then incremented by two. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) 1 14 0F Opcode Example: The following illustration shows one example of how the NEXT instruction is used. Example diagrams for the ENTER, EXIT, and NEXT instructions illustrate how these instructions can be used together in a program. BEFORE IP PC 0043 0120 AFTER IP ADDR 43 44 45 120 DATA ADDR H ADDR L ADDR H NEXT MEMORY 6­60 01 30 PC 0045 0130 ADDR DATA 43 44 45 ADDR H ADDR L ADDR H 130 ROUTINE MEMORY S3C8444 S3C8444 SAM8 INSTRUCTION SET NOP - No Operation NOP Operation: No action is performed by this instruction. It is typically used for timing delays. Flags: No flags are affected. Format: Bytes Opcode Example: Cycles Opcode (Hex) 1 6 FF When the instruction NOP is encountered in a program, no operation occurs. Instead, there is a slight execution timing delay. 6­61 SAM8 INSTRUCTION SET S3C8444 S3C8444 OR - Logical or OR dst,src Operation: dst dst OR src The source operand is logically ORed with the destination operand and the result is stored in the destination. The contents of the source are unaffected. The OR operation results in a "1" being stored whenever either of the corresponding bits in the two operands is a "1"; otherwise a "0" is stored. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Always cleared to "0". Unaffected. Unaffected. Format: Bytes Opcode Examples: src dst dst src 6 42 r r 43 r lr 10 44 R R 10 Opcode 2 dst | src Opcode (Hex) 6 Opcode Cycles 45 R IR 10 46 R IM 3 3 Addr Mode dst src Given: R0 = 15H, R1 = 2AH, R2 = 01H, register 00H = 08H, register 01H = 37H, and register 08H = 8AH: OR OR OR OR OR R0,R1 R0,@R2 00H,01H 01H,@00H 00H,#02H R0 = 3FH, R1 = 2AH R0 = 37H, R2 = 01H, register 01H = 37H Register 00H = 3FH, register 01H = 37H Register 00H = 08H, register 01H = 0BFH Register 00H = 0AH In the first example, if working register R0 contains the value 15H and register R1 the value 2AH, the statement "OR R0,R1" logical-ORs the R0 and R1 register contents and stores the result (3FH) in destination register R0. The other examples show the use of the logical OR instruction with the various addressing modes and formats. 6­62 S3C8444 S3C8444 SAM8 INSTRUCTION SET POP - Pop From Stack POP dst Operation: dst @SP SP SP + 1 The contents of the location addressed by the stack pointer are loaded into the destination. The stack pointer is then incremented by one. Flags: No flags affected. Format: Bytes Examples: Addr Mode dst 2 dst Opcode (Hex) 10 50 R 10 Opcode Cycles 51 IR Given: Register 00H = 01H, register 01H = 1BH, SPH (0D8H) = 00H, SPL (0D9H) = 0FBH, and stack register 0FBH = 55H: POP POP 00H @00H Register 00H = 55H, SP = 00FCH 00FCH Register 00H = 01H, register 01H = 55H, SP = 00FCH 00FCH In the first example, general register 00H contains the value 01H. The statement "POP 00H" loads the contents of location 00FBH 00FBH (55H) into destination register 00H and then increments the stack pointer by one. Register 00H then contains the value 55H and the SP points to location 00FCH 00FCH. 6­63 SAM8 INSTRUCTION SET S3C8444 S3C8444 POPUD - Pop User Stack (Decrementing) POPUD dst,src Operation: dst src IR IR ­ 1 This instruction is used for user-defined stacks in the register file. The contents of the register file location addressed by the user stack pointer are loaded into the destination. The user stack pointer is then decremented. Flags: No flags are affected. Format: Bytes Opcode Example: src dst Cycles Opcode (Hex) 3 10 Addr Mode dst src 92 R IR Given: Register 00H = 42H (user stack pointer register), register 42H = 6FH, and register 02H = 70H: POPUD 02H,@00H Register 00H = 41H, register 02H = 6FH, register 42H = 6FH If general register 00H contains the value 42H and register 42H the value 6FH, the statement "POPUD 02H,@00H" loads the contents of register 42H into the destination register 02H. The user stack pointer is then decremented by one, leaving the value 41H. 6­64 S3C8444 S3C8444 SAM8 INSTRUCTION SET POPUI - Pop User Stack (Incrementing) POPUI dst,src Operation: dst src IR IR + 1 The POPUI instruction is used for user-defined stacks in the register file. The contents of the register file location addressed by the user stack pointer are loaded into the destination. The user stack pointer is then incremented. Flags: No flags are affected. Format: Bytes Opcode Example: src dst Cycles Opcode (Hex) 3 10 93 Addr Mode dst src R IR Given: Register 00H = 01H and register 01H = 70H: POPUI 02H,@00H Register 00H = 02H, register 01H = 70H, register 02H = 70H If general register 00H contains the value 01H and register 01H the value 70H, the statement "POPUI 02H,@00H" loads the value 70H into the destination general register 02H. The user stack pointer (register 00H) is then incremented by one, changing its value from 01H to 02H. 6­65 SAM8 INSTRUCTION SET S3C8444 S3C8444 PUSH - Push To Stack PUSH src Operation: SP SP ­ 1 @SP src The contents of the stack pointer are decremented, then the contents of the source are loaded into the location addressed by the decremented stack pointer, thus adding a new value to the top of the stack. Flags: No flags are affected. Format: Bytes Examples: Addr Mode dst 2 src Opcode (Hex) 10 (internal clock) 12 (external clock) 70 R 12 (internal clock) 14 (external clock) Opcode Cycles 71 IR Given: Register 40H = 4FH, register 4FH = 0AAH, SPH = 00H, and SPL = 00H: PUSH 40H Register 40H = 4FH, stack register 0FFH = 4FH, SPH = 0FFH, SPL = 0FFH PUSH @40H Register 40H = 4FH, register 4FH = 0AAH, stack register 0FFH = 0AAH, SPH = 0FFH, SPL = 0FFH In the first example, if the stack pointer contains the value 0000H 0000H, and general register 40H the value 4FH, the statement "PUSH 40H" decrements the stack pointer from 0000 to 0FFFFH. Then it loads the contents of register 40H into location 0FFFFH and adds this new value to the top of the stack. 6­66 S3C8444 S3C8444 SAM8 INSTRUCTION SET PUSHUD - Push User Stack (Decrementing) PUSHUD dst,src Operation: IR IR ­ 1 dst src This instruction is used for user-defined stacks in the register file. The user stack pointer is decremented, then the contents of the source are loaded into the register file location addressed by the decremented user stack pointer. Flags: No flags are affected. Format: Bytes Opcode Example: dst src Cycles Opcode (Hex) 3 10 82 Addr Mode dst src IR R Given: Register 00H = 03H, register 01H = 05H, and register 02H = 1AH: PUSHUD @00H,01H Register 00H = 02H, register 01H = 05H, register 02H = 05H If the user stack pointer (register 00H, for example) contains the value 03H, the statement "PUSHUD @00H,01H" decrements the user stack pointer by one, leaving the value 02H. Then, the 01H register value 05H is loaded into the location addressed by the decremented user stack pointer. 6­67 SAM8 INSTRUCTION SET S3C8444 S3C8444 PUSHUI - Push User Stack (Incrementing) PUSHUI dst,src Operation: IR IR + 1 dst src This instruction is used for user-defined stacks in the register file. The user stack pointer is incremented, then the contents of the source are loaded into the register file location addressed by the incremented user stack pointer. Flags: No flags are affected. Format: Bytes Opcode Example: dst src Cycles Opcode (Hex) 3 10 83 Addr Mode dst src IR R Given: Register 00H = 03H, register 01H = 05H, and register 04H = 2AH: PUSHUI @00H,01H Register 00H = 04H, register 01H = 05H, register 04H = 05H If the user stack pointer (register 00H, for example) contains the value 03H, the statement "PUSHUI @00H,01H" increments the user stack pointer by one, leaving the value 04H. Then, the 01H register value (05H) is loaded into the location addressed by the incremented user stack pointer. 6­68 S3C8444 S3C8444 SAM8 INSTRUCTION SET RCF - Reset Carry Flag RCF RCF Operation: C 0 The carry flag is cleared to logic zero, regardless of its previous value. Flags: C: Cleared to "0". No other flags are affected. Format: Bytes Opcode Example: Cycles Opcode (Hex) 1 6 CF Given: The carry flag (C) = "1" or "0": The instruction RCF clears the carry flag to logic zero. 6­69 SAM8 INSTRUCTION SET S3C8444 S3C8444 RET - Return RET Operation: PC @SP SP SP + 2 The RET instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a CALL instruction. The contents of the location addressed by the stack pointer are popped into the program counter. The next statement executed is that addressed by the new contents of the program counter. Flags: No flags are affected. Format: Bytes Example: Opcode (Hex) 1 Opcode Cycles 14 AF Given: SP = 00FCH 00FCH, (SP) = 101AH 101AH, and PC = 1234: RET PC = 101AH 101AH, SP = 00FEH 00FEH The statement "RET" pops the contents of stack pointer location 00FCH 00FCH (10H) into the high byte of the program counter. The stack pointer then pops the value in location 00FEH 00FEH (1AH) into the PC's low byte and the instruction at location 101AH 101AH is executed. The stack pointer now points to memory location 00FEH 00FEH. 6­70 S3C8444 S3C8444 SAM8 INSTRUCTION SET RL - Rotate Left RL dst Operation: C dst (7) dst (0) dst (7) dst (n + 1) dst (n), n = 0­6 The contents of the destination operand are rotated left one bit position. The initial value of bit 7 is moved to the bit zero (LSB) position and also replaces the carry flag. 7 0 C Flags: C: Z: S: V: D: H: Set if the bit rotated from the most significant bit position (bit 7) was "1". Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Set if arithmetic overflow occurred; cleared otherwise. Unaffected. Unaffected. Format: Bytes Examples: Addr Mode dst 2 dst Opcode (Hex) 6 90 R 6 Opcode Cycles 91 IR Given: Register 00H = 0AAH, register 01H = 02H and register 02H = 17H: RL RL 00H @01H Register 00H = 55H, C = "1" Register 01H = 02H, register 02H = 2EH, C = "0" In the first example, if general register 00H contains the value 0AAH (10101010B 10101010B), the statement "RL 00H" rotates the 0AAH value left one bit position, leaving the new value 55H (01010101B 01010101B) and setting the carry and overflow flags. 6­71 SAM8 INSTRUCTION SET S3C8444 S3C8444 RLC - Rotate Left Through Carry RLC dst Operation: dst (0) C C dst (7) dst (n + 1) dst (n), n = 0­6 The contents of the destination operand with the carry flag are rotated left one bit position. The initial value of bit 7 replaces the carry flag (C); the initial value of the carry flag replaces bit zero. 7 0 C Flags: C: Z: S: V: Set if the bit rotated from the most significant bit position (bit 7) was "1". Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. D: Unaffected. H: Unaffected. Format: Bytes Examples: Addr Mode dst 2 dst Opcode (Hex) 6 10 R 6 Opcode Cycles 11 IR Given: Register 00H = 0AAH, register 01H = 02H, and register 02H = 17H, C = "0": RLC RLC 00H @01H Register 00H = 54H, C = "1" Register 01H = 02H, register 02H = 2EH, C = "0" In the first example, if general register 00H has the value 0AAH (10101010B 10101010B), the statement "RLC 00H" rotates 0AAH one bit position to the left. The initial value of bit 7 sets the carry flag and the initial value of the C flag replaces bit zero of register 00H, leaving the value 55H (01010101B 01010101B). The MSB of register 00H resets the carry flag to "1" and sets the overflow flag. 6­72 S3C8444 S3C8444 SAM8 INSTRUCTION SET RR - Rotate Right RR dst Operation: C dst (0) dst (7) dst (0) dst (n) dst (n + 1), n = 0­6 The contents of the destination operand are rotated right one bit position. The initial value of bit zero (LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C). 7 0 C Flags: C: Z: S: V: Set if the bit rotated from the least significant bit position (bit zero) was "1". Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. D: Unaffected. H: Unaffected. Format: Bytes Examples: Addr Mode dst 2 dst Opcode (Hex) 6 E0 R 6 Opcode Cycles E1 IR Given: Register 00H = 31H, register 01H = 02H, and register 02H = 17H: RR RR 00H @01H Register 00H = 98H, C = "1" Register 01H = 02H, register 02H = 8BH, C = "1" In the first example, if general register 00H contains the value 31H (00110001B 00110001B), the statement "RR 00H" rotates this value one bit position to the right. The initial value of bit zero is moved to bit 7, leaving the new value 98H (10011000B 10011000B) in the destination register. The initial bit zero also resets the C flag to "1" and the sign flag and overflow flag are also set to "1". 6­73 SAM8 INSTRUCTION SET S3C8444 S3C8444 RRC - Rotate Right Through Carry RRC dst Operation: dst (7) C C dst (0) dst (n) dst (n + 1), n = 0­6 The contents of the destination operand and the carry flag are rotated right one bit position. The initial value of bit zero (LSB) replaces the carry flag; the initial value of the carry flag replaces bit 7 (MSB). 7 0 C Flags: C: Z: S: V: Set if the bit rotated from the least significant bit position (bit zero) was "1". Set if the result is "0" cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. D: Unaffected. H: Unaffected. Format: Bytes Examples: Addr Mode dst 2 dst Opcode (Hex) 6 C0 R 6 Opcode Cycles C1 IR Given: Register 00H = 55H, register 01H = 02H, register 02H = 17H, and C = "0": RRC RRC 00H @01H Register 00H = 2AH, C = "1" Register 01H = 02H, register 02H = 0BH, C = "1" In the first example, if general register 00H contains the value 55H (01010101B 01010101B), the statement "RRC 00H" rotates this value one bit position to the right. The initial value of bit zero ("1") replaces the carry flag and the initial value of the C flag ("1") replaces bit 7. This leaves the new value 2AH (00101010B 00101010B) in destination register 00H. The sign flag and overflow flag are both cleared to "0". 6­74 S3C8444 S3C8444 SAM8 INSTRUCTION SET SB0 - Select Bank 0 SB0 Operation: BANK 0 This instruction causes the bank address flag (bit zero) of the FLAGS register (0D5H) to be cleared to logic zero, selecting bank 0 of register set one. Flags: No flags are affected. Format: Bytes Opcode Example: Cycles Opcode (Hex) 1 6 4F The statement SB0 clears the zero bit of the FLAGS register (0D5H) to logic zero, selecting bank 0 register addressing. 6­75 SAM8 INSTRUCTION SET S3C8444 S3C8444 SB1 - Select Bank 1 SB1 Operation: BANK 1 The SB1 instruction sets the bank address flag (bit zero) of the FLAGS register (0D5H) to logical one, selecting bank 1 of register set one. (Bank 1 is not implemented in some of the S3C8 series microcontrollers.) Flags: No flags are affected. Format: Bytes Opcode Example: Cycles Opcode (Hex) 1 6 5F The statement SB1 sets the zero bit of the FLAGS register (0D5H) to logic one, selecting bank 1 register addressing. 6­76 S3C8444 S3C8444 SAM8 INSTRUCTION SET SBC - Subtract With Carry SBC dst,src Operation: dst dst ­ src ­ c The source operand, along with the setting of the carry flag, is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the twos-complement of the source operand to the destination operand. In multiple precision arithmetic, this instruction permits the carry ("borrow") from the subtraction of the low-order operands to be subtracted from the subtraction of high-order operands. Flags: Set if a borrow occurred (src > dst); cleared otherwise. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred, that is, if the operands were of opposite sign and the sign of the result is the same as the sign of the source; cleared otherwise. D: Always set to "1". H: Cleared if there is a carry from the most significant bit of the low-order four bits of the result; set otherwise, indicating a "borrow". C: Z: S: V: Format: Bytes 2 dst | src 6 Opcode (Hex) 32 6 Opcode Cycles 33 Addr Mode dst src r r r lr NOTE: In the second byte of the two-byte instruction format, the destination and source addresses are each four bits long. Opcode dst 3 10 10 34 35 R R R IR Opcode Examples: src dst src 3 10 36 R IM Given: R1 = 10H, R2 = 03H, C = "1", register 01H = 20H, register 02H = 03H, and register 03H = 0AH: SBC SBC SBC SBC SBC R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#8AH R1 = 0CH, R2 = 03H R1 = 05H, R2 = 03H, register 03H = 0AH Register 01H = 1CH, register 02H = 03H Register 01H = 15H,register 02H = 03H, register 03H = 0AH Register 01H = 95H; C, S, and V = "1" In the first example, if working register R1 contains the value 10H and register R2 the value 03H, the statement "SBC R1,R2" subtracts the source value (03H) and the C flag value ("1") from the destination (10H) and then stores the result (0CH) in register R1. 6­77 SAM8 INSTRUCTION SET S3C8444 S3C8444 SCF - Set Carry Flag SCF Operation: C 1 The carry flag (C) is set to logic one, regardless of its previous value. Flags: C: Set to "1". No other flags are affected. Format: Bytes Opcode Example: The statement SCF sets the carry flag to logic one. 6­78 Cycles Opcode (Hex) 1 6 DF S3C8444 S3C8444 SAM8 INSTRUCTION SET SRA - Shift Right Arithmetic SRA dst Operation: dst (7) dst (7) C dst (0) dst (n) dst (n + 1), n = 0­6 An arithmetic shift right one bit position is performed on the destination operand. Bit zero (LSB) replaces the carry flag. Bit 7 (the sign bit) is unchanged, and its value is also shifted into bit position 6. 7 6 0 C Flags: C: Z: S: V: D: H: Set if the bit shifted from the LSB position (bit zero) was "1". Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Always cleared to "0". Unaffected. Unaffected. Format: Bytes Examples: Addr Mode dst 2 dst Opcode (Hex) 6 D0 R 6 Opcode Cycles D1 IR Given: Register 00H = 9AH, register 02H = 03H, register 03H = 0BCH, and C = "1": SRA SRA 00H @02H Register 00H = 0CD, C = "0" Register 02H = 03H, register 03H = 0DEH, C = "0" In the first example, if general register 00H contains the value 9AH (10011010B 10011010B), the statement "SRA 00H" shifts the bit values in register 00H right one bit position. Bit zero ("0") clears the C flag and bit 7 ("1") is then shifted into the bit 6 position (bit 7 remains unchanged). This leaves the value 0CDH (11001101B 11001101B) in destination register 00H. 6­79 SAM8 INSTRUCTION SET S3C8444 S3C8444 SRP/SRP0/SRP1 - Set Register Pointer SRP src SRP0 src SRP1 src Operation: If src (1) = 1 and src (0) = 0 then: RP0 (3­7) src (3­7) If src (1) = 0 and src (0) = 1 then: RP1 (3­7) src (3­7) If src (1) = 0 and src (0) = 0 then: RP0 (4­7) src (4­7), RP0 (3) 0 RP1 (4­7) src (4­7), RP1 (3) 1 The source data bits one and zero (LSB) determine if one or both of the register pointers is to be written. Bits 3­7 of the selected register pointer are written unless both register pointers are selected. Then bit 3 of RP0 is forced to logic zero and bit 3 of RP1 is forced to logic one. Flags: No flags are affected. Format: Bytes Opcode Examples: src Cycles Opcode (Hex) Addr Mode src 2 6 31 IM The statement SRP #40H sets register pointer 0 (RP0) at location 0D6H to 40H and register pointer 1 (RP1) at location 0D7H to 48H. The statement "SRP0 #50H" sets RP0 to 50H, and the statement "SRP1 #68H" sets RP1 to 68H. 6­80 S3C8444 S3C8444 SAM8 INSTRUCTION SET STOP - Stop Operation STOP Operation: The STOP instruction stops the system clock. The contents of on-chip CPU registers, peripheral and I/O port control and data registers remain intact during Stop mode. Stop mode can be released only by an external reset operati