16-BIT S1C17602 ADC10SA S1C17 ADC10 AP-11 AP-12 AP-13 AP-14 AP-15 AP-16 AP-17 - Datasheet Archive

 

S1C17602 Technical Manual NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the

 

CMOS 16-BIT 16-BIT SINGLE CHIP MICROCOMPUTER S1C17602 S1C17602 Technical Manual NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of Economy, Trade and Industry or other approval from another government agency. © SEIKO EPSON CORPORATION 2009, All rights reserved. Configuration of product number Devices S1 C 17xxx F 00E1 00 Packing specifications 00 : Besides tape & reel 0A : TCP BL 2 directions 0B : Tape & reel BACK 0C : TCP BR 2 directions 0D : TCP BT 2 directions 0E : TCP BD 2 directions 0F : Tape & reel FRONT 0G : TCP BT 4 directions 0H : TCP BD 4 directions 0J : TCP SL 2 directions 0K : TCP SR 2 directions 0L : Tape & reel LEFT 0M: TCP ST 2 directions 0N : TCP SD 2 directions 0P : TCP ST 4 directions 0Q : TCP SD 4 directions 0R : Tape & reel RIGHT 99 : Specs not fixed Specification Package D: die form; F: QFP, B: BGA Model number Model name C: microcomputer, digital products Product classification S1: semiconductor Development tools 17000 C S5U1 H2 1 00 Packing specifications 00: standard packing Version 1: Version 1 Tool type Hx : ICE Dx : Evaluation board Ex : ROM emulation board Mx : Emulation memory for external ROM Tx : A socket for mounting Cx : Compiler package Sx : Middleware package Corresponding model number 17xxx: for S1C17xxx Tool classification C: microcomputer use Product classification S5U1: development tool for semiconductor products S1C17602 S1C17602 Technical Manual 1 Overview 2 CPU 3 Memory Map and Bus Control 4 Power Supply Voltage 5 Initial Reset 6 Interrupt Controller 7 Oscillator Circuit (OSC) 8 Clock Generator (CLG) 9 Prescaler (PSC) 10 Input/Output Port (P) 11 16-bit Timer (T16) 12 8-bit Timer (T8F) 13 PWM Timer (T16E) 14 8-bit OSC1 Timer (T8OSC1) 15 Clock Timer (CT) 16 Stopwatch Timer (SWT) 17 Watchdog Timer (WDT) 18 UART 19 SPI 20 I2C Master 2CM I 21 I2C Slave 2CS I 22 Remote Controller (REMC) 23 LCD Driver (LCD8) 24 A/D Converter (ADC10SA ADC10SA) 25 RF Converters (RFC) 26 Power Supply Voltage Detection Circuit (SVD) 27 On-chip Debugger (DBG) 28 Multiplier/Divider 29 Electrical Characteristics 30 Basic External Connection Diagram 31 Package Appendix Overview CPU MAP Power Reset ITC OSC CLG PSC IOPort T16 T8F T16E T8OSC1 CT SWT WDT UART SPI I2CM I2CS REMC LCD8 ADC10SA ADC10SA RFC SVD DBG M/D EC BECD Pack AP CONTENTS - CONTENTS 1 Overview .1-1 1.1 Features . 1-2 1.2 Block Diagram. 1-3 1.3 Pins . 1-4 1.3.1 Pinout Diagram . 1-4 1.3.2 Pin Descriptions . 1-8 2 CPU 2.1 2.2 2.3 2.4 .2-1 S1C17 S1C17 Core Features . 2-1 CPU Registers. 2-2 Instruction Set . 2-3 Vector Table. 2-7 2.5 PSR Readout . 2-8 2.6 Processor Information . 2-9 3 Memory Map and Bus Control.3-1 3.1 Bus Cycle . 3-2 3.1.1 Access Size Restrictions . 3-2 3.1.2 Instruction Execution Cycle Restrictions . 3-2 3.2 Flash Area . 3-3 3.2.1 Internal Flash Memory . 3-3 3.2.2 Flash Memory Programming . 3-3 3.2.3 Protect Bits . 3-3 0x17ffc­0x17ffe: Flash Protect Bits . 3-4 3.2.4 Flash Controller Access Control . 3-4 0x5320: FLASHC/SRAMC Control Register (MISC_FL) . 3-4 3.3 Internal RAM Area . 3-5 3.3.1 Internal RAM . 3-5 0x5326: IRAM Size Select Register (MISC_IRAMSZ). 3-5 3.4 Display RAM Area . 3-6 3.4.1 Display RAM . 3-6 3.5 Internal Peripheral Circuit Area . 3-7 3.5.1 Internal Peripheral Circuit Area 1 (0x4000 onward) . 3-7 3.5.2 Internal Peripheral Circuit Area 2 (0x5000 onward) . 3-7 3.6 Core I/O Reserved Area . 3-8 4 Power Supply Voltage .4-1 4.1 4.2 4.3 4.4 4.5 Power Supply Voltage . 4-1 Internal Power Supply Circuit . 4-2 Power Supply Circuit Control. 4-3 Heavy Load Protection Function. 4-4 Control Register Details . 4-5 0x5120: VD1 Control Register (VD1_CTL) . 4-6 0x50a3: LCD Voltage Regulator Control Register (LCD_VREG). 4-7 4.6 Precautions . 4-8 5 Initial Reset .5-1 5.1 Initial Reset Factors . 5-1 5.1.1 #RESET pin . 5-1 5.1.2 P0 Port Key-Entry Reset. 5-2 5.1.3 Reset by Watchdog Timer . 5-2 S1C17602 S1C17602 TECHNICAL MANUAL EPSON i CONTENTS 5.2 Initial Reset Sequence . 5-3 5.3 Initial Settings at Initial Resetting . 5-4 6 Interrupt Controller .6-1 6.1 ITC Configuration . 6-1 6.2 Vector Table. 6-2 6.3 Maskable Interrupt Control . 6-3 6.3.1 Peripheral Module Interrupt Control Bit. 6-3 6.3.2 ITC Interrupt Request Processing . 6-3 6.3.3 S1C17 S1C17 Core Interrupt Processing. 6-4 6.4 NMI. 6-5 6.5 Software Interrupts . 6-6 6.6 HALT and SLEEP Mode Cancellation . 6-7 6.7 Control Register Details . 6-8 0x4306: Interrupt Level Setup Register 0 (ITC_LV0). 6-9 0x4308: Interrupt Level Setup Register 1 (ITC_LV1). 6-10 0x430a: Interrupt Level Setup Register 2 (ITC_LV2). 6-11 0x430c: Interrupt Level Setup Register 3 (ITC_LV3). 6-12 0x430e: Interrupt Level Setup Register 4 (ITC_LV4). 6-13 0x4310: Interrupt Level Setup Register 5 (ITC_LV5). 6-14 0x4312: Interrupt Level Setup Register 6 (ITC_LV6). 6-15 0x4314: Interrupt Level Setup Register 7 (ITC_LV7). 6-16 0x4316: Interrupt Level Setup Register 8 (ITC_LV8). 6-17 0x4318: Interrupt Level Setup Register 9 (ITC_LV9). 6-18 6.8 Precautions . 6-19 7 Oscillator Circuit (OSC) .7-1 7.1 OSC Module Configuration . 7-1 7.2 IOSC Oscillator Circuit . 7-2 7.3 OSC3 Oscillator Circuit . 7-3 7.4 OSC1 Oscillator Circuit . 7-4 7.5 Clock Switching . 7-5 7.6 LCD Clock Control . 7-6 7.7 8-bit OSC1 Timer Clock Control . 7-7 7.8 SVD Clock Control . 7-8 7.9 RFC Clock Control . 7-9 7.10 Clock External Output (FOUTH, FOUT1) . 7-10 7.11 RESET and NMI Input Noise Filters . 7-12 7.12 Control Register Details . 7-13 0x5060: Clock Source Select Register (OSC_SRC) . 7-14 0x5061: Oscillation Control Register (OSC_CTL) . 7-15 0x5062: Noise Filter Enable Register (OSC_NFEN) . 7-17 0x5063: LCD Clock Setup Register (OSC_LCLK) . 7-18 0x5064: FOUT Control Register (OSC_FOUT) . 7-19 0x5065: T8OSC1 Clock Control Register (OSC_T8OSC1) . 7-20 0x5066: SVD Clock Control Register (OSC_SVD) . 7-21 0x5067: RFC Clock Control Register (OSC_RFC) . 7-22 7.13 Precautions . 7-23 8 Clock Generator (CLG) .8-1 8.1 8.2 8.3 8.4 ii Clock Generator Configuration . 8-1 CPU Core Clock (CCLK) Control . 8-2 Peripheral Module Clock (PCLK) Control . 8-3 Control Register Details . 8-4 EPSON S1C17602 S1C17602 TECHNICAL MANUAL CONTENTS 0x5080: PCLK Control Register (CLG_PCLK) . 8-5 0x5081: CCLK Control Register (CLG_CCLK) . 8-6 8.5 Precautions . 8-7 9 Prescaler (PSC) .9-1 9.1 Prescaler Configuration. 9-1 9.2 Control Register Details . 9-2 0x4020: Prescaler Control Register (PSC_CTL) . 9-2 9.3 Precautions . 9-3 10 Input/Output Port (P) .10-1 10.1 10.2 10.3 10.4 Input/Output Port Configuration . 10-1 Input/Output Pin Function Selection (Port MUX) . 10-2 Data Input/Output . 10-3 Pull-up Control . 10-5 10.5 10.6 10.7 10.8 Input Interface Level . 10-6 P0 and P1 Port Chattering Filter Function . 10-7 Port Input Interrupt. 10-8 Control Register Details . 10-10 0x5200/0x5210/0x5220/0x5230/0X5240: Px Port Input Data Registers (Px_IN) . 10-11 0x5201/0x5211/0x5221/0x5231/0X5241: Px Port Output Data Registers (Px_OUT) . 10-12 0x5202/0x5212/0x5222/0x5232/0x5242: Px Port Output Enable Registers (Px_OEN) . 10-13 0x5203/0x5213/0x5223/0x5233/0x5234: Px Port Pull-up Control Registers (Px_PU) . 10-14 0x5204/0x5214: Px Port Schmitt Trigger Control Registers (Px_SM) . 10-15 0x5205/5215: Px Port Interrupt Mask Registers (Px_IMSK) . 10-16 0x5206/5216: Px Port Interrupt Edge Select Registers (Px_EDGE) . 10-17 0x5207/5217: Px Port Interrupt Flag Registers (Px_IFLG) . 10-18 0x5208/0x5218: Px Port Chattering Filter Control Register (Px_CHAT) . 10-19 0x5209: P0 Port Key-Entry Reset Configuration Register (P0_KRST) . 10-21 0x520a/0x521a/0x522a/0x523a/0x524a: Px Port Input Enable Registers (Px_IEN) . 10-22 0x52a0: P0 Port Function Select Register (P0_PMUX) . 10-23 0x52a1: P0 Port Function Select Register (P0_PMUX) . 10-24 0x52a2: P1 Port Function Select Register (P1_PMUX) . 10-25 0x52a3: P1 Port Function Select Register (P1_PMUX) . 10-26 0x52a4: P2 Port Function Select Register (P2_PMUX) . 10-27 0x52a5: P2 Port Function Select Register (P2_PMUX) . 10-28 0x52a6: P3 Port Function Select Register (P3_PMUX) . 10-29 0x52a7: P3 Port Function Select Register (P3_PMUX) . 10-30 0x52a8: P4 Port Function Select Register (P4_PMUX) . 10-31 10.9 Precautions . 10-32 11 16-bit Timer (T16).11-1 11.1 16-bit Timer Overview . 11-1 11.2 16-bit Timer Operating Modes . 11-2 11.2.1 Internal Clock Mode . 11-2 11.2.2 External Clock Mode . 11-3 11.2.3 Pulse Width Measurement Mode . 11-4 11.3 Count Mode . 11-5 11.4 16-bit Timer Reload Register and Underflow Cycle . 11-6 11.5 16-bit Timer Reset . 11-7 11.6 16-bit Timer RUN/STOP Control. 11-8 11.7 16-bit Timer Output Signal. 11-9 11.8 16-bit Timer Interrupts . 11-10 11.9 Control Register Details . 11-11 0x4220/0x4240/0x4260: 16-bit Timer Ch.x Input Clock Select Registers (T16_CLKx) . 11-12 S1C17602 S1C17602 TECHNICAL MANUAL EPSON iii CONTENTS 0x4222/0x4242/0x4262: 16-bit Timer Ch.x Reload Data Registers (T16_TRx) . 11-13 0x4224/0x4244/0x4264: 16-bit Timer Ch.x Counter Data Registers (T16_TCx) . 11-14 0x4226/0x4246/0x4266: 16-bit Timer Ch.x Control Registers (T16_CTLx) . 11-15 0x4228/0x4248/0x4268: 16-bit Timer Ch.x Interrupt Control Registers (T16_INTx) . 11-17 11.10 Precautions . 11-18 12 8-bit Timer (T8F) .12-1 12.1 8-bit Timer Overview . 12-1 12.2 8-bit Timer Count Mode. 12-2 12.3 Count Clock . 12-3 12.4 8-bit Timer Reload Register and Underflow Cycle . 12-4 12.5 8-bit Timer Reset . 12-5 12.6 8-bit Timer RUN/STOP Control. 12-6 12.7 8-bit Timer Output Signal. 12-7 12.8 Fine Mode . 12-8 12.9 8-bit Timer Interrupts . 12-9 12.10 Control Register Details . 12-10 0x4200/0x4280: 8-bit Timer Ch.x Input Clock Select Register (T8F_CLKx) . 12-11 0x4202/0x4282: 8-bit Timer Ch.x Reload Data Register (T8F_TRx) . 12-12 0x4204/0x4284: 8-bit Timer Ch.x Counter Data Register (T8F_TCx) . 12-13 0x4206/0x4286: 8-bit Timer Chx Control Register (T8F_CTLx) . 12-14 0x4208/0x4288: 8-bit Timer Ch.x Interrupt Control Register (T8F_INTx). 12-16 12.11 Precautions . 12-17 13 PWM Timer (T16E) .13-1 13.1 13.2 13.3 13.4 13.5 13.6 13.7 13.8 PWM Timer Overview . 13-1 PWM Timer Operating Modes . 13-2 Setting and Resetting Counter Value . 13-3 Compare Data Settings. 13-4 PWM Timer RUN/STOP Control . 13-5 Clock Output Control . 13-6 PWM Timer Interrupts . 13-9 Control Register Details . 13-11 0x5300: PWM Timer Compare Data A Register (T16E_CA) . 13-12 0x5302: PWM Timer Compare Data B Register (T16E_CB). 13-13 0x5304: PWM Timer Counter Data Register (T16E_TC) . 13-14 0x5306: PWM Timer Control Register (T16E_CTL) . 13-15 0x5308: PWM Timer Input Clock Select Register (T16E_CLK) . 13-17 0x530a: PWM Timer Interrupt Mask Registers (T16E_IMSK). 13-18 0x530c: PWM Timer Interrupt Flag Registers (T16E_IFLG). 13-19 13.9 Precautions . 13-20 14 8-bit OSC1 Timer (T8OSC1) .14-1 14.1 8-bit OSC1 Timer Overview . 14-1 14.2 8-bit OSC1 Timer Count Mode . 14-2 14.3 Count Clock . 14-3 14.4 Resetting 8-bit OSC1 Timer . 14-4 14.5 Compare Data Settings. 14-5 14.6 8-bit OSC1 Timer RUN/STOP Control . 14-6 14.7 8-bit OSC1 Timer Interrupts. 14-7 14.8 PWM output . 14-8 14.9 Control Register Details . 14-9 0x50c0: 8-bit OSC1 Timer Control Register (T8OSC1_CTL) . 14-10 iv EPSON S1C17602 S1C17602 TECHNICAL MANUAL CONTENTS 0x50c1: 8-bit OSC1 Timer Counter Data Register (T8OSC1_CNT) . 14-11 0x50c2: 8-bit OSC1 Timer Compare Data Register (T8OSC1_CMP) . 14-12 0x50c3: 8-bit OSC1 Timer Interrupt Mask Register (T8OSC1_IMSK). 14-13 0x50c4: 8-bit OSC1 Timer Interrupt Flag Register (T8OSC1_IFLG). 14-14 0x50c5: 8-bit OSC1 Timer PWM Duty Data Register (T8OSC1_DUTY) . 14-15 14.10 Precautions . 14-16 15 Clock Timer (CT) .15-1 15.1 15.2 15.3 15.4 15.5 15.6 Clock Timer Overview . 15-1 Operation Clock . 15-2 Clock Timer Resetting. 15-3 Clock Timer RUN/STOP Control . 15-4 Clock Timer Interrupts . 15-5 Control Register Details . 15-6 0x5000: Clock Timer Control Register (CT_CTL) . 15-7 0x5001: Clock Timer Counter Register (CT_CNT) . 15-8 0x5002: Clock Timer Interrupt Mask Register (CT_IMSK) . 15-9 0x5003: Clock Timer Interrupt Flag Register (CT_IFLG) . 15-10 15.7 Precautions . 15-11 16 Stopwatch Timer (SWT).16-1 16.1 16.2 16.3 16.4 16.5 16.6 16.7 Stopwatch Timer Overview . 16-1 BCD Counters . 16-2 Operation Clock . 16-3 Stopwatch Timer Resetting . 16-4 Stopwatch Timer RUN/STOP Control . 16-5 Stopwatch Timer Interrupts . 16-6 Control Register Details . 16-7 0x5020: Stopwatch Timer Control Register (SWT_CTL) . 16-8 0x5021: Stopwatch Timer BCD Counter Register (SWT_BCNT) . 16-9 0x5022: Stopwatch Timer Interrupt Mask Register (SWT_IMSK) . 16-10 0x5023: Stopwatch Timer Interrupt Flag Register (SWT_IFLG) . 16-11 16.8 Precautions . 16-12 17 Watchdog Timer (WDT) .17-1 17.1 Watchdog Timer Overview . 17-1 17.2 Operation Clock . 17-2 17.3 Watchdog Timer Control . 17-3 17.3.1 NMI/Reset Mode Selection. 17-3 17.3.2 Watchdog Timer Run/Stop Control . 17-3 17.3.3 Watchdog Timer Resetting . 17-3 17.3.4 Operation in Standby Mode . 17-3 17.4 Control Register Details . 17-4 0x5040: Watchdog Timer Control Register (WDT_CTL) . 17-5 0x5041: Watchdog Timer Status Register (WDT_ST) . 17-6 17.5 Precautions . 17-7 18 UART .18-1 18.1 18.2 18.3 18.4 18.5 18.6 UART Configuration . 18-1 UART Pin . 18-2 Transfer Clock . 18-3 Transfer Data Settings. 18-4 Data Transfer Control . 18-5 Receive Errors . 18-8 S1C17602 S1C17602 TECHNICAL MANUAL EPSON v CONTENTS 18.7 UART Interrupts . 18-9 18.8 IrDA Interface . 18-11 18.9 Control Register Details . 18-13 0x4100: UART Status Register (UART_ST) . 18-14 0x4101/0x4121: UART Ch.x Transmit Data Registers (UART_TXDx) . 18-16 0x4102/0x4122: UART Ch.x Receive Data Registers (UART_RXDx) . 18-17 0x4103/0x4123: UART Ch.x Mode Registers (UART_MODx) . 18-18 0x4104/0x4124: UART Ch.x Control Registers (UART_CTLx) . 18-19 0x4105/0x4125: UART Ch.x Expansion Registers (UART_EXPx) . 18-20 18.10 Precautions . 18-21 19 SPI 19.1 19.2 19.3 19.4 19.5 19.6 19.7 .19-1 SPI Configuration . 19-1 SPI Input/Output Pins . 19-2 SPI Clock . 19-3 Data Transfer Condition Settings . 19-4 Data Transfer Control . 19-5 SPI Interrupts . 19-8 Control Register Details . 19-9 0x4320: SPI Status Register (SPI_ST) . 19-10 0x4322: SPI Transmit Data Register (SPI_TXD) . 19-11 0x4324: SPI Receive Data Register (SPI_RXD) . 19-12 0x4326: SPI Control Register (SPI_CTL) . 19-13 19.8 Precautions . 19-15 20 I2C Master (I2CM) .20-1 20.1 20.2 20.3 20.4 20.5 20.6 20.7 I2C Master Configuration . 20-1 I2C Master Input/Output Pins . 20-2 I2C Master Clock . 20-3 Settings Before Data Transfer . 20-4 Data Transfer Control . 20-5 I2C Master Interrupts . 20-10 Control Register Details . 20-11 0x4340: I2C Enable Register (I2C_EN) . 20-12 0x4342: I2C Control Register (I2C_CTL) . 20-13 0x4344: I2C Data Register (I2C_DAT) . 20-15 0x4346: I2C Interrupt Control Register (I2C_ICTL) . 20-17 21 I2C Slave (I2CS) .21-1 Configuration of the I2C Slave Module . 21-1 I2C Slave I/O Pins . 21-2 I2C Slave Clock . 21-3 Initializing the I2C Slave. 21-4 21.4.1 Reset . 21-4 21.4.2 Setting the Slave Address . 21-4 21.4.3 Optional Functions . 21-4 21.5 Data Transmit/Receive Control . 21-6 21.6 I2C Slave Interrupt . 21-11 21.7 Details of Control Registers . 21-13 21.1 21.2 21.3 21.4 0x4360: I2C Slave Transmit Data Register (I2CS_TRNS) . 21-14 0x4362: I2C Slave Receive Data Register (I2CS_RECV) . 21-15 0x4364: I2C Slave Address Setup Register (I2CS_SADRS) . 21-16 0x4366: I2C Slave Control Register (I2CS_CTL). 21-17 vi EPSON S1C17602 S1C17602 TECHNICAL MANUAL CONTENTS 0x4368: I2C Slave Status Register (I2CS_STAT). 21-20 0x436a: I2C Slave Access Status Register (I2CS_ASTAT). 21-23 0x436c: I2C Slave Interrupt Control Register (I2CS_ICTL) . 21-24 21.8 Precautions . 21-25 22 Remote Controller (REMC) .22-1 22.1 22.2 22.3 22.4 22.5 22.6 22.7 REMC Configuration . 22-1 REMC Input/output Pin . 22-2 Carrier Generation. 22-3 Data Length Counter Clock Settings . 22-4 Data Transfer Control . 22-5 REMC Interrupts . 22-8 Control Register Details . 22-10 0x5340: REMC Configuration Register (REMC_CFG) . 22-11 0x5342: REMC Carrier Length Setup Register (REMC_CAR) . 22-13 0x5344: REMC Length Counter Register (REMC_LCNT). 22-14 0x5346: REMC Interrupt Control Register (REMC_INT) . 22-15 22.8 Precautions . 22-17 23 LCD Driver (LCD8) .23-1 23.1 LCD Driver Configuration . 23-1 23.2 LCD Power Supply. 23-2 23.3 LCD Clock . 23-3 23.3.1 LCD Operating Clock. 23-3 23.3.2 Frame Signal . 23-3 23.4 Driver Duty Switching . 23-4 23.5 Display Memory . 23-10 23.6 Display Control. 23-12 23.6.1 Display On/Off . 23-12 23.6.2 LCD Contrast Adjustment. 23-12 23.6.3 Inverted Display . 23-12 23.7 LCD Interrupt . 23-13 23.8 Control Register Details . 23-14 0x50a0: LCD Display Control Register (LCD_DCTL) . 23-15 0x50a1: LCD Contrast Adjust Register (LCD_CADJ) . 23-17 0x50a2: LCD Clock Control Register (LCD_CCTL) . 23-18 0x50a3: LCD Voltage Regulator Control Register (LCD_VREG). 23-19 0x50a5: LCD Interrupt Mask Register (LCD_IMSK) . 23-20 0x50a6: LCD Interrupt Flag Register (LCD_IFLG) . 23-21 23.9 Precautions . 23-22 24 A/D Converter (ADC10SA ADC10SA) .24-1 24.1 24.2 24.3 24.4 24.5 24.6 Outline of A/D Converter . 24-1 ADC Terminal . 24-2 A/D Converter Settings . 24-3 A/D Conversion Control and Operations . 24-6 A/D Converter Interrupt. 24-9 Controlling Register Details . 24-11 0x5380: ADC10 ADC10 Conversion Result Register (ADC10 ADC10_ADD) . 24-12 0x5382: ADC10 ADC10 Trigger/Channel Selection Register (ADC10 ADC10_TRG) . 24-13 0x5384: ADC10 ADC10 Control/Status Register (ADC10 ADC10_CTL) . 24-15 0x5386: ADC10 ADC10 Divided Frequency Register (ADC10 ADC10_DIV) . 24-17 24.7 Notes . 24-18 S1C17602 S1C17602 TECHNICAL MANUAL EPSON vii CONTENTS 25 RF Converters (RFC) .25-1 25.1 25.2 25.3 25.4 25.5 25.6 Overview of R/F Converter. 25-1 RFC pins . 25-2 Operation Mode . 25-3 Conversion Operations . 25-6 R/F Converter Interrupts . 25-9 Control Register Details . 25-11 0x53a0: RFC Control Register (RFC_CTL) . 25-12 0x53a2: RFC Oscillation Start Register (RFC_TRG) . 25-13 0x53a4/0x53a6: RFC Measurement Counter Data Register (RFC_MC) . 25-14 0x53a8/0x53aa: RFC Time Base Counter Data Register (RFC_TC) . 25-15 0x53ac: RFC Interrupt Mask Register (RFC_IMSK) . 25-16 0X53ae: RFC Interrupt Flag Register (RFC_IFLG) . 25-17 25.7 Precautions . 25-18 26 Power Supply Voltage Detection Circuit (SVD) .26-1 26.1 26.2 26.3 26.4 26.5 26.6 SVD Module Configuration . 26-1 SVD Clock . 26-2 Comparison Voltage Setting . 26-3 SVD Circuit Control . 26-4 SVD Interrupt . 26-5 Control Register Details . 26-6 0x5100: SVD Enable Register (SVD_EN) . 26-7 0x5101: SVD Compare Voltage Register (SVD_CMP) . 26-8 0x5102: SVD Detection Result Register (SVD_RSLT) . 26-9 0x5103: SVD Interrupt Mask Register (SVD_IMSK) . 26-10 0x5104: SVD Interrupt Flag Register (SVD_IFLG) . 26-11 26.7 Precautions . 26-12 27 On-chip Debugger (DBG) .27-1 27.1 27.2 27.3 27.4 Resource Requirements and Debugging Tool . 27-1 Debug Break Operation Status . 27-2 Additional Debugging Function . 27-3 Control Register Details . 27-4 0x5322: OSC1 Peripheral Control Register (MISC_OSC1) . 27-5 0x5326: IRAM Size Select Register (MISC_IRAMSZ). 27-6 0xffff90: Debug RAM Base Register (DBRAM) . 27-7 0xffffa0: Debug Control Register (DCR) . 27-8 0xffffb8: Instruction Break Address Register 2 (IBAR2) . 27-10 0xffffbc: Instruction Break Address Register 3 (IBAR3). 27-11 0xffffd0: Instruction Break Address Register 4 (IBAR4) . 27-12 28 Multiplier/Divider .28-1 28.1 28.2 28.3 28.4 28.5 28.6 Overview . 28-1 Operating Mode and Output Mode. 28-2 Multiplication . 28-3 Division. 28-4 Product-sum Operation . 28-5 Arithmetic Results Reading. 28-7 29 Electrical Characteristics .29-1 29.1 Absolute Maximum Ratings . 29-1 29.2 Recommended Operating Conditions . 29-1 29.3 Current Consumption. 29-2 viii EPSON S1C17602 S1C17602 TECHNICAL MANUAL CONTENTS 29.4 Input/Output Terminal Characteristics . 29-4 29.5 LCD Driver Circuit Characteristics . 29-6 29.6 SVD Circuit Characteristics. 29-9 29.7 A/D Converter Characteristics . 29-10 29.8 Flash Memory Characteristics . 29-11 29.9 SPI Characteristics . 29-12 29.10 I2C Characteristics . 29-13 29.11 External Clock Input Characteristics . 29-14 29.12 Oscillation Circuit Characteristics . 29-15 29.13 R/F Converter Characteristics . 29-16 30 Basic External Connection Diagram .30-1 31 Package .31-1 Appendix A: I/O Register List. AP-1 0x4020 0x4100­0x4125 0x4200­0x4208 0x4220­0x4268 0x4280­0x4288 0x4306­0x4318 0x4320­0x4326 0x4340­0x4346 0x4360­0x436c 0x5000­0x5003 0x5020­0x5023 0x5040­0x5041 0x5060­0x5067 0x5080­0x5081 0x50a0­0x50a6 0x50c0­0x50c4 0x5100­0x5104 0x5120 0x5200­0x52a8 0x5300­0x530c 0x5320­0x532a 0x5340­0x5346 0x5380­0x5386 0x53a0­0x53ae 0x53c0­0x53e7 0xffff84­0xffffd0 Prescaler. AP-5 UART (with IrDA) . AP-6 8-bit Timer (with Fine Mode) Ch.0 . AP-8 16-bit Timer . AP-9 8-bit Timer (with Fine Mode) Ch.1 . AP-11 AP-11 Interrupt Controller . AP-12 AP-12 SPI . AP-13 AP-13 I2C Master . AP-14 AP-14 I2C Slave . AP-15 AP-15 Clock Timer . AP-16 AP-16 Stopwatch Timer . AP-17 AP-17 Watchdog Timer . AP-18 AP-18 Oscillator . AP-19 AP-19 Clock Generator . AP-20 AP-20 LCD Driver . AP-21 AP-21 8-bit OSC1 Timer . AP-22 AP-22 SVD Circuit . AP-23 AP-23 Power Generator . AP-24 AP-24 P Port & Port MUX. AP-25 AP-25 PWM Timer . AP-29 AP-29 MISC Registers . AP-30 AP-30 Remote Controller . AP-31 AP-31 ADC10SA ADC10SA . AP-32 AP-32 RFC . AP-33 AP-33 SEGRAM . AP-34 AP-34 S1C17 S1C17 Core I/O . AP-35 AP-35 Appendix B: Flash Memory Programming . AP-36 AP-36 B.1 Debugger Programming . AP-36 AP-36 B.2 Self-programming via User Programs . AP-37 AP-37 Appendix C: Power Saving . AP-38 AP-38 C.1 Clock Control Power Saving . AP-38 AP-38 C.2 Reducing Power Consumption via Power Supply Control. AP-41 AP-41 Appendix D: Mounting Precautions . AP-42 AP-42 Appendix E: Initialization Routine . AP-46 AP-46 Appendix F: Recommended Oscillators . AP-48 AP-48 S1C17602 S1C17602 TECHNICAL MANUAL EPSON ix 1 Overview S1C17602 S1C17602 Technical Manual 1 Overview 1 Overview 1 Overview 1 Overview The S1C17602 S1C17602 is a 16-bit MCU featuring high-speed low-power operations, compact dimensions, wide address space and on-chip ICE. A/D converter and R/F converter are built in and sensor of various analog I/F can be connected. It is suitable for the application of health care product, sports watch and meter module etc. with sensor that is required a small size and micro display in the battery driven. *This product uses SuperFlash® technology licensed by Silicon Storage Technology, Inc. S1C17602 S1C17602 TECHNICAL MANUAL EPSON 1-1 1 Overview 1.1 Features The main features of the S1C17602 S1C17602 are listed below. CPU · Epson original 16-bit RISC CPU core S1C17 S1C17 · 16 bit x 16 bit + 32 bit product-sum operation, 16 bit ÷ 16bit division arithmetic unit IOSC oscillator circuit · 2.7MHz (typ.) · Oscillating start up 5 µs (max.) · Boot Clock (External components not required.) OSC3 oscillator circuit · Crystal oscillator circuit or ceramic oscillator circuit, 8.2 MHz (max.) or external clock input OSC1 oscillator circuit · Crystal oscillator circuit 32.768 kHz (typ.) Internal flash memory · 64 Kbytes (for both instructions and data) · Allows 1,000 rewrites (min.) · Read/write protection function · Allows onboard rewriting with the ICD Mini (S5U1C17702H S5U1C17702H) debug tool and self-rewriting via software. Internal RAM · 4 Kbytes Internal Display RAM · 40 bytes A/D Converter · 10 bit resolution 8ch R/F Converter · DC oscillation/AC oscillation/External input 2ch. Input/output port · Max. 36-bit general purpose input/output (shared with peripheral circuit input/output pins) Serial interface · SPI (master/slave) 1ch. · I2C (master) 1ch. · I2C (slave) 1ch. · UART (460,800bps, IrDA1.0 compatible) 2ch. · Remote controller (REMC) 1ch. Timer · 8-bit timer (T8F) 2ch. · 16-bit timer (T16) 3ch. · PWM timer (T16E) 1ch. · Clock timer (CT) 1ch. · Stopwatch timer (SWT) 1ch. · Watchdog timer (WDT) 1ch. · 8-bit OSC1 PWM timer (T8OSC1) 1ch. LCD driver · 36 SEG x 8 COM or 40 SEG x 4 COM (1/3 bias) · Internal booster power supply circuit (16-value programmable contrast) Power supply voltage detection (SVD) circuit · 15-value programmable (1.8 V to 3.2 V) Interrupt · NMI, P Port Input interrupt 3ch. · Serial Interface interrupt 5ch. · Timer interrupt 9ch. · LCD, SVD, ADC, RFC interrupt Power supply voltage · 1.8 V to 3.6 V (for normal operations) · 2.7 V to 3.6 V (for flash deletion/programing) · Including voltage regulator circuit (with binary programmable operating voltage) Operating temperatures · -25°C to 70°C Current consumption · SLEEP mode: 0.75 µA typ. (OSC1=OFF, IOSC=OFF, OSC3=OFF) · HALT mode: 2.5 µA typ. (OSC1=32kHz, IOSC=OFF, OSC3=OFF, PCKEN=0x0, LCD OFF) 3.5 µA typ. (OSC1=32kHz, IOSC=OFF, OSC3=OFF, PCKEN=0x0, LCD ON (All LCD On, maximum contrast, VC2 standard) · When operating: 15 µA typ. (OSC1=32kHz, IOSC=OFF, OSC3=OFF, LCD OFF) 410 µA typ. (OSC1=OFF, IOSC=OFF, OSC3=1MHz ceramic oscillator) Configuration as shipped · TQFP14-100 TQFP14-100 12 mm x 12 mm body, 0.4 mm pitch · VFBGA7H-144 VFBGA7H-144 7 mm x 7 mm, body, 0.5 mm pitch · Bare chip 100 µm pitch 1-2 EPSON S1C17602 S1C17602 TECHNICAL MANUAL 1 Overview 1 Overview 1.2 Block Diagram DCLK, DST2, DSIO(P41­43) CPU Core S1C17 S1C17 32 bits 1 cycle 8/16 bits 1 cycle Internal RAM (4K bytes) I/O 2 (0x5000­) Power generator TEST1­3 Flash memory (64K bytes) Display RAM (40 bytes) 16 bits 1­5 cycles R/F converter 16 bits 1 cycles A/D converter VDD, VSS, VD1, VC1­VC3, CA­CB RFIN0, REF0, SENA0, SENB0(P26­23) RFIN1, REF1, SENA1, SENB1(P27,P30­32), RFCLK0(P36) AIN0­7, #ADTRG (P22­20, P17­13, P03) SVD circuit #TEST Test circuit LCD driver Reset circuit 8/16 bits 1 cycle I/O 1 (0x4000­) Interrupt system #RESET SEG0­36/39, COM0­7/4 LFR0(P37) MISC register Oscillator/ Clock generator Interrupt controller 8-bit OSC1 PWM timer Prescaler Clock timer 8-bit timer Stopwatch timer EXCL0­2 (P02, P13, P14) 16-bit timer Watchdog timer SIN0, SOUT0, SCLK0(P12­10), SIN1, SOUT1, SCLK1(P30­29,P16) UART (2ch) 16-bit PWM timer SPI Remote controller SDA0, SCL0(P32­31) or (P34­33) I2C master (1ch) I/O port/ I/O MUX SDA1, SCL1(P34­33) #BFR(P35) OSC1­2, OSC3­4 FOUT1(P35), FOUTH(P40) I2C slave (1ch) SDI, SDO, SPICLK(P06­04) #SPISS(P07) TOUT4(P37) EXCL3(P15), TOUT3(P36), TOUTN3(P37) REMI(P01), REMO(P00) P00­07, P10­17, P20­27, P30­37, P40­43 Figure 1.2.1: Block diagram S1C17602 S1C17602 TECHNICAL MANUAL EPSON 1-3 1 Overview 1.3 Pins 1.3.1 Pinout Diagram #RESET 59 VDD P00/REMO P00/REMO 60 OSC4 P01/REMI P01/REMI 61 51 P02/EXCL0 P02/EXCL0 62 OSC3 P03/#ADTRG 63 52 P04/SPICLK P04/SPICLK 64 VSS P05/SDO P05/SDO 65 53 P06/SDI P06/SDI 66 54 P07/#SPISS 67 OSC2 P10/SCLK0 P10/SCLK0 68 VD1 P11/SOUT0 P11/SOUT0 69 55 P12/SIN0 P12/SIN0 70 56 P13/EXCL1/AIN7 P13/EXCL1/AIN7 71 #TEST P14/EXCL2/AIN6 P14/EXCL2/AIN6 72 OSC1 P15/EXCL3/AIN5 P15/EXCL3/AIN5 73 57 VSS 74 58 AVDD 75 TQFP14-100pin P16/SCLK1/AIN4 P16/SCLK1/AIN4 76 50 VSS P17/AIN3 P17/AIN3 77 49 VC1 P20/AIN2 P20/AIN2 78 48 VC2 P21/AIN1 P21/AIN1 79 47 VC3 P22/AIN0 P22/AIN0 80 46 CA VDD 81 45 CB P23/SENB0 P23/SENB0 82 44 TEST2 P24/SENA0 P24/SENA0 83 43 COM0 P25/REF0 P25/REF0 84 42 COM1 P26/RFIN0 P26/RFIN0 85 41 COM2 VSS 86 40 COM3 P27/SOUT1/RFIN1 P27/SOUT1/RFIN1 87 39 SEG39/COM4 SEG39/COM4 P30/ SIN1/REF1 88 38 SEG38/COM5 SEG38/COM5 1 18 19 20 21 22 23 24 25 SEG1 SEG19 SEG19 SEG20 SEG20 SEG21 SEG21 SEG22 SEG22 SEG23 SEG23 SEG24 SEG24 SEG25 SEG25 SEG26 SEG26 SEG18 SEG18 26 17 SEG27 SEG27 100 SEG0 SEG17 SEG17 27 16 99 SEG16 SEG16 SEG28 SEG28 DCLK/P43 DCLK/P43 15 28 SEG15 SEG15 98 14 SEG29 SEG29 DST2/P42 DST2/P42 SEG14 SEG14 29 13 97 SEG13 SEG13 SEG30 SEG30 DSIO/P41 DSIO/P41 12 30 SEG12 SEG12 96 11 SEG31 SEG31 P40/FOUTH P40/FOUTH SEG11 SEG11 31 10 95 SEG10 SEG10 SEG32 SEG32 P37/TOUTN3/LFRO/TOUT4 P37/TOUTN3/LFRO/TOUT4 9 32 SEG9 94 8 SEG33 SEG33 P36/TOUT3/RFCLKO P36/TOUT3/RFCLKO SEG8 33 7 93 SEG7 SEG34 SEG34 P35/ FOUT1/#BFR 6 34 SEG6 92 5 SEG35 SEG35 P34/SDA1/SDA0 P34/SDA1/SDA0 SEG5 35 4 91 SEG4 SEG36/COM7 SEG36/COM7 P33/SCL1/SCL0 P33/SCL1/SCL0 3 SEG37/COM6 SEG37/COM6 36 SEG3 37 90 2 89 SEG2 P31/SCL0/SENA1 P31/SCL0/SENA1 P32/SDA0/SENB1 P32/SDA0/SENB1 Figure 1.3.1.1: Pinout diagram TQFP14-100pin 1-4 EPSON S1C17602 S1C17602 TECHNICAL MANUAL 1 Overview 1 Overview VFBGA7H-144 VFBGA7H-144 2 3 4 DCLK 1 DST2 DSIO 5 6 7 8 VSS P27 P34 P37 9 10 VDD P26 11 P21 12 13 P16 A A N.C. N.C. SEG0 SEG1 P24 P30 P31 P33 P36 VSS VSS P22 P20 AVDD VSS B B SEG4 SEG3 SEG2 VSS P32 P35 P40 VSS P25 P23 P17 P15 P14 C C SEG6 SEG5 VSS VSS VSS VSS VSS VSS VSS VSS VDD P13 P12 D D SEG7 SEG8 VSS VDD VSS VDD P11 P10 E E SEG10 SEG10 SEG11 SEG11 SEG9 VDD VSS VDD P07 P06 F F SEG13 SEG13 SEG14 SEG14 SEG12 SEG12 VSS VSS P05 P04 P03 Top View G SEG16 SEG16 SEG15 SEG15 VSS G VDD VSS P02 P01 P00 H H SEG18 SEG18 SEG17 SEG17 VSS VDD VSS VDD #TEST #RESET J J SEG21 SEG21 SEG20 SEG20 SEG19 SEG19 VDD VSS VSS VSS VSS VSS VD1 VSS OSC1 OSC2 K K SEG23 SEG23 SEG22 SEG22 SEG29 SEG29 VSS SEG32 SEG32 COM6 COM3 COM0 TEST1 VDD VDD VC3 VSS L L SEG25 SEG25 SEG24 SEG24 SEG27 SEG27 SEG30 SEG30 SEG34 SEG34 COM7 COM4 COM1 TEST2 CA VC1 OSC3 OSC4 M M SEG26 SEG26 SEG28 SEG28 SEG31 SEG31 SEG33 SEG33 SEG35 SEG35 COM5 COM2 TEST3 CB VSS VC2 N N N.C. 1 N.C. 2 3 4 5 6 7 8 9 10 11 12 13 Figure 1.3.1.2: Pinout diagram VFBGA7HX-144pin S1C17602 S1C17602 TECHNICAL MANUAL EPSON 1-5 1 Overview CHIP-118pad Note: are is NC pad is a die number. 1-6 Opening of Pad Pad No. 129, 608887×85m Pad No. 3059, 8911885×87m Chip thickness 400 m EPSON S1C17602 S1C17602 TECHNICAL MANUAL 1 Overview 1 Overview Pad Coordinates PAD No. X (mm) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 -1.400 -1.300 -1.200 -1.100 -1.000 -0.900 -0.800 -0.700 -0.600 -0.500 -0.400 -0.300 -0.200 -0.100 0.000 0.100 0.200 0.300 0.400 0.500 0.600 0.700 0.800 0.900 1.000 1.100 1.200 1.300 1.400 1.849 1.849 1.849 1.849 1.849 1.849 1.849 1.849 1.849 1.849 1.849 1.849 1.849 1.849 1.849 1.849 1.849 1.849 1.849 1.849 1.849 Y (mm) Assignment PAD No. X (mm) -1.827 -1.827 -1.827 -1.827 -1.827 -1.827 -1.827 -1.827 -1.827 -1.827 -1.827 -1.827 -1.827 -1.827 -1.827 -1.827 -1.827 -1.827 -1.827 -1.827 -1.827 -1.827 -1.827 -1.827 -1.827 -1.827 -1.827 -1.827 -1.827 -1.430 -1.330 -1.230 -1.130 -1.030 -0.930 -0.830 -0.730 -0.630 -0.530 -0.430 -0.330 -0.230 -0.130 -0.030 0.070 0.170 0.270 0.370 0.470 0.570 S1C17602 S1C17602 TECHNICAL MANUAL NC SEG1 NC SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG10 SEG11 SEG11 SEG12 SEG12 SEG13 SEG13 SEG14 SEG14 SEG15 SEG15 SEG16 SEG16 SEG17 SEG17 SEG18 SEG18 SEG19 SEG19 SEG20 SEG20 SEG21 SEG21 SEG22 SEG22 SEG23 SEG23 SEG24 SEG24 NC SEG25 SEG25 NC NC SEG26 SEG26 NC SEG27 SEG27 NC SEG28 SEG28 SEG29 SEG29 SEG30 SEG30 SEG31 SEG31 SEG32 SEG32 SEG33 SEG33 SEG34 SEG34 SEG35 SEG35 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1.849 1.849 1.849 1.849 1.849 1.849 1.849 1.849 1.849 1.500 1.400 1.300 1.200 1.000 0.900 0.800 0.700 0.600 0.500 0.400 0.300 0.200 0.100 0.000 -0.100 -0.200 -0.300 -0.400 -0.500 -0.600 -0.700 -0.800 -0.900 -1.000 -1.100 -1.200 -1.300 -1.400 -1.849 -1.849 -1.849 -1.849 -1.849 -1.849 -1.849 -1.849 -1.849 -1.849 -1.849 -1.849 Y (mm) Assignment PAD No. X (mm) 0.670 0.770 0.870 0.970 1.070 1.170 1.270 1.370 1.480 1.827 1.827 1.827 1.827 1.827 1.827 1.827 1.827 1.827 1.827 1.827 1.827 1.827 1.827 1.827 1.827 1.827 1.827 1.827 1.827 1.827 1.827 1.827 1.827 1.827 1.827 1.827 1.827 1.827 1.470 1.370 1.270 1.170 1.070 0.970 0.870 0.770 0.670 0.570 0.470 0.370 EPSON TEST3 TEST2 TEST1 CB CA VC3 VC2 VC1 VSS VDD OSC4 OSC3 VSS VD1 OSC2 OSC1 #TEST #RESET NC P00 NC P01 P02 P03 P04 P05 P06 P07 P10 P11 NC P12 NC P13 P14 P15 VSS AVDD P16 P17 P20 P21 P22 VDD P23 P24 P25 P26 VSS NC 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 -1.849 -1.849 -1.849 -1.849 -1.849 -1.849 -1.849 -1.849 -1.849 -1.849 -1.849 -1.849 -1.849 -1.849 -1.849 -1.849 -1.849 -1.849 Y (mm) Assignment 0.270 0.170 0.070 -0.030 -0.130 -0.230 -0.330 -0.430 -0.530 -0.630 -0.730 -0.830 -0.930 -1.030 -1.130 -1.230 -1.330 -1.430 P27 P30 P31 P32 P33 P34 P35 P36 P37 NC P40 DSIO DST2 NC DCLK NC SEG0 NC 1-7 1 Overview 1.3.2 Pin Descriptions Table 1.3.2.1: Pin descriptions PAD/Pin/Ball No. CHIP TQFP VFBGA 2 *6 *7 1-35 36-39 *7 51 52 53 54 55 56 57 58 59 60 61 62 40-43 44 45 46 47 48 49 50 51 52 53 63 64 65 66 67 68 70 72 73 74 75 76 77 78 79 80 82 84 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 K11 K13 K12 J12 J13 H13 H12 H11 G13 G12 G11 F13 F12 E13 E12 D13 D12 85 72 C13 86 73 C12 87 88 89 74 75 76 B13 A12 90 91 92 93 94 95 96 97 98 99 101 77 78 79 80 81 82 83 84 85 86 87 C11 B11 A11 B10 102 88 B8 1-8 3 3 N9 M9 L9 N10 M10 L10 N11 M11 4 5 M13 M12 4 4 5 C10 B9 C9 A9 4 A7 Name I/O Default status SEG1-35 SEG1-35 COM7-4/ SEG36-39 SEG36-39 COM3-0 TEST3 TEST2 TEST1 CB CA VC3 VC2 VC1 VSS VDD OSC4 OSC3 O O O(L) O(L) LCD segment output LCD common output1 /LCD segment output O - O(L) - - - O I O I VSS VD1 OSC2 OSC1 #TEST #RESET P00/REMO P00/REMO P01/REMI P01/REMI P02/ EXCL0 P03/#ADTRG P04/SPICLK P04/SPICLK P05/SDO P05/SDO P06/SDI P06/SDI P07/#SPISS P10/SCLK0 P10/SCLK0 P11/SOUT0 P11/SOUT0 P12/SIN0 P12/SIN0 P13/EXCL1/ P13/EXCL1/ AIN7 P14/EXCL2/ P14/EXCL2/ AIN6 P15/ EXCL3/ AIN5 VSS AVDD P16/SCLK1/ P16/SCLK1/ AIN4 P17/AIN3 P17/AIN3 P20/AIN2 P20/AIN2 P21/AIN1 P21/AIN1 P22/AIN0 P22/AIN0 VDD P23/SENB0 P23/SENB0 P24/SENA0 P24/SENA0 P25/REF0 P25/REF0 P26/RFIN0 P26/RFIN0 VSS P27/SOUT1/ P27/SOUT1/ RFIN1 P30/STN1/ P30/STN1/ REF1 O I I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O I I(Pull-UP) I(Pull-UP) I(Pull-UP) I(Pull-UP) I(Pull-UP) I(Pull-UP) I(Pull-UP) I(Pull-UP) I(Pull-UP) I(Pull-UP) I(Pull-UP) I(Pull-UP) I(Pull-UP) I(Pull-UP) I/O I(Pull-UP) I/O I(Pull-UP) I/O I/O I(Pull-UP) I(Pull-UP) I/O I/O I/O I/O I/O I/O I/O I/O I/O I(Pull-UP) I(Pull-UP) I(Pull-UP) I(Pull-UP) I(Pull-UP) I(Pull-UP) I(Pull-UP) I(Pull-UP) I(Pull-UP) I/O I(Pull-UP) LCD common output Test pin (open it) 8 Test pin (open it or fixed to VDD Test pin (open it) LCD booster capacitor connector LCD booster capacitor connector LCD circuit drive voltage output LCD circuit drive voltage output LCD circuit drive voltage output Power supply (-) Digital power supply (+) OSC3 oscillator output OSC3 oscillator input external clock input of VDD-VSS level is also available Power supply (-) Internal logic and oscillator circuit constant-voltage circuit output OSC1 oscillator output OSC1 oscillator input Test pin (fixed to VDD) Initial set input I/O common port (with inturrupt) 1/REMC output I/O common port (with inturrupt)1/REMC input I/O common port (with inturrupt)1/T16 1/T16 Ch0 external clock input I/O common port (with inturrupt)1/ A/D convert external trigger I/O common port (with inturrupt)1/SPI clock I/O I/O common port (with inturrupt)1/SPI data output I/O common port (with inturrupt)1/SPI data input I/O common port (with inturrupt)1/SPI slave select input I/O common port (with inturrupt)1/UART Ch0 clock input I/O common port (with inturrupt)1/UART Ch0 data output I/O common port (with inturrupt)1/UART Ch0 data input I/O common port (with inturrupt)1/T16 1/T16 Ch1 external clock input/ AD converter Ch7 input I/O common port (with inturrupt)1/T16 1/T16 Ch2 external clock input/ AD converter Ch6 input I/O common port (with inturrupt)1/T16E 1/T16E Ch0 external clock input/AD converter Ch5 input Power supply (-) Analog power supply (+) I/O common port (with inturrupt)1/UART Ch1 external clock input/AD converter Ch4 input I/O common port (with inturrupt)1/ A/D converter Ch3 input I/O common port1/ A/D converter Ch2 input I/O common port1/ A/D converter Ch1 input I/O common port1/ A/D converter Ch0 input Power supply (+) I/O common port1/for R/F converter Ch.0 I/O common port1/for R/F converter Ch.0 I/O common port1/for R/F converter Ch.0 I/O common port1/for R/F converter Ch.0 Power supply (-) I/O common port1/UART Ch1 external clock output / for R/F converter Ch.1 I/O common port1UART Ch1 external clock input / for R/F converter Ch.1 Function EPSON S1C17602 S1C17602 TECHNICAL MANUAL 1 Overview PAD/Pin/Ball No. CHIP TQFP VFBGA 103 89 B7 104 90 C7 105 91 B6 106 92 A6 107 93 C6 108 94 B5 109 95 A5 111 112 113 115 *6 96 97 98 99 100 C5 A4 A3 A2 2 1 Overview Name I/O Default status P31/SCL0/ P31/SCL0/ SENA1 P32/SDA0/ P32/SDA0/ SENB1 P33/SCL1/ P33/SCL1/ SCL0 P34/SDA1/ P34/SDA1/ SDA0 P35/ FOUT1/ #BFR P36/TOUT3/ P36/TOUT3/ RFCLKO P37/TOUTN3/ P37/TOUTN3/ LFRO/TOUT4 P40/FOUTH P40/FOUTH DSIO/P41 DSIO/P41 DST2/P42 DST2/P42 DCLK/P43 DCLK/P43 SEG0 I/O I(Pull-UP) I/O I(Pull-UP) I/O I(Pull-UP) I/O common port1/I2C master clock output/ for R/F converter Ch.1 I/O common port1/I2C master data I/O /for R/F converter Ch.1 I/O common port1/I2C slave clock input/I2C master clock output I/O I(Pull-UP) I/O common port1/I2C slave data I/O /I2C master data I/O I/O I(Pull-UP) I/O I(Pull-UP) I/O I(Pull-UP) I/O I/O I/O I/O O I(Pull-UP) I(Pull-UP) O(L) O(H) O(L) I/O common port1/OSC1 external clock output/I2C slave bus open I/O common port1/T16E Ch0 PWM signal output (non-inverted)/ R/F clock output terminal I/O common port1/T16E Ch0 PWM signal output (inverted)/LCD flame output /T8OSC1 PWM signal output terminal I/O common port1/HSCLK clock output (with divide) On-chip debugger data I/O1/I/O common port On-chip debugger status output1/I/O common port On-chip debugger clock output1/I/O common port LCD segment output Function *1: Default function settings *2: SEG0 to 35 ball numbers (VFBGA) SEG No. Ball No. SEG No. Ball No. SEG No. Ball No. 0 B2 16 H1 32 L5 1 B1 17 J2 33 N5 2 C3 18 J1 34 M5 3 C1 19 K3 35 N6 4 C2 20 K2 5 D1 21 K1 6 D2 22 L2 7 E2 23 L1 4 M7 5 N7 6 L6 8 E1 24 M2 9 F3 25 M1 10 F1 26 N2 11 F2 27 M3 12 G3 28 N3 13 G1 29 L4 14 G2 30 M4 15 H2 31 N4 7 M6 *3: COM7 to 0 ball numbers (VFBGA) COM No. Ball No. 0 L8 1 M8 2 N8 3 L7 *4: VSS ball numbers B3, D3, E3,H3, J3, L3, 4B, 4C, 4D, 4E, 4F, 4G, 4H, 4J, 4K, D5, K5, D6, K6, D7, K7, A8, C8, D8, K8, D9, D10, G10, K10, B12, N12, L13 5: VDD ball numbers K9, A10, E10, F10, H10, J10, D11, E11, F11, J11, L11, L12 6: SEG0 to 35 PAD numbers. CHIP SEG No. PAD No. SEG No. PAD No. SEG No. PAD No. 0 117 16 18 32 39 1 2 17 19 33 40 2 4 18 20 34 41 3 5 19 21 35 42 4 6 20 22 5 7 21 23 6 8 22 24 7 9 23 25 4 46 5 45 6 44 8 10 24 26 9 11 25 28 10 12 26 31 11 13 27 33 12 14 28 35 13 15 29 36 14 16 30 37 15 17 31 38 7 43 7: COM7 to 0 PAD numbers CHIP COM No. PAD No. 0 50 1 49 2 48 3 47 8: Note: When using mask ROM items (such as S1C17121 S1C17121) and boards for common, be sure to set the test 2 pin to open. Note: Do not perform any bonding in NC Pin of VFBGA and CHIP. S1C17602 S1C17602 TECHNICAL MANUAL EPSON 1-9 1 Overview This page intentionally left blank. 1-10 EPSON S1C17602 S1C17602 TECHNICAL MANUAL 2 CPU S1C17602 S1C17602 Technical Manual 2 CPU 2 CPU 2 CPU 2 CPU The S1C17602 S1C17602 uses an S1C17 S1C17 core as the core processor. The S1C17 S1C17 core is an original Seiko Epson 16-bit RISC processor. It features low power consumption, high-speed operation, wide address space, main instructions single-clock execution, and gate-saving design. It is ideal for use in controllers or sequencers, in which 8-bit CPUs are widely used. For detailed information on the S1C17 S1C17 core, refer to the S1C17 S1C17 Family S1C17 S1C17 Core Manual. 2.1 S1C17 S1C17 Core Features Processor type · Seiko Epson original 16-bit RISC processor · 0.35 µm to 0.15 µm low-power CMOS process technology Instruction set · Code length Fixed 16-bit length · Number of instructions 111 basic instructions (184 in total) · Execution cycle Main instructions executed in one cycle · Immediate expansion instructions Expansion of immediate to 24 bits · Compact, high-speed instruction set optimized for development with C Register set · 24-bit general purpose register x 8 · 24-bit special register x 2 · 8-bit special register x 1 Memory space, buses · Up to 16 Mbytes of memory space (24-bit address) · Harvard architecture with separate instruction bus (16-bit) and data bus (32-bit) Interrupt · Supports reset, NMI, and 32 different types of external interrupt · Irregular address interrupt · Debug interrupt · Reading vector from vector table and direct branching to interrupt processing routines · Permits software interrupts using vector numbers (all vector numbers can be specified) Power saving · HALT (halt instruction) · SLEEP (slp instruction) Coprocessor interface · 16 bits x 16 bits + 32 bits product-sum arithmetic unit · 16 bits/16 bits division arithmetic unit S1C17602 S1C17602 TECHNICAL MANUAL EPSON 2-1 2 CPU 2.2 CPU Registers The S1C17 S1C17 core contains eight general purpose registers and three special registers. Special registers General purpose registers Bit 23 Bit 0 Bit 23 7 6 5 4 3 2 1 0 PC SP PSR 7 6 IL[2:0] 5 4 IE 3 C 2 V 1 Z 0 N Bit 0 R7 R6 R5 R4 R3 R2 R1 R0 Figure 2.2.1: Registers 2-2 EPSON S1C17602 S1C17602 TECHNICAL MANUAL 2 CPU 2.3 Instruction Set 2 CPU The S1C17 S1C17 core instruction codes are all 16-bit and fixed-length. Major instructions are executed in a single cycle using pipeline processing. For more information on the various instructions, refer to the S1C17 S1C17 Family S1C17 S1C17 Core Manual. Table 2.3.1: S1C17 S1C17 core instruction list Type Data transfer ld.b ld.ub ld ld.a Mnemonic %rd,%rs %rd,[%rb] %rd,[%rb]+ %rd,[%rb]%rd,-[%rb] %rd,[%sp+imm7] %rd,[imm7] [%rb],%rs [%rb]+,%rs [%rb]-,%rs -[%rb],%rs [%sp+imm7],%rs [imm7],%rs %rd,%rs %rd,[%rb] %rd,[%rb]+ %rd,[%rb]%rd,-[%rb] %rd,[%sp+imm7] %rd,[imm7] %rd,%rs %rd,sign7 %rd,[%rb] %rd,[%rb]+ %rd,[%rb]%rd,-[%rb] %rd,[%sp+imm7] %rd,[imm7] [%rb],%rs [%rb]+,%rs [%rb]-,%rs -[%rb],%rs [%sp+imm7],%rs [imm7],%rs %rd,%rs %rd,imm7 %rd,[%rb] %rd,[%rb]+ %rd,[%rb]%rd,-[%rb] %rd,[%sp+imm7] %rd,[imm7] [%rb],%rs [%rb]+,%rs [%rb]-,%rs -[%rb],%rs [%sp+imm7],%rs [imm7],%rs %rd,%sp %rd,%pc %rd,[%sp] %rd,[%sp]+ %rd,[%sp]%rd,-[%sp] S1C17602 S1C17602 TECHNICAL MANUAL Function General purpose register (byte) General purpose register (sign extension) Memory (byte) General purpose register (sign extension) Memory address post-increment/post-decrement A pre-decrement function can be used Stack (byte) General purpose register (sign extension) Memory (byte) General purpose register (sign extension) General purpose register (byte) Memory Memory address post-increment/post-decrement A pre-decrement function can be used General purpose register (byte) Stack General purpose register (byte) Memory General purpose register (byte) General purpose register (zero extension) Memory (byte) General purpose register (zero extension) Memory address post-increment/post-decrement A pre-decrement function can be used Stack (byte) General purpose register (zero extension) Memory (byte) General purpose register (zero extension) General purpose register (16 bits) General purpose register Immediate General purpose register (sign extension) Memory (16 bits) General purpose register Memory address post-increment/post-decrement A pre-decrement function can be used Stack (16 bits) General purpose register Memory (16 bits) General purpose register General purpose register (16 bits) Memory Memory address post-increment/post-decrement A pre-decrement function can be used General purpose register (16 bits) Stack General purpose register (16 bits) Memory General purpose register (24 bits) General purpose register Immediate General purpose register (zero extension) Memory (32 bits) General purpose register (*1) Memory address post-increment/post-decrement A pre-decrement function can be used Stack (32 bits) General purpose register (*1) Memory (32 bits) General purpose register (*1) General purpose register (32 bits, zero extension) Memory (*1) Memory address post-increment/post-decrement A pre-decrement function can be used General purpose register (32 bits, zero extension) Stack (*1) General purpose register (32 bits, zero extension) Memory (*1) SP General purpose register PC General purpose register Stack (32 bits) General purpose register (*1) Stack pointer post-increment/post-decrement A pre-decrement function can be used EPSON 2-3 2 CPU Type Data transfer ld.a Mnemonic [%sp],%rs [%sp]+,%rs [%sp]-,%rs -[%sp],%rs %sp,%rs %sp,imm7 %rd,%rs Integer arithmetic add add/c add/nc add %rd,imm7 add.a %rd,%rs add.a/c add.a/nc add.a %sp,%rs %rd,imm7 %sp,imm7 adc %rd,%rs adc/c adc/nc adc %rd,imm7 sub %rd,%rs sub/c sub/nc sub %rd,imm7 sub.a %rd,%rs sub.a/c sub.a/nc sub.a %sp,%rs %rd,imm7 %sp,imm7 sbc %rd,%rs sbc/c sbc/nc sbc %rd,imm7 cmp %rd,%rs cmp/c cmp/nc cmp %rd,sign7 cmp.a %rd,%rs cmp.a/c cmp.a/nc cmp.a %rd,imm7 cmc %rd,%rs cmc/c cmc/nc cmc %rd,sign7 %rd,%rs Logic operations and and/c and/nc and %rd,sign7 or %rd,%rs or/c or/nc or %rd,sign7 xor %rd,%rs xor/c xor/nc xor %rd,sign7 not %rd,%rs not/c not/nc not %rd,sign7 2-4 Function General purpose register (32 bits, zero extension) Stack (*1) Stack pointer post-increment/post-decrement A pre-decrement function can be used General purpose register (24 bits) SP Immediate SP Adds 16 bits between general purpose registers Supports conditional execution (/c: Executed when C = 1, /nc: Executed when C = 0) Adds general purpose register and immediate 16 bits Adds 24 bits between general purpose registers Supports conditional execution (/c: Executed when C = 1, /nc: Executed when C = 0) Adds SP and general purpose register 24 bits Adds general purpose register and immediate 24 bits Adds SP and immediate 24 bits Adds 16 bits with carry between general purpose registers Supports conditional execution (/c: Executed when C = 1, /nc: Executed when C = 0) Adds general purpose register and immediate 16 bits with carry Subtracts 16 bits between general purpose registers Supports conditional execution (/c: Executed when C = 1, /nc: Executed when C = 0) Subtracts general purpose register and immediate 16 bits Subtracts 24 bits between general purpose registers Supports conditional execution (/c: Executed when C = 1, /nc: Executed when C = 0) Subtracts SP and general purpose register 24 bits Subtracts general purpose register and immediate 24 bits Subtracts SP and immediate 24 bits Subtracts 16 bits with carry between general purpose registers Supports conditional execution (/c: Executed when C = 1, /nc: Executed when C = 0) Subtracts general purpose register and immediate 16 bits with carry Compares 16 bits between general purpose registers Supports conditional execution (/c: Executed when C = 1, /nc: Executed when C = 0) Compares general purpose registers and immediate 16 bits Compares 24 bits between general purpose registers Supports conditional execution (/c: Executed when C = 1, /nc: Executed when C = 0) Compares general purpose registers and immediate 24 bits Compares 16 bits with carry between general purpose registers Supports conditional execution (/c: Executed when C = 1, /nc: Executed when C = 0) Compares general purpose register and immediate 16 bits with carry AND operation between general purpose registers Supports conditional execution (/c: Executed when C = 1, /nc: Executed when C = 0) AND operation for general purpose register and immediate OR operation between general purpose registers Supports conditional execution (/c: Executed when C = 1, /nc: Executed when C = 0) OR operation for general purpose register and immediate EXCLUSIVE OR between general purpose registers Supports conditional execution (/c: Executed when C = 1, /nc: Executed when C = 0) EXCLUSIVE OR for general purpose register and immediate NOT operation between general purpose registers (1 complement) Supports conditional execution (/c: Executed when C = 1, /nc: Executed when C = 0) NOT operation for general purpose register and immediate (1 complement) EPSON S1C17602 S1C17602 TECHNICAL MANUAL 2 CPU Type Shift & swap sr sa sl swap Immediate extension ext cv.ab Conversion cv.as cv.al cv.la cv.ls jpr Branch jpr.d jpa ipa.d jrgt jrgt.d jrge jrge.d jrlt jrlt.d jrle jrle.d jrugt jrugt.d jruge jruge.d jrult jrult.d jrule jrule.d jreq jreq.d jrne jrne.d call call.d calla calla.d ret ret.d int intl reti reti.d brk retd nop System control halt slp ei di ld.cw Coprocessor control ld.ca ld.cf Mnemonic %rd,%rs %rd,imm7 %rd,%rs %rd,imm7 %rd,%rs %rd,imm7 %rd,%rs imm13 %rd,%rs %rd,%rs %rd,%rs %rd,%rs %rd,%rs sign10 %rb imm7 %rb sign7 sign7 sign7 sign7 sign7 sign7 sign7 sign7 sign7 sign7 sign10 %rb imm7 %rb imm5 imm5,imm3 %rd,%rs %rd,imm7 %rd,%rs %rd,imm7 %rd,%rs %rd,imm7 Function Right logic shift (shift bit number specified by register) Right logic shift (shift bit number specified by immediate) Right operation shift (shift bit number specified by register) Right operation shift (shift bit number specified by immediate) Left logic shift (shift bit number specified by register) Left logic shift (shift bit number specified by immediate) Byte swap at 16-bit boundary Extend operand for next instruction Convert 8-bit coded data to 24 bits Convert 16-bit coded data to 24 bits Convert 32-bit data to 24 bits Convert 24-bit data to 32 bits Convert 16-bit data to 32 bits PC-relative jump Allows delayed branching Absolute jump Allows delayed branching Conditional PC-relative jump Branch conditions: !Z & !(N ^ V) Allows delayed branching Conditional PC-relative jump Branch conditions: !(N ^ V) Allows delayed branching Conditional PC-relative jump Branch conditions: N ^ V Allows delayed branching Conditional PC-relative jump Branch conditions: Z | N ^ V Allows delayed branching Conditional PC-relative jump Branch conditions: !Z & !C Allows delayed branching Conditional PC-relative jump Branch conditions: !C Allows delayed branching Conditional PC-relative jump Branch conditions: C Allows delayed branching Conditional PC-relative jump Branch conditions: Z | C Allows delayed branching Conditional PC-relative jump Branch conditions: Z Allows delayed branching Conditional PC-relative jump Branch conditions: !Z Allows delayed branching PC-relative subroutine call Allows delayed branching Absolute subroutine call Allows delayed branching Return from subroutine Allows delayed branching Software interrupt Software interrupt with interrupt level specification Return from interrupt Allows delayed branching Debug interrupt Return from debug processing No operation HALT SLEEP Permits interrupt Prevents interrupt Transfer data to coprocessor 2 CPU Transfer data to coprocessor and obtain results and flag status Transfer data to coprocessor and obtain flag status 1 Instruction ld.a accesses 32-bit memory. When data is transferred from register to memory, 32 bits of data with the first 8 bits set to 0 are written to memory. When data is read from memory, the first 8 bits are ignored. S1C17602 S1C17602 TECHNICAL MANUAL EPSON 2-5 2 CPU The codes used in this table are explained below. Table 2.3.2: Code meanings Code %rs %rd [%rb] [%rb]+ [%rb]-[%rb] %sp [%sp],[%sp+imm7] [%sp]+ [%sp]-[%sp] imm3,imm5,imm7,imm13 sign7,sign10 2-6 Description General purpose source register General purpose destination register Memory specified indirectly by general purpose register Memory specified indirectly by general purpose register (with address post-increment) Memory specified indirectly by general purpose register (with address post-decrement) Memory specified indirectly by general purpose register (with address pre-decrement) Stack pointer Stack Stack (with address post-increment) Stack (with address post-decrement) Stack (with address pre-decrement) Immediate without code (number indicates bit length) Immediate with code (number indicates bit length) EPSON S1C17602 S1C17602 TECHNICAL MANUAL 2 CPU 2.4 Vector Table 2 CPU The vector table contains the vectors (processing routine start addresses) for interrupt processing routines. When an interrupt occurs, the S1C17 S1C17 core reads the vector corresponding to the interrupt and executes that processing routine. The boot address for starting program execution must be written at the top of the vector table after resetting. The S1C17602 S1C17602 vector table starts from address 0x8000. The vector table base address can be read from the TTBR (vector table base register) at address 0xffff80. For more information on Vector Table, refer to "6. Interrupt Controller" The base (top) address for the vector table for writing interrupt vectors can be set using the MISC_TTBRL and MISC_TTBRH registers (0x5328 and 0x532a). The MISC_TTBRL and MISC_TTBRH registers are set to the 0x8000 address after initial resetting. This means only the reset vector must be written to the above address, even when changing the vector table location. Bits 7 to 0 in the MISC_TTBRL register are fixed to 0; the initial address of the vector table normally starts from the 256 byte boundary. 0x5328­0x532a: Vector Table Address Low/High Registers (MISC_TTBRL, MISC_TTBRH) Setting Init. R/W Vector Table Address Low Register (MISC_TTBRL) Register name Address 0x5328 (16 bits) D15­8 TTBR[15:8] Vector table base address A[15:8] D7­0 TTBR[7:0] Vector table base address A[7:0] (fixed at 0) Bit Name Function 0x0­0xff 0x0 0x80 R/W 0x0 R Remarks Vector Table Address High Register (MISC_TTBRH) 0x532a (16 bits) D15­8 ­ reserved D7­0 TTBR[23:16] Vector table base address A[23:16] ­ 0x0­0xff ­ ­ 0 when being read. 0x0 R/W Note: The MISC_TTBRL and MISC_TTBRH registers are write-protected. To write to these registers, write-protection must be overridden by writing 0x96 to the MISC Protect Register (0x5324). Normally, the MISC Protect Register (0x5324) should be set to a value other than 0x96, except when writing to the MISC_TTBRL and MISC_TTBRH registers, since unnecessary writes may result in system malfunctions. S1C17602 S1C17602 TECHNICAL MANUAL EPSON 2-7 2 CPU 2.5 PSR Readout The S1C17602 S1C17602 incorporates a PSR register (0x532c) for reading out the contents of the PSR (Processor Status Register) in the S1C17 S1C17 core. Reading out the contents of this register makes it possible to check the contents of the PSR using application software. Note that data cannot be written to the PSR. 0x532c: PSR Register (MISC_PSR) Register name Address PSR Register (MISC_PSR) 0x532c (16 bits) Bit D15­8 D7­5 D4 D3 D2 D1 D0 Name ­ PSRIL[2:0] PSRIE PSRC PSRV PSRZ PSRN Function reserved PSR interrupt level (IL) bits PSR interrupt enable (IE) bit PSR carry (C) flag PSR overflow (V) flag PSR zero (Z) flag PSR negative (N) flag Setting 1 1 1 1 1 Init. R/W ­ 0x0 to 0x7 1 (enable) 0 0 (disable) 1 (set) 0 0 (cleared) 1 (set) 0 0 (cleared) 1 (set) 0 0 (cleared) 1 (set) 0 0 (cleared) D[7:5] PSRC: PSR Carry (C) Flag Read out the value of the PSR C (carry) flag. 1(R): 1 0(R): 0 (default) D2 PSRV: PSR Overflow (V) Flag Read out the value of the PSR V (overflow) flag. 1(R): 1 0(R): 0 (default) D1 PSRZ: PSR Zero (Z) Flag Read out the value of the PSR Z (zero) flag. 1(R): 1 0(R): 0 (default) D0 Remarks 0 when being read. PSRIE: PSR Interrup Enable (IE) Bit Read out the value (interrupt enable) of the PSR IE bit. 1(R): 1 (Interrupt permitted) 0(R): 0 (Interrupt prohibited) (default) D3 ­ R R R R R R PSRIL[2:0]: PSR Interrupt Level (IL) Bits Read out the value (interrupt level) of the IL bit of the PSR. (default: 0x0) D4 ­ 0x0 0 0 0 0 0 PSRN: PSR Negative (N) Flag Read out the value of the PSR N (negative) flag. 1(R): 1 0(R): 0 (default) 2-8 EPSON S1C17602 S1C17602 TECHNICAL MANUAL 2 CPU 2.6 Processor Information 2 CPU The S1C17602 S1C17602 contains a processor ID register (0xffff84) to allow specification of the CPU core type by the application software. 0xffff84: Processor ID Register (IDIR) Register name Address Processor ID Register (IDIR) 0xffff84 (8 bits) Bit Name D7­0 IDIR[7:0] Function Processor ID 0x10: S1C17 S1C17 Core Setting 0x10 Init. R/W 0x10 Remarks R This is the read-only register containing the ID code indicating the processor type. The S1C17 S1C17 core ID code is 0x10. S1C17602 S1C17602 TECHNICAL MANUAL EPSON 2-9 2 CPU This page intentionally left blank. 2-10 EPSON S1C17602 S1C17602 TECHNICAL MANUAL 3 MAP S1C17602 S1C17602 Technical Manual 3 Memory Map and Bus Control 3 Memory Map and Bus Control 3 Memory Map and Bus Control 3 MAP Figure 3.1 shows the S1C17602 S1C17602 memory map. 0xff ffff 0xff fc00 0xff fbff Core I/O reserved area (1 Kbyte, 1 cycle) reserved 0x01 8000 0x01 7fff Flash area (64 Kbytes, 1-5 cycles) (Device size: 16 bits) 0x00 8000 0x00 7fff 0x00 6000 0x00 5fff 0x00 5000 0x00 4fff 0x00 4400 0x00 43ff 0x00 4000 0x00 3fff 0x00 1000 0x00 0fff 0x00 0fc0 Vector table reserved Internal peripheral circuit area 2 (4 Kbytes, 1 cycle) reserved Internal peripheral circuit area 1 (1 Kbyte, 1 cycle) reserved Debug RAM area (64 bytes) Internal RAM area (4 Kbytes, 1 cycle) (Device size: 32 bits) 0x00 0000 Peripheral functions (Device size) 0x5400~0x5fff reserved - 0x53c0~0x53ff LCD Display RAM (16 bits) 0x53a0~0x53bf R/F Converter (16 bits) 0x5380~0x539f A/D Converter (16 bits) 0x5360~0x537f reserved - 0x5340~0x535f Remote controller (16 bits) 0x5320~0x533f MISC register (16 bits) 0x5300~0x531f PWM timer Ch.0 (16 bits) 0x52c0~0x52ff reserved - 0x52a0~0x52bf Port MUX (8 bits) 0x5280~0x529f reserved - 0x5200~0x527f P port (8 bits) 0x5140~0x51ff reserved - 0x5120~0x513f Power supply control circuit (8 bits) 0x5100~0x511f SVD circuit (8 bits) 0x50e0~0x50ff reserved - 0x50c0~0x50df 8-bit OSC1 timer (8 bits) 0x50a0~0x50bf LCD driver (8 bits) 0x5080~0x509f Clock generator (8 bits) 0x5060~0x507f Oscillator circuit (8 bits) 0x5040~0x505f Watchdog timer (8 bits) 0x5020~0x503f Stopwatch timer (8 bits) 0x5000~0x501f Clock timer (8 bits) 0x4380~0x43ff 0x4360~0x437f 0x4340~0x435f 0x4320~0x433f 0x42c0~0x431f 0x4280~0x42ff 0x4260~0x427f 0x4240~0x425f 0x4220~0x423f 0x4200~0x421f 0x4120~0x41ff 0x4100~0x411f 0x4040~0x40ff 0x4020~0x403f 0x4000~0x401f reserved I2C (Slave) I2C (Master) SPI Interrupt controller 8-bit timer Ch.1 16-bit timer Ch.2 16-bit timer Ch.1 16-bit timer Ch.0 8-bit timer Ch.0 UART Ch.1 UART Ch.0 reserved Prescaler reserved - (16 bits) (16 bits) (16 bits) (16 bits) (16 bits) (16 bits) (16 bits) (16 bits) (16 bits) (8 bits) (8 bits) - (8 bits) - Figure 3.1: S1C17602 S1C17602 memory map S1C17602 S1C17602 TECHNICAL MANUAL EPSON 3-1 3 Memory Map and Bus Control 3.1 Bus Cycle The CPU operates using CCLK as a datum. For more information on CCLK, refer to "8.2 CPU Core Clock (CCLK) Control." The time from one CCLK rise-up to the next forms 1 CCLK, defined as one bus cycle. As shown in Figure 3.1, the number of cycles required for a single bus access depends on the peripheral circuits and memory. The number of bus accesses also varies and depends on the CPU instruction (access size) and device size. Table 3.1.1: Bus access numbers Device size 8 bits 16 bits 32 bits CPU access size 8 bits 16 bits 32 bits * 8 bits 16 bits 32 bits * 8 bits 16 bits 32 bits * Bus access number 1 2 4 1 1 2 1 1 1 First 8 bits of data for 32-bit data access The first 8 bits of 32-bit data are written to memory as 0. The first 8 bits are ignored when read from memory. Interrupt processing stack operation involves reading and writing 32 bits with the PSR value in the first 8 bits and the return address in the last 24 bits. 3.1.1 Access Size Restrictions When programming, note that the modules listed below are subject to access size restrictions. Flash memory Only 16-bit write instructions can be used for flash memory programming. No particular restrictions apply