16-BIT S1C17554/564 S1C17554 S1C17564 S1C17 03PMUX 13PMUX 17PMUX 23PMUX 27PMUX - Datasheet Archive

 

S1C17554/564 Technical Manual Rev.1.0 NOTICE No part of this material may be reproduced or duplicated in any form or by any means

 

CMOS 16-BIT 16-BIT SINGLE CHIP MICROCONTROLLER S1C17554/564 S1C17554/564 Technical Manual Rev.1.0 NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of Economy, Trade and Industry or other approval from another government agency. All brands or product names mentioned herein are trademarks and/or registered trademarks of their respective companies. © SEIKO EPSON CORPORATION 2010, All rights reserved. Configuration of product number Devices S1 C 17xxx F 00E1 00 Packing specifications 00 : Besides tape & reel 0A : TCP BL 2 directions 0B : Tape & reel BACK 0C : TCP BR 2 directions 0D : TCP BT 2 directions 0E : TCP BD 2 directions 0F : Tape & reel FRONT 0G : TCP BT 4 directions 0H : TCP BD 4 directions 0J : TCP SL 2 directions 0K : TCP SR 2 directions 0L : Tape & reel LEFT 0M : TCP ST 2 directions 0N : TCP SD 2 directions 0P : TCP ST 4 directions 0Q : TCP SD 4 directions 0R : Tape & reel RIGHT 99 : Specs not fixed Specification Package D: die form; F: QFP, B: BGA Model number Model name C: microcomputer, digital products Product classification S1: semiconductor Development tools S5U1 C 17000 H2 1 00 Packing specifications 00: standard packing Version 1: Version 1 Tool type Hx : ICE Dx : Evaluation board Ex : ROM emulation board Mx : Emulation memory for external ROM Tx : A socket for mounting Cx : Compiler package Sx : Middleware package Yx : Writer software Corresponding model number 17xxx: for S1C17xxx Tool classification C: microcomputer use Product classification S5U1: development tool for semiconductor products CONTENTS ­ Contents ­ 1 Overview.1-1 1.1 Features .1-1 1.2 Block Diagram .1-3 1.3 Pins .1-5 1.3.1 S1C17554 S1C17554 Pin Configuration Diagrams .1-5 1.3.2 S1C17564 S1C17564 Pin Configuration Diagram .1-9 1.3.3 Pin Descriptions .1-12 2 CPU .2-1 2.1 2.2 2.3 2.4 2.5 Features of the S1C17 S1C17 Core .2-1 CPU Registers .2-2 Instruction Set .2-2 Reading PSR .2-5 Processor Information .2-6 3 Memory Map, Bus Control .3-1 3.1 Bus Cycle .3-1 3.1.1 Restrictions on Access Size.3-2 3.1.2 Restrictions on Instruction Execution Cycles .3-2 3.2 Flash Area .3-2 3.2.1 Embedded Flash Memory.3-2 3.2.2 Flash Programming .3-2 3.2.3 Protect Bits .3-3 3.2.4 Flash Memory Read Wait Cycle Setting .3-3 FLASHC Read Wait Control Register (FLASHC_WAIT) . 3-3 3.3 Internal RAM Area.3-4 3.3.1 Embedded RAM .3-4 IRAM Size Register (MISC_IRAMSZ) . 3-4 3.4 Internal Peripheral Area .3-5 3.4.1 Internal Peripheral Area 1 (0x4000­) .3-5 3.4.2 Internal Peripheral Area 2 (0x5000­) .3-5 3.5 S1C17 S1C17 Core I/O Area .3-5 4 Power Supply .4-1 4.1 4.2 4.3 4.4 4.5 4.6 Core Power Supply Voltage (LVDD) .4-1 I/O Power Supply Voltage (HVDD) .4-1 Analog Power Supply Voltage (AVDD) .4-1 Flash Programming Power Supply Voltage (VPP) .4-1 Embedded Regulator (S1C17564 S1C17564) .4-2 Control Register Details (S1C17564 S1C17564) .4-2 VD1 Control Register (VD1_CTL) . 4-2 4.7 Precautions on Power Supply .4-3 5 Initial Reset .5-1 5.1 Initial Reset Sources .5-1 5.1.1 #RESET Pin .5-1 5.1.2 P0 Port Key-Entry Reset .5-1 5.1.3 Resetting by the Watchdog Timer .5-1 5.2 Initial Reset Sequence .5-2 5.3 Initial Settings After an Initial Reset .5-2 S1C17554/564 S1C17554/564 TECHNICAL MANUAL Seiko Epson Corporation i CONTENTS 6 Interrupt Controller (ITC) .6-1 6.1 ITC Module Overview .6-1 6.2 Vector Table .6-2 Vector Table Address Low/High Registers (MISC_TTBRL, MISC_TTBRH) . 6-4 6.3 Control of Maskable Interrupts .6-4 6.3.1 Interrupt Control Bits in Peripheral Modules .6-4 6.3.2 ITC Interrupt Request Processing .6-4 6.3.3 Interrupt Processing by the S1C17 S1C17 Core .6-5 6.4 NMI.6-6 6.5 Software Interrupts .6-6 6.6 HALT and SLEEP Mode Cancellation .6-6 6.7 Control Register Details .6-6 Interrupt Level Setup Register x (ITC_LVx) . 6-7 7 Clock Generator (CLG).7-1 7.1 CLG Module Overview .7-1 7.2 CLG Input/Output Pins .7-2 7.3 Oscillators .7-2 7.3.1 OSC3 Oscillator .7-2 7.3.2 OSC1 Oscillator .7-4 7.3.3 IOSC Oscillator (S1C17564 S1C17564) .7-5 7.4 System Clock Switching .7-6 7.5 CPU Core Clock (CCLK) Control .7-7 7.6 Peripheral Module Clock (PCLK) Control .7-8 7.7 Clock External Output (FOUTA, FOUTB) .7-9 7.8 Control Register Details .7-10 Clock Source Select Register (CLG_SRC) . 7-10 Oscillation Control Register (CLG_CTL) . 7-11 Noise Filter Enable Register (CLG_NFEN) . 7-13 FOUTA Control Register (CLG_FOUTA) . 7-14 FOUTB Control Register (CLG_FOUTB) . 7-15 IOSC Control Register (CLG_IOSC) . 7-16 PCLK Control Register (CLG_PCLK) . 7-16 CCLK Control Register (CLG_CCLK). 7-17 8 I/O Ports (P) .8-1 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 ii P Module Overview .8-1 Input/Output Pin Function Selection (Port MUX) .8-2 Data Input/Output .8-3 Pull-up Control .8-3 P0­P3 Port Chattering Filter Function .8-4 Port Input Interrupt .8-4 P0 Port Key-Entry Reset .8-5 Control Register Details .8-5 Px Port Input Data Registers (Px_IN) . 8-7 Px Port Output Data Registers (Px_OUT) . 8-7 Px Port Output Enable Registers (Px_OEN) . 8-7 Px Port Pull-up Control Registers (Px_PU) . 8-8 Px Port Interrupt Mask Registers (Px_IMSK) . 8-8 Px Port Interrupt Edge Select Registers (Px_EDGE) . 8-9 Px Port Interrupt Flag Registers (Px_IFLG). 8-9 Px Port Chattering Filter Control Registers (Px_CHAT) . 8-10 P0 Port Key-Entry Reset Configuration Register (P0_KRST) . 8-10 Px Port Input Enable Registers (Px_IEN) . 8-11 S1C17554/564 S1C17554/564 TECHNICAL MANUAL Seiko Epson Corporation CONTENTS P0[3:0] Port Function Select Register (P00_03PMUX 03PMUX) . 8-11 P1[3:0] Port Function Select Register (P10_13PMUX 13PMUX) . 8-12 P1[7:4] Port Function Select Register (P14_17PMUX 17PMUX) . 8-13 P2[3:0] Port Function Select Register (P20_23PMUX 23PMUX) . 8-14 P2[7:4] Port Function Select Register (P24_27PMUX 27PMUX) . 8-15 P3[3:0] Port Function Select Register (P30_33PMUX 33PMUX) . 8-16 P3[7:4] Port Function Select Register (P34_37PMUX 37PMUX) . 8-17 P4[3:0] Port Function Select Register (P40_43PMUX 43PMUX) . 8-18 P4[5:4] Port Function Select Register (P44_45PMUX 45PMUX) . 8-18 P5[3:0] Port Function Select Register (P50_53PMUX 53PMUX) . 8-19 P5[5:4] Port Function Select Register (P54_55PMUX 55PMUX) . 8-20 9 16-bit Timers (T16) .9-1 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 T16 Module Overview .9-1 Count Clock .9-2 Count Mode.9-2 Reload Data Register and Underflow Cycle .9-2 Timer Reset .9-3 Timer RUN/STOP Control .9-3 T16 Output Signals.9-4 T16 Interrupts .9-4 Control Register Details .9-5 T16 Ch.x Count Clock Select Registers (T16_CLKx) . 9-5 T16 Ch.x Reload Data Registers (T16_TRx). 9-6 T16 Ch.x Counter Data Registers (T16_TCx) . 9-6 T16 Ch.x Control Registers (T16_CTLx) . 9-6 T16 Ch.x Interrupt Control Registers (T16_INTx) . 9-7 10 Fine Mode 16-bit Timers (T16F) .10-1 10.1 T16F Module Overview .10-1 10.2 Count Clock .10-2 10.3 Count Mode.10-2 10.4 Reload Data Register and Underflow Cycle .10-2 10.5 Timer Reset .10-3 10.6 Timer RUN/STOP Control .10-3 10.7 T16F Output Signals .10-4 10.8 Fine Mode .10-4 10.9 T16F Interrupts .10-5 10.10 Control Register Details .10-6 T16F Ch.x Count Clock Select Registers (T16F_CLKx) . 10-6 T16F Ch.x Reload Data Registers (T16F_TRx) . 10-6 T16F Ch.x Counter Data Registers (T16F_TCx) . 10-7 T16F Ch.x Control Registers (T16F_CTLx). 10-7 T16F Ch.x Interrupt Control Registers (T16F_INTx) . 10-8 11 16-bit PWM Timers (T16A).11-1 11.1 11.2 11.3 11.4 T16A Module Overview .11-1 T16A Input/Output Pins .11-2 Count Clock .11-3 T16A Operating Modes .11-4 11.4.1 Comparator Mode and Capture Mode .11-4 11.4.2 Repeat Mode and One-Shot Mode .11-6 11.4.3 Normal Channel Mode and Multi-Comparator/Capture Mode .11-6 S1C17554/564 S1C17554/564 TECHNICAL MANUAL Seiko Epson Corporation iii CONTENTS 11.5 Counter Control .11-8 11.5.1 Counter Reset .11-8 11.5.2 Counter RUN/STOP Control .11-8 11.5.3 Reading Counter Values .11-8 11.5.4 Timing Charts.11-8 11.6 Timer Output Control .11-9 11.7 T16A Interrupts.11-10 11.8 Control Register Details .11-12 T16A Clock Control Register Ch.x (T16A_CLKx) . 11-13 T16A Counter Ch.x Control Registers (T16A_CTLx) . 11-14 T16A Counter Ch.x Data Registers (T16A_TCx) . 11-15 T16A Comparator/Capture Ch.x Control Registers (T16A_CCCTLx) . 11-16 T16A Comparator/Capture Ch.x A Data Registers (T16A_CCAx) . 11-18 T16A Comparator/Capture Ch.x B Data Registers (T16A_CCBx) . 11-18 T16A Comparator/Capture Ch.x Interrupt Enable Registers (T16A_IENx) . 11-19 T16A Comparator/Capture Ch.x Interrupt Flag Registers (T16A_IFLGx) . 11-20 12 Clock Timer (CT) .12-1 12.1 12.2 12.3 12.4 12.5 12.6 CT Module Overview .12-1 Operation Clock.12-1 Timer Reset .12-1 Timer RUN/STOP Control .12-1 CT Interrupts .12-2 Control Register Details .12-3 Clock Timer Control Register (CT_CTL). 12-3 Clock Timer Counter Register (CT_CNT) . 12-3 Clock Timer Interrupt Mask Register (CT_IMSK) . 12-4 Clock Timer Interrupt Flag Register (CT_IFLG). 12-4 13 Stopwatch Timer (SWT).13-1 13.1 13.2 13.3 13.4 13.5 13.6 13.7 SWT Module Overview .13-1 Operation Clock.13-1 BCD Counters .13-1 Timer Reset .13-2 Timer RUN/STOP Control .13-2 SWT Interrupts .13-3 Control Register Details .13-4 Stopwatch Timer Control Register (SWT_CTL). 13-4 Stopwatch Timer BCD Counter Register (SWT_BCNT) . 13-4 Stopwatch Timer Interrupt Mask Register (SWT_IMSK) . 13-5 Stopwatch Timer Interrupt Flag Register (SWT_IFLG). 13-5 14 Watchdog Timer (WDT).14-1 14.1 WDT Module Overview .14-1 14.2 Operation Clock.14-1 14.3 WDT Control.14-1 14.3.1 NMI/Reset Mode Selection .14-1 14.3.2 WDT Run/Stop Control .14-1 14.3.3 WDT Reset .14-2 14.3.4 Operations in HALT and SLEEP Modes .14-2 14.4 Control Register Details .14-2 Watchdog Timer Control Register (WDT_CTL) . 14-2 Watchdog Timer Status Register (WDT_ST) . 14-3 iv Seiko Epson Corporation S1C17554/564 S1C17554/564 TECHNICAL MANUAL CONTENTS 15 UART .15-1 15.1 15.2 15.3 15.4 15.5 15.6 15.7 15.8 15.9 UART Module Overview .15-1 UART Input/Output Pins .15-2 Baud Rate Generator .15-2 Transfer Data Settings .15-4 Data Transfer Control .15-5 Receive Errors.15-7 UART Interrupts .15-8 IrDA Interface .15-9 Control Register Details .15-9 UART Ch.x Status Registers (UART_STx) . 15-10 UART Ch.x Transmit Data Registers (UART_TXDx). 15-12 UART Ch.x Receive Data Registers (UART_RXDx). 15-12 UART Ch.x Mode Registers (UART_MODx) . 15-12 UART Ch.x Control Registers (UART_CTLx) . 15-13 UART Ch.x Expansion Registers (UART_EXPx). 15-14 UART Ch.x Baud Rate Registers (UART_BRx). 15-14 UART Ch.x Fine Mode Registers (UART_FMDx) . 15-15 UART Ch.x Clock Control Registers (UART_CLKx) . 15-16 16 SPI .16-1 16.1 16.2 16.3 16.4 16.5 16.6 16.7 SPI Module Overview .16-1 SPI Input/Output Pins.16-1 SPI Clock .16-2 Data Transfer Condition Settings .16-2 Data Transfer Control .16-3 SPI Interrupts .16-5 Control Register Details .16-6 SPI Ch.x Status Registers (SPI_STx) . 16-6 SPI Ch.x Transmit Data Registers (SPI_TXDx) . 16-7 SPI Ch.x Receive Data Registers (SPI_RXDx) . 16-7 SPI Ch.x Control Registers (SPI_CTLx) . 16-7 17 I2C Master (I2CM) .17-1 17.1 17.2 17.3 17.4 17.5 17.6 17.7 I2CM Module Overview .17-1 I2CM Input/Output Pins .17-1 Synchronization Clock .17-2 Settings Before Data Transfer .17-2 Data Transfer Control .17-2 I2CM Interrupts .17-6 Control Register Details .17-7 I2C Master Enable Register (I2CM_EN) . 17-7 I2C Master Control Register (I2CM_CTL) . 17-8 I2C Master Data Register (I2CM_DAT) . 17-9 I2C Master Interrupt Control Register (I2CM_ICTL) . 17-10 18 I2C Slave (I2CS) .18-1 18.1 18.2 18.3 18.4 I2CS Module Overview .18-1 I2CS Input/Output Pins .18-1 Operation Clock.18-2 Initializing I2CS .18-2 18.4.1 Reset .18-2 18.4.2 Setting Slave Address .18-2 S1C17554/564 S1C17554/564 TECHNICAL MANUAL Seiko Epson Corporation v CONTENTS 18.4.3 Optional Functions .18-2 18.5 Data Transfer Control .18-3 18.6 I2CS Interrupts .18-8 18.7 Control Register Details .18-9 I2C Slave Transmit Data Register (I2CS_TRNS) . 18-9 I2C Slave Receive Data Register (I2CS_RECV) . 18-10 I2C Slave Address Setup Register (I2CS_SADRS) . 18-10 I2C Slave Control Register (I2CS_CTL) . 18-10 I2C Slave Status Register (I2CS_STAT) . 18-13 I2C Slave Access Status Register (I2CS_ASTAT) . 18-15 I2C Slave Interrupt Control Register (I2CS_ICTL) . 18-16 19 Universal Serial Interface (USI) [S1C17564 S1C17564] .19-1 19.1 19.2 19.3 19.4 19.5 19.6 19.7 19.8 USI Module Overview .19-1 USI Pins .19-2 USI Clock Sources .19-2 USI Module Settings .19-4 19.4.1 USI Module Software Reset.19-4 19.4.2 Interface Mode .19-4 19.4.3 General Settings for All Interface Modes .19-4 19.4.4 Settings for UART Mode .19-4 19.4.5 Settings for SPI Master Mode .19-5 19.4.6 Settings for I2C Mode .19-6 Data Transfer Control .19-6 19.5.1 Data Transfer in UART Mode .19-6 19.5.2 Data Transfer in SPI Master Mode .19-7 19.5.3 Data Transfer in I2C Mode .19-9 Receive Errors.19-19 USI Interrupts .19-19 19.7.1 Interrupts in UART Mode .19-20 19.7.2 Interrupts in SPI Master Mode .19-20 19.7.3 Interrupts in I2C Master Mode .19-21 19.7.4 Interrupts in I2C Slave Mode .19-22 Control Register Details .19-22 USI Ch.x Global Configuration Registers (USI_GCFGx). 19-23 USI Ch.x Transmit Data Buffer Registers (USI_TDx). 19-23 USI Ch.x Receive Data Buffer Registers (USI_RDx). 19-24 USI Ch.x UART Mode Configuration Registers (USI_UCFGx). 19-24 USI Ch.x UART Mode Interrupt Enable Registers (USI_UIEx). 19-25 USI Ch.x UART Mode Interrupt Flag Registers (USI_UIFx) . 19-25 USI Ch.x SPI Master Mode Configuration Registers (USI_SCFGx). 19-27 USI Ch.x SPI Master Mode Interrupt Enable Registers (USI_SIEx). 19-28 USI Ch.x SPI Master Mode Interrupt Flag Registers (USI_SIFx) . 19-29 USI Ch.x SPI Master Mode Receive Data Mask Registers (USI_SMSKx) . 19-30 USI Ch.x I2C Master Mode Trigger Registers (USI_IMTGx) . 19-30 USI Ch.x I2C Master Mode Interrupt Enable Registers (USI_IMIEx) . 19-31 USI Ch.x I2C Master Mode Interrupt Flag Registers (USI_IMIFx) . 19-31 USI Ch.x I2C Slave Mode Trigger Registers (USI_ISTGx) . 19-32 USI Ch.x I2C Slave Mode Interrupt Enable Registers (USI_ISIEx). 19-33 USI Ch.x I2C Slave Mode Interrupt Flag Registers (USI_ISIFx) . 19-34 19.9 Precautions .19-35 20 IR Remote Controller (REMC) .20-1 20.1 REMC Module Overview .20-1 20.2 REMC Input/Output Pins .20-1 vi Seiko Epson Corporation S1C17554/564 S1C17554/564 TECHNICAL MANUAL CONTENTS 20.3 20.4 20.5 20.6 20.7 Carrier Generation .20-1 Data Length Counter Clock Settings .20-2 Data Transfer Control .20-3 REMC Interrupts .20-5 Control Register Details .20-6 REMC Configuration Register (REMC_CFG) . 20-6 REMC Carrier Length Setup Register (REMC_CAR). 20-7 REMC Length Counter Register (REMC_LCNT) . 20-8 REMC Interrupt Control Register (REMC_INT) . 20-9 21 A/D Converter (ADC10 ADC10) .21-1 21.1 ADC10 ADC10 Module Overview .21-1 21.2 ADC10 ADC10 Input Pins.21-2 21.3 A/D Converter Settings .21-2 21.3.1 A/D Conversion Clock Setting .21-2 21.3.2 Selecting A/D Conversion Start and End Channels .21-3 21.3.3 A/D Conversion Mode Setting .21-3 21.3.4 Trigger Selection .21-4 21.3.5 Sampling Time Setting .21-4 21.3.6 Setting Conversion Result Storing Mode .21-5 21.4 A/D Conversion Control and Operations .21-5 21.4.1 Activating A/D Converter.21-5 21.4.2 Starting A/D conversion .21-5 21.4.3 Reading A/D Conversion Results .21-6 21.4.4 Terminating A/D Conversion .21-6 21.4.5 Timing Charts.21-6 21.5 A/D Converter Interrupts .21-7 21.6 Control Register Details .21-8 A/D Conversion Result Register (ADC10 ADC10_ADD) . 21-8 A/D Trigger/Channel Select Register (ADC10 ADC10_TRG) . 21-9 A/D Control/Status Register (ADC10 ADC10_CTL) . 21-10 A/D Clock Control Register (ADC10 ADC10_CLK) . 21-12 A/D Comparator Setting Register (ADC10 ADC10_COM) . 21-13 22 On-chip Debugger (DBG) .22-1 22.1 22.2 22.3 22.4 Resource Requirements and Debugging Tools .22-1 Debug Break Operation Status .22-1 Additional Debugging Function .22-2 Control Register Details .22-2 Debug Mode Control Register 1 (MISC_DMODE1) . 22-2 Debug Mode Control Register 2 (MISC_DMODE2) . 22-3 IRAM Size Select Register (MISC_IRAMSZ) . 22-3 Debug RAM Base Register (DBRAM) . 22-4 Debug Control Register (DCR) . 22-4 Instruction Break Address Register 2 (IBAR2) . 22-5 Instruction Break Address Register 3 (IBAR3) . 22-5 Instruction Break Address Register 4 (IBAR4) . 22-6 23 Multiplier/Divider (COPRO) .23-1 23.1 23.2 23.3 23.4 23.5 Overview .23-1 Operation Mode and Output Mode .23-1 Multiplication .23-2 Division.23-3 MAC .23-4 S1C17554/564 S1C17554/564 TECHNICAL MANUAL Seiko Epson Corporation vii CONTENTS 23.6 Reading Results .23-6 24 Electrical Characteristics.24-1 24.1 Absolute Maximum Ratings .24-1 24.2 Recommended Operating Conditions .24-1 24.3 Current Consumption .24-2 24.4 DC Regulator Characteristics.24-3 24.5 Oscillation Characteristics .24-4 24.6 External Clock Input Characteristics .24-5 24.7 System Clock Characteristics .24-5 24.8 Input/Output Pin Characteristics .24-6 24.9 SPI Characteristics.24-7 24.10 I2C Characteristics .24-7 24.11 USI Characteristics (S1C17564 S1C17564) .24-8 24.12 A/D Converter Characteristics.24-9 24.13 Flash Memory Characteristics.24-10 25 Basic External Connection Diagram.25-1 26 Package .26-1 Appendix A List of I/O Registers. AP-A-1 0x4100­0x4107, 0x506c 0x4120­0x4127, 0x506d 0x4200­0x4208 0x4220­0x4228 0x4240­0x4248 0x4260­0x4268 0x4280­0x4288 0x4306­0x431c 0x4320­0x4326 0x4340­0x4346 0x4360­0x436c 0x4380­0x4386 0x43a0­0x43a6 0x5000­0x5003 0x5020­0x5023 0x5040­0x5041 0x5060­0x5081 0x50c0­0x50cf 0x50e0­0x50ef 0x5121 0x5200­0x52ab 0x4020, 0x5322­0x532c 0x5340­0x5346 0x5380­0x5388 0x5068, 0x5400­0x540c 0x5069, 0x5420­0x542c 0x506a, 0x5440­0x544c 0x506b, 0x5460­0x546c 0x54b0 0xffff84­0xffffd0 viii UART (with IrDA) Ch.0. AP-A-5 UART (with IrDA) Ch.1. AP-A-6 Fine Mode 16-bit Timer Ch.0 . AP-A-7 16-bit Timer Ch.0 . AP-A-8 16-bit Timer Ch.1 . AP-A-8 16-bit Timer Ch.2 . AP-A-9 Fine Mode 16-bit Timer Ch.1 . AP-A-9 Interrupt Controller. AP-A-10 AP-A-10 SPI Ch.0 . AP-A-11 AP-A-11 I2C Master. AP-A-11 AP-A-11 I2C Slave . AP-A-11 AP-A-11 SPI Ch.1 . AP-A-12 AP-A-12 SPI Ch.2 . AP-A-12 AP-A-12 Clock Timer. AP-A-13 AP-A-13 Stopwatch Timer . AP-A-13 AP-A-13 Watchdog Timer. AP-A-13 AP-A-13 Clock Generator . AP-A-14 AP-A-14 USI Ch.0 . AP-A-15 AP-A-15 USI Ch.1 . AP-A-17 AP-A-17 Power Generator . AP-A-19 AP-A-19 P Port & Port MUX. AP-A-19 AP-A-19 MISC Registers . AP-A-26 AP-A-26 IR Remote Controller . AP-A-27 AP-A-27 A/D Converter . AP-A-27 AP-A-27 16-bit PWM Timer Ch.0 . AP-A-28 AP-A-28 16-bit PWM Timer Ch.1 . AP-A-30 AP-A-30 16-bit PWM Timer Ch.2 . AP-A-31 AP-A-31 16-bit PWM Timer Ch.3 . AP-A-33 AP-A-33 Flash Controller . AP-A-34 AP-A-34 S1C17 S1C17 Core I/O . AP-A-34 AP-A-34 Seiko Epson Corporation S1C17554/564 S1C17554/564 TECHNICAL MANUAL CONTENTS Appendix B Power Saving . AP-B-1 B.1 Clock Control Power Saving. AP-B-1 B.2 Reducing Power Consumption via Power Supply Control . AP-B-2 Appendix C Mounting Precautions . AP-C-1 Appendix D Initialization Routine . AP-D-1 Appendix E Recommended Resonators . AP-E-1 Revision History S1C17554/564 S1C17554/564 TECHNICAL MANUAL Seiko Epson Corporation ix 1 OVERVIEW 1 Overview 1.1 Features The main features of the S1C17554/564 S1C17554/564 are listed below. Table 1.1.1 Features Model CPU CPU core Multiplier/Divider (COPRO) Embedded Flash memory Capacity Erase/program count Other Embedded RAM Capacity Clock generator System clock source IOSC oscillator circuit OSC3 oscillator circuit OSC1 oscillator circuit Other I/O ports Number of general-purpose I/O ports Serial interfaces SPI I2C master (I2CM) I2C slave (I2CS) UART IR remote controller (REMC) Universal serial interface (USI) Timers 16-bit timer (T16) Fine mode 16-bit timer (T16F) 16-bit PWM timer (T16A) Clock timer (CT) Stopwatch timer (SWT) Watchdog timer (WDT) A/D converter Conversion method Number of analog input channels Resolution Interrupts Reset interrupt NMI Programmable interrupts Power supply voltage Core voltage (LVDD) S1C17554 S1C17554 S1C17564 S1C17564 Seiko Epson original 16-bit RISC CPU core S1C17 S1C17 · 16-bit × 16-bit multiplier · 16-bit × 16-bit + 32-bit multiply and accumulation unit · 16-bit ÷ 16-bit divider 128K bytes (for both instructions and data) Min. 1 time · Read/program protection function · An erasing/programming power supply (VPP) is required. · Allows on-board programming using a debugging tool such as ICDmini. 16K bytes 2 sources (OSC3/OSC1) 3 sources (IOSC/OSC3/OSC1) 2/4/8/12 MHz(typ.) internal oscillator circuit 24 MHz (max.) crystal or ceramic oscillator circuit Supports an external clock input. 32.768 kHz (typ.) crystal oscillator circuit Supports an external clock input. · Core clock frequency control · Peripheral module clock supply control Max. 40 bits (TQFP13-64pin package) Max. 34 bits (WCSP-48 WCSP-48 package) (Pins are shared with the peripheral I/O.) Max. 40 bits (Pins are shared with the peripheral I/O.) 3 channels 1 channel 1 channel 2 channels (IrDA1.0 supported) 1 channel 2 channels (Usable as a UART, SPI, or I2C) 3 channels 2 channels 4 channels 1 channel 1 channel 1 channel Successive approximation type 4 channels (max.) 10 bits #RESET pin Watchdog timer 23 systems (8 levels) 1.65 V to 1.95 V I/O voltage (HVDD) 1.65 V to 5.5 V Analog voltage (AVDD) Flash programming voltage (VPP) 1.65 V to 1.95 V (Not required when the regulator is used.) 2.0 V to 5.5 V (Regulator used) 1.65 V to 5.5 V (Regulator not used) 2.7 V to 5.5 V 7V S1C17554/564 S1C17554/564 Technical Manual Seiko Epson Corporation 1-1 1 OVERVIEW Model Regulator Input voltage Output voltage Other S1C17554 S1C17554 S1C17564 S1C17564 2.0 V to 5.5 V 1.8 V Enables the system to operate with a 3.3 V or 5.0 V single power supply. Operating temperature Operating temperature range -40°C to 85°C Current consumption (Typ value, LVDD = HVDD = 1.8 V) SLEEP state 0.8 µA (OSC1 = Off, OSC3 = Off) HALT state 2.7 µA (OSC1 = 32 kHz, OSC3 = Off) Run state 16 µA (OSC1 = 32 kHz, OSC3 = Off) 3000 µA (OSC1 = Off, OSC3 = 8 MHz ceramic) A/D conversion Shipping form 1 2 3 1-2 1.2 µA (OSC1 = Off, IOSC = Off, OSC3 = Off) 3.1 µA (OSC1 = 32 kHz, IOSC = Off, OSC3 = Off) 16 µA (OSC1 = 32 kHz, IOSC = Off, OSC3 = Off) 3000 µA (OSC1 = Off, IOSC = Off, OSC3 = 8 MHz ceramic) 4500 µA (OSC1 = Off, IOSC = 12 MHz, OSC3 = Off) 380 µA (AVDD = 3.6 V, 100 kHz sampling, FSEL[1:0] = 0x0, XPD[1:0] = 0x3) TQFP13-64pin (10 mm × 10 mm × 1.0 mm, lead pitch: 0.5 mm) Die form (3.137 mm × 3.137 mm, pad pitch: 140 µm) WCSP-48 WCSP-48 (3.137 mm × 3.137 mm × 0.72 mm, ball pitch: 0.4 mm) Seiko Epson Corporation S1C17554/564 S1C17554/564 Technical Manual 1 OVERVIEW 1.2 Block Diagram S1C17554 S1C17554 DCLK, DST2, DSIO CPU Core S1C17 S1C17 32 bits 8/16 bits Internal RAM (16K bytes) Flash memory (128K bytes) I/O 2 (0x5000­) 16 bits A/D converter #RESET Test circuit Reset circuit 8/16 bits I/O 1 (0x4000­) Interrupt system TEST AVDD AINx, #ADTRG MISC register Clock generator (with oscillators) OSC1­2, OSC3­4 FOUTA, FOUTB Interrupt controller Clock timer 16-bit timer (3 ch.) Stopwatch timer Fine mode 16-bit timer (2 ch.) Watchdog timer UART (2 ch.) 16-bit PWM timer (4 ch.) EXCLx, CAPx, TOUTx SDIx, SDOx, SPICLKx, #SPISSx SPI (3 ch.) IR remote controller REMI, REMO SDA0, SCL0 I2C master SDA1, SCL1, #BFR I2C slave SINx, SOUTx, SCLKx I/O port/ port MUX Pxx Figure 1.2.1 S1C17554 S1C17554 Block Diagram S1C17554/564 S1C17554/564 Technical Manual Seiko Epson Corporation 1-3 1 OVERVIEW S1C17564 S1C17564 DCLK, DST2, DSIO CPU Core S1C17 S1C17 32 bits 8/16 bits Internal RAM (16K bytes) Flash memory (128K bytes) I/O 2 (0x5000­) Regulator 16 bits VIN, VOUT, REGEN AVDD AINx, #ADTRG A/D converter #RESET Test circuit Reset circuit 8/16 bits I/O 1 (0x4000­) Interrupt system TEST MISC register Clock generator (with oscillators) OSC1­2, OSC3­4 FOUTA, FOUTB Interrupt controller Clock timer 16-bit timer (3 ch.) Stopwatch timer Fine mode 16-bit timer (2 ch.) Watchdog timer UART (2 ch.) 16-bit PWM timer (4 ch.) EXCLx, CAPx, TOUTx SDIx, SDOx, SPICLKx, #SPISSx SPI (3 ch.) IR remote controller REMI, REMO SDA0, SCL0 I2C master USI (2 ch.) SDA1, SCL1, #BFR I2C slave I/O port/ port MUX SINx, SOUTx, SCLKx US_SDIx, US_SDOx, US_SCKx, US_SSIx Pxx Figure 1.2.2 S1C17564 S1C17564 Block Diagram 1-4 Seiko Epson Corporation S1C17554/564 S1C17554/564 Technical Manual 1 OVERVIEW 1.3 Pins 1.3.1 S1C17554 S1C17554 Pin Configuration Diagrams WCSP-48 WCSP-48 (S1C17554 S1C17554) A1 Corner Top View A1 Corner Bottom View A A Index B B C C D D E E F F G G 1 2 3 4 5 6 7 7 6 5 4 3 2 1 Top View P10 SDI0 2 P11 SDO0 P01 AIN1 P00 AIN0 P03 AIN3 P02 AIN2 P17 SCL0 P32 TOUT4 CAP4 FOUTA P42 SCLK0 TOUT1 CAP1 LVDD P23 (EXCL2) SDI2 1 A B C D P45 (EXCL0) E SDA0 P40 SIN0 F TOUT6 CAP6 #RESET G 3 P13 #SPISS0 TOUT5 CAP5 P12 SPICLK0 4 P14 SIN1 SDI1 5 P43 SDA1 REMI 6 P24 (EXCL3) SDO2 7 P26 SDA1 P15 SOUT1 SDO1 P44 SCL1 REMO P25 #BFR #SPISS2 P27 SCL1 HVDD P16 SCLK1 SPICLK1 VSS P30 TOUT0 CAP0 AVDD VSS LVDD P31 #BFR #ADTRG DST2 P37 P41 SOUT0 TOUT7 CAP7 P22 (EXCL1) FOUTB HVDD DCLK P35 TEST DSIO P36 P20 TOUT2 CAP2 VPP P34 REMO #SPISS1 P33 REMI SPICLK2 P21 TOUT3 CAP3 OSC4 OSC3 OSC2 OSC1 Figure 1.3.1.1 S1C17554 S1C17554 Pin Configuration Diagram (WCSP-48 WCSP-48) S1C17554/564 S1C17554/564 Technical Manual Seiko Epson Corporation 1-5 1 OVERVIEW 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 P54 P34/REMO/ P34/REMO/#SPISS1 P33/REMI/SPICLK2 P33/REMI/SPICLK2 DCLK/P35 DCLK/P35 TEST DSIO/P36 DSIO/P36 DST2/P37 DST2/P37 P31/#BFR/#ADTRG P53 LVDD P30/TOUT0/CAP0 P30/TOUT0/CAP0 HVDD VSS P27/SCL1 P27/SCL1 P26/SDA1 P26/SDA1 P52 P50 SDI0/P10 SDI0/P10 VSS SDO0/P11 SDO0/P11 SPICLK0/P12 SPICLK0/P12 #SPISS0/TOUT5/CAP5/P13 SPISS0/TOUT5/CAP5/P13 LVDD HVDD SIN1/SDI1/P14 SIN1/SDI1/P14 P51 SOUT1/SDO1/P15 SOUT1/SDO1/P15 SCLK1/SPICLK1/P16 SCLK1/SPICLK1/P16 SDA1/REMI/P43 SDA1/REMI/P43 SCL1/REMO/P44 SCL1/REMO/P44 SDO2/P24 SDO2/P24(EXCL3) #BFR/#SPISS2/P25 SPISS2/P25 #RESET LVDD SIN0/TOUT6/CAP6/P40 SIN0/TOUT6/CAP6/P40 SOUT0/TOUT7/CAP7/P41 SOUT0/TOUT7/CAP7/P41 SCLK0/TOUT1/CAP1/P42 SCLK0/TOUT1/CAP1/P42 SDA0/P45 SDA0/P45(EXCL0) HVDD VSS SCL0/P17 SCL0/P17 TOUT4/CAP4/FOUTA/P32 N.C. AVDD AIN3/P03 AIN3/P03 AIN2/P02 AIN2/P02 AIN1/P01 AIN1/P01 AIN0/P00 AIN0/P00 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VSS VSS HVDD LVDD P23(EXCL2)/SDI2 P22(EXCL1)/FOUTB P21/TOUT3/CAP3 P21/TOUT3/CAP3 P20/TOUT2/CAP2 P20/TOUT2/CAP2 HVDD OSC4 OSC3 VPP OSC2 OSC1 VSS P55 TQFP13-64pin (S1C17554 S1C17554) Figure 1.3.1.2 S1C17554 S1C17554 Pin Configuration Diagram (TQFP13-64pin) 1-6 Seiko Epson Corporation S1C17554/564 S1C17554/564 Technical Manual 1 OVERVIEW N.C. VSS N.C. N.C. LVDD P23(EXCL2)/SDI2 P22(EXCL1)/FOUTB P21/TOUT3/CAP3 P21/TOUT3/CAP3 P20/TOUT2/CAP2 P20/TOUT2/CAP2 HVDD OSC4 VSS OSC3 VPP OSC2 OSC1 VSS P55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 Chip (S1C17554 S1C17554) 55 36 P54 LVDD 56 35 P34/REMO/ P34/REMO/#SPISS1 SIN0/TOUT6/CAP6/P40 SIN0/TOUT6/CAP6/P40 57 34 P33/REMI/SPICLK2 P33/REMI/SPICLK2 SOUT0/TOUT7/CAP7/P41 SOUT0/TOUT7/CAP7/P41 58 33 DCLK/P35 DCLK/P35 SCLK0/TOUT1/CAP1/P42 SCLK0/TOUT1/CAP1/P42 59 32 TEST SDA0/P45 SDA0/P45(EXCL0) 60 31 DSIO/P36 DSIO/P36 HVDD 61 30 LVDD VSS 62 29 DST2/P37 DST2/P37 SCL0/P17 SCL0/P17 63 28 P31/#BFR/#ADTRG TOUT4/CAP4/FOUTA/P32 64 27 P53 N.C. 65 26 LVDD AVDD 66 25 P30/TOUT0/CAP0 P30/TOUT0/CAP0 AVDD 67 24 HVDD AIN3/P03 AIN3/P03 68 23 VSS AIN2/P02 AIN2/P02 69 22 VSS AIN1/P01 AIN1/P01 70 21 P27/SCL1 P27/SCL1 AIN0/P00 AIN0/P00 71 20 P26/SDA1 P26/SDA1 N.C. 72 19 P52 Y (0, 0) X 12 13 14 15 16 17 18 SDA1/REMI/P43 SDA1/REMI/P43 SCL1/REMO/P44 SCL1/REMO/P44 HVDD SDO2/P24 SDO2/P24(EXCL3) #BFR/#SPISS2/P25 SPISS2/P25 VSS 8 HVDD SCLK1/SPICLK1/P16 SCLK1/SPICLK1/P16 7 LVDD 11 6 #SPISS0/TOUT5/CAP5/P13 SPISS0/TOUT5/CAP5/P13 SOUT1/SDO1/P15 SOUT1/SDO1/P15 5 SPICLK0/P12 SPICLK0/P12 10 4 SDO0/P11 SDO0/P11 P51 3 VSS 9 2 SIN1/SDI1/P14 SIN1/SDI1/P14 1 P50 SDI0/P10 SDI0/P10 Die No. CJ554D0B0 CJ554D0B0 3.137 mm #RESET 3.137 mm Figure 1.3.1.3 S1C17554 S1C17554 Pad Configuration Diagram Chip size Pad opening X = 3.137 mm, Y = 3.137 mm No. 1 to 18, 37 to 54: X = 122 µm, Y = 85 µm No. 19 to 36, 55 to 72: X = 85 µm, Y = 122 µm Chip thickness 400 µm S1C17554/564 S1C17554/564 Technical Manual Seiko Epson Corporation 1-7 1 OVERVIEW Table 1.3.1.1 S1C17554 S1C17554 Pad Coordinates No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 1-8 Name P50 P10/SDI0 P10/SDI0 VSS P11/SDO0 P11/SDO0 P12/SPICLK0 P12/SPICLK0 P13/#SPISS0/TOUT5/CAP5 LVDD HVDD P14/SIN1/SDI1 P14/SIN1/SDI1 P51 P15/SOUT1/SDO1 P15/SOUT1/SDO1 P16/SCLK1/SPICLK1 P16/SCLK1/SPICLK1 P43/SDA1/REMI P43/SDA1/REMI P44/SCL1/REMO P44/SCL1/REMO HVDD P24(EXCL3)/SDO2 P25/#BFR/SPISS2 VSS P52 P26/SDA1 P26/SDA1 P27/SCL1 P27/SCL1 VSS VSS HVDD P30/TOUT0/CAP0 P30/TOUT0/CAP0 LVDD P53 P31/#BFR/ADTRG DST2/P37 DST2/P37 LVDD DSIO/P36 DSIO/P36 TEST DCLK/P35 DCLK/P35 P33/REMI/SPICLK2 P33/REMI/SPICLK2 P34/REMO/ P34/REMO/#SPISS1 P54 X (mm) Y (mm) No. -1190 -1050 -910 -770 -630 -490 -350 -210 -70 70 210 350 490 630 770 910 1050 1190 1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1190 -1050 -910 -770 -630 -490 -350 -210 -70 70 210 350 490 630 770 910 1050 1190 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Name P55 VSS OSC1 OSC2 VPP OSC3 VSS OSC4 HVDD P20/TOUT2/CAP2 P20/TOUT2/CAP2 P21/TOUT3/CAP3 P21/TOUT3/CAP3 P22(EXCL1)/FOUTB P23(EXCL2)/SDI2 LVDD N.C. N.C. VSS N.C. #RESET LVDD P40/SIN0/TOUT6/CAP6 P40/SIN0/TOUT6/CAP6 P41/SOUT0/TOUT7/CAP7 P41/SOUT0/TOUT7/CAP7 P42/SCLK0/TOUT1/CAP1 P42/SCLK0/TOUT1/CAP1 P45(EXCL0)/SDA0 HVDD VSS P17/SCL0 P17/SCL0 P32/TOUT4/CAP4/FOUTA P32/TOUT4/CAP4/FOUTA N.C. AVDD AVDD P03/AIN3 P03/AIN3 P02/AIN2 P02/AIN2 P01/AIN1 P01/AIN1 P00/AIN0 P00/AIN0 N.C. Seiko Epson Corporation X (mm) Y (mm) 1190 1050 910 770 630 490 350 210 70 -70 -210 -350 -490 -630 -770 -910 -1050 -1190 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 1190 1050 910 770 630 490 350 210 70 -70 -210 -350 -490 -630 -770 -910 -1050 -1190 S1C17554/564 S1C17554/564 Technical Manual 1 OVERVIEW 1.3.2 S1C17564 S1C17564 Pin Configuration Diagram 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 P54/US P54/US_SDO1 P34/REMO/ P34/REMO/#SPISS1 P33/REMI/SPICLK2 P33/REMI/SPICLK2 DCLK/P35 DCLK/P35 TEST DSIO/P36 DSIO/P36 DST2/P37 DST2/P37 P31/#BFR/#ADTRG P53/US P53/US_SDI1 LVDD P30/TOUT0/CAP0 P30/TOUT0/CAP0 HVDD VSS P27/SCL1 P27/SCL1 P26/SDA1 P26/SDA1 P52/US P52/US_SCK0 US_SDI0/P50 SDI0/P50 SDI0/P10 SDI0/P10 VSS SDO0/P11 SDO0/P11 SPICLK0/P12 SPICLK0/P12 #SPISS0/TOUT5/CAP5/P13 SPISS0/TOUT5/CAP5/P13 LVDD HVDD SIN1/SDI1/P14 SIN1/SDI1/P14 US_SDO0/P51 SDO0/P51 SOUT1/SDO1/P15 SOUT1/SDO1/P15 SCLK1/SPICLK1/P16 SCLK1/SPICLK1/P16 SDA1/REMI/P43 SDA1/REMI/P43 SCL1/REMO/P44 SCL1/REMO/P44 SDO2/P24 SDO2/P24(EXCL3) #BFR/#SPISS2/P25 SPISS2/P25 #RESET LVDD SIN0/TOUT6/CAP6/P40 SIN0/TOUT6/CAP6/P40 SOUT0/TOUT7/CAP7/P41 SOUT0/TOUT7/CAP7/P41 SCLK0/TOUT1/CAP1/P42 SCLK0/TOUT1/CAP1/P42 SDA0/P45 SDA0/P45(EXCL0) HVDD VSS SCL0/P17 SCL0/P17 TOUT4/CAP4/FOUTA/P32 N.C. AVDD AIN3/US_SSI1/P03 SSI1/P03 AIN2/US_SSI0/P02 SSI0/P02 AIN1/P01 AIN1/P01 AIN0/P00 AIN0/P00 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 REGEN VSS VIN VOUT P23(EXCL2)/SDI2 P22(EXCL1)/FOUTB P21/TOUT3/CAP3 P21/TOUT3/CAP3 P20/TOUT2/CAP2 P20/TOUT2/CAP2 HVDD OSC4 OSC3 VPP OSC2 OSC1 VSS P55/US P55/US_SCK1 TQFP13-64pin (S1C17564 S1C17564) Figure 1.3.2.1 S1C17564 S1C17564 Pin Configuration Diagram (TQFP13-64pin) S1C17554/564 S1C17554/564 Technical Manual Seiko Epson Corporation 1-9 1 OVERVIEW REGEN VSS VIN VOUT LVDD P23(EXCL2)/SDI2 P22(EXCL1)/FOUTB P21/TOUT3/CAP3 P21/TOUT3/CAP3 P20/TOUT2/CAP2 P20/TOUT2/CAP2 HVDD OSC4 VSS OSC3 VPP OSC2 OSC1 VSS P55/US P55/US_SCK1 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 Chip (S1C17564 S1C17564) 55 36 P54/US P54/US_SDO1 LVDD 56 35 P34/REMO/ P34/REMO/#SPISS1 SIN0/TOUT6/CAP6/P40 SIN0/TOUT6/CAP6/P40 57 34 P33/REMI/SPICLK2 P33/REMI/SPICLK2 SOUT0/TOUT7/CAP7/P41 SOUT0/TOUT7/CAP7/P41 58 33 DCLK/P35 DCLK/P35 SCLK0/TOUT1/CAP1/P42 SCLK0/TOUT1/CAP1/P42 59 32 TEST SDA0/P45 SDA0/P45(EXCL0) 60 31 DSIO/P36 DSIO/P36 HVDD 61 30 LVDD VSS 62 29 DST2/P37 DST2/P37 SCL0/P17 SCL0/P17 63 28 P31/#BFR/#ADTRG TOUT4/CAP4/FOUTA/P32 64 27 P53/US P53/US_SDI1 N.C. 65 26 LVDD AVDD 66 25 P30/TOUT0/CAP0 P30/TOUT0/CAP0 AVDD 67 24 HVDD AIN3/US_SSI1/P03 SSI1/P03 68 23 HVDD AIN2/US_SSI0/P02 SSI0/P02 69 22 VSS AIN1/P01 AIN1/P01 70 21 P27/SCL1 P27/SCL1 AIN0/P00 AIN0/P00 71 20 P26/SDA1 P26/SDA1 N.C. 72 19 P52/US P52/US_SCK0 Y (0, 0) X 14 15 16 17 SCL1/REMO/P44 SCL1/REMO/P44 HVDD SDO2/P24 SDO2/P24(EXCL3) #BFR/#SPISS2/P25 SPISS2/P25 18 13 SDA1/REMI/P43 SDA1/REMI/P43 VSS 12 8 HVDD SCLK1/SPICLK1/P16 SCLK1/SPICLK1/P16 7 LVDD 11 6 #SPISS0/TOUT5/CAP5/P13 SPISS0/TOUT5/CAP5/P13 SOUT1/SDO1/P15 SOUT1/SDO1/P15 5 SPICLK0/P12 SPICLK0/P12 10 4 SDO0/P11 SDO0/P11 US_SDO0/P51 SDO0/P51 3 VSS 9 2 SDI0/P10 SDI0/P10 SIN1/SDI1/P14 SIN1/SDI1/P14 1 US_SDI0/P50 SDI0/P50 Die No. CJ554D0B0 CJ554D0B0 3.137 mm #RESET 3.137 mm Figure 1.3.2.2 S1C17564 S1C17564 Pad Configuration Diagram Chip size Pad opening X = 3.137 mm, Y = 3.137 mm No. 1 to 18, 37 to 54: X = 122 µm, Y = 85 µm No. 19 to 36, 55 to 72: X = 85 µm, Y = 122 µm Chip thickness 400 µm 1-10 Seiko Epson Corporation S1C17554/564 S1C17554/564 Technical Manual 1 OVERVIEW Table 1.3.2.1 S1C17564 S1C17564 Pad Coordinates No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Name P50/US P50/US_SDI0 P10/SDI0 P10/SDI0 VSS P11/SDO0 P11/SDO0 P12/SPICLK0 P12/SPICLK0 P13/#SPISS0/TOUT5/CAP5 LVDD HVDD P14/SIN1/SDI1 P14/SIN1/SDI1 P51/US P51/US_SDO0 P15/SOUT1/SDO1 P15/SOUT1/SDO1 P16/SCLK1/SPICLK1 P16/SCLK1/SPICLK1 P43/SDA1/REMI P43/SDA1/REMI P44/SCL1/REMO P44/SCL1/REMO HVDD P24(EXCL3)/SDO2 P25/#BFR/SPISS2 VSS P52/US P52/US_SCK0 P26/SDA1 P26/SDA1 P27/SCL1 P27/SCL1 VSS HVDD HVDD P30/TOUT0/CAP0 P30/TOUT0/CAP0 LVDD P53/US P53/US_SDI1 P31/#BFR/ADTRG DST2/P37 DST2/P37 LVDD DSIO/P36 DSIO/P36 TEST DCLK/P35 DCLK/P35 P33/REMI/SPICLK2 P33/REMI/SPICLK2 P34/REMO/ P34/REMO/#SPISS1 P54/US P54/US_SDO1 S1C17554/564 S1C17554/564 Technical Manual X (mm) Y (mm) No. -1190 -1050 -910 -770 -630 -490 -350 -210 -70 70 210 350 490 630 770 910 1050 1190 1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1190 -1050 -910 -770 -630 -490 -350 -210 -70 70 210 350 490 630 770 910 1050 1190 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Name P55/US P55/US_SCK1 VSS OSC1 OSC2 VPP OSC3 VSS OSC4 HVDD P20/TOUT2/CAP2 P20/TOUT2/CAP2 P21/TOUT3/CAP3 P21/TOUT3/CAP3 P22(EXCL1)/FOUTB P23(EXCL2)/SDI2 LVDD VOUT VIN VSS REGEN #RESET LVDD P40/SIN0/TOUT6/CAP6 P40/SIN0/TOUT6/CAP6 P41/SOUT0/TOUT7/CAP7 P41/SOUT0/TOUT7/CAP7 P42/SCLK0/TOUT1/CAP1 P42/SCLK0/TOUT1/CAP1 P45(EXCL0)/SDA0 HVDD VSS P17/SCL0 P17/SCL0 P32/TOUT4/CAP4/FOUTA P32/TOUT4/CAP4/FOUTA N.C. AVDD AVDD P03/AIN3/US P03/AIN3/US_SSI1 P02/AIN2/US P02/AIN2/US_SSI0 P01/AIN1 P01/AIN1 P00/AIN0 P00/AIN0 N.C. Seiko Epson Corporation X (mm) Y (mm) 1190 1050 910 770 630 490 350 210 70 -70 -210 -350 -490 -630 -770 -910 -1050 -1190 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 -1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 1455.5 1190 1050 910 770 630 490 350 210 70 -70 -210 -350 -490 -630 -770 -910 -1050 -1190 1-11 1 OVERVIEW 1.3.3 Pin Descriptions Note: The pin names described in boldface type are default settings. Table 1.3.3.1 Pin Descriptions Name HVDD LVDD VSS VPP AVDD VIN VOUT REGEN OSC3 OSC4 OSC1 OSC2 #RESET TEST P00 AIN0 P01 AIN1 P02 AIN2 US_SSI0 P03 AIN3 US_SSI1 P10 SDI0 P11 SDO0 P12 SPICLK0 P13 #SPISS0 TOUT5 CAP5 P14 SIN1 SDI1 P15 SOUT1 SDO1 P16 SCLK1 SPICLK1 P17 SCL0 P20 TOUT2 CAP2 P21 TOUT3 CAP3 P22 (EXCL1) FOUTB P23 (EXCL2) SDI2 P24 (EXCL3) SDO2 1-12 I/O Default status ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ I I I I O O I I O O I I(Pull-up) I I(Pull-down) I/O I(Pull-up) I I/O I(Pull-up) I I/O I(Pull-up) I I/O I/O I(Pull-up) I I/O I/O I(Pull-up) I I/O I(Pull-up) O I/O I(Pull-up) I/O I/O I(Pull-up) I O I I/O I(Pull-up) I I I/O I(Pull-up) O O I/O I(Pull-up) I I/O I/O I(Pull-up) I/O I/O I(Pull-up) O I I/O I(Pull-up) O I I/O I(Pull-up) O I/O I(Pull-up) I I/O I(Pull-up) O Available ( )/unavailable (­) S1C17554 S1C17554 S1C17564 S1C17564 TQFP/ TQFP/ WCSP Chip Chip Function I/O power supply pins (1.65 to 5.5 V) Core power supply pins (1.65 to 1.95 V) GND pins Flash programming power supply pin (7 V) (Leave the pin open during normal operation.) Analog power supply pin (2.7 to 5.5 V) Regulator input pin (2.0 to 5.5 V) Regulator output pin (1.8 V) Regulator enable input pin OSC3 oscillator input or external clock (LVDD level) input pin OSC3 oscillator output pin OSC1 oscillator input or external clock (LVDD level) input pin OSC1 oscillator output pin Initial reset input pin Test input pin (Connect to VSS for normal operation.) I/O port pin A/D converter Ch.0 analog signal input pin I/O port pin A/D converter Ch.1 analog signal input pin I/O port pin A/D converter Ch.2 analog signal input pin USI Ch.0 slave select signal input or data input/output pin (S1C17564 S1C17564) I/O port pin A/D converter Ch.3 analog signal input pin USI Ch.1 slave select signal input or data input/output pin (S1C17564 S1C17564) I/O port pin SPI Ch.0 data input pin I/O port pin SPI Ch.0 data output pin I/O port pin SPI Ch.0 clock input/output pin I/O port pin SPI Ch.0 slave select signal input pin T16A Ch.2 TOUT B signal output pin T16A Ch.2 capture B trigger signal input pin I/O port pin UART Ch.1 data input pin SPI Ch.1 data input pin I/O port pin UART Ch.1 data output pin SPI Ch.1 data output pin I/O port pin UART Ch.1 external clock input pin SPI Ch.1 clock input/output pin I/O port pin I2C master SCL input/output pin I/O port pin T16A Ch.1 TOUT A signal output pin T16A Ch.1 capture A trigger signal input pin I/O port pin T16A Ch.1 TOUT B signal output pin T16A Ch.1 capture B trigger signal input pin I/O port pin (T16A Ch.1 external clock input pin) Clock output pin I/O port pin (T16A Ch.2 external clock input pin) SPI Ch.2 data input pin I/O port pin (T16A Ch.3 external clock input pin) SPI Ch.2 data output pin Seiko Epson Corporation ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ S1C17554/564 S1C17554/564 Technical Manual 1 OVERVIEW Name P25 #BFR #SPISS2 P26 SDA1 P27 SCL1 P30 TOUT0 CAP0 P31 #BFR #ADTRG P32 TOUT4 CAP4 FOUTA P33 REMI SPICLK2 P34 REMO #SPISS1 DCLK P35 DSIO P36 DST2 P37 P40 SIN0 TOUT6 CAP6 P41 SOUT0 TOUT7 CAP7 P42 SCLK0 TOUT1 CAP1 P43 SDA1 REMI P44 SCL1 REMO P45 (EXCL0) SDA0 P50 US_SDI0 P51 US_SDO0 P52 US_SCK0 P53 US_SDI1 P54 US_SDO1 P55 US_SCK1 I/O I/O I I I/O I/O I/O I/O I/O O I I/O I I I/O O I O I/O I I/O I/O O I O I/O I/O I/O O I/O I/O I O I I/O O O I I/O I O I I/O I/O I I/O I/O O I/O I/O I/O I/O I/O O I/O I/O I/O I/O I/O O I/O I/O Default status I(Pull-up) I(Pull-up) I(Pull-up) I(Pull-up) I(Pull-up) I(Pull-up) I(Pull-up) I(Pull-up) O(H) I(Pull-up) O(L) I(Pull-up) I(Pull-up) I(Pull-up) I(Pull-up) I(Pull-up) I(Pull-up) I(Pull-up) I(Pull-up) I(Pull-up) I(Pull-up) I(Pull-up) I(Pull-up) Function I/O port pin I2C slave bus free request input pin SPI Ch.2 slave select signal input pin I/O port pin I2C slave data input/output pin I/O port pin I2C slave SCL input/output pin I/O port pin T16A Ch.0 TOUT A signal output pin T16A Ch.0 capture A trigger signal input pin I/O port pin I2C slave bus free request input pin A/D converter external trigger input pin I/O port pin T16A Ch.2 TOUT A signal output pin T16A Ch.2 capture A trigger signal input pin Clock output pin I/O port pin REMC input pin SPI Ch.2 clock input/output pin I/O port pin REMC output pin SPI Ch.1 slave select signal input pin On-chip debugger clock output pin I/O port pin On-chip debugger data input/output pin I/O port pin On-chip debugger status output pin I/O port pin I/O port pin UART Ch.0 data input pin T16A Ch.3 TOUT A signal output pin T16A Ch.3 capture A trigger signal input pin I/O port pin UART Ch.0 data output pin T16A Ch.3 TOUT B signal output pin T16A Ch.3 capture B trigger signal input pin I/O port pin UART Ch.0 external clock input pin T16A Ch.0 TOUT B signal output pin T16A Ch.0 capture B trigger signal input pin I/O port pin I2C slave data input/output pin REMC input pin I/O port pin I2C slave SCL input/output pin REMC output pin I/O port pin (T16A Ch.0 external clock input pin) I2C master data input/output pin I/O port pin USI Ch.0 data input/output pin (S1C17564 S1C17564) I/O port pin USI Ch.0 data output pin (S1C17564 S1C17564) I/O port pin USI Ch.0 clock input/output pin (S1C17564 S1C17564) I/O port pin USI Ch.1 data input/output pin (S1C17564 S1C17564) I/O port pin USI Ch.1 data output pin (S1C17564 S1C17564) I/O port pin USI Ch.1 clock input/output pin (S1C17564 S1C17564) S1C17554/564 S1C17554/564 Technical Manual Seiko Epson Corporation Available ( )/unavailable (­) S1C17554 S1C17554 S1C17564 S1C17564 TQFP/ TQFP/ WCSP Chip Chip ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ 1-13 2 CPU 2 CPU The S1C17554/564 S1C17554/564 contains the S1C17 S1C17 Core as its core processor. The S1C17 S1C17 Core is a Seiko Epson original 16-bit RISC-type processor. It features low power consumption, high-speed operation, large address space, main instructions executable in one clock cycle, and a small sized design. The S1C17 S1C17 Core is suitable for embedded applications such as controllers and sequencers for which an eight-bit CPU is commonly used. For details of the S1C17 S1C17 Core, refer to the "S1C17 S1C17 Family S1C17 S1C17 Core Manual." 2.1 Features of the S1C17 S1C17 Core Processor type · Seiko Epson original 16-bit RISC processor · 0.35­0.15 µm low power CMOS process technology Instruction set · Code length: 16-bit fixed length · Number of instructions: 111 basic instructions (184 including variations) · Execution cycle: Main instructions executed in one cycle · Extended immediate instructions: Immediate extended up to 24 bits · Compact and fast instruction set optimized for development in C language Register set · Eight 24-bit general-purpose registers · Two 24-bit special registers · One 8-bit special register Memory space and bus · Up to 16M bytes of memory space (24-bit address) · Harvard architecture using separated instruction bus (16 bits) and data bus (32 bits) Interrupts · Reset, NMI, and 32 external interrupts supported · Address misaligned interrupt · Debug interrupt · Direct branching from vector table to interrupt handler routine · Programmable software interrupts with a vector number specified (all vector numbers specifiable) Power saving · HALT (halt instruction) · SLEEP (slp instruction) Coprocessor interface · 16-bit × 16-bit multiplier · 16-bit ÷ 16-bit divider · 16-bit × 16-bit + 32-bit multiply and accumulation unit S1C17554/564 S1C17554/564 Technical Manual Seiko Epson Corporation 2-1 2 CPU 2.2 CPU Registers The S1C17 S1C17 Core contains eight general-purpose registers and three special registers. Special registers bit 23 General-purpose registers bit 0 PC SP PSR 7 6 IL[2:0] 5 4 IE 3 C 2 V 1 0 Z N bit 23 7 6 5 4 3 2 1 0 R7 R6 R5 R4 R3 R2 R1 R0 bit 0 Figure 2.2.1 Registers 2.3 Instruction Set The S1C17 S1C17 Core instruction codes are all fixed to 16 bits in length which, combined with pipelined processing, allows most important instructions to be executed in one cycle. For details, refer to the "S1C17 S1C17 Family S1C17 S1C17 Core Manual." Table 2.3.1 List of S1C17 S1C17 Core Instructions Classification Data transfer ld.b ld.ub ld ld.a 2-2 Mnemonic %rd,%rs %rd,[%rb] %rd,[%rb]+ %rd,[%rb]%rd,-[%rb] %rd,[%sp+imm7] %rd,[imm7] [%rb],%rs [%rb]+,%rs [%rb]-,%rs -[%rb],%rs [%sp+imm7],%rs [imm7],%rs %rd,%rs %rd,[%rb] %rd,[%rb]+ %rd,[%rb]%rd,-[%rb] %rd,[%sp+imm7] %rd,[imm7] %rd,%rs %rd,sign7 %rd,[%rb] %rd,[%rb]+ %rd,[%rb]%rd,-[%rb] %rd,[%sp+imm7] %rd,[imm7] [%rb],%rs [%rb]+,%rs [%rb]-,%rs -[%rb],%rs [%sp+imm7],%rs [imm7],%rs %rd,%rs %rd,imm7 Function General-purpose register (byte) general-purpose register (sign-extended) Memory (byte) general-purpose register (sign-extended) Memory address post-increment, post-decrement, and pre-decrement functions can be used. Stack (byte) general-purpose register (sign-extended) Memory (byte) general-purpose register (sign-extended) General-purpose register (byte) memory Memory address post-increment, post-decrement, and pre-decrement functions can be used. General-purpose register (byte) stack General-purpose register (byte) memory General-purpose register (byte) general-purpose register (zero-extended) Memory (byte) general-purpose register (zero-extended) Memory address post-increment, post-decrement, and pre-decrement functions can be used. Stack (byte) general-purpose register (zero-extended) Memory (byte) general-purpose register (zero-extended) General-purpose register (16 bits) general-purpose register Immediate general-purpose register (sign-extended) Memory (16 bits) general-purpose register Memory address post-increment, post-decrement, and pre-decrement functions can be used. Stack (16 bits) general-purpose register Memory (16 bits) general-purpose register General-purpose register (16 bits) memory Memory address post-increment, post-decrement, and pre-decrement functions can be used. General-purpose register (16 bits) stack General-purpose register (16 bits) memory General-purpose register (24 bits) general-purpose register Immediate general-purpose register (zero-extended) Seiko Epson Corporation S1C17554/564 S1C17554/564 Technical Manual 2 CPU Classification Data transfer Integer arithmetic operation ld.a Mnemonic %rd,[%rb] %rd,[%rb]+ %rd,[%rb]%rd,-[%rb] %rd,[%sp+imm7] %rd,[imm7] [%rb],%rs [%rb]+,%rs [%rb]-,%rs -[%rb],%rs [%sp+imm7],%rs [imm7],%rs %rd,%sp %rd,%pc %rd,[%sp] %rd,[%sp]+ %rd,[%sp]%rd,-[%sp] [%sp],%rs [%sp]+,%rs [%sp]-,%rs -[%sp],%rs %sp,%rs %sp,imm7 %rd,%rs add add/c add/nc add %rd,imm7 add.a %rd,%rs add.a/c add.a/nc add.a %sp,%rs %rd,imm7 %sp,imm7 adc %rd,%rs adc/c adc/nc adc %rd,imm7 sub %rd,%rs sub/c sub/nc sub %rd,imm7 sub.a %rd,%rs sub.a/c sub.a/nc sub.a %sp,%rs %rd,imm7 %sp,imm7 sbc %rd,%rs sbc/c sbc/nc sbc %rd,imm7 cmp %rd,%rs cmp/c cmp/nc cmp %rd,sign7 cmp.a %rd,%rs cmp.a/c cmp.a/nc cmp.a %rd,imm7 cmc %rd,%rs cmc/c cmc/nc cmc %rd,sign7 S1C17554/564 S1C17554/564 Technical Manual Function Memory (32 bits) general-purpose register (*1) Memory address post-increment, post-decrement, and pre-decrement functions can be used. Stack (32 bits) general-purpose register (*1) Memory (32 bits) general-purpose register (*1) General-purpose register (32 bits, zero-extended) memory (*1) Memory address post-increment, post-decrement, and pre-decrement functions can be used. General-purpose register (32 bits, zero-extended) stack (*1) General-purpose register (32 bits, zero-extended) memory (*1) SP general-purpose register PC general-purpose register Stack (32 bits) general-purpose register (*1) Stack pointer post-increment, post-decrement, and pre-decrement functions can be used. General-purpose register (32 bits, zero-extended) stack (*1) Stack pointer post-increment, post-decrement, and pre-decrement functions can be used. General-purpose register (24 bits) SP Immediate SP 16-bit addition between general-purpose registers Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0). 16-bit addition of general-purpose register and immediate 24-bit addition between general-purpose registers Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0). 24-bit addition of SP and general-purpose register 24-bit addition of general-purpose register and immediate 24-bit addition of SP and immediate 16-bit addition with carry between general-purpose registers Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0). 16-bit addition of general-purpose register and immediate with carry 16-bit subtraction between general-purpose registers Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0). 16-bit subtraction of general-purpose register and immediate 24-bit subtraction between general-purpose registers Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0). 24-bit subtraction of SP and general-purpose register 24-bit subtraction of general-purpose register and immediate 24-bit subtraction of SP and immediate 16-bit subtraction with carry between general-purpose registers Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0). 16-bit subtraction of general-purpose register and immediate with carry 16-bit comparison between general-purpose registers Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0). 16-bit comparison of general-purpose register and immediate 24-bit comparison between general-purpose registers Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0). 24-bit comparison of general-purpose register and immediate 16-bit comparison with carry between general-purpose registers Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0). 16-bit comparison of general-purpose register and immediate with carry Seiko Epson Corporation 2-3 2 CPU Classification Logical operation Shift and swap and and/c and/nc and or or/c or/nc or xor xor/c xor/nc xor not not/c not/nc not sr sa sl swap Immediate extension ext cv.ab Conversion cv.as cv.al cv.la cv.ls jpr Branch jpr.d jpa jpa.d jrgt jrgt.d jrge jrge.d jrlt jrlt.d jrle jrle.d jrugt jrugt.d jruge jruge.d jrult jrult.d jrule jrule.d jreq jreq.d jrne jrne.d call call.d calla calla.d ret ret.d int intl reti reti.d brk 2-4 Mnemonic %rd,%rs Function Logical AND between general-purpose registers Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0). %rd,sign7 %rd,%rs Logical AND of general-purpose register and immediate Logical OR between general-purpose registers Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0). %rd,sign7 %rd,%rs Logical OR of general-purpose register and immediate Exclusive OR between general-purpose registers Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0). %rd,sign7 %rd,%rs Exclusive OR of general-purpose register and immediate Logical inversion between general-purpose registers (1's complement) Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0). %rd,sign7 %rd,%rs %rd,imm7 %rd,%rs %rd,imm7 %rd,%rs %rd,imm7 %rd,%rs imm13 %rd,%rs %rd,%rs %rd,%rs %rd,%rs %rd,%rs sign10 %rb imm7 %rb sign7 Logical inversion of general-purpose register and immediate (1's complement) Logical shift to the right with the number of bits specified by the register Logical shift to the right with the number of bits specified by immediate Arithmetic shift to the right with the number of bits specified by the register Arithmetic shift to the right with the number of bits specified by immediate Logical shift to the left with the number of bits specified by the register Logical shift to the left with the number of bits specified by immediate Bytewise swap on byte boundary in 16 bits Extend operand in the following instruction Converts signed 8-bit data into 24 bits Converts signed 16-bit data into 24 bits Converts 32-bit data into 24 bits Converts 24-bit data into 32 bits Converts 16-bit data into 32 bits PC relative jump Delayed branching possible Absolute jump Delayed branching possible PC relative conditional jump Branch condition: !Z & !(N ^ V) Delayed branching possible PC relative conditional jump Branch condition: !(N ^ V) Delayed branching possible PC relative conditional jump Branch condition: N ^ V Delayed branching possible Branch condition: Z | N ^ V PC relative conditional jump Delayed branching possible PC relative conditional jump Branch condition: !Z & !C Delayed branching possible PC relative conditional jump Branch condition: !C Delayed branching possible PC relative conditional jump Branch condition: C Delayed branching possible PC relative conditional jump Branch condition: Z | C Delayed branching possible Branch condition: Z PC relative conditional jump Delayed branching possible PC relative conditional jump Branch condition: !Z Delayed branching possible PC relative subroutine call Delayed call possible Absolute subroutine call Delayed call possible Return from subroutine Delayed return possible Software interrupt Software interrupt with interrupt level setting Return from interrupt handling Delayed call possible Debug interrupt sign7 sign7 sign7 sign7 sign7 sign7 sign7 sign7 sign7 sign10 %rb imm7 %rb imm5 imm5,imm3 Seiko Epson Corporation S1C17554/564 S1C17554/564 Technical Manual 2 CPU Classification Branch System control Mnemonic retd nop halt slp ei di Coprocessor control ld.cw ld.ca ld.cf Function %rd,%rs %rd,imm7 %rd,%rs %rd,imm7 %rd,%rs %rd,imm7 Return from debug processing No operation HALT mode SLEEP mode Enable interrupts Disable interrupts Transfer data to coprocessor Transfer data to coprocessor and get results and flag statuses Transfer data to coprocessor and get flag statuses *1 The ld.a instruction accesses memories in 32-bit length. During data transfer from a register to a memory, the 32-bit data in which the eight high-order bits are set to 0 is written to the memory. During reading from a memory, the eight high-order bits of the read data are ignored. The symbols in the above table each have the meanings specified below. Table 2.3.2 Symbol Meanings Symbol Description General-purpose register, source General-purpose register, destination Memory addressed by general-purpose register Memory addressed by general-purpose register with address post-incremented Memory addressed by general-purpose register with address post-decremented Memory addressed by general-purpose register with address pre-decremented Stack pointer Stack Stack with address post-incremented Stack with address post-decremented Stack with address pre-decremented Unsigned immediate (numerals indicating bit length) Signed immediate (numerals indicating bit length) %rs %rd [%rb] [%rb]+ [%rb]-[%rb] %sp [%sp],[%sp+imm7] [%sp]+ [%sp]-[%sp] imm3,imm5,imm7,imm13 sign7,sign10 2.4 Reading PSR The S1C17554/564 S1C17554/564 includes the MISC_PSR register for reading the contents of the PSR (Processor Status Register) in the S1C17 S1C17 Core. Reading the contents of this register makes it possible to check the contents of the PSR using the application software. Note that data cannot be written to the PSR. PSR Register (MISC_PSR) Register name Address PSR Register (MISC_PSR) 0x532c (16 bits) Bit D15­8 D7­5 D4 D3 D2 D1 D0 Name ­ PSRIL[2:0] PSRIE PSRC PSRV PSRZ PSRN Function reserved PSR interrupt level (IL) bits PSR interrupt enable (IE) bit PSR carry (C) flag PSR overflow (V) flag PSR zero (Z) flag PSR negative (N) flag Setting 1 1 1 1 1 ­ 0x0 to 0x7 1 (enable) 0 0 (disable) 1 (set) 0 0 (cleared) 1 (set) 0 0 (cleared) 1 (set) 0 0 (cleared) 1 (set) 0 0 (cleared) D[15:8] ­ R R R R R R Remarks 0 when being read. PSRIL[2:0]: PSR Interrupt Level (IL) Bits The value of the PSR IL (interrupt level) bits can be read out. (Default: 0x0) D4 ­ 0x0 0 0 0 0 0 Reserved D[7:5] Init. R/W PSRIE: PSR Interrupt Enable (IE) Bit The value of the PSR IE (interrupt enable) bit can be read out. 1 (R): 1 (interrupt enabled) 0 (R): 0 (interrupt disabled) (default) S1C17554/564 S1C17554/564 Technical Manual Seiko Epson Corporation 2-5 2 CPU D3 PSRC: PSR Carry (C) Flag Bit The value of the PSR C (carry) flag can be read out. 1 (R): 1 0 (R): 0 (default) D2 PSRV: PSR Overflow (V) Flag Bit The value of the PSR V (overflow) flag can be read out. 1 (R): 1 0 (R): 0 (default) D1 PSRZ: PSR Zero (Z) Flag Bit The value of the PSR Z (zero) flag can be read out. 1 (R): 1 0 (R): 0 (default) D0 PSRN: PSR Negative (N) Flag Bit The value of the PSR N (negative) flag can be read out. 1 (R): 1 0 (R): 0 (default) 2.5 Processor Information The S1C17554/564 S1C17554/564 has the IDIR register shown below that allows the application software to identify CPU core type. Processor ID Register (IDIR) Register name Address Processor ID Register (IDIR) 0xffff84 (8 bits) Bit D7­0 Name IDIR[7:0] Function Processor ID 0x10: S1C17 S1C17 Core Setting 0x10 Init. R/W 0x10 Remarks R This is a read-only register that contains the ID code to represent a processor model. The S1C17 S1C17 Core's ID code is 0x10. 2-6 Seiko Epson Corporation S1C17554/564 S1C17554/564 Technical Manual 3 MEMORY MAP, BUS CONTROL 3 Memory Map, Bus Control Figure 3.1 shows the S1C17554/564 S1C17554/564 memory map. 0xff ffff 0xff fc00 0xff fbff Reserved for core I/O area (1K bytes) reserved 0x02 8000 0x02 7fff Flash area (128K bytes) (Device size: 16 bits) 0x00 0x00 0x00 0x00 8000 7fff 6000 5fff 0x00 0x00 0x00 0x00 5000 4fff 4400 43ff 0x00 4000 0x00 3fff 0x00 3fc0 Vector table reserved Internal peripheral area 2 (4K bytes) reserved Internal peripheral area 1 (1K bytes) Debug RAM area (64 bytes) Internal RAM area (16K bytes) (Device size: 32 bits) 0x00 0000 0x5500­0x5fff 0x5480­0x54ff 0x5400­0x547f 0x53a0­0x53ff 0x5380­0x539f 0x5360­0x537f 0x5340­0x535f 0x5320­0x533f 0x52c0­0x531f 0x52a0­0x52bf 0x5280­0x529f 0x5200­0x527f 0x5140­0x51ff 0x5120­0x513f 0x5100­0x511f 0x50c0­0x50ff 0x50a0­0x50bf 0x5060­0x509f 0x5040­0x505f 0x5020­0x503f 0x5000­0x501f Peripheral function (Device size) reserved ­ Flash controller (16 bits) 16-bit PWM timer Ch.0­3 (16 bits) reserved ­ A/D converter (16 bits) reserved ­ IR remote controller (16 bits) MISC registers (16 bits) reserved ­ Port MUX (8 bits) reserved ­ P ports (8 bits) reserved ­ Power generator (S1C17564 S1C17564) (8 bits) reserved ­ USI Ch.0­1 (S1C17564 S1C17564) (8 bits) reserved ­ Clock generator (8 bits) Watchdog timer (8 bits) Stopwatch timer (8 bits) Clock timer (8 bits) 0x43c0­0x43ff 0x4380­0x43bf 0x4360­0x437f 0x4340­0x435f 0x4320­0x433f 0x42e0­0x431f 0x4280­0x42df 0x4220­0x427f 0x4200­0x421f 0x4140­0x41ff 0x4100­0x413f 0x4040­0x40ff 0x4020­0x403f 0x4000­0x401f reserved SPI Ch.1­2 I2C slave I2C master SPI Ch.0 Interrupt controller Fine mode 16-bit timer Ch.1 16-bit timer Ch.0­2 Fine mode 16-bit timer Ch.0 reserved UART Ch.0­1 reserved MISC registers reserved ­ (16 bits) (16 bits) (16 bits) (16 bits) (16 bits) (16 bits) (16 bits) (16 bits) ­ (8 bits) ­ (8 bits) ­ Figure 3.1 S1C17554/564 S1C17554/564 Memory Map 3.1 Bus Cycle The CPU uses the system clock for bus access operations. For more information on the system clock, see "System Clock Switching" in the "Clock Generator (CLG)" chapter. Note that the Flash area and other areas require different number of system clocks for one bus cycle as follows: Instruction/data read from areas other than the Flash area: One system clock per one bus cycle Instruction read from the Flash area: One to three system clocks or equivalent per one bus cycle Data read from the Flash area: Two to four system clocks per one bus cycle Furthermore, the number of bus accesses depends on the CPU instruction (access size) and device size. S1C17554/564 S1C17554/564 Technical Manual Seiko Epson Corporation 3-1 3 MEMORY MAP, BUS CONTROL Table 3.1.1 Number of Bus Accesses Device size CPU access size Number of bus accesses 8 bits 8 bits 16 bits 32 bits* 8 bits 16 bits 32 bits* 8 bits 16 bits 32 bits* 1 2 4 1 1 2 1 1 1 16 bits 32 bits * Handling the eight high-order bits during 32-bit accesses The size of the S1C17 S1C17 Core general-purpose registers is 24 bits. During writing, the eight high-order bits are written as 0. During reading from a memory, the eight high-order bits are ignored. However, the stack operation in an interrupt handling reads/writes 32-bit data that consists of the PSR value as the high-order 8 bits and the return address as the low order 24 bits. For more information, refer to the "S1C17 S1C17 Core Manual." 3.1.1 Restrictions on Access Size The peripheral modules can be accessed with an 8-bit, 16-bit, or 32-bit instruction. However, reading for an unnecessary register may change the peripheral module status and it may cause a problem. Therefore, use the appropriate instructions according to the device size. 3.1.2 Restrictions on Instruction Execution Cycles An instruction fetch and a data access are not performed simultaneously under one of the conditions listed below. This prolongs the instruction fetch cycle for the number of data area bus cycles. · When the S1C17554/564 S1C17554/564 executes the instruction stored in the Flash area and accesses data in the Flash area · When the S1C17554/564 S1C17554/564 executes the instruction stored in the internal RAM area and accesses data in the internal RAM area 3.2 Flash Area 3.2.1 Embedded Flash Memory The 128K-byte area from address 0x8000 to address 0x27fff contains a Flash memory (4K bytes × 32 sectors) for storing application programs and data. Address 0x8000 is defined as the vector table base address, therefore a vector table (see "Vector Table" in the "Interrupt Controller (ITC)" chapter) must be placed from the beginning of the area. The vector table base address can be modified with the MISC_TTBRL/MISC_TTBRH registers. 3.2.2 Flash Programming The S1C17554/564 S1C17554/564 supports on-board programming of the Flash memory, it makes it possible to program the Flash memory with the application programs/data by using the debugger through an ICDmini. The Flash memory supports sector erase method. For the Flash programming using the debugger, see the "S5U1C17001C S5U1C17001C Manual" included in the S1C17 S1C17 Family C Compiler Package. For the self-programming controlled by the user program, see the "Self-Programming (FLS) Application Notes" for the S1C17554/564 S1C17554/564. 3-2 Seiko Epson Corporation S1C17554/564 S1C17554/564 Technical Manual 3 MEMORY MAP, BUS CONTROL 3.2.3 Protect Bits In order to protect the memory contents, the Flash memory provides two protection features, write protection and data read protection, that can be configured for every 16K-byte areas. The write protection disables writing data to the configured area and erasing the sectors (except the sector that includes the protect bits). The data-read protection disables reading data from the configured area (the read value is always 0x0000). However, it does not disable the instruction fetch operation by the CPU. The Flash memory provides the protect bits listed below. Program the protect bit corresponding to the area to be protected to 0. The protection can only be disabled using the debugger. Flash Protect Bits Address Bit 0x27ffc (16 bits) D15­8 D7 D6 D5 D4 D3 D2 D1 D0 D15­8 D7 D6 D5 D4 D3 D2 D1 D0 0x27ffe (16 bits) Function Setting reserved reserved Flash write-protect bit for 0x20000­0x23fff Flash write-protect bit for 0x1c000­0x1ffff Flash write-protect bit for 0x18000­0x1bfff Flash write-protect bit for 0x14000­0x17fff Flash write-protect bit for 0x10000­0x13fff Flash write-protect bit for 0xc000­0xffff Flash write-protect bit for 0x8000­0xbfff reserved Flash data-read-protect bit for 0x24000­0x27fff Flash data-read-protect bit for 0x20000­0x23fff Flash data-read-protect bit for 0x1c000­0x1ffff Flash data-read-protect bit for 0x18000­0x1bfff Flash data-read-protect bit for 0x14000­0x17fff Flash data-read-protect bit for 0x10000­0x13fff Flash data-read-protect bit for 0xc000­0xffff reserved Init. R/W ­ 1 1 1 1 1 1 1 1 Writable Writable Writable Writable Writable Writable Writable 0 0 0 0 0 0 0 1 1 1 1 1 1 1 Readable Readable Readable Readable Readable Readable Readable Protected Prot