S1215 STS-12/STM-4 GR-253 OC-12/ 5/TU-11 VT2/TU-12 OC-12/STM4 STS-12 PB2013 - Datasheet Archive

 

5 21 S1 UR AM S1215 (Amur) Deep channelization SONET/SDH to PDH framer and 1K Channels HDLC/ATM/GFP processor Overview SONET/SDH

 

Product Brief 5 21 S1 UR AM S1215 S1215 (Amur) Deep channelization SONET/SDH to PDH framer and 1K Channels HDLC/ATM/GFP processor Overview SONET/SDH Line Features Tributary Features S1215 S1215 (Amur) interfaces with 155Mbps/622Mbps SONET/SDH (1xSTS-12/STM-4, 4xSTS-3/STM-1) optical signals and 12x DS3/E3 or 32xDS1/E1/J1 copper signals. The device performs standardscompliant framing, channelization and termination following SONET/SDH (STS-1 to VT/TU) and PDH (DS3/E3 to DS1/E1/J1) multiplexing hierarchies. Built-in data processors support Frame Relay, PPP, GFP and ATM data mappings for up to 1024 channels with DS-0 granularity. Additionally, S1215 S1215 (Amur) supports add/drop functionality for TDM traffic with selection down to DS-0 level, enabling applications such as Circuit Emulation Services or Voice Processing in Media-Gateways or DS-0 crossconnects. The high-density channelization, termination and service assignment flexibility enables deployment of small form factor access/edge switches and routers with multi-protocol line cards. S1215 S1215 (Amur), along with nP3705, significantly reduces the size, power and cost of MPLS switches and routers. The programmable features of the solution enables future software upgrades to support evolving requirements. · Provides line-interface for single STS-12/STM-4 STS-12/STM-4 or quad STS-3/STM-1. · Processes any valid combination of SONET/SDH STS-3c/AU-4, or STS-1/AU-3 tributaries within an STS-3/STM-1. · Terminates/generates SONET/SDH section, line, and path overhead. SONET/SDH processing of all defined TOH/POH bytes, compliant with Telcordia GR-253 GR-253 and ANSI T1.105, and ITU G.751, G.783, G.804. · Supports independent loop-timing for OC-12/ OC-12/ STM-4 and quad OC-3/STM-1 line configuration. · Processes up to 4 concatenated STS-3c payloads. · Provides DS3/E3 mapping and demapping for up to 12 DS3/E3 tributaries. · Provides framing for 168 DS1/J1 or 126 E1/J1 channels. · Provides channelized mapping for up to 168 DS1/J1 into VT1.5/TU-11 5/TU-11 or 126 E1/J1 into VT2/TU-12 VT2/TU-12 or any valid combination. · Supports loop-timing for DS3/E3 and DS1/E1/J1 on a per tributary basis. · Supports full-featured DS3/E3 and DS1/E1/J1 PMON. · Supports M23 and C-bit parity DS3 frame formats for demapped tributaries or for native DS3 line interfaces. · Supports G.751and G.832-based E3 formats. · Supports M13, C-bit parity, and G.747 (21xE1 into DS-3) for channelized DS3 applications. · On chip PRBS generators and receivers for DS1/E1/J1 and DS3/ E3. · Loopback capabilities for SONET/ SDH line side. · Channelized loopbacks at payload, VT1.5/TU-11 5/TU-11, DS1/E1/J1, · DS3/E3 and TU-3/VC-3 levels. · 16-bit general purpose microprocessor interface supporting · Intel and Motorola modes. · Configurable power down modes for different applications. DS1/E1/J1 Line Interface · Provides serial LIU ports for 32 individual DS1/ E1/J1 lines for termination/origination of payload. DS3/E3 Line Interface · Provides serial LIU ports for 12 individual DS3/E3 lines for termination/origination of payload. SONET/SDH Protection · Support protection-switching configurations {1+1, 1:n}. RLDRAM-2/ FCRAM Data Memory Substrate DS3/E3 12xDS3/E3 Line I/F OC-12/STM4 OC-12/STM4 4xOC3/STM1 Full Framer OC-12/STM4 OC-12/STM4 4xOC3/STM1 Light Framer Ptr Proc 12ch Ptr Proc 12ch Bstruct SRAM MMU Queue Mgrs QAB bus STS-1 STS-3c/12c HO POH STS-1/ VC3 x12 Timeslot 2 channel mapper 12 x DS3/E3 Framers M13 X6 VT/TU Map 168 VT 126 TU12 LO POH DS1/E1/J1 Framers 168 DS1 126 E1 CAS Signaling 4032 DSO 1024 Channels HDLC ATM 168 Ch GFP Two-frame slip buffers 4-port SPI-3 TDM Highway FTI 32xDS1/E1/J1 Line I/F Host I/F 16-bit, 66MHz Figure 1. Block Diagram 8/32 Mb/s 104MHz 8/16 Mb/s 21 Lanes 8-bit, 78MHz S1215 S1215 (Amur) Data Termination Features TDM and Voice Features · Store and forward architecture with extensive buffering using external RLDRAM/FCRAM II memory. · 1023 duplex channels that can be configured as bit-sync HDLC, bytesync HDLC, ATM, or direct-mapped payload. · 168 channels can be assigned for GFP-F. · Supports up to 12 subrate DS3 channels. · On-chip queue management with programmable watermarks and thresholds. · Extensive layer 2 error monitoring and statistics collection. · Packets/cells delivered over a 8/32-bit SPI-3 bus running up to 104 MHz. · 4-port SPI-3 interface with a prepended tag for channel ID, length, error status, and service-specific fields. · Supports add/drop of TDM tributaries through a Flexible Tributary Interface Level 2 (FTI-2) providing extraction of VT/TU/STS and PDH signals with DS0 level marking · FTI interface provides connectivity to external devices for applications such as Circuit Emulation Services. · Supports Voice termination through a synchronous TDM Highway interface, with an aggregate bandwidth of 2xOC-3/STM-1 · TDM Highway is compatible with H-MVIP and ST-Bus specifications · Channel Associated Signaling (CAS) processing for up to 4032 DS-0 signals · CAS marking on FTI and TDM Highway interfaces · Mixed data / voice termination between internal GHAP processor and TDM highway supported with per-DS-0 selection Applications · Edge Routers and Multi-Service Switches: High integration, deep channelization (DS1/E1, DS0) data interfaces for ATM, GFP, IMA, MPLS, Frame Relay, ML-FR, IP/PPP, ML-PPP, services with IP Fragmentation/ reassembly, SARing, QoS, traffic shaping, policing, protocol conversion · Mixed data/Voice termination in Media/Voice/Wireless Gateways nP3705 Layer 3 ~ 7 Processing Layer 2 Protocol Inter Working - FRF 8.1, Martini PPP FR ATM MPLS ML-PPP ML-FR IMA Per Flow / Per Channel Traffic Management S1215 S1215 (AMUR) RL/FC-DRAMII Packets Packets Cells HDLC ATM TC/ PLCP nxDS3/E3, nxDS1/E1/J1, nxDS0 STS-12 STS-12, STS-3, STS-1 Ethernet MAC 10/100 Mbps & 1Gbps Figure 2. Complete MISSION Access protocol stack support with S1215 S1215 (Amur) and nP3705 6290 Sequence Drive San Diego, CA 92121 P 858.450.9333 F 858.450.9885 www.amcc.com RL/FC-DRAMII SPI-3 Channelized 2xOC-3 / STM-1, 6 xT3/E3, or 32 x DS1/E1/J1 S1215 S1215 AMUR QAB nP3705 SPI-3 or SPI-4.2 Flexible Tributary Interface Circuit Emulation Services SPI-3 or GE QDR SRAM CPU Control Plane Figure 3. CES Solution Example Block Diagram AMCC reserves the right to make changes to its products, or to discontinue any product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied upon is current. AMCC is a registered trademark of Applied Micro Circuits Corporation. 3ware, SwitchedRAID and 3DM are registered trademarks in the United States and StorSwitch is a trademark in the United States, of Applied Micro Circuits Corporation. All other trademarks are the property of their respective holders. Copyright © 2004 Applied Micro Circuits Corporation. All Rights Reserved. S1215 S1215_PB2013 PB2013_10/03/04