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Part Manufacturer Description Datasheet BUY
74ACT11377NT Texas Instruments Octal D-Type Flip-Flops With Clock Enable 24-PDIP -40 to 85 visit Texas Instruments
SN74HC377DWR Texas Instruments Octal D-Type Flip-Flops With Clock Enable 20-SOIC -40 to 85 visit Texas Instruments Buy
SN74HC378N3 Texas Instruments 6-Bit D-Type Flip-Flops With Clock Enable 16-PDIP -40 to 85 visit Texas Instruments
SN74HCT377DWG4 Texas Instruments Octal D-Type Flip-Flops With Clock Enable 20-SOIC -40 to 85 visit Texas Instruments
SN74LS377N Texas Instruments Octal D-Type Flip-Flops With Clock Enable 20-PDIP 0 to 70 visit Texas Instruments
74ACT11378N Texas Instruments Hex D-Type Flip-Flops With Clock Enable 20-PDIP -40 to 85 visit Texas Instruments

S-R flip flop clock

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: buffer register and resets the SR flip flop. CLOCK: Input Mode: This input strobes data into the buffer when it is activated (high) and sets the SR flip flop (SR = 0) while latching data on its negative , from the peripheral into the 8 bit buffer register by a logic high on the Clock signal input; the negative clock transition sets the service request flip flop low (SR = 0) and latches data. When the CS1 , request flip flop. The 1852 operates over a 4â'"10.5 voltage range while the 1852C operates over a -
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H1852 H1852C

sr flip flop

Abstract: S-R flip flop clock PSoC CreatorTM Component Datasheet ® SR Flip Flop 1.0 Features Clocked for safe use in synchronous circuits. Configurable width for array of SR Flip Flops. General Description The SR Flip Flop stores a digital value that can be set or reset. When to Use an SR Flip Flop Use the SR Flip Flop to , connections for the SR Flip Flop. s ­ Input This input sets the output (to logic high `1'). The output , , 2012 SR Flip Flop PSoC CreatorTM Component Datasheet ® Component Parameters Drag a Toggle
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sr flip flop S-R flip flop clock high frequency flip flop

4 input d flip flop

Abstract: D Flip Flops PSoC CreatorTM Component Datasheet ® D Flip Flop 1.30 Features Asynchronous reset or , Description The D Flip Flop stores a digital value. When to Use a D Flip Flop Use the D Flip Flop to , connections for the D Flip Flop. An asterisk (*) in the list of I/Os states that the I/O may be hidden on the , 95134-1709 · 408-943-2600 Document Number: 001-84971 Rev. * Revised December 3, 2012 D Flip Flop PSoC , Output The stored value of the D Flip Flop. Component Parameters Drag a D Flip Flop onto your design
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4 input d flip flop D Flip Flops D flip flop

D Flip Flops

Abstract: Revised June 20, 2012 D Flip Flop PSoC CreatorTM Component Datasheet ® of the clock signal , to ArrayWidth. All D Flip Flop components in the same PLD must have the same clock signal for , PSoC CreatorTM Component Datasheet ® D Flip Flop 1.20 Features Asynchronous reset or , width General Description The D Flip Flop stores a digital value. When to Use a D Flip Flop Use the D Flip Flop to implement sequential logic. Input/Output Connections This section describes the
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asynchronous 4bit up down counter using jk flip flop

Abstract: counter 74168 D-type latch 3 (2) 93 L205 D-type latch with reset 4 (2) D-type flip flops 94 DFF D-type flip flop 6 (3) 95 DFR D-type flip flop with reset 8 (3) 96 F112 D-type flip flop with reset 7 (3) 97 F113 D-type flip flop with set 7 (3) 98 DF D-type flip flop with set/reset 9 (3) 99 F114 D-type flip flop with set/reset 8 (3) 100 F115 D-type flip flop with reset 7 (3) 101 F116 D-type flip flop with set 7 (3) 102 DF1 D-type flip flop with set/reset 8 (3) 103 F121 D-type flip flop 6 (4) 104 F125
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asynchronous 4bit up down counter using jk flip flop counter 74168 Multiplexer 74152 3-8 decoder 74138 synchronous counter using 4 flip flip 74183 alu MSM70V000 MSM-71V000 MSM72V000 MSM73V000 MSM74V000 MSM79V000

counter 74168

Abstract: 3-8 decoder 74138 3 (2) 93 L205 D-type latch with reset 4 (2) D-type flip flops 94 DFF D-type flip flop 6 (3) 95 DFR D-type flip flop with reset 8 (3) 96 F112 D-type flip flop with reset 7 (3) 97 F1 13 D-type flip flop with set 7 (3) 98 DF D-type flip flop with set/reset 9 (3) 99 F114 D-type flip flop with set/reset 8 (3) 100 F115 D-type flip flop with reset 7 (3) 101 F116 D-type flip flop with set 7 (3) 102 DF 1 D-type flip flop with set/reset 8 (3) 103 F121 D-type flip flop 6 (4) 104 F125 D-type
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counter 74169 74183 adder 74169 binary counter 74381 alu 74175 flip flops flip flop 74379 MSM75V000 MSM-76V000 MSM77V000 MSM78V000

74139 for bcd to excess 3 code

Abstract: design a bcd counter using jk flip flop L205 D-type latch with reset 4 (2) D-type flip flops 94 DFF D-type flip flop 6 (3) 95 DFR D-type flip flop with reset 8 (3) 96 F112 D-type flip flop with reset 7 (3) 97 F113 D-type flip flop with set 7 (3) 98 DF D-type flip flop with set/reset 9 (3) 99 F114 D-type flip flop with set/reset 8 (3) 100 F115 D-type flip flop with reset 7 (3) 101 F116 D-type flip flop with sit 7 (3) 102 DF1 D-type flip flop with set /reset 8 (3) 103 F121 D-type flip flop 6 (4) 104 F125 D-type flip flop with
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74139 for bcd to excess 3 code design a bcd counter using jk flip flop ttl 74118 priority encoder 74148 alu 74381 jk flip flop to d flip flop conversion MSM70H000 MSM-71H000 MSM72H000 MSM73H000 MSM74H000 MSM79H000

sr flip flop pin diagram

Abstract: latching flip flop buffer reglster by a logie high on the Clock signal input; the negative clock transition sets the service request flip flop low (SR = 0) and latches data. When the CS1 and CS2 signais are enabled, the data , the port's register (DO O-DO 7) and service request flip flop. The 1852 operates over a 4â'"10.5 , and resets the SR flip f lop. CLOCK: Input Mode: This input strobes data into the buffer when it is activated (high) and sets the SR flip flop (SR = 0} while latching data on its negative transition. Output
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sr flip flop pin diagram latching flip flop Hughes newport D00-D0

priority encoder 74148

Abstract: priority encoder 74147 146 D2N Internal invert driver-2 4 50 3.4 1-47 D3N Internal invert driver-3 7 70 33 Flip flop 1-48 DLT D-type latch with reset 4 8 55 1-49 DFF D-type flip flop 6 8 5.6/7.2 , ) Maximum No. of fan-out Delay time tpd (ns) (*1> Flip flop 1-53 JKFR J-K flip flop with reset _ 11 8 6.9
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MSM72000 priority encoder 74147 shift register 7495 msm7200 MSM7000 msm7500 MSM70000 MSM71000 MSM73000 MSM74000 MSM75000

74169 SYNCHRONOUS 4-BIT BINARY COUNTER

Abstract: 74139 demultiplexer Flip Flop with Reset D-Type Flip Flop with Set/Reset J-K Flip Flop with Reset J-K Flip Flop with Set/R eset Toggle Flip Flop with Reset Dual Inverter Dual 2-Input NAND Dual 3-Input NAND Dual 4-Input NAND Dual 2-Input NOR Dual 3-Input NOR Dual 4-Input NOR Dual S-R Type Latch Dual D-Type Flip Flop with Reset , /Up Mode Control Synchronous BCD Up/Down Dual Clock Counter with Clear Synchronous 4-Bit Binary Up/Down Dual Clock Counter with Clear 4-Bit Bidirectional Universal Shift Register 4-Bit Parallel-Access
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74169 SYNCHRONOUS 4-BIT BINARY COUNTER 74139 demultiplexer 3-8 decoder 74138 pin diagram CI 74151 pin diagram 41 multiplexer 74153 JK Shift Register 74195 MSM60300 MSM60700 MSM61000

1LB553

Abstract: Rauland ETS-003 Primitive Cells (Cont.) Name Flip Flop FD1x FD1SX FD2x FD2Sx FD3x FD3SX FD4x FD4Sx FJK1X FJKISx FJK2X , D-Flip flop D-flip flop with scan D-flip flop with clear D-flip flop with clear/scan D-flip flop with preset/clear D-flip flop with preset/clear and scan D-flip flop with preset D-flip flop with preset/scan J-K flip flop J-K flip flop with scan J-K flip flop with clear J-K flip flop with clear/scan J-K flip flop with preset/clear J-K flip flop with preset/clear and scan Toggle flip flop with clear Toggle flip
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1LB553 Rauland ETS-003 Silec Semiconductors 4057A transistor sr52 logos 4012B IEC179 TDA1510 TDA1510A

siemens master drive circuit diagram

Abstract: SR flip flop IC Reset 2 8 41 DFR D-Type Flip Flop with Reset 4 8 42 DF D-Type Flip Flop with Set/Reset 5 8 43 JKFR J-K Flip Flop with Reset 6 8 44 JKF J-K Rip Flop with Set/Reset 7 8 45 TFR Toggle Flip Flop with , -lnput NOR 2 3 53 LT2 Dual S-R Type Latch 3 8 54 DFR2 Dual D-Type Flip Flop with Reset 8 8 55 2AD2 Dual 2 , 31 74193 Synchronous 4-Bit Binary Up/Down Dual Clock Counter with Clear (0193) 46 32 74194 4 , B1 Clock Buffer-1 (Invert) 1 10 63 B2 Clock Buffer-2 (Through) 1 20 64 B3 Clock Buffer-3 (Through
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TC110G siemens master drive circuit diagram SR flip flop IC toshiba tc110g SC11C1 JK flip flop IC M33S004

74139 demultiplexer

Abstract: 74169 SYNCHRONOUS 4-BIT BINARY COUNTER 0869 9 Bar Code Reader Figure 10. CNTTC Detector Circuitry Toggle Flip Flop SAMPLE D0 SMCLK Q0 CNTS CLK CD Edge "D" Flip Flop SAMPLE D0 CNTS SMCLK Q0 CLK , DIN2 Bar Code Reader Figure 11. Edge Detector Circuitry "D" Flip Flop "D" Flip Flop DIN , SMCLK LASTHALF D0 K0 Q0 FJK21 LASTHALF CLK "D" Flip Flop D0 SECOND_HALF , Flip Flop to store the lower 4 bits of the bar's width FD24 ([C0.C3]), [L0.L3], LATCH, RST
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bcd counter using j-k flip flop diagram pin diagram priority decoder 74148 74181 74175 clock 74165 block diagram 74151 demultiplexer 74195 TTL shift register MSMC0300

CBU34

Abstract: SRR38 Circuitry Toggle Flip Flop SAMPLE D0 SMCLK Q0 CNTS CLK CD Edge "D" Flip Flop , "D" Flip Flop "D" Flip Flop DIN D0 Q0 DIN1 SMCLK Q0 CLK CLK RST RST , "D" Flip Flop D0 SECOND_HALF SECOND_HALF LATCH CLK CD RST LCHAR LHK , , GND)]; END; SYM GLB A4 1; // This is the Flip Flop to store the lower 4 bits of the bar's width FD24 ([C0.C3]), [L0.L3], LATCH, RST); END; SYM GLB A5 1; // This is the Flip Flop to store
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SRR38 MUX22 CBU34 CBU44 CBU42 bar code reader SRR31

bar code reader

Abstract: 8 shift register by using D flip-flop exception of Syn chronous Reset. Parallel load inputs and flip -flo p outputs are m ultiplexed to m inim ize pin count. Separate inputs and outputs are provided fo r flip -flop s Qo and Q7 to allow easy , D-type flip -flop s and the interstage logic necessary to perform synchronous reset, shift left, shift , modes are activated on the LO W -to-HIG H transition of the Clock. T-T so [ 7 O l i [2 ö l2 [ä l/O , /O7 DESCRIPTION Clock Pulse Input (Active Rising Edge) Serial Data Input fo r Right Shift Serial Data
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8 shift register by using D flip-flop Umux

S-R flip flop clock

Abstract: sr flip flop PIN DIAGRAM Bar Code Reader Figure 10. CNTTC Detector Circuitry Toggle Flip Flop SAMPLE D0 Q0 CNTS SMCLK CLK CD Edge "D" Flip Flop SAMPLE CNTS D0 Q0 DIN2 SMCLK CLK RST 0870 , Figure 11. Edge Detector Circuitry "D" Flip Flop "D" Flip Flop DIN D0 Q0 DIN1 D0 , LASTHALF D0 Q0 LHK K0 FJK21 LASTHALF SMCLK CLK "D" Flip Flop D0 SECOND_HALF , 1; // FD21 END; This is the Flip Flop to store the MSB of the bar's width (C8, VCC, LATCH, RST
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54LS/74LS323 JI/01 74LS323PC 74LS323DC 74LS323FC 54LS323DM

SRR38

Abstract: CBU34 Hi-Z Flip-Flop outputs app ear on I/O lines A syn chro nous reset fo r all flip -flop s S ynchro nous reset for all flip -flop s Parallel load all flip -flop s Hold Hold (TC held high) C ount up C o unt dow , , are initiated by the rising edge of the clock. TC output is not recommended for use as a clock or , level X = D on't care T = Low-to-High clock transition (not LL) = CS and PE should never both be low
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FD-24

sr flip flop IC

Abstract: B93 60x60 MCC851 MCC951 Monostable Multivibrator 29H 55x55 MCC852 MCC952 Dual J-K Flip Flop (common Clock and CD) 45 N 60x62 MCC853 MCC953 Dual J-K Flip Flop (Separate Clock and SD) 45N 60x62 MCC855 MCC955 Dual J-K Flip Flop (2K Pullup Resistor) 45N 60x62 MCC856 MCC956 Dual J-K Flip Flop (2K Pullup
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MC74F579

MC1741C

Abstract: MC1741CP1 Flop SAMPLE D0 SMCLK Q0 CNTS CLK CD Edge "D" Flip Flop SAMPLE D0 CNTS , Circuitry "D" Flip Flop "D" Flip Flop DIN D0 Q0 DIN1 SMCLK D0 Q0 DIN2 CLK , K0 Q0 FJK21 LASTHALF CLK "D" Flip Flop D0 SECOND_HALF SECOND_HALF LATCH , , CNTLD, CNTTC, START, IDLE, GND)]; END; SYM GLB A4 1; // This is the Flip Flop to store the lower 4 , ; // This is the Flip Flop to store the upper 4 bits of the bar's width FD24 ([C4.C7]), [L4.L7
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MC1741C MC1741CP1 MCC1741C MCC830 MCC831 MCC832 MIL-STD-883 MCC862 MCC962 MCC863 MCC963 MCC1800
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