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PROMOCLOCKE Freescale Semiconductor BINARY CLOCK 9S08QG8 ri Buy
74ACT11379N Texas Instruments Quadruple D-Type Flip-Flops With Clock Enable 20-PDIP -40 to 85 ri Buy
74ACT11379DW Texas Instruments Quadruple D-Type Flip-Flops With Clock Enable 20-SOIC -40 to 85 ri Buy

S-R flip flop clock

Catalog Datasheet Results Type PDF Document Tags
Abstract: PSoC CreatorTM Component Datasheet ® SR Flip Flop 1.0 Features Clocked for safe use in synchronous circuits. Configurable width for array of SR Flip Flops. General Description The SR Flip Flop stores a digital value that can be set or reset. When to Use an SR Flip Flop Use the SR Flip Flop to , connections for the SR Flip Flop. s ­ Input This input sets the output (to logic high `1'). The output , , 2012 SR Flip Flop PSoC CreatorTM Component Datasheet ® Component Parameters Drag a Toggle ... Original
datasheet

3 pages,
107.76 Kb

high frequency flip flop S-R flip flop clock sr flip flop datasheet abstract
datasheet frame
Abstract: PSoC CreatorTM Component Datasheet ® D Flip Flop 1.30 Features Asynchronous reset or , Description The D Flip Flop stores a digital value. When to Use a D Flip Flop Use the D Flip Flop to , connections for the D Flip Flop. An asterisk (*) in the list of I/Os states that the I/O may be hidden on the , 95134-1709 · 408-943-2600 Document Number: 001-84971 Rev. * Revised December 3, 2012 D Flip Flop PSoC , Output The stored value of the D Flip Flop. Component Parameters Drag a D Flip Flop onto your design ... Original
datasheet

5 pages,
161.13 Kb

"D Flip Flops" D flip flop 4 input d flip flop datasheet abstract
datasheet frame
Abstract: Revised June 20, 2012 D Flip Flop PSoC CreatorTM Component Datasheet ® of the clock signal. , logical equation implemented in macrocell product terms: Q = D & ~SR Table 1. 1-ArrayWidth D Flip Flop , to ArrayWidth. All D Flip Flop components in the same PLD must have the same clock signal for , PSoC CreatorTM Component Datasheet ® D Flip Flop 1.20 Features Asynchronous reset or , width General Description The D Flip Flop stores a digital value. When to Use a D Flip Flop Use the ... Original
datasheet

4 pages,
153.72 Kb

datasheet abstract
datasheet frame
Abstract: Internal invert tristate bus driver -1 4 F0^12 84 BHD1 Bus hold -1 3 Latches 85 LTND S-R NAND latch 3 86 LTNR S-R NOR latch 3 87 L101 S-R latch with enable 4 88 L102 S-R latch with clear 4 89 , flip flop 6 (3) 95 DFR D-type flip flop with reset 8 (3) 96 F112 D-type flip flop with reset 7 (3) 97 F1 13 D-type flip flop with set 7 (3) 98 DF D-type flip flop with set/reset 9 (3) 99 F114 D-type flip flop with set/reset 8 (3) 100 F115 D-type flip flop with reset 7 (3) 101 F116 D-type flip ... OCR Scan
datasheet

23 pages,
575.25 Kb

74168 74183 alu flip flop 74379 shift register 7491 alu 74381 74137 demultiplexer 74169 SYNCHRONOUS 4-BIT BINARY COUNTER MH 74151 74175 flip flops alu 74181 encoder 74147 74183 adder 38 decoder using 74138 datasheet abstract
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Abstract: 83 TB11 Internal invert tristate bus driver -1 4 F0 , DFF D-type flip flop 6 (3) 95 DFR D-type flip flop with reset 8 (3) 96 F112 D-type flip flop with reset 7 (3) 97 F113 D-type flip flop with set 7 (3) 98 DF D-type flip flop with set/reset 9 (3) 99 F114 D-type flip flop with set/reset 8 (3) 100 F115 D-type flip flop with reset 7 (3) 101 F116 ... OCR Scan
datasheet

30 pages,
733.51 Kb

74183 alu 74259 74169 binary counter 74151 adder priority encoder 74147 decoder 3-8 74ls with nor gate TTL 74139 74138 logic circuit 74139 Dual 2 to 4 line decoder 74139 demultiplexer 74118 design excess 3 counter using 74161 74541 buffer datasheet abstract
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Abstract: F0^12 84 BHD1 Bus hold -1 3 Latches 85 LTND S-R NAND latch 3 86 LTNR S-R NOR latch 3 87 L101 S-R latch with enable 4 88 L102 S-R latch with clear 4 89 DLT D-type latch with reset 4 (1) 90 , D-type latch with reset 4 (2) D-type flip flops 94 DFF D-type flip flop 6 (3) 95 DFR D-type flip flop with reset 8 (3) 96 F112 D-type flip flop with reset 7 (3) 97 F113 D-type flip flop with set 7 (3) 98 DF D-type flip flop with set/reset 9 (3) 99 F114 D-type flip flop with set/reset 8 (3) 100 ... OCR Scan
datasheet

23 pages,
1040.92 Kb

74139 for bcd to excess 3 code 74183 adder 74139 demultiplexer 74381 alu multiplexer 74151 7482 full adder priority encoder 74147 alu 74381 shift register 7495 counter 74169 74183 alu 74169 SYNCHRONOUS 4-BIT BINARY COUNTER 71V000 73V000 71V000 abstract
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Abstract: S-R Type Latch D-Type Latch with Reset D-Type Flip Flop with Reset D-Type Flip Flop with Set/Reset J-K Flip Flop with Reset J-K Flip Flop with Set/R eset Toggle Flip Flop with Reset Dual Inverter Dual , S-R Type Latch Dual D-Type Flip Flop with Reset Dual 2-Input AND Dual 3-Input AND Dual 2-Input OR Dual , Up/Down Counter with Down/Up Mode Control Synchronous BCD Up/Down Dual Clock Counter with Clear Synchronous 4-Bit Binary Up/Down Dual Clock Counter with Clear 4-Bit Bidirectional Universal Shift Register ... OCR Scan
datasheet

8 pages,
403.21 Kb

pin diagram priority decoder 74138 Multiplexer 74153 74181 74175 clock pin diagram priority decoder 74148 decoder 74139 74138 logic gates counter 74162 ttl 74165 74139 decoder counter schematic diagram using 74193 CI 74151 74169 binary counter MSM60300 MSM60700 MSM60300 abstract
datasheet frame
Abstract: Function No. of Unit Cells FO. Max. 37 44 R 4-lnput 4-Wide OR-AND 5 3 38 1CRY 1 Bit Carry 2 10 39 LT S-R Type Latch 2 8 40 DLT D-Type Latch with Reset 2 8 41 DFR D-Type Flip Flop with Reset 4 8 42 DF D-Type Flip Flop with Set/Reset 5 8 43 JKFR J-K Flip Flop with Reset 6 8 44 JKF J-K Rip Flop with Set/Reset 7 8 45 TFR Toggle Flip Flop with Reset 4 8 46 INV2 Dual Inverter 1 10 47 2ND2 Dual 2-lnput NAND , 3NR2 Dual 3-lnput NOR 2 4 52 4NR2 Dual 4-lnput NOR 2 3 53 LT2 Dual S-R Type Latch 3 8 54 DFR2 Dual ... OCR Scan
datasheet

8 pages,
224.2 Kb

74151 adder TTL 74139 bcd counter using t flip flop diagram counter 74190 counter schematic diagram 74161 Ci 74153 inverter 74169 binary counter 7493 binary counter diagram 74151 demultiplexer 74195 TTL shift register CI 74151 74169 binary counter MSM60300 MSM60700 MSM60300 abstract
datasheet frame
Abstract: , pulse) the S-R flip flop (constructed from two NOR gates of the CD4001A CD4001A) generates a reset pulse which , goes high at this time. Coincidence of the clock low and decoded "0" output low resets the S-R flip , to a decimal number. Inputs include a CLOCK, a RESET, and a CLOCK INHIBIT signal. The decade counter Is advanced one count at the positive clock signal transition if the CLOCK INHIBIT signal is low. Counter advancement via the clock line is inhibited when the clock INHIBIT signal is high. A high reset ... OCR Scan
datasheet

4 pages,
178.15 Kb

CMOS decade counter CD4017 features CD4001A CMOS counter divider 10 100 1000 S-R flip flop clock cd4017 application notes ican6166 CD4017 gate diagram CD4017 application of i CD4017 johnson decade counter cd4017 applications CD4017A CA-CD4017A CD4017A abstract
datasheet frame
Abstract: with the exception of Syn chronous Reset. Parallel load inputs and flip -flo p outputs are m ultiplexed to m inim ize pin count. Separate inputs and outputs are provided fo r flip -flop s Qo and Q7 to , D-type flip -flop s and the interstage logic necessary to perform synchronous reset, shift left, shift , parallel load. All modes are activated on the LO W -to-HIG H transition of the Clock. T-T so [ 7 O l i , INPUT LOADING/FAN-OUT: See Section 3 fo r U.L. definitions PIN NAMES CP Dso DS7 So, Si SR OE 1 , OE2 l/O ... OCR Scan
datasheet

3 pages,
178.28 Kb

S-R flip flop clock 54LS/74LS323 54LS/74LS323 abstract
datasheet frame

Datasheet Content (non pdf)

Abstract Saved from Date Saved File Size Type Download
Over 1.1 million files (1986-2014): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer.
 
No abstract text available
www.datasheetarchive.com/download/54425949-995932ZC/xapp220.zip (LFSR2_vhd.vhd)
Xilinx 13/12/2000 5.98 Kb ZIP xapp220.zip
No abstract text available
www.datasheetarchive.com/download/26794946-996405ZC/verilog.tar
Xilinx 20/01/1997 13424.65 Kb TAR verilog.tar
No abstract text available
www.datasheetarchive.com/download/54803669-39594ZC/test102.zip (ATM1500.VLB)
Atmel 19/01/1998 463.64 Kb ZIP test102.zip
8 BIT PISO SHIFT REGISTER | Contents | M54HCT174 M54HCT174 M54HCT174 M54HCT174 - HEX D-TYPE FLIP FLOP WITH CLEAR OCTAL D TYPE FLIP FLOP WITH CLEAR | Contents | M54HCT30 M54HCT30 M54HCT30 M54HCT30 - 8 INPUT NAND GATE | Contents INVERTING , HCT533 HCT533 HCT533 HCT533 INVERTING | Contents | M54HCT374 M54HCT374 M54HCT374 M54HCT374 - OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT | Contents | M54HCT534 M54HCT534 M54HCT534 M54HCT534 - OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT HCT374 HCT374 HCT374 HCT374 NON INVERTING , HCT534 HCT534 HCT534 HCT534 NON INVERTING | Contents | M54HCT564 M54HCT564 M54HCT564 M54HCT564 - OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT HCT564 HCT564 HCT564 HCT564
www.datasheetarchive.com/files/stmicroelectronics/stonline/books/pdf/alpha/ds/m-v1.htm
STMicroelectronics 07/04/1999 170.76 Kb HTM m-v1.htm
No abstract text available
www.datasheetarchive.com/download/54425949-995932ZC/xapp220.zip (LFSR2_ver.v)
Xilinx 13/12/2000 5.98 Kb ZIP xapp220.zip
| Contents | M54HC107 M54HC107 M54HC107 M54HC107 - DUAL J-K FLIP FLOP WITH CLEAR | Contents | M54HC109 M54HC109 M54HC109 M54HC109 - DUAL J-K FLIP FLOP - DUAL J-K FLIP FLOP WITH PRESET AND CLEAR | Contents | M54HC113 M54HC113 M54HC113 M54HC113 - DUAL J-K FLIP FLOP WITH | M54HC173 M54HC173 M54HC173 M54HC173 - QUAD D-TYPE REGISTER (3-STATE) | Contents | M54HC174 M54HC174 M54HC174 M54HC174 - HEX D-TYPE FLIP FLOP WITH CLEAR - TRIPLE 3-INPUT NOR GATE | Contents | M54HC273 M54HC273 M54HC273 M54HC273 - OCTAL D TYPE FLIP FLOP WITH CLEAR | Contents | M54HC279 M54HC279 M54HC279 M54HC279 - QUAD S-R LATCH | Contents | M54HC280 M54HC280 M54HC280 M54HC280 - 9 BIT PARITY GENERATOR
www.datasheetarchive.com/files/stmicroelectronics/stonline/books/pdf/alpha/ds/m.htm
STMicroelectronics 26/03/1998 234.92 Kb HTM m.htm
this time. Coin- cidence of the clock low and decoded "0" output high resets the S-R flip flop to ) with N Decoded Out- puts. When the N th decoded output is reached (N th clock pulse) the S-R flip-flop , respectively. Inputs include a CLOCK, a RESET, and a CLOCK INHIBIT signal. Schmitt trigger action in the CLOCK input circuit pro- vides pulse shaping that allows unlimited clock input pulse rise and fall times. These counters are ad- vanced one count at the positive clock signal tran- sition if the CLOCK INHIBIT
www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/2029-v1.htm
STMicroelectronics 02/04/1999 10.55 Kb HTM 2029-v1.htm
and decoded "0" output high resets the S-R flip flop to enable the HCC/HCF4017B HCC/HCF4017B HCC/HCF4017B HCC/HCF4017B . If the N th pulse) the S-R flip-flop (constructed from two NOR gates of the HCC/HCF4001B HCC/HCF4001B HCC/HCF4001B HCC/HCF4001B ) gener- ates a reset counters having 10 and 8 decoded outputs, respectively. Inputs include a CLOCK, a RESET, and a CLOCK INHIBIT signal. Schmitt trigger action in the CLOCK input circuit pro- vides pulse shaping that allows unlimited clock input pulse rise and fall times. These counters are ad- vanced one count at the positive
www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/2029-v3.htm
STMicroelectronics 25/05/2000 12.37 Kb HTM 2029-v3.htm
this time. Coin- cidence of the clock low and decoded "0" output high resets the S-R flip flop to ) with N Decoded Out- puts. When the N th decoded output is reached (N th clock pulse) the S-R flip-flop , respectively. Inputs include a CLOCK, a RESET, and a CLOCK INHIBIT signal. Schmitt trigger action in the CLOCK input circuit pro- vides pulse shaping that allows unlimited clock input pulse rise and fall times. These counters are ad- vanced one count at the positive clock signal tran- sition if the CLOCK INHIBIT
www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/2029-v2.htm
STMicroelectronics 14/06/1999 10.51 Kb HTM 2029-v2.htm
the S-R flip flop to enable the HCC/HCF4017B HCC/HCF4017B HCC/HCF4017B HCC/HCF4017B . If the N th decoded output is less than 6, the C ) with N Decoded Out- puts. When the N th decoded output is reached (N th clock pulse) the S-R and 8 decoded outputs, respectively. Inputs include a CLOCK, a RESET, and a CLOCK INHIBIT signal. Schmitt trigger action in the CLOCK input circuit pro- vides pulse shaping that allows unlimited clock input pulse rise and fall times. These counters are ad- vanced one count at the positive clock signal
www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/2029.htm
STMicroelectronics 20/10/2000 12.98 Kb HTM 2029.htm