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S 014124C0E Nordic Power i Stromstad Power Supply Unit Dimensions L x W x H: 183 x 99 x 55 mm Input frequency: 48...63 Hz Output current: 5 A Output voltage: 24 VDC Input voltage: 190...264 VAC, 48...63 Hz Residual ripple: 100 mV Weight: 900 g Connection, primary side: Type F (CEE 7/4) Conne 35 from €108.60 (Aug 2016) Distrelec Buy
S 014148C0E Nordic Power i Stromstad Power Supply Unit Dimensions L x W x H: 183 x 99 x 55 mm Input frequency: 48...63 Hz Output current: 2.5 A Output voltage: 48 VDC Input voltage: 190...264 VAC, 48...63 Hz Residual ripple: 100 mV Weight: 900 g Connection, primary side: Type F (CEE 7/4) Con 3 from €108.60 (Aug 2016) Distrelec Buy
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S-R flip flop clock

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: PSoC CreatorTM Component Datasheet ® SR Flip Flop 1.0 Features Clocked for safe use in synchronous circuits. Configurable width for array of SR Flip Flops. General Description The SR Flip Flop stores a digital value that can be set or reset. When to Use an SR Flip Flop Use the SR Flip Flop to , connections for the SR Flip Flop. s ­ Input This input sets the output (to logic high `1'). The output , , 2012 SR Flip Flop PSoC CreatorTM Component Datasheet ® Component Parameters Drag a Toggle ... Cypress Semiconductor
Original
datasheet

3 pages,
107.76 Kb

high frequency flip flop S-R flip flop clock sr flip flop TEXT
datasheet frame
Abstract: PSoC CreatorTM Component Datasheet ® D Flip Flop 1.30 Features Asynchronous reset or , Description The D Flip Flop stores a digital value. When to Use a D Flip Flop Use the D Flip Flop to , connections for the D Flip Flop. An asterisk (*) in the list of I/Os states that the I/O may be hidden on the , 95134-1709 · 408-943-2600 Document Number: 001-84971 Rev. * Revised December 3, 2012 D Flip Flop PSoC , Output The stored value of the D Flip Flop. Component Parameters Drag a D Flip Flop onto your design ... Cypress Semiconductor
Original
datasheet

5 pages,
161.13 Kb

"D Flip Flops" D flip flop D Flip Flops 4 input d flip flop TEXT
datasheet frame
Abstract: Revised June 20, 2012 D Flip Flop PSoC CreatorTM Component Datasheet ® of the clock signal , to ArrayWidth. All D Flip Flop components in the same PLD must have the same clock signal for , PSoC CreatorTM Component Datasheet ® D Flip Flop 1.20 Features Asynchronous reset or , width General Description The D Flip Flop stores a digital value. When to Use a D Flip Flop Use the D Flip Flop to implement sequential logic. Input/Output Connections This section describes the ... Cypress Semiconductor
Original
datasheet

4 pages,
153.72 Kb

D Flip Flops TEXT
datasheet frame
Abstract: D-type latch 3 (2) 93 L205 D-type latch with reset 4 (2) D-type flip flops 94 DFF D-type flip flop 6 (3) 95 DFR D-type flip flop with reset 8 (3) 96 F112 D-type flip flop with reset 7 (3) 97 F113 D-type flip flop with set 7 (3) 98 DF D-type flip flop with set/reset 9 (3) 99 F114 D-type flip flop with set/reset 8 (3) 100 F115 D-type flip flop with reset 7 (3) 101 F116 D-type flip flop with set 7 (3) 102 DF1 D-type flip flop with set/reset 8 (3) 103 F121 D-type flip flop 6 (4) 104 F125 ... OCR Scan
datasheet

23 pages,
1040.92 Kb

74139 demultiplexer 74381 alu multiplexer 74151 74183 4 bit priority encoder 74147 7482 full adder 74139 for bcd to excess 3 code alu 74381 shift register 7495 counter 74169 MH 74151 74169 SYNCHRONOUS 4-BIT BINARY COUNTER 74183 alu MSM70V000 MSM70V000 synchronous counter using 4 flip flip MSM70V000 MSM70V000 3-8 decoder 74138 MSM70V000 MSM70V000 Multiplexer 74152 MSM70V000 MSM70V000 counter 74168 MSM70V000 MSM70V000 MSM70V000 MSM70V000 MSM70V000 MSM-71V000 MSM72V000 MSM73V000 MSM74V000 MSM79V000 MSM75V000 MSM-76V000 MSM77V000 MSM78V000 TEXT
datasheet frame
Abstract: 3 (2) 93 L205 D-type latch with reset 4 (2) D-type flip flops 94 DFF D-type flip flop 6 (3) 95 DFR D-type flip flop with reset 8 (3) 96 F112 D-type flip flop with reset 7 (3) 97 F1 13 D-type flip flop with set 7 (3) 98 DF D-type flip flop with set/reset 9 (3) 99 F114 D-type flip flop with set/reset 8 (3) 100 F115 D-type flip flop with reset 7 (3) 101 F116 D-type flip flop with set 7 (3) 102 DF 1 D-type flip flop with set/reset 8 (3) 103 F121 D-type flip flop 6 (4) 104 F125 D-type ... OCR Scan
datasheet

23 pages,
575.25 Kb

shift register 7491 MH 74151 alu 74181 74139 for bcd to excess 3 code multiplier 74261 MH 74150 encoder 74147 alu 74381 38 decoder using 74138 74137 demultiplexer 74175 flip flops flip flop 74379 74151 8 by 1 Multiplexer MSM70V000 MSM70V000 74381 alu MSM70V000 MSM70V000 74169 binary counter MSM70V000 MSM70V000 74183 adder MSM70V000 MSM70V000 Multiplexer 74152 MSM70V000 MSM70V000 counter 74169 MSM70V000 MSM70V000 3-8 decoder 74138 MSM70V000 MSM70V000 counter 74168 MSM70V000 MSM70V000 MSM70V000 MSM70V000 MSM70V000 MSM-71V000 MSM72V000 MSM73V000 MSM74V000 MSM79V000 MSM75V000 MSM-76V000 MSM77V000 MSM78V000 TEXT
datasheet frame
Abstract: L205 D-type latch with reset 4 (2) D-type flip flops 94 DFF D-type flip flop 6 (3) 95 DFR D-type flip flop with reset 8 (3) 96 F112 D-type flip flop with reset 7 (3) 97 F113 D-type flip flop with set 7 (3) 98 DF D-type flip flop with set/reset 9 (3) 99 F114 D-type flip flop with set/reset 8 (3) 100 F115 D-type flip flop with reset 7 (3) 101 F116 D-type flip flop with sit 7 (3) 102 DF1 D-type flip flop with set /reset 8 (3) 103 F121 D-type flip flop 6 (4) 104 F125 D-type flip flop with ... OCR Scan
datasheet

30 pages,
733.51 Kb

74169 binary counter 74373 cmos dual s-r latch TTL 74139 74138 logic circuit Multiplexer 74152 74139 Dual 2 to 4 line decoder decoder 3-8 74ls with nor gate 74118 7493 Decade Counter 74139 demultiplexer two 3 to 8 decoders 74138 design excess 3 counter using 74161 MSM70H000 MSM70H000 74541 buffer MSM70H000 MSM70H000 jk flip flop to d flip flop conversion MSM70H000 MSM70H000 alu 74381 MSM70H000 MSM70H000 priority encoder 74148 MSM70H000 MSM70H000 ttl 74118 MSM70H000 MSM70H000 design a bcd counter using jk flip flop MSM70H000 MSM70H000 74139 for bcd to excess 3 code MSM70H000 MSM70H000 MSM70H000 MSM70H000 MSM70H000 MSM-71H000 MSM72H000 MSM73H000 MSM74H000 MSM79H000 MSM75H000 MSM-76H000 MSM77H000 MSM78H000 TEXT
datasheet frame
Abstract: buffer reglster by a logie high on the Clock signal input; the negative clock transition sets the service request flip flop low (SR = 0) and latches data. When the CS1 and CS2 signais are enabled, the data , the port's register (DO O-DO 7) and service request flip flop. The 1852 operates over a 4—10.5 , and resets the SR flip f lop. CLOCK: Input Mode: This input strobes data into the buffer when it is activated (high) and sets the SR flip flop (SR = 0} while latching data on its negative transition. Output ... OCR Scan
datasheet

4 pages,
200.69 Kb

sr flip flop pin diagram sr flip flop latching flip flop Hughes newport TEXT
datasheet frame
Abstract: 146 D2N Internal invert driver-2 4 50 3.4 1-47 D3N Internal invert driver-3 7 70 33 Flip flop 1-48 DLT D-type latch with reset 4 8 55 1-49 DFF D-type flip flop 6 8 5.6/7.2 , ) Maximum No. of fan-out Delay time tpd (ns) (*1> Flip flop 1-53 JKFR J-K flip flop with reset _ 11 8 6.9 ... OCR Scan
datasheet

27 pages,
582.64 Kb

74181 3-8 decoder 74138 ttl 74165 data sheet MS70K design a bcd counter using jk flip flop 74179 74373 cmos dual s-r latch counter 74168 74541 buffer M74000 multiplexers 74 LS 150 74150 demultiplexer MSM72000 MSM70000 MSM71000 msm7500 MSM70000 MSM71000 alu 74381 MSM70000 MSM71000 MSM7000 MSM70000 MSM71000 msm7200 MSM70000 MSM71000 shift register 7495 MSM70000 MSM71000 priority encoder 74147 MSM70000 MSM71000 priority encoder 74148 MSM70000 MSM71000 MSM70000 MSM70000 MSM71000 MSM71000 MSM73000 MSM74000 MSM75000 TEXT
datasheet frame
Abstract: Flip Flop with Reset D-Type Flip Flop with Set/Reset J-K Flip Flop with Reset J-K Flip Flop with Set/R eset Toggle Flip Flop with Reset Dual Inverter Dual 2-Input NAND Dual 3-Input NAND Dual 4-Input NAND Dual 2-Input NOR Dual 3-Input NOR Dual 4-Input NOR Dual S-R Type Latch Dual D-Type Flip Flop with Reset , /Up Mode Control Synchronous BCD Up/Down Dual Clock Counter with Clear Synchronous 4-Bit Binary Up/Down Dual Clock Counter with Clear 4-Bit Bidirectional Universal Shift Register 4-Bit Parallel-Access ... OCR Scan
datasheet

8 pages,
403.21 Kb

74151 8 by 1 Multiplexer 74139 decoder ci 74194 74138 logic gates 74139 Dual 2 to 4 line decoder inverter 74169 binary counter pin diagram priority decoder 74148 74181 74175 clock 74169 binary counter 74280 parity generator manual CI 74138 Multiplexer 74153 MSM60300 MSM60700 bcd counter using j-k flip flop diagram MSM60300 MSM60700 JK Shift Register 74195 MSM60300 MSM60700 pin diagram 41 multiplexer 74153 MSM60300 MSM60700 CI 74151 MSM60300 MSM60700 3-8 decoder 74138 MSM60300 MSM60700 3-8 decoder 74138 pin diagram MSM60300 MSM60700 74139 demultiplexer MSM60300 MSM60700 74169 SYNCHRONOUS 4-BIT BINARY COUNTER MSM60300 MSM60700 MSM60300 MSM60300 MSM60700 MSM60700 MSM61000 TEXT
datasheet frame
Abstract: from the peripheral into the 8 bit buffer register by a logic high on the Clock signal input; the negative clock transition sets the service request flip flop low (SR = 0) and latches data. When the CS1 , buffer register and resets the SR flip flop. CLOCK: Input Mode: This input strobes data into the buffer when it is activated (high) and sets the SR flip flop (SR = 0) while latching data on its negative , request flip flop. The 1852 operates over a 4—10.5 voltage range while the 1852C 1852C operates over a ... OCR Scan
datasheet

4 pages,
189.62 Kb

H1852 H1852C TEXT
datasheet frame

Archived Files

Abstract Saved from Date Saved File Size Type Download
No abstract text available
/download/54425949-995932ZC/xapp220.zip ()
Xilinx 13/12/2000 5.98 Kb ZIP xapp220.zip
| M54HC10 M54HC10 - TRIPLE 3-INPUT NAND GATE | Contents | M54HC107 M54HC107 - DUAL J-K FLIP FLOP WITH CLEAR | Contents | M54HC109 M54HC109 - DUAL J-K FLIP FLOP WITH PRESET AND CLEAR | Contents | M54HC11 M54HC11 - TRIPLE 3-INPUT AND GATE | Contents | M54HC112 M54HC112 - DUAL J-K FLIP FLOP WITH PRESET AND CLEAR | Contents | M54HC113 M54HC113 - DUAL J-K FLIP FLOP WITH PRESET | Contents | M54HC123 M54HC123 - DUAL ) | Contents | M54HC174 M54HC174 - HEX D-TYPE FLIP FLOP WITH CLEAR | Contents | M54HC175 M54HC175 - QUAD D-TYPE
/datasheets/files/stmicroelectronics/stonline/books/pdf/alpha/ds/m.htm
STMicroelectronics 26/03/1998 234.92 Kb HTM m.htm
| M54HCT174 M54HCT174 - HEX D-TYPE FLIP FLOP WITH CLEAR | Contents | M54HCT240 M54HCT240 - OCTAL BUS BUFFER WITH 3 ) | Contents | M54HCT27 M54HCT27 - TRIPLE 3-INPUT NOR GATE | Contents | M54HCT273 M54HCT273 - OCTAL D TYPE FLIP FLOP | Contents | M54HCT374 M54HCT374 - OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT HCT374 HCT374 NON INVERTING , HCT534 HCT534 - OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT HCT374 HCT374 NON INVERTING , HCT534 HCT534 INVERTING | Contents | M54HCT564 M54HCT564 - OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT HCT564 HCT564 INVERTING , HCT574 HCT574 NON
/datasheets/files/stmicroelectronics/stonline/books/pdf/alpha/ds/m-v2.htm
STMicroelectronics 14/06/1999 184.33 Kb HTM m-v2.htm
| Contents | M54HCT165 M54HCT165 - 8 BIT PISO SHIFT REGISTER | Contents | M54HCT174 M54HCT174 - HEX D-TYPE FLIP FLOP | Contents | M54HCT273 M54HCT273 - OCTAL D TYPE FLIP FLOP WITH CLEAR | Contents | M54HCT30 M54HCT30 - 8 INPUT NAND D-TYPE FLIP FLOP WITH 3 STATE OUTPUT HCT374 HCT374 NON INVERTING , HCT534 HCT534 INVERTING | Contents HCT373 HCT373 NON INVERTING , HCT533 HCT533 INVERTING | Contents | M54HCT534 M54HCT534 - OCTAL D-TYPE FLIP FLOP WITH 3 | M54HCT564 M54HCT564 - OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT HCT564 HCT564 INVERTING , HCT574 HCT574 NON INVERTING
/datasheets/files/stmicroelectronics/stonline/books/pdf/alpha/ds/m-v1.htm
STMicroelectronics 07/04/1999 170.76 Kb HTM m-v1.htm
issyntax.hlp "D Flip Flop" *NAME=d_dff;A;A;#6 *FAMILY Din Din Din Din Dout Dout *PARAM=clk_delay;clk delay () * *SRC=JKFF;JKFF_Def;Digital;Generic;JK-flip flop *SYM=d_jkff *HELP issyntax.hlp "JK Flip Flop ) *Connections s clk r pr cl q qn * *SRC=TFF;TFF_Def;Digital;Generic;Toggle flip flop *SYM=d_tff *HELP issyntax.hlp "Toggle Flip Flop" *NAME=d_tff;A;A;#6 *FAMILY Din Din Din Din Dout Dout ;SRFF_Def;Digital;Generic;Set-reset flip flop *SYM=d_srff *HELP issyntax.hlp "Set-Reset Flip Flop
/datasheets/files/spicemodels/misc/modelos/spice_complete/cm2.lib
Spice Models 18/04/2010 25.86 Kb LIB cm2.lib
No abstract text available
/datasheets/files/national/other/nsc08873.txt
National 18/12/1998 1615.16 Kb TXT nsc08873.txt
No abstract text available
/download/26794946-996405ZC/verilog.tar
Xilinx 20/01/1997 13424.65 Kb TAR verilog.tar
6498 OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT NON INVERTING 74VHCT574A 74VHCT574A 6499 1 MBIT (64KB X16, BOOT L4901A L4901A 2110 8 BIT PISO SHIFT REGISTER M54HCT165 M54HCT165 M74HCT165 M74HCT165 2111 HEX D-TYPE FLIP FLOP WITH CLEAR M54HCT174 M54HCT174 3-INPUT NOR GATE M54HCT27 M54HCT27 M74HCT27 M74HCT27 2117 OCTAL D TYPE FLIP FLOP WITH CLEAR M54HCT273 M54HCT273 M74HCT273 M74HCT273 2118 8 INPUT M74HCT533 M74HCT533 2122 OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT HCT374 HCT374 NON INVERTING , HCT534 HCT534 INVERTING M54HCT374 M54HCT374 IC VB027SP VB027SP 2126 OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT HCT564 HCT564 INVERTING , HCT574 HCT574 NON INVERTING
/datasheets/files/stmicroelectronics/stonline/db/psearch-v3.txt
STMicroelectronics 30/03/1999 189.32 Kb TXT psearch-v3.txt
2-INPUT AND GATE (OPEN DRAIN) ST | TRIPLE 3-INPUT NAND GATE ST | DUAL J-K FLIP FLOP WITH CLEAR ST | DUAL J-K FLIP FLOP WITH PRESET AND CLEAR ST | TRIPLE 3-INPUT AND GATE ST | DUAL J-K FLIP FLOP WITH PRESET AND CLEAR ST | DUAL J-K FLIP FLOP WITH PRESET ST | DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATOR ) ST | HEX D-TYPE FLIP FLOP WITH CLEAR ST | QUAD D-TYPE FLIP-FLOP WITH CLEAR ST | ARITHMETIC LOGIC HC266 HC266 QUAD EXCLUSIVE NOR GATE WITH OPEN DRAIN ST | TRIPLE 3-INPUT NOR GATE ST | OCTAL D TYPE FLIP FLOP
/datasheets/files/stmicroelectronics/stonline/newfts/ds.tit
STMicroelectronics 20/10/2000 158.98 Kb TIT ds.tit
low and decoded "0" output high resets the S-R flip flop to enable the HCC/HCF4017B HCC/HCF4017B . If the N th counters having 10 and 8 decoded outputs, respectively. Inputs include a CLOCK, a RESET, and a CLOCK INHIBIT signal. Schmitt trigger action in the CLOCK input circuit pro- vides pulse shaping that allows unlimited clock input pulse rise and fall times. These counters are ad- vanced one count at the positive clock signal tran- sition if the CLOCK INHIBIT signal is low. Counter advancement via the clock line is
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/2029.htm
STMicroelectronics 20/10/2000 12.98 Kb HTM 2029.htm