NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: F0^12 84 BHD1 Bus hold -1 3 Latches 85 LTND S-R NAND latch 3 86 LTNR S-R NOR latch 3 87 L101 S-R latch with enable 4 88 L102 S-R latch with clear 4 89 DLT D-type latch with reset 4 (1) 90 , D-type latch with reset 4 (2) D-type flip flops 94 DFF D-type flip flop 6 (3) 95 DFR D-type flip flop with reset 8 (3) 96 F112 D-type flip flop with reset 7 (3) 97 F113 D-type flip flop with set 7 (3) 98 DF D-type flip flop with set/reset 9 (3) 99 F114 D-type flip flop with set/reset 8 (3) 100 ... | OCR Scan |
23 pages, |
7449 DECODER 7495 4-bit latch 74381 alu 74139 for bcd to excess 3 code multiplexer 74151 counter 74169 7482 full adder priority encoder 74147 alu 74381 74183 alu 74169 SYNCHRONOUS 4-BIT BINARY COUNTER shift register 7495 MH 74151 MSM70V000 MSM70V000 MSM70V000 abstract |
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| Abstract: 83 TB11 Internal invert tristate bus driver -1 4 F0 , DFF D-type flip flop 6 (3) 95 DFR D-type flip flop with reset 8 (3) 96 F112 D-type flip flop with reset 7 (3) 97 F113 D-type flip flop with set 7 (3) 98 DF D-type flip flop with set/reset 9 (3) 99 F114 D-type flip flop with set/reset 8 (3) 100 F115 D-type flip flop with reset 7 (3) 101 F116 ... | OCR Scan |
30 pages, |
74183 alu Multiplexer 74152 74150 demultiplexer ttl 74183 74259 priority encoder 74147 74139 Dual 2 to 4 line decoder 74169 binary counter 74151 adder TTL 74139 74138 logic circuit decoder 3-8 74ls with nor gate 74139 demultiplexer MSM70H000 MSM70H000 MSM70H000 abstract |
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| Abstract: Internal invert tristate bus driver -1 4 F0^12 84 BHD1 Bus hold -1 3 Latches 85 LTND S-R NAND latch 3 86 LTNR S-R NOR latch 3 87 L101 S-R latch with enable 4 88 L102 S-R latch with clear 4 89 , flip flop 6 (3) 95 DFR D-type flip flop with reset 8 (3) 96 F112 D-type flip flop with reset 7 (3) 97 F1 13 D-type flip flop with set 7 (3) 98 DF D-type flip flop with set/reset 9 (3) 99 F114 D-type flip flop with set/reset 8 (3) 100 F115 D-type flip flop with reset 7 (3) 101 F116 D-type flip ... | OCR Scan |
23 pages, |
alu 74381 synchronous counter using 4 flip flip 74381 alu priority encoder 16 to 4 74148 BCIC 74169 binary direction counter design a bcd counter using jk flip flop 74131 74168 Toggle flip flop 74169 SYNCHRONOUS 4-BIT BINARY COUNTER 74175 flip flops MSM70V000 MSM70V000 MSM70V000 abstract |
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| Abstract: , pulse) the S-R flip flop (constructed from two NOR gates of the CD4001A CD4001A) generates a reset pulse which , goes high at this time. Coincidence of the clock low and decoded "0" output low resets the S-R flip , to a decimal number. Inputs include a CLOCK, a RESET, and a CLOCK INHIBIT signal. The decade counter Is advanced one count at the positive clock signal transition if the CLOCK INHIBIT signal is low. Counter advancement via the clock line is inhibited when the clock INHIBIT signal is high. A high reset ... | OCR Scan |
4 pages, |
CD4001A CMOS decade counter CD4017 features CD4017 gate diagram S-R flip flop clock CD4017 cd4017 application notes application of i CD4017 CD4017A johnson decade counter cd4017 applications RCA-CD4017A ICAN-6166 CD4017A abstract |
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| Abstract: Function No. of Unit Cells FO. Max. 37 44 R 4-lnput 4-Wide OR-AND 5 3 38 1CRY 1 Bit Carry 2 10 39 LT S-R Type Latch 2 8 40 DLT D-Type Latch with Reset 2 8 41 DFR D-Type Flip Flop with Reset 4 8 42 DF D-Type Flip Flop with Set/Reset 5 8 43 JKFR J-K Flip Flop with Reset 6 8 44 JKF J-K Rip Flop with Set/Reset 7 8 45 TFR Toggle Flip Flop with Reset 4 8 46 INV2 Dual Inverter 1 10 47 2ND2 Dual 2-lnput NAND , 3NR2 Dual 3-lnput NOR 2 4 52 4NR2 Dual 4-lnput NOR 2 3 53 LT2 Dual S-R Type Latch 3 8 54 DFR2 Dual ... | OCR Scan |
8 pages, |
74151 adder Ci 74153 bcd counter using t flip flop diagram counter schematic diagram 74161 TTL 74139 7493 binary counter diagram CI 74151 counter 74190 74181 74175 clock inverter 74169 binary counter 74151 demultiplexer 74195 TTL shift register MSM60300 MSM60700 MSM60300 abstract |
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| Abstract: request flip flop low (SR = 0) and latches data. When the CS1 and CS2 signais are enabled, the data , : This asynchronous reset control clears the buffer register and resets the SR flip f lop. CLOCK: Input Mode: This input strobes data into the buffer when it is activated (high) and sets the SR flip flop (SR , the port's register (DO O-DO 7) and service request flip flop. The 1852 operates over a 4-10.5 voltage , : Clear to SR, tRSR3 _ _ s 10 _ 170 65 340 170 - 170 340 Clock lo SR, tcsR 3 : - 5 10 120 60 240 120 ... | OCR Scan |
4 pages, |
sr flip flop pin diagram sr flip flop 1852C 1852C abstract |
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| Abstract: Input-voltage test circuit. When the Nth decoded output is reached (Nth clock pulse) the S-R flip flop , output low resets the S-R flip flop to enable the CD4017B CD4017B or CD4022B CD4022B. If the N«h decoded output is less , a CLOCK, a RESET, and a CLOCK INHIBIT signal. Schmitt trigger action in the CLOCK input circuit provides pulse shaping that allows unlimited clock input pulse rise and fall times. These counters are advanced one count at the positive clock signal transition if the CLOCK INHIBIT signal is low. Counter ... | OCR Scan |
5 pages, |
ICAN-6166 CD4001 PIN Description CD4017B 20 pins cd4017 applications CD4001 pin 4022B cd4017b application 92CS-33064 description and pin diagram of cd4017 sr flip flop CD4017B CD4017 features application of i CD4017 CD4017B abstract |
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| Abstract: ,h clock pulse) the S-R flip flop (constructed from two NOR gates of the CD4001A CD4001A) generates a reset , S-R flip flop to enable the CD4017A CD4017A. If the Nth decoded output is less than 6, the CoUT '¡ne not go , to a decimal number. Inputs include a CLOCK, a RESET, and a CLOCK INHIBIT signal. The decade counter is advanced one count at the positive clock signal transition if the CLOCK INHIBIT signal is low. Counter advancement via the clock line is inhibited when the clock INHIBIT signal is high. A high reset ... | OCR Scan |
4 pages, |
cd4017 application notes divide by 60 CD4001A application of i CD4017 cd4017 applications CD4017 features CD4017 gate diagram CD4017A ICAN-6166 CD4017 sr flip flop CD4017 divide by 60 counter cd4017 application CD4017A abstract |
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| Abstract: Features Each flip flop can be used independently Direct-coupled set and reset inputs Positive-edge , -Vol 1. Measurement made for each flip flop. 2. CL includes probe and tool floating capacitance. 3. , Waveforms Notes Notes 1. Measurement made for each flip flop. 1. Reset, Set Input waveform: tr g 15 ns, tf , 14-pin pEastic DIL package P-4 14-pin Panaflat package (SO-14D SO-14D) Clock Pin configuration (top view , IoL 8 mA Operating temperature range Topr -20 25 75 °c Clock frequency fc lock 0 25 MHz Pulse ... | OCR Scan |
3 pages, |
S-R flip flop clock DN74LS74A DN74LS DN74LS abstract |
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| Abstract: and decoded "0" output high resets the S-R flip flop to enable the HCC/ HCF 4017B 4017B. If the Nth decoded , output is reached (IN'" clock pulse) the S-R flip-flop (constructed from two NOR gates of the HCC/ HCF , , respectively. Inputs include a CLOCK, a RESET, and a CLOCK INHIBIT signal. Schmitt trigger action in the CLOCK input circuit provides pulse shaping that allows unlimited clock input pulse rise and fall times. These counters are advanced one count at the positive clock signal transition if the CLOCK INHIBIT signal is low. ... | OCR Scan |
8 pages, |
sr flip flop 4017 led 4022B-OCTAL and pin diagram of 4017 decade-counter circuit diagram HEF SCHMITT-TRIGGER IN 4001B S-R flip flop clock 4017 counter 4022B pin configuration 4017 cmos 4017 CMOS 4017 series 4O170 HCC/HCF/4022 4O170 abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
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| /Loadable Flip-Flop with Toggle and Clock Enable and Synchronous Set and Reset XC3000 XC3000 XC3000 XC3000 XC4000E XC4000E XC4000E XC4000E XC4000X XC4000X XC4000X XC4000X XC FTSRLE is a toggle/loadable flip-flop with toggle and clock enable and synchronous set and reset. The overridden and data on data input (D) is loaded into the flip-flop during the Low-to-High clock transition. When the toggle enable input (T) and CE are High and S, R, and L are Low, output Q toggles, or changes FPGAs, the flip-flop is asynchronously cleared, output Low, when global reset (GR for XC5200 XC5200 XC5200 XC5200) or global www.datasheetarchive.com/files/xilinx/docs/wcd00040/wcd04092.htm |
Xilinx | 16/02/1999 | 5.15 Kb | HTM | wcd04092.htm |
| 21 clock generator/drivers 24 input buffer configurations 72 output buffers 21 flip-flops and latches 9 scan flip-flops and latches 64 logic gates and multistage Boolean functions Clock Generator/Drivers CK 21 D-Type Flip-Flops DT 6 Buffers IP 8 Inverters IV 7 J-K Flip-Flops JK 2 D-Type and S-R Latches LA 12 Bus Holder LH 1 www.datasheetarchive.com/files/texas-instruments/sc/docs/military/product/asic/tgc1000/fds/library.htm |
Texas Instruments | 07/11/1996 | 8.35 Kb | HTM | library.htm |
| reset Low during the Low-to-High clock transition. Data is loaded into the flip-flop when S and R are FDSRE FDSRE D Flip-Flop with Macro Macro Macro Macro Macro Macro Macro N/A FDSRE is a single D-type flip-flop with ignored. The flip-flop is asynchronously cleared, output Low, when power is applied. For CPLDs, the inverter in front of the GR/GSR input of the STARTUP symbol. Inputs Outputs S R CE D C Q 1 X X www.datasheetarchive.com/files/xilinx/docs/wcd00040/wcd0407c.htm |
Xilinx | 16/02/1999 | 4.46 Kb | HTM | wcd0407c.htm |
| precedence over Reset.) When reset (R) is High and S is Low, the flip-flop is reset, output Low, on the Low-to-High clock transition. Data on the D input is loaded into the flip-flop when S and R are Low on the Low-to-High clock transition. The flip-flop is asynchronously cleared, output Low, when power is applied. For FDSR FDSR D Flip-Flop with Macro Macro Macro Macro Macro N/A FDSR is a single D-type flip-flop with data (D www.datasheetarchive.com/files/xilinx/docs/wcd00040/wcd0407b.htm |
Xilinx | 16/02/1999 | 4.19 Kb | HTM | wcd0407b.htm |
| flip-flop with toggle and clock enable and synchronous set and reset. The synchronous set input, when state, during the Low-to-High clock transition. The flip-flop is asynchronously cleared, output Low FTSRE FTSRE Toggle Flip-Flop with Toggle and Clock Enable and Synchronous Set and Reset XC3000 XC3000 XC3000 XC3000 XC4000E XC4000E XC4000E XC4000E XC4000X XC4000X XC4000X XC4000X XC5200 XC5200 XC5200 XC5200 XC9000 XC9000 XC9000 XC9000 STARTUP_VIRTEX symbol. Inputs Outputs S R CE T C Q 1 X X X 1 0 1 X X 0 0 0 0 X X No Chg www.datasheetarchive.com/files/xilinx/docs/wcd00040/wcd04091.htm |
Xilinx | 16/02/1999 | 4.36 Kb | HTM | wcd04091.htm |
| -K-type flip-flop with J, K, synchronous set (S), synchronous reset (R), and clock enable (CE) inputs and data FJKSRE FJKSRE J-K Flip-Flop with Clock Enable and Synchronous Set and Reset XC3000 XC3000 XC3000 XC3000 XC4000E XC4000E XC4000E XC4000E XC4000X XC4000X XC4000X XC4000X XC5200 XC5200 XC5200 XC5200 XC9000 XC9000 XC9000 XC9000 Spartan transitions are ignored. The flip-flop is asynchronously cleared, output Low, when power is applied. For . Inputs Outputs S R CE J K C Q 1 X X X X 1 0 1 X X X 0 0 0 0 X X X No Chg 0 0 1 0 0 X No www.datasheetarchive.com/files/xilinx/docs/wcd00040/wcd04084.htm |
Xilinx | 16/02/1999 | 4.89 Kb | HTM | wcd04084.htm |
| -Type Transparent Latches and Edge-Triggered Flip-Flops DM54LS374 DM54LS374 DM54LS374 DM54LS374 - Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops DM54LS377 DM54LS377 DM54LS377 DM54LS377 - Octal D Flip-Flop with Common Enable and Clock DM54LS42 DM54LS42 DM54LS42 DM54LS42 - BCD to Decimal with Complementary Outputs DM54LS174 DM54LS174 DM54LS174 DM54LS174 - Hex D Flip-Flop with Clear DM54LS175 DM54LS175 DM54LS175 DM54LS175 - Quad D Flip-Flop Gate DM54LS273 DM54LS273 DM54LS273 DM54LS273 - 8-Bit Register with Clear DM54LS279 DM54LS279 DM54LS279 DM54LS279 - Quad S-R Latch DM54LS283 DM54LS283 DM54LS283 DM54LS283 - 4-Bit Binary www.datasheetarchive.com/files/national/htm/nsc00979-v4.htm |
National | 16/09/1998 | 15.69 Kb | HTM | nsc00979-v4.htm |
| -Triggered Flip-Flops DM54LS374 DM54LS374 DM54LS374 DM54LS374 - Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops DM54LS377 DM54LS377 DM54LS377 DM54LS377 - Octal D Flip-Flop with Common Enable and Clock DM54LS42 DM54LS42 DM54LS42 DM54LS42 - BCD to Decimal Decoder DM54LS447 DM54LS447 DM54LS447 DM54LS447 - BCD Shift Register with Complementary Outputs DM54LS174 DM54LS174 DM54LS174 DM54LS174 - Hex D Flip-Flop with Clear DM54LS175 DM54LS175 DM54LS175 DM54LS175 - Quad D Flip-Flop with Clear and Complementary Outputs DM54LS20 DM54LS20 DM54LS20 DM54LS20 - Dual 4-Input NAND Gate DM54LS240 DM54LS240 DM54LS240 DM54LS240 - Dual 5-Input NOR Gate DM54LS273 DM54LS273 DM54LS273 DM54LS273 - 8-Bit Register with Clear DM54LS279 DM54LS279 DM54LS279 DM54LS279 - Quad S-R Latch DM54LS DM54LS DM54LS DM54LS www.datasheetarchive.com/files/national/docs/wcd00044/wcd0443e.htm |
National | 03/04/1998 | 13.64 Kb | HTM | wcd0443e.htm |
| and Edge-Triggered Flip-Flops - LCC, Cerdip, Cerpack 20 Full production DM54LS377 DM54LS377 DM54LS377 DM54LS377 Octal D Flip-Flop with Common Enable and Clock - Cerpack, wafer Title Price Package Type No. of Pins Status DM54LS279 DM54LS279 DM54LS279 DM54LS279 Quad S-R Latch production DM54LS373 DM54LS373 DM54LS373 DM54LS373 Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops www.datasheetarchive.com/files/national/htm/nsc01131-v4.htm |
National | 16/09/1998 | 8.9 Kb | HTM | nsc01131-v4.htm |
| Up/Down Clocks Cerpack 16 Lifetime buy - JD54F374SRA JD54F374SRA JD54F374SRA JD54F374SRA Octal D Flip-Flop with - JD54F109SEA JD54F109SEA JD54F109SEA JD54F109SEA Dual JK (Note: Overbar Over the K) Positive Edge-Triggered Flip-Flop Cerdip 16 -Triggered Flip-Flop Cerpack 16 Full production - JD54F153SEA JD54F153SEA JD54F153SEA JD54F153SEA Dual 4-Input Multiplexer Cerdip 16 Lifetime buy - JD54F174SEA JD54F174SEA JD54F174SEA JD54F174SEA Hex D Flip-Flop with Master Reset Cerdip - JD54F534BSA JD54F534BSA JD54F534BSA JD54F534BSA Octal D Flip-Flop with TRI-STATE Outputs Cerpack 20 Lifetime buy www.datasheetarchive.com/files/national/htm/nsc03836-v3.htm |
National | 16/09/1998 | 33.19 Kb | HTM | nsc03836-v3.htm |