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HCS163KMSR Intersil Corporation HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDFP16, CERAMIC, DFP-16 visit Intersil
HCS163DMSR Intersil Corporation HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDIP16, SIDE BRAZED, CERAMIC, DIP-16 visit Intersil
SN74S163FN Texas Instruments S SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PQCC20 visit Texas Instruments
SN75ALS163DW-00R Texas Instruments LINE TRANSCEIVER, PDSO20 visit Texas Instruments
LM3S1637-IQC50-A2T Texas Instruments Stellaris LM3S Microcontroller 100-LQFP -40 to 85 visit Texas Instruments

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S-163 Datasheet

Part Manufacturer Description PDF Type
S1632 Pericom Semiconductor CMOS Original
S1633 Pericom Semiconductor CMOS/TTL Compatible Original
S1634 Pericom Semiconductor CMOS/TTL Compatible Original
S-1634A(09) Hirose Electric SUMICON; HRS No: 216-0007-1 09; No. of Positions: 34; Connector Type: Cable; Contact Gender: Female; Contact Spacing (mm): 2.5; Terminal Pitch (mm): 2.5; Termination Style: Soldering; Current Rating(Amps)(Max.): 3; Rated Voltage(VAC): 300; Mating/Unmating Cycles: 1000; Contact Mating Area Plating: Silver; General Description: Soldering connector unit Original
S-1634A-CA(50) Hirose Electric SUMICON; HRS No: 216-0126-0 50; No. of Positions: 34; Connector Type: Cable; Contact Gender: Female; Contact Spacing (mm): 2.5; Terminal Pitch (mm): 2.5; Termination Style: Soldering; Current Rating(Amps)(Max.): 3; Mating/Unmating Cycles: 1000; Contact Mating Area Plating: Silver; General Description: Connector unit with top-touch lock type plug cover Original
S-1634A-CA(51) Hirose Electric SUMICON; HRS No: 216-0126-0 51; No. of Positions: 34; Connector Type: Cable; Contact Gender: Female; Contact Spacing (mm): 2.5; Terminal Pitch (mm): 2.5; Termination Style: Soldering; Current Rating(Amps)(Max.): 3; Rated Voltage(VAC): 300; Mating/Unmating Cycles: 1000; Contact Mating Area Plating: Silver; General Description: Connector unit with top-touch lock type plug cover; Conforming to NTT specifications (Spec. number 1931); 34GLWPFSA marking; CN-4534GLWPFSA connector Original
S-1634A-J(50) Hirose Electric SUMICON; HRS No: 216-0142-7 50; No. of Positions: 34; General Description: Only side lock type jack cover Original
S-1634A-STA(50) Hirose Electric SUMICON; HRS No: 216-0114-1 50; Contact Mating Area Plating: Silver Original
S-1634A-STA(51) Hirose Electric SUMICON; HRS No: 216-0114-1 51; No. of Positions: 34; Connector Type: Panel; Contact Gender: Female; Contact Spacing (mm): 2.5; Terminal Pitch (mm): 2.5; Termination Style: Soldering; Current Rating(Amps)(Max.): 3; Rated Voltage(VAC): 300; Mating/Unmating Cycles: 1000; Contact Mating Area Plating: Silver; General Description: Connector with Top-touch lock type stopper bracket; Conforming to NTT specifications (Spec. number 1931); 34GJFSA marking Original
S-1634G(09) Hirose Electric SUMICON; HRS No: 216-0061-7 09; No. of Positions: 34; Connector Type: Cable; Contact Gender: Female; Contact Spacing (mm): 2.5; Terminal Pitch (mm): 2.5; Termination Style: Soldering; Current Rating(Amps)(Max.): 3; Rated Voltage(VAC): 300; Mating/Unmating Cycles: 1000; Contact Mating Area Plating: Gold; General Description: Soldering connector unit Original

S-163

Catalog Datasheet MFG & Type PDF Document Tags

E16 TR

Abstract: -1* SOIC ;16 pin;.150" Dwg: 21-0041B (PDF) Use pkgcode/variation: S16-3* SOIC ;16 pin;.150" Dwg: 21-0041B (PDF) Use pkgcode/variation: S16-3* SOIC ;16 pin;.150" Dwg: 21-0041B (PDF) Use pkgcode/variation: S16+3* SOIC ;16 pin;.150" Dwg: 21-0041B (PDF) Use pkgcode/variation: S16+3* SOIC ;16 pin;.150" Dwg: 21-0041B (PDF) Use pkgcode/variation: S16-3* -40C to +85C RoHS/Lead-Free: No Materials Analysis RoHS , /variation: S16-3* SOIC ;16 pin;.150" Dwg: 21-0041B (PDF) Use pkgcode/variation: S16+3* -40C to +85C
Maxim Integrated Products
Original
E16 TR MAX327 MAX327C SE-TG002 MAX327EJE J16-3 MAX327MJE

64713

Abstract: S160 -bit decade counters and the S161 and S163 are 4-bit binary counters. The carry output is decoded by means of , 50 pF and RL = 280!!. Note 3: Applies only lo 'S162 anü S163 which have synchronous clear inputs , Copyrighted By Its Respective Manufacturer 'S160 thru 'S163 Electrical Characteristics over recommended , 'S162 and 'S163. 5-89 This Material Copyrighted By Its Respective Manufacturer co , Respective Manufacturer Logic Diagrams (continued) S161,S163 CARRY TL/F/6471-3 y^ S 161 optic 5-91
-
OCR Scan
64713 S160 DM54S160/ DM74S160 DM54S161 DM54S1621DM74S162 DM54S163/DM74S163

pulse width measure counter delay clock

Abstract: counters and the S161 and S163 are 4-bit binary counters. The carry output is decoded by means of a NOR , 280[l Note 2: CL = 50 pF and RL = 280!!. Note 3: Applies onìy lo 'S162 anü S163 which have , Electronic-Library Service CopyRight 2003 'S160 thru 'S163 Electrical Characteristics over recommended operating free , 'S163. 5-89 Powered by ICminer.com Electronic-Library Service CopyRight 2003 co , Service CopyRight 2003 Logic Diagrams (conimued) S161,S163 CARRY TL/F/6471-3 X S 161 optic 5-91 Powered
-
OCR Scan
pulse width measure counter delay clock DM54S162/DM74S162 TL/F/6471-7
Abstract: S161*S163 National Semiconductor DM54S161/DM74S161, DM54S163/DM74S163 Synchronous 4-Bit Binary , , DM74S161N, or DM74S163N See NS Package Number J16A, N16E or W16A 3 3-71 S161*S163 Absolute , . Note 2: Cu = 50 pF, RL = 200ft, TA * 25*C and Vcc = 5V. Note 3: Applies only to the 'S163 which has , S161*S163 Electrical Characteristics Symbol V| v OH Parameter Input Clamp Voltage High Level Output , for the 'S161 and from the clock input transition for the 'S163. 3-73 Logic Diagram S161, S163 -
OCR Scan
S161/163

DG211DY

Abstract: DG211CJ pkgcode/variation: P16-1* SOIC;16 pin; Dwg: 21-0041 (PDF) Use pkgcode/variation: S16+3* 0°C to +70°C , : S16-3* SOIC;16 pin; Dwg: 21-0041 (PDF) Use pkgcode/variation: S16-3* SOIC;16 pin; Dwg: 21-0041 (PDF) Use pkgcode/variation: S16-3* SOIC;16 pin; Dwg: 21-0041 (PDF) Use pkgcode/variation: S16+3* SOIC;16 pin; Dwg: 21-0041 (PDF) Use pkgcode/variation: S16+3* -40°C to +85°C Buy DG201ACSE Sample , pkgcode/variation: S16-3* SOIC;16 pin; Dwg: 21-0041 (PDF) Use pkgcode/variation: S16+3* -40°C to +85°C
Maxim Integrated Products
Original
DG201ACJ DG211CJ DG211DY DG211DJ DG201A DG211 DG201A/DG211 DG201ACUE DG201C/D

S163

Abstract: 0.56" Quadruple Digit Display with Right Pin ELF-566GWB/S163 MODEL NO : Features : ECN , specification. Chip PART NO C.C. or C.A. Material ELF-566GWB/S163 Emitted Color GaP Green , Condition mcd If=10mA 0.56" Quadruple Digit Display with Right Pin MODEL NO : ELF-566GWB/S163 , -566GWB/S163 ECN : Reliability test item and condition: NO Item Test Conditions Test Hours , 0.56" Quadruple Digit Display with Right Pin MODEL NO: ELF-566GWB/S163 ECN : Typical
EVERLIGHT
Original
S163 DDF-566-024 ELF-566GWB/S163 ELF-566 T99474 B990867

SNJ54LS161AJ

Abstract: SN74LS160A decade counters and the '161, '163, 'LS161A, 'LS163A, and 'S163 are 4-bit binary counters. Synchronous , or 'S163. The clear function for the '160, '161, 'LS160A, and 'LS161A is asynchronous and a low level , , or enable inputs. The clear function for the '162, '163, 'LS162A, 'LS163A, 'S162, and 'S163 is , the 'LS160A thru 'LS163A or 'S162 and 'S163 are allowed regardless of the level of the clock input. 'LS160A thru 'LS163A, 'S162 and 'S163 feature a fully independent clock circuit. Changes at control inputs
Texas Instruments
Original
SN74LS160A SNJ54LS161AJ sn74163 SN54160 SN54163 SN54LS160A SN54LS163A SN54S162 SN54S163

N16E

Abstract: DM74S161 VCc = 5V. Note 3: CL = 50 pF, RL = 280Q, TA = 25"C and Vcc = 5V. Note 4: Applies only to the 'S163 , the 'S163. 3 www.fairchildsemi.com This Material Copyrighted By Its Respective Manufacturer Logic Diagram S161, S163 X S IBI option DS006471-2 www.fairchildsemi.com 4 This Material Copyrighted By Its Respective Manufacturer Logic Diagram (Continued) CLEAR - S161 CLEAR â  S163 I (ASYM , : Outputs Qpand carry are tested at tn + 16 for S161, S163 where tn is the bit time when all outputs are low
-
OCR Scan
DM74S161 N16E Synchronous 4-Bit Binary Counters
Abstract: SYNCHRONOUS COUNTERS WITH DIRECT CLEAR '162, '163, 'LS162A, 'LS163A, 'S162, 'S163 . FULLY SYNCHRONOUS , , '163, 'LS161A, 'LS163A, and 'S163 are 4-bit binary counters. Synchronous operation is provided by , the transition. This restriction is not applicable to the 'LS160A thru 'LS163A or 'S162 or 'S163. The , inputs. The clear function for the '162, '163, 'LS162A, 'LS163A, 'S162, and 'S163 is synchronous and a , the 'LS160A thru 'LS163A or 'S162 and 'S163 are allowed regardless of the level of the clock input Texas Instruments
Original
SN74160 SN74LS163A SN74S162 SN74S163 SDLS060 SN54162
Abstract: , 'LS161A . SYNCHRONOUS COUNTERS WITH DIRECT CLEAR '162, '163, 'LS162A, 'LS163A, 'S162, 'S163 . FULLY , counters and the '161, '163, 'LS161A, 'LS163A, and 'S163 are 4-bit binary counters. Synchronous operation , or 'S163. The clear function for the '160, '161, 'LS160A, and 'LS161A is asynchronous and a low level , , or enable inputs. The clear function for the '162, '163, 'LS162A, 'LS163A, 'S162, and 'S163 is , or T inputs of the 'LS160A thru 'LS163A or 'S162 and 'S163 are allowed regardless of the level of the Texas Instruments
Original
SN74162 SN54161 SN74161 SN54LS162A SN74LS162A SDYA009C

Synchronous 4-Bit Binary Counters

Abstract: DM74S163N 25 C and VCC e 5V Note 3 Applies only to the 'S163 which has synchronous clear inputs Note 4 , 'S161 and from the clock input transition for the 'S163 3 MHz Logic Diagram S161 S163 TL F 6471 ­ 2 4 Timing Diagram S161 S163 Synchronous Binary Counters Typical Clear Preset Count and , to measure fMAX Note B Outputs QD and carry are tested at tn a 16 for S161 S163 where tn is the bit
National Semiconductor
Original
DM74S163 C1995

SN74160

Abstract: SDLS060 , '163, 'LS161A, 'LS163A, and 'S163 are 4-bit binary counters. Synchronous operation is provided by , the transition. This restriction is not applicable to the 'LS160A thru 'LS163A or 'S162 or 'S163. The , inputs. The clear function for the '162, '163, 'LS162A, 'LS163A, 'S162, and 'S163 is synchronous and a , thru 'LS163A or 'S162 and 'S163 are allowed regardless of the level of the clock input. 'LS160A thru 'LS163A, 'S162 and 'S163 feature a fully independent clock circuit. Changes at control inputs (enable P or
Texas Instruments
Original
SN74LS161A SN74LS161AD SN74LS161ADR SN74LS161AN SN74LS161AN3 SN74LS161ANSR SN54/74LS123

0Q703

Abstract: DM54S161W 'C and Vcc = 6V. Nota 3: Applies only to the 'S163 which has synchronous clear Inputs. Note 4: Applies , Input for the 'S161 and (rom exceed one second. the clock Input transition for the 'S163. 3-73 NATIONAL SEMICOND -CLOGIO 33.E D â  tSOliaa 0Q70324 0 Logic Diagram J-^S-^QS S161 oplion S161, S163 tl/f/6471-2 3-74 NATIONAL SEMICOND -CLOGIO 31E D bSOllHE 0G7Q3S5 2 Timing Diagram S161, S163 Synchronous Blnary Counters Typlcal Clear, Preset, Count and Inhiblt Sequences CLEAR " S161 CLEAR -S163 LOAD* ~l i
-
OCR Scan
0Q703 DM54S161W
Abstract: measured from clear input fo r the â'™S161 and from the clock input transition fo r the â'™S163. 3 MHz 35 Logic Diagram S161, S163 X SIG I option T L /F /6 4 7 1 -2 Timing Diagram S161, S163 Synchronous Binary Counters Typical Clear, Preset, Count and Inhibit Sequences CLEAR , '™S163 which has synchronous clear inputs. Note 4: A pplies only to the â'™S161 which has asynchronous , S161, S163 where t n is the bit time when all outputs are low. N oteC :V R E F = i.sv. Switching -
OCR Scan
DM74S161/DM74S163
Abstract: , 'LS162A, 'LS163A, 'S162, 'S163 . FULLY SYNCHRONOUS COUNTERS q q q q q q Internal Look-Ahead for Fast , , and 'S162 are decade counters and the '161, '163, 'LS161A, 'LS163A, and 'S163 are 4-bit binary , thru 'LS163A or 'S162 or 'S163. The clear function for the '160, '161, 'LS160A, and 'LS161A is , , and 'S163 is synchronous and a low level at the clear input sets all four of the flip-flop outputs low , the enable P or T inputs of the 'LS160A thru 'LS163A or 'S162 and 'S163 are allowed regardless of the Texas Instruments
Original
59629754801QEA 59629754801QFA SN54163J SNJ54163J 5962V 9754801QEA
Abstract: SYNCHRONOUS COUNTERS WITH DIRECT CLEAR '162, '163, 'LS162A, 'LS163A, 'S162, 'S163 . FULLY SYNCHRONOUS , 'S163 are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked , is not applicable to the 'LS160A thru 'LS163A or 'S162 or 'S163. The clear function for the '160 , '162, '163, 'LS162A, 'LS163A, 'S162, and 'S163 is synchronous and a low level at the clear input , 'LS163A or 'S162 and 'S163 are allowed regardless of the level of the clock input. 'LS160A thru 'LS163A Texas Instruments
Original

DM74S161

Abstract: DM74S161N VCC = 5V. Note 3: CL = 50 pF, RL = 280, TA = 25°C and VCC = 5V. Note 4: Applies only to the 'S163 , 'S163. 3 www.fairchildsemi.com Logic Diagram S161, S163 DS006471-2 www.fairchildsemi.com , tested at tn + 16 for S161, S163 where tn is the bit time when all outputs are low Note C: VREF = 1.5V
Fairchild Semiconductor
Original

land pattern for TSsOP 16

Abstract: 8 PIN Plastic DIP land pattern ) Land Pattern: 90-0097 (PDF) Use pkgcode/variation: S16-3* N.SO;16 pin Land Pattern: Not Available 0 , ) Land Pattern: 90-0097 (PDF) Use pkgcode/variation: S16-3* PDIP(N);16 pin;158.4 mm² Outline Drawing , ² Outline Drawing:21-0041 (PDF) Land Pattern: 90-0097 (PDF) Use pkgcode/variation: S16+3* N.SO; Land Pattern , mm² Outline Drawing:21-0041 (PDF) Land Pattern: 90-0097 (PDF) Use pkgcode/variation: S16+3* -40°C , ² Outline Drawing:21-0041 (PDF) Land Pattern: 90-0097 (PDF) Use pkgcode/variation: S16-3* N.SO;16 pin Land
Maxim Integrated Products
Original
land pattern for TSsOP 16 8 PIN Plastic DIP land pattern maxim 1584 land pattern for TSSOP land pattern for TSSOP 24 pin land pattern for SOIC 16 MAX4591/MAX4592/MAX4593 MAX4591 MAX4592 MAX4593 MAX391 DG611/DG612/DG613

two-dimensional inverse discrete cosine transform

Abstract: 56800E , c163, s163 c161, s161, c41/4, s81/4 c81/4, c41, s161/4, c161/4 c163/4, s163/4, c161/4, s161/4 c41 = , ) s163 = sin(3pi/16) Implementation on the DSP56800E 3 Implementation on the DSP56800E The , ;// ;// ;// ;// ;// ;// ;// ;// ;// ;// ;// ;// ;// ;// ;// ;// ;// a = c161*s4(7), c163 ->x0 a = s161*s4(4) + c161*s4(7) pipeline stall a1 -> v(1) a = -s163*s4(5) a = c163*s4(6) - s163*s4(5) r0 = input+8 a1 -> v(3) a = s163*s4(6) a = c163*s4(5) + c163*s4(6 , r2 to v+1 = v(1), s163 -> y1 = v(3) = v(5) = v(7), a1 -> v(5) Reinitialization for
Motorola
Original
56800E two-dimensional inverse discrete cosine transform AN2123/D

31512bea

Abstract: , '162, 'LS160A, 'LS162A, and 'S162 are decade counters and the '161, '163, 'LS161A, 'LS163A, and 'S163 , restriction is not applicable to the 'LS160A thru 'LS163A or 'S162 or 'S163. The clear function for the '160 , '162, '163, 'LS162A, 'LS163A, 'S162, and 'S163 is synchronous and a low level at the clear input sets , 'LS163A or 'S162 and 'S163 are allowed regardless of the level of the clock input. 'LS160A thru 'LS163A, 'S162 and 'S163 feature a fully independent clock circuit. Changes at control inputs (enable P or T, or
Texas Instruments
Original
31512bea 7603401EA 7603401FA JM38510/31512B2A JM38510/31512BEA JM38510/31512BFA SN54LS163AJ

SN74LS161

Abstract: SYNCHRO NO US CO UNTERS W ITH DIRECT CLEAR LS163A, S163 . FULLY SYNCHRONOUS CO UNTERS · Internal , . The '161, *LS161A, 'LS163A, and 'S163 are 4-bit binary counters. Synchronous operation is p r o v id e , or 'S163. The clear function for the'161 and 'LS161A Is asynchronous and a low level at the clear , Inputs. The clear function for the 'LS163A and 'S163 is synchronous and low level at the clear input sets , high-speed n-bit counter. The '161, 'L S I 61 A, 'LS163A or 'S163 will count in binary. Virtually any count
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OCR Scan
SN74LS161 SN54LS161A N54LS161A

SN74LS161

Abstract: 74160 decade ,'S163 . . . FULLY SYNCHRONOUS COUNTERS Internal Look-Ahead for Fast Counting · Carry Output for n-Bit , 2-49 5 L S 1 6 2 A , S162 CTRDIV10 5CT*0 Ml M2 G3 G4 3 C T* 9 'L S 1 6 3 A , S163 CTRDIV16 5CT=0 , , SN74LS163A, SN74S163 SYNCHRONOUS 4-BIT COUNTERS '161, 'LS161A, '163, 'LS163A, 'S163 BINARY COUNTERS typical
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OCR Scan
74160 decade 74LS160A CTRD1V10
Abstract: ,'LS162A,'LS163A,'S162,'S163 . . . FULLY SYNCHRONOUS COUNTERS Internal Look-Ahead for Fast Counting , , and 'S163 are 4-bit binary counters. Synchronous operation is provided by having all flip-flops , 'LS160A thru 'LS163A or 'S162 or 'S163. The clear function for the '160, '161/LS160A, and 'LS161A is , , and 'S163 is synchronous and a low level at the clear in­ put sets all four of the flip-flop outputs , input is high. Transitions at the enable P or T inputs of the 'LS160A thru 'LS163A or 'S162 and 'S163 -
OCR Scan
LS160A/LS162A
Abstract: '™S163 which has synchronous clear inputs. Note 4: A pplies only to the â'™S161 which has asynchronous , measured from clear input fo r the â'™S161 and from the clock input transition fo r the â'™S163. 3 MHz 35 Logic Diagram S161, S163 X SIG I option T L /F /6 4 7 1 -2 Timing Diagram S161, S163 Synchronous Binary Counters Typical Clear, Preset, Count and Inhibit Sequences CLEAR , S161, S163 where t n is the bit time when all outputs are low. N oteC :V R E F = i.sv. Switching -
OCR Scan
DS1633X DS1633 DS1633-A DS1633-B DS1633-C DS1633-D
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