RS8228/M28228 RS8228 28228-DSH-001-C RS8228EBG RS8228EBGB M28228 100064B - Datasheet Archive

 

Octal ATM Transmission Convergence PHY Device The RS8228 Octal ATM Transmission Convergence PHY device dramatically improves

 

RS8228/M28228 RS8228/M28228 Octal ATM Transmission Convergence PHY Device The RS8228 RS8228 Octal ATM Transmission Convergence PHY device dramatically improves performance for switch and access system low-speed ports by integrating all the ATM physical layer processing functions found in the ATM Forum Cell Based Transmission Convergence Sublayer specification (af-phy-0043.000) for eight individual ports. Each port can be independently configured for operation at speeds ranging from 64 kbps to 52 Mbps. There is also a powerdown mode option for each TC port. A UTOPIA Level 2 Multi-PHY interface connects the device to the host switch or terminal system and concentrates the ATM cell traffic onto one interface. Typical system implementations center around the concentration of ATM cells over standard PDH data rates such as T1/E1 lines, DS3/E3 lines, and multiple Digital Subscriber Line (DSL) formats such as HDSL, ADSL or VDSL*. For each format, external devices perform the appropriate Physical Media Dependent (PMD) layer functions and present the RS8228 RS8228 with a payload bit stream. The RS8228 RS8228 then performs all cell alignment functions on that bit stream. This gives system designers a simple, modular, and low-cost architecture for supporting all UNI and NNI ATM interfaces below 52 Mbps. Because the RS8228 RS8228 performs only the cell-based portion of the protocol stack, designers can select the most integrated framer and Line Interface Unit (LIU) available or reuse existing devices and software. The RS8228 RS8228 can also be used in combination with a Conexant Segmentation and Reassembly (SAR) device. The RS8228 RS8228 gluelessly connects to the SAR via the UTOPIA and microprocessor interfaces. The device can be configured and controlled optionally through a generic microprocessor interface. The RS8228 RS8228's chip-select feature allows the microprocessor to select any of the framers through the PHY. The RS8228 RS8228's eight interrupt inputs provide an internal mechanism for registering and controlling generated interrupts. * The term xDSL is used throughout this document to refer to the various DSL formats as a group. Distinguishing Features · · · · · · · · · 8 cell-based TC Ports UTOPIA interface ­ Level 2 ­ 8/16 bit modes ­ Multi-PHY ­ Redundant channel Glueless interface to Conexant's: ­ T1/E1 framers ­ T3/E3 framers ­ HDSL/SDSL devices ­ SAR devices Software reference material provided 8 chip selects for external framers 8 interrupt inputs for external framers Octet- and bit-level cell delineation ITU I.432-compliant Available in either 27 mm or 17 mm BGA packages Functional Block Diagram Host RS8228 RS8228 LCs[7] LCs[0] LInt~[7] LInt~[0] External PMD or Framer Microprocessor Interface Interrupt Status UTOPIA Level 2 Multi-PHY Cell Processor Line Interface G.804 Cell Framer Tx/Rx FIFO 4 Cells ATM Layer Device Port 0 Framer (Line) Interface External PMD or Framer 8/16 UTOPIA Level 2 Interface Cell Processor Line Interface G.804 Cell Framer Tx/Rx FIFO 4 Cells Port 7 28228-DSH-001-C 28228-DSH-001-C Mindspeed TechnologiesTM Mindspeed Proprietary and Confidential April 2005 Ordering Information Model Number Manufacturing Part Number Product Revision Package Operating Temperature RS8228EBG RS8228EBG 28228-11 A 272-ball, 27 mm BGA ­40 °C to 85 °C RS8228EBGB RS8228EBGB 28228-12 B 272-ball, 27 mm BGA ­40 °C to 85 °C M28228 M28228 28228-21 A 256-ball, 17 mm BGA ­40 °C to 85 °C Revision History Revision Level Date Description C - April 2005 Corrected 0x05-IOMODE (Input/Output Mode Control Register), bits 5 and 3. B - November 2003 Placed registers in numerical order. A - November 2001 This version has the 17 mm BGA information included. Note that this document was previously released under the document numbers 100064A and 100064B 100064B. © 2005 Mindspeed TechnologiesTM, Inc. All rights reserved. Information in this document is provided in connection with Mindspeed TechnologiesTM ("MindspeedTM") products. These materials are provided by Mindspeed as a service to its customers and may be used for informational purposes only. Except as provided in Mindspeed's Terms and Conditions of Sale for such products or in any separate agreement related to this document, Mindspeed assumes no liability whatsoever. Mindspeed assumes no responsibility for errors or omissions in these materials. Mindspeed may make changes to specifications and product descriptions at any time, without notice. Mindspeed makes no commitment to update the information and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to its specifications and product descriptions. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. THESE MATERIALS ARE PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, RELATING TO SALE AND/OR USE OF MINDSPEED PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, CONSEQUENTIAL OR INCIDENTAL DAMAGES, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. MINDSPEED FURTHER DOES NOT WARRANT THE ACCURACY OR COMPLETENESS OF THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE MATERIALS. MINDSPEED SHALL NOT BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION, LOST REVENUES OR LOST PROFITS, WHICH MAY RESULT FROM THE USE OF THESE MATERIALS. Mindspeed products are not intended for use in medical, lifesaving or life sustaining applications. Mindspeed customers using or selling Mindspeed products for use in such applications do so at their own risk and agree to fully indemnify Mindspeed for any damages resulting from such improper use or sale. 28228-DSH-001-C 28228-DSH-001-C Mindspeed TechnologiesTM Mindspeed Proprietary and Confidential Framer (Line) Interface Section · · Programmable bit or byte synchronous serial interface Direct connection to external Conexant components for: ­ T1/E1 ­ DS3 ­ E3 ­ J2 ­ xDSL ­ General purpose mode ­ Interrupt and chip select signals for each external framer Cell Alignment Framing Section · · · · · · · Supports ATM cell interface for: ­ Circuit-based physical layer ­ Cell-based physical layer Passes or rejects idle cells or selected cells based on header register configuration Recovers cell alignment from Header Error Correction (HEC) Performs single-bit HEC correction and single- or multiple-bit detection Generates cell status bits, cell counts, and error counts Inserts headers and generates HEC Inserts idle cells when no traffic is ready UTOPIA Level 2 Interface · · · PHY cell to UTOPIA interface 50 MHz maximum clock rate 8/16-bit data path interface 28228-DSH-001-C 28228-DSH-001-C · Multi-PHY capability Control and Status Microprocessor Interface · · · · · · · · Asynchronous SRAM-like interface mode Synchronous, glueless Bt8233/RS8234 SAR interface mode 8-bit data bus Open-drain interrupt output Open-drain ready output 8­50 MHz operation All control registers are read/write Four programmable status indicator signals per port Counters/Status Register Section · · · · Summary interrupt indications Configuration of interrupt enables One-second counter latching Counters for: ­ LOCD events ­ Corrected HEC errors ­ Uncorrected HEC errors ­ Transmitted cells ­ Matching received cells ­ Non-matching received cells Mindspeed TechnologiesTM Mindspeed Proprietary and Confidential Table of Contents List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii List of Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .viii 1.0 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 1.2 1.3 1.4 1.5 Application Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 27 mm Pin Diagram and Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 17 mm Pin Diagram and Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Block Diagram and Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 2.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 2.2 2.3 2.4 ATM Cell Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 2.1.1 ATM Cell Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 2.1.1.1 HEC Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2.1.2 ATM Cell Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2.0.0.1 Cell Delineation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2.0.0.2 Cell Screening . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2.1.3 Cell Scrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2.0.0.1 SSS Scrambling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2.0.0.2 DSS Scrambling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Framing Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2.2.1 T1/E1 Timing for the CX28229 CX28229 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2.2.2 DS3 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.2.3 E3/G.832 34.368 Mbps Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 2.2.4 J2 6.312 Mbps Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 2.2.5 General Purpose Mode Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 UTOPIA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 2.3.1 UTOPIA Transmit and Receive FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 2.3.2 UTOPIA 8-bit and 16-bit Bus Widths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 2.3.3 UTOPIA Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 2.3.4 UTOPIA Multi-PHY Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 2.3.5 UTOPIA Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 2.3.6 Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 2.4.1 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 2.4.2 Status Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 2.4.3 Counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 2.4.4 One-second Latching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 28228-DSH-001-C 28228-DSH-001-C Mindspeed TechnologiesTM Mindspeed Proprietary and Confidential iv 2.4.5 2.4.6 2.5 External Framer Interrupts and Chip Selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 2.0.0.1 Interrupt Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 2.4.6.1 Interrupt Servicing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Source Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 3.0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0x00-SUMINT (Summary Interrupt Indication Status Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 0x01-ENSUMINT (Summary Interrupt Control Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 0x04-PMODE (Port Mode Control Register). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 0x05-IOMODE (Input/Output Mode Control Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 0x06-VERSION (Part Number/Version Status Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 0x07-OUTSTAT (Output Pin Control Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 0x08-CGEN (Cell Generation Control Register). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 0x09-HDRFIELD (Header Field Control Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 0x0A-IDLPAY (Transmit Idle Cell Payload Control Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 0x0B-ERRPAT (Error Pattern Control Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 0x0C-CVAL (Cell Validation Control Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 0x0D-UTOP1 (UTOPIA Control Register 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 0x0E-UTOP2 (UTOPIA Control Register 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 0x10-TXHDR1 (Transmit Cell Header Control Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 0x11-TXHDR2 (Transmit Cell Header Control Register 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 0x12-TXHDR3 (Transmit Cell Header Control Register 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 0x13-TXHDR4 (Transmit Cell Header Control Register 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 0x14-TXIDL1 (Transmit Idle Cell Header Control Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 0x15-TXIDL2 (Transmit Idle Cell Header Control Register 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 0x16-TXIDL3 (Transmit Idle Cell Header Control Register 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 0x17-TXIDL4 (Transmit Idle Cell Header Control Register 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 0x18-RXHDR1 (Receive Cell Header Control Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 0x19-RXHDR2 (Receive Cell Header Control Register 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 0x1A-RXHDR3 (Receive Cell Header Control Register 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 0x1B-RXHDR4 (Receive Cell Header Control Register 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 0x1C-RXMSK1 (Receive Cell Mask Control Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 0x1D-RXMSK2 (Receive Cell Mask Control Register 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 0x1E-RXMSK3 (Receive Cell Mask Control Register 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 0x1F-RXMSK4 (Receive Cell Mask Control Register 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 0x20-RXIDL1 (Receive Idle Cell Header Control Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 0x21-RXIDL2 (Receive Idle Cell Header Control Register 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 0x22-RXIDL3 (Receive Idle Cell Header Control Register 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 0x23-RXIDL4 (Receive Idle Cell Header Control Register 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 0x24-IDLMSK1 (Receive Idle Cell Mask Control Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 0x25-IDLMSK2 (Receive Idle Cell Mask Control Register 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 0x26-IDLMSK3 (Receive Idle Cell Mask Control Register 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 0x27-IDLMSK4 (Receive Idle Cell Mask Control Register 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 0x28-ENCELLT (Transmit Cell Interrupt Control Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 0x29-ENCELLR (Receive Cell Interrupt Control Register). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 28228-DSH-001-C 28228-DSH-001-C Mindspeed TechnologiesTM Mindspeed Proprietary and Confidential v RS8228/M28228 RS8228/M28228 Octal ATM Transmission Convergence PHY Device 0x2C-TXCELLINT (Transmit Cell Interrupt Indication Status Register). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 0x2D-RXCELLINT (Receive Cell Interrupt Indication Status Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 0x2E-TXCELL (Transmit Cell Status Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 0x2F-RXCELL (Receive Cell Status Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 0x30-LOCDCNT (LOCD Event Counter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 0x31-CORRCNT (Corrected HEC Error Counter). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 0x32-UNCCNT (Uncorrected HEC Error Counter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 0x34-TXCNTL (Transmitted Cell Counter [Low Byte]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 0x35-TXCNTM (Transmitted Cell Counter [Mid Byte]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 0x36-TXCNTH (Transmitted Cell Counter [High Byte]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 0x38-RXCNTL (Received Cell Counter [Low Byte]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 0x39-RXCNTM (Received Cell Counter [Mid Byte]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 0x3A-RXCNTH (Received Cell Counter [High Byte]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 0x3C-NONCNTL (Non-matching Cell Counter [Low Byte]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 0x3D-NONCNTH (Non-matching Cell Counter [High Byte]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 0x0200-SUMPORT (Summary Port Interrupt Status Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 0x0201-ENSUMPORT (Summary Port Interrupt Control Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 0x0202-MODE (Device Mode Control Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 4.0 Electrical and Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4.1 4.2 4.3 4.4 4.5 Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 4.1.1 Microprocessor Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 4.1.2 Framer (Line) Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 4.1.3 UTOPIA Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 4.1.4 JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 4.1.5 One-second Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 27 mm Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 17 mm Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Appendix A:Related Standards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Appendix B:Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 B.1 B.2 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 BYPASS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Appendix C:Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 28228-DSH-001-C 28228-DSH-001-C Mindspeed TechnologiesTM Mindspeed Proprietary and Confidential vi List of Figures Figure 1-1. Figure 1-2. Figure 1-3. Figure 1-4. Figure 1-5. Figure 2-1. Figure 2-2. Figure 2-3. Figure 2-4. Figure 2-5. Figure 2-6. Figure 2-7. Figure 2-8. Figure 2-9. Figure 2-10. Figure 2-11. Figure 2-12. Figure 4-1. Figure 4-2. Figure 4-3. Figure 4-4. Figure 4-5. Figure 4-6. Figure 4-7. Figure 4-8. Figure 4-9. Figure 4-10. Figure 4-11. Figure 4-12. Figure 4-13. Figure 4-14. Figure 4-15. Figure 4-16. Figure 4-17. Figure B-2. Figure C-1. 28228-DSH-001-C 28228-DSH-001-C RS8228 RS8228 Connected to a RS8398 RS8398 Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 RS8228 RS8228 Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 RS8228 RS8228 27 mm Pinout Diagram (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 M28228 M28228 17 mm Pinout Diagram (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 RS8228 RS8228 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Cell Delineation Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Header Error Check Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Bt8370 Interface Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Transmit Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Receive Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Bt8330 Interface Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 E3/G.832 36,368 kbps Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 J2 6312 kbps Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 General Purpose Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Interrupt Indication Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Interrupt Indication Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Source Loopback Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Input Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Output Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Microprocessor Timing Diagram-Asynchronous Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 MIcroprocessor Timing Diagram-Asynchronous Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Microprocessor Timing Diagram-Synchronous Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Microprocessor Timing Diagram-Synchronous Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Framer (Line) Control Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Framer (Line) Transmit Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Framer (Line) Receive Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 UTOPIA Transmit Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 UTOPIA Receive Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 JTAG Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 One-second Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 RS8228 RS8228 27 mm Mechanical Drawing (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 RS8228 RS8228 27 mm Mechanical Drawing (Top and Side Views) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 M28228 M28228 17 mm Mechanical Drawing (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 M28228 M28228 17 mm Mechanical Drawing (Top and Side Views) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Test Circuitry Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Mindspeed TechnologiesTM Mindspeed Proprietary and Confidential vii List of Tables Table 1-1. Table 1-2. Table 2-1. Table 2-2. Table 2-3. Table 2-4. Table 2-5. Table 2-6. Table 3-1. Table 3-2. Table 3-3. Table 3-4. Table 3-5. Table 3-6. Table 3-7. Table 3-8. Table 3-9. Table 4-1. Table 4-2. Table 4-3. Table 4-4. Table 4-5. Table 4-6. Table 4-7. Table 4-8. Table 4-9. Table 4-10. Table 4-11. Table 4-12. Table 4-13. Table 4-14. Table B-1. Table 2-3. Table 2-4. 28228-DSH-001-C 28228-DSH-001-C RS8228 RS8228 27 mm Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 RS8228 RS8228 17 mm Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Cell Screening-Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Cell Screening-Accept/Reject Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Cell Format for 8-bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Cell Format for 16-bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 LStatOut Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Chip Selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Address Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Device Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Port Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 General Use Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Cell Transmit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Cell Receive Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 UTOPIA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Status and Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Timing Diagram Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Microprocessor Timing Table-Asynchronous Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Microprocessor Timing Table-Asynchronous Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Microprocessor Timing Table-Synchronous Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Microprocessor Timing Table-Synchronous Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Framer (Line) Control Timing Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Framer (Line) Transmit Timing Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Framer (Line) Receive Timing Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 UTOPIA Transmit Timing Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 UTOPIA Receive Timing Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 JTAG Timing Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 One-second Timing Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Boundary Scan Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 IEEE Std. 1149.1 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Boundary Scan Register Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Mindspeed TechnologiesTM Mindspeed Proprietary and Confidential viii 1 1.0 Product Description The RS8228 RS8228 Octal ATM Transmission Convergence (TC) PHY device dramatically increases the level of integration for switches and access systems. The RS8228 RS8228 integrates all the ATM Layer processing functions found in the ATM Forum Cell Based Transmission Convergence Sublayer specification (af-phy-0043.000) in each of eight individual ports. A UTOPIA Level 2 Multi-PHY interface connects the device to the host switch or terminal system and concentrates the ATM cell traffic onto one bus interface. Because the RS8228 RS8228 performs only the cell-based portion of the protocol stack, designers may choose the line formatter. Each port may be configured for operation at speeds from 64 kbps to 52 Mbps, allowing a maximum aggregate bandwidth of 416 Mbps for all active ports. Typical system implementations center around the concentration of multiple standard data rates such as T1 and E1 lines, DS3 and E3 lines, and multiple Digital Subscriber Line (DSL) formats such as HDSL, ADSL or VDSL. For each specific format, external devices perform the appropriate PMDlayer functions and present the RS8228 RS8228 with a payload bit stream. The RS8228 RS8228 then performs all cell alignment functions on that bit stream. This gives system designers a simple, modular, and low-cost architecture for supporting all ATM interfaces below 52 Mbps. It also enables them to select the most integrated framer and LIU available, or reuse existing devices and software. The RS8228 RS8228 device provides a low-cost ATM interface architecture for UNI or NNI interfaces. NOTE: Both the 27 mm and 17 mm packages use the same silicon die. All references to the RS8228 RS8228 apply to the M28228 M28228. 1.1 Application Overview The RS8228 RS8228 is typically used with line framer devices like the RS8398 RS8398 T1/E1 octal transceiver, the Bt8970 Zip Wire or the Bt8953 HDLC Framer. It provides a chip-select feature that allows the microprocessor to select any framer connected to it. The RS8228 RS8228 also has eight interrupt inputs so interrupts from the framers can be registered and controlled in the PHY. Figure 1-1 illustrates a typical application. 28228-DSH-001-C 28228-DSH-001-C Mindspeed TechnologiesTM Mindspeed Proprietary and Confidential 1-1 M02063 M02063 Non-Conformance Figure 1-1. RS8228 RS8228 Connected to a RS8398 RS8398 Transceiver RS8228 RS8228 RS8398 RS8398 CX8380 CX8380 Port 0 Port 1 ATM Switch or SAR UTOPIA Level 2 Bus LIU 2 Port 2 ATM Octal PHY LIU 1 LIU 3 Port 3 Octal T1/E1 Framer Quad LIU TX1 RX1 TX2 RX2 TX3 RX3 TX4 RX4 Quad LIU TX5 RX5 TX6 RX6 TX7 RX7 TX8 RX8 LIU 4 Port 4 LIU 5 Port 5 LIU 6 Port 6 LIU 7 Port 7 LIU 8 CX8380 CX8380 Microprocessor Bus 28228-DSH-001-C 28228-DSH-001-C Mindspeed TechnologiesTM Mindspeed Proprietary and Confidential 1-2 1.0 Product Description 1.2 Logic Diagram Figure 1-2 illustrates a logic diagram of the RS8228 RS8228's functional modules. Pin descriptions are listed in Table 1-1. Figure 1-2. RS8228 RS8228 Logic Diagram Reset I One Second Input I 8kHzIn Clock I Reset OneSecIn 8kHzIn Reset One Second Interface OneSecOut O One Second Output LTxClk[0] LTxData[0] LTxSync[0] LCs[0] LInt[0] LStatOut[3:0][0] I O I O I O LTxClk[7] LTxData[7] LTxSync[7] LCs[7] LInt[7] LStatOut[3:0][7] I O I O I O Receive Clock Receive Data Receive Frame Synchronization Receive Hold I I I I Line Interface LRxClk[0] LRxData[0] Port 0 LRxSync[0] LRxHld[0] Receive Clock Receive Data Receive Frame Synchronization Receive Hold I I I I LRxClk[7] Line Interface LRxData[7] Port 7 LRxSync[7] LRxHld[7] Sync/Async Mode Select Microprocessor Clock Chip Select Address Strobe, Write Control Write/Read, Read Control Address Bus I I I I I I MSyncMode MClk Microprocessor MInt MCs Interface MRdy MAs, MWr MData[7:0] MW/R, MRd MAddr[12:0] Test Reset Test Clock Test Mode Select Test Data Input I I I I TRST TCK TMS TDI Transmit Clock Transmit Enable Transmit Address Bus I I I UTxClk UTxEnb UTxAddr[4:0] Receive Clock Receive Enable Receive Address Bus I I I URxClk URxEnb URxAddr[4:0] JTAG Interface UTOPIA Transmit Interface UTOPIA Receive Interface TDO Transmit Clock Transmit Data Transmit Frame Synchronization External Framer Chip Select Line Interrupt Request Status Output Bus Transmit Clock Transmit Data Transmit Frame Synchronization External Framer Chip Select Line Interrupt Request Status Output Bus O Summary Interrupt O Ready I/O Microprocessor Data Bus O Test Data Output UTxClAv UTxSOC UTxPrty UTxData[15:0] O I I I Transmit Cell Available Transmit Start Of Cell Transmit Parity Transmit Data Bus URxClAv URxSOC URxPrty URxData[15:0] O O O O Receive Cell Available Receive Start of Cell Receive Parity Receive Data Bus NOTE(S): The overscore on inverted signals in this diagram equates to the "~" in the text of the document. 28228-DSH-001-C 28228-DSH-001-C Mindspeed TechnologiesTM Mindspeed Proprietary and Confidential 1-3 M02063 M02063 Non-Conformance 1.3 27 mm Pin Diagram and Definitions Figure 1-3 illustrates a pinout diagram for the RS8228 RS8228. It is a single CMOS integrated circuit packaged in a 272-pin BGA. All unused input pins should be connected to ground or power. Unused outputs should be left unconnected. NOTE: The port numbers following the pin names in the Port Interface section represent each of the eight ports as follows: LTxSync[0]-Line transmit sync for port 0. LStatOut[3][0]-Line status output bit number 3 for port 0. Figure 1-3. RS8228 RS8228 27 mm Pinout Diagram (Top View) 1 A 2 3 LStatOut[2][4]1 C 27 mm BGA D LStatOut[1][3]1 G H P R W GND MData[1] MAddr[10] GND MAddr[6] MAddr[3] MW/R~,MRd~ URxAddr[2] URxData[ 15] GND PWR UTxAddr[1] LRxData[0] UTxAddr[0] LTxSync[0] UTxAddr[3] UTxData[10] UTxData[13] UTxSOC UTxEnb~ URxData[10] URxData[0] URxSOC URxAddr[0] URxData[ 12] URxData[ 8] URxData[ 5] NC URxEnb~ UTxClAv UTxData[15] URxData[2] URxClAv UTxClk URxAddr[1] URxData[13] NC URxData[1] URxAddr[4] URxAddr[3] URxData[14] GND URxData[4] URxPrty URxClk UTxPrty UTxData[14] UTxData[12] PWR NC NC UTxData[11] URxData[ 7] NC GND NC NC UTxData[9] UTxData[8] NC NC NC UTxData[7] UTxData[5] UTxData[1] PWR NC UTxData[6] UTxData[4] UTxData[0] UTxAddr[2] GND UTxData[3] UTxData[2] UTxAddr[4] NC NC MAs~,MWr~ MCs~ PWR LRxSync[0] LTxClk[0] MAddr[2] MAddr[1] MRdy PWR LStatOut[2][0]1 LTxData[0] VGG MAddr[0] NC LTxClk[1] LRxHld[0] MAddr[5] MAddr[4] GND LRxClk[1] LStatOut[1][0]1 MAddr[8] MAddr[7] NC GND GND LTxData[1] MAddr[11] MAddr[9] PWR GND GND MAddr[12] MData[0] NC GND GND MData[2] MData[3] GND GND GND MData[5] MData[6] NC LStatOut[1][1]1 LStatOut[3][1]1 NC Y GND GND LRxSync[1] LCs[0] LInt~[0] MData[4] GND LStatOut[0][1]1 LRxClk[0] V LInt~[1] GND GND PWR LStatOut[3][0]1 U GND NC NC LTxSync[1] LCs[1] LCs[2] MData[7] NC LStatOut[0][0]1 T LCs[3] PWR GND LTxData[2] LRxData[1] LInt~[2] LInt~[3] NC LRxHld[2] LRxHld[1] LCs[4] LCs[5] GND LStatOut[2][1]1 N LCs[6] (viewed from top of device) LStatOut[2][2]1 LStatOut[0][2]1 LTxSync[2] LInt~[5] LInt~[6] GND LTxData[3] LRxData[2] LInt~[7] Reset~ PWR RS8228 RS8228 272 BGA Package NC LTxSync[3] LRxSync[2] LCs[7] Mint~ NC LRxSync[3] LTxClk[3] NC MSyncMode OneSecOut TCK 20 NC MClk TMS GND 19 LInt~[4] PWR LRxData[3] LRxClk[3] LTxClk[2] M TDO Test 2 LRxHld[7] 18 8kHzIn TRST~ LStatOut[1][7]1 PWR 17 OneSecIn Test 3 LStatOut[2][7]1 LRxSync[7] NC NC 16 TDI Test 1 LRxData[7] LTxSync[7] GND NC 15 NC LRxClk[2] L LRxSync[6] 14 LStatOut[0][7]1 LStatOut[3][7]1 LTxData[7] LStatOut[2][6]1 LTxData[6] 13 LRxClk[4] LStatOut[3][2]1 K 12 LRxClk[7] LTxClk[4] LStatOut[1][2]1 J LStatOut[1][6]1 LStatOut[2][3]1 LRxHld[3] 11 LTxClk[7] LRxHld[6] LStatOut[1][5]1 NC LStatOut[3][3]1 F 10 LStatOut[0][6]1 LStatOut[3][6]1 LRxClk[6] PWR LRxData[4] 9 LTxClk[6] LRxHld[5] GND LRxSync[4] 8 LRxData[6] LTxSync[6] LStatOut[2][5]1 LRxClk[5] NC LTxSync[4] 7 LRxSync[5] LTxClk[5] LRxHld[4] LTxData[4] 6 LStatOut[0][5]1 LTxData[5] LStatOut[3][4]1 LStatOut[0][4]1 LStatOut[0][3]1 E 5 LStatOut[3][5]1 LTxSync[5] GND LStatOut[1][4]1 B 4 LRxData[5] URxData[ 6] URxData[ 3] NC URxData[ 11] NC URxData[9] NOTE(S): The LStatOut pin names list the signal index first [3:0], then the port number [7:0]. 28228-DSH-001-C 28228-DSH-001-C Mindspeed TechnologiesTM Mindspeed Proprietary and Confidential 1-4 1.0 Product Description Table 1-1. RS8228 RS8228 27 mm Pin Descriptions (1 of 11) Reset Pin Label Signal Name No. Type Driver I/O Strength Description D16 TTL - I When asserted low, resets the device. OneSecIn One-Second Input A17 TTL - I When asserted high, the device may latch and hold its status, provided either EnStatLat (bit 5) or EnCntLat (bit 4) in the MODE register (0x0202) are written to a logic 1. This pin is typically strobed at one-second intervals. It is typically driven by OneSecOut (pin C16) but can also be driven by an external one-second source. OneSecOut One-Second Output C16 TTL 4 mA O When active high, indicates that 8000 periods of the 8kHzIn input (pin A18) have passed. Typically active at one second intervals. Remains active for one period of the 8kHzIn pin. It typically drives OneSecIn. 8kHzIn One Second Interface Device Reset One-Second Reference Clock Input A18 TTL - I A clock input used to derive OneSecOut (pin C16). Typically operates at a frequency of 8 kHz). 27 mm BGA Reset~ 28228-DSH-001-C 28228-DSH-001-C Mindspeed TechnologiesTM Mindspeed Proprietary and Confidential 1-5 M02063 M02063 Non-Conformance Table 1-1. RS8228 RS8228 27 mm Pin Descriptions (2 of 11) Pin Label Signal Name No. Type Driver I/O Strength Description Line Transmit Clock Input (ports 0­7) W2 R3 M2 H1 E3 C4 B7 A11 TTL - I Used for the framer (line) transmit timing source. The polarity is set by TxClkPol (bit 3) in the IOMODE register (0x05). LTxData[0] LTxData[1] LTxData[2] LTxData[3] LTxData[4] LTxData[5] LTxData[6] LTxData[7] Line Transmit Data Output (ports 0­7) W1 R2 L3 H3 C1 B4 C8 B11 TTL 4 mA O Used for serial transmit output data. LTxSync[0] LTxSync[1] LTxSync[2] LTxSync[3] LTxSync[4] LTxSync[5] LTxSync[6] LTxSync[7] Line Transmit Frame Synchronization (ports 0­7) V3 T1 M1 H2 D1 A3 A7 C11 TTL - I When transferring framed data, must be connected to the framer's start-of-frame output. In general purpose mode, this pin is ignored. The polarity is set by TxMrkPol (bit 4) in the IOMODE register (0x05). LRxClk[0] LRxClk[1] LRxClk[2] LRxClk[3] LRxClk[4] LRxClk[5] LRxClk[6] LRxClk[7] Line Receive Clock Input (ports 0­7) V2 P3 L2 G1 E4 C5 B8 A12 TTL - I Used for the framer (line) receive timing source. The polarity is set by RxClkPol (bit 5) in the IOMODE register (0x05). LRxData[0] LRxData[1] LRxData[2] LRxData[3] LRxData[4] LRxData[5] LRxData[6] LRxData[7] Framer (Line) Interfaces (ports 0­7) 27 mm BGA LTxClk[0] LTxClk[1] LTxClk[2] LTxClk[3] LTxClk[4] LTxClk[5] LTxClk[6] LTxClk[7] Line Receive Data Input (ports 0­7) U3 R1 L1 G2 D3 A4 A8 B12 TTL - I Used for serial receive input data. 28228-DSH-001-C 28228-DSH-001-C Mindspeed TechnologiesTM Mindspeed Proprietary and Confidential 1-6 1.0 Product Description Table 1-1. RS8228 RS8228 27 mm Pin Descriptions (3 of 11) Pin Label Signal Name No. Type Driver I/O Strength Description Line Receive Frame Synchronization (ports 0-7) T4 P2 K1 G3 D2 B5 C9 C12 TTL - I When transferring framed data, must be connected to the framer's start-of-frame output. In general purpose mode, this pin is ignored. The polarity is set by RxSyncPol (bit 4) in the IOMODE register (0x05). LRxHld[0] LRxHld[1] LRxHld[2] LRxHld[3] LRxHld[4] LRxHld[5] LRxHld[6] LRxHld[7] Line Receiver Hold Input (ports 0-7) V1 P1 K3 F1 C2 C6 B9 D12 TTL - I Stops receive cell processing when asserted. The polarity is set by RxHldPol (bit 7) in the IOMODE register (0x05). When asserted, all receiver state machines are held in reset. Tie to 3.3 V for normal operation. LCs[0] LCs[1] LCs[2] LCs[3] LCs[4] LCs[5] LCs[6] LCs[7] Line External Framer Chip Select (ports 0-7) G20 F20 F19 F18 D20 D19 D18 B20 TTL 4 mA O When asserted, the corresponding external framer will be selected. The polarity is set by CsPol (bit 2) in the IOMODE register (0x05). LInt~[0] LInt~[1] LInt~[2] LInt~[3] LInt~[4] LInt~[5] LInt~[6] LInt~[7] Line Interrupt Request G19 (ports 0-7) G18 E20 E19 E18 C20 C19 C18 TTL - I When asserted low, the corresponding framer needs servicing. The RS8228 RS8228 may be used to transfer the interrupt request to the microprocessor via MInt~ (pin B19) if it is enabled. These pins have pull-up resistors. LStatOut[3][0] LStatOut[3][1] LStatOut[3][2] LStatOut[3][3] LStatOut[3][4] LStatOut[3][5] LStatOut[3][6] LStatOut[3][7] Framer (Line) Interfaces (ports 0-7) (Continued) 27 mm BGA LRxSync[0] LRxSync[1] LRxSync[2] LRxSync[3] LRxSync[4] LRxSync[5] LRxSync[6] LRxSync[7] Line Status Output 3 (ports 0-7) TTL 4 mA O Reflects port signals based on the value of StatSel (bits 0 and 1) in the IOMODE register (0x05): U2 N3 K2 F2 B1 A5 A9 A13 LStatOut RcvrHld[7:0] NonMatch[7:0] RxOvfl[7:0] OutStat[3][7:0](0x07, bit 3) StatSelect 00 01 10 11 Eight RcvrHld, NonMatch, and RxOvfl signals (0­7) have numbers that correspond to the eight ports. 28228-DSH-001-C 28228-DSH-001-C Mindspeed TechnologiesTM Mindspeed Proprietary and Confidential 1-7 M02063 M02063 Non-Conformance Table 1-1. RS8228 RS8228 27 mm Pin Descriptions (4 of 11) Pin Label Framer (Line) Interfaces (port 0-7) (Continued) 27 mm BGA LStatOut[2][0] LStatOut[2][1] LStatOut[2][2] LStatOut[2][3] LStatOut[2][4] LStatOut[2][5] LStatOut[2][6] LStatOut[2][7] Signal Name Line Status Output 2 (ports 0-7) No. Type T3 N2 J1 F3 A2 B6 C10 B13 TTL Driver I/O Strength 4 mA O Description Reflects various port signals based on the value of StatSel (0x05, bits 0 and 1): LStatOut[3] HECCorr[7:0] IdleRcvd[7:0] TxOvfl[7:0] OutStat[2][7:0](0x07, bit 2) StatSelect 00 01 10 11 Eight HECCorr, IDlRcvd, and TxOvfl signals (0­7) have numbers that correspond to the eight ports. LStatOut[1][0] LStatOut[1][1] LStatOut[1][2] LStatOut[1][3] LStatOut[1][4] LStatOut[1][5] LStatOut[1][6] LStatOut[1][7] Line Status Output 1 (ports 0-7) U1 N1 J2 E1 B2 C7 B10 C13 TTL 4 mA O This pin reflects various port signals depending on the value of StatSel (0x05, bits 0 and 1): LStatOut[3] StatSelect HECDet[7:0] 00 CellRcvd[7:0] 01 SOCErr[7:0] 10 OutStat[1][7:0](0x07, bit 1) 11 Eight HECDet, CellRcvd, and SOCErr signals (0­7) have numbers that correspond to the eight ports. LStatOut[0][0] LStatOut[0][1] LStatOut[0][2] LStatOut[0][3] LStatOut[0][4] LStatOut[0][5] LStatOut[0][6] LStatOut[0][7] Line Status Output 0 (ports 0-7) T2 M4 J3 E2 B3 A6 A10 A14 TTL 4 mA O This pin reflects various port signals depending on the value of StatSel (0x05, bits 0 and 1): LStatOut[3] LOCD[7:0] CellSent[7:0] ParErr[7:0] OutStat[0][7:0](0x07, bit 0) StatSelect 00 01 10 11 Eight LOCD, CellSent, and ParErr signals (0­7) have numbers that correspond to the eight ports. 28228-DSH-001-C 28228-DSH-001-C Mindspeed TechnologiesTM Mindspeed Proprietary and Confidential 1-8 1.0 Product Description Table 1-1. RS8228 RS8228 27 mm Pin Descriptions (5 of 11) Pin Label Signal Name No. Type Driver I/O Strength Description TTL - I An 8­50 MHz clock signal input. The RS8228 RS8228 samples the microprocessor interface pins (MCs~, MW/R~, MAs~, MAddr[6:0], and MData[7:0]) on the rising edge of this signal. The microprocessor interface output pins (MData[7:0], MInt~) are clocked on the rising edge of MClk. Microprocessor Synchronous/ Asynchronous Bus Mode Select B18 TTL - I Selects synchronous or asynchronous bus mode, which determines the functions of two pins, MW/R~,MRd~ (pin P17) and MAs~,MWr~ (pin R20). A logic 1 selects the synchronous bus mode, compatible with Bt8230 and Bt8233. In this mode, these pins are defined as follows: MW/R~ (P17) and MAs~ (R20). A logic 0 selects the asynchronous SRAM-type bus mode. In this mode, the pins are defined as follows: MRd~ (P17) and MWr~ (R20). MCs~ Microprocessor Chip Select R19 TTL - I When asserted low, the device is selected for read and write accesses. When asserted high, the device will not respond to input signal transitions on MClk, MW/R~, MRd~, or MAs~, MWr~. Additionally, when MCs~ is asserted high, the MData[7:0] pins are in a high-impedance state but the MInt~ pin remains operational. NOTE(S): MCs~ must be asserted when using the LCs pins to select external framers. 27 mm BGA Microprocessor Clock B17 MSyncMode Microprocessor Interface MClk 28228-DSH-001-C 28228-DSH-001-C Mindspeed TechnologiesTM Mindspeed Proprietary and Confidential 1-9 M02063 M02063 Non-Conformance Table 1-1. RS8228 RS8228 27 mm Pin Descriptions (6 of 11) Pin Label MW/R~ Microprocessor Interface (Continued) 27 mm BGA or Signal Name No. Type Microprocessor Write/ P17 Read TTL Driver I/O Strength - I or MRd~ Microprocessor Address Strobe or MWr~ 28228-DSH-001-C 28228-DSH-001-C or Write Control When MSyncMode is asserted high, this pin is a read/write control pin. In this mode, when MW/R~ is asserted high, a write access is enabled and the MData[7:0] pin values will be written to the memory location indicated by the MAddr[6:0] pins. Also, when MW/R~ is asserted low in this mode, a read access is enabled and the memory location indicated by the MAddr[6:0] pins is read. Its value is placed on the MData[7:0] pins. Both read and write accesses assume the device is chip selected (MCs~ = 0), the address is valid (MAs~ = 0), and the device is not being reset (Reset~ = 1). When MSyncMode is asserted low, this pin is a read control pin. In this mode, when MRd~ is asserted low, a read access is enabled and the memory location indicated by the MAddr[6:0] pins is read. Its value is placed on the MData[7:0] pins. The read access assumes the device is chip selected (MCs~ = 0), a write access is not being requested (MWr~ = 1), and the device is not being reset (Reset~ = 1). Read Control MAs~ Description R20 TTL - I When MSyncMode is asserted high, this pin is an address strobe pin. When the MAs~ pin is asserted low, it indicates a valid address, MAddr[6:0]. This signal is used to qualify read and write accesses. When MSyncMode is asserted low, this pin is a write control pin. When MWr~ is asserted low, a write access is enabled and the MData[7:0] pin values will be written to the memory location indicated by the MAddr[6:0] pins. The write access assumes the device is chip selected (MCs~ = 0), a read access is not being requested (MRd~ = 1), and the device is not being reset (Reset~ = 1). Mindspeed TechnologiesTM Mindspeed Proprietary and Confidential 1-10 1.0 Product Description Table 1-1. RS8228 RS8228 27 mm Pin Descriptions (7 of 11) Pin Label MAddr[12] Signal Name Driver I/O Strength TTL L20 TTL I MAddr[10] L18 TTL I MAddr[9] L19 TTL I MAddr[8] M20 TTL I MAddr[7] M19 TTL I MAddr[6] M18 TTL I MAddr[5] N20 TTL I MAddr[4] N19 TTL I MAddr[3] N18 TTL I MAddr[2] P20 TTL I MAddr[1] P19 TTL I MAddr[0] P18 TTL I H18 TTL 8 mA I/O A bidirectional data bus for transferring read and write data. H19 TTL 8 mA I/O MData[5] H20 TTL 8 mA I/O MData[4] J18 TTL 8 mA I/O MData[3] J19 TTL 8 mA I/O MData[2] J20 TTL 8 mA I/O MData[1] K18 TTL 8 mA I/O MData[0] K19 TTL 8 mA I/O Microprocessor Interface (Continued) 27 mm BGA MData[7] MData[6] Microprocessor Data Bus - I Description K20 MAddr[11] Microprocessor Address Bus No. Type These 13 bits are an address input for identifying the register to access. Registers are mapped into the address space 0000­1FFF. MRdy Microprocessor Ready R18 TTL 4 mA O When active high, the current read or write transaction has been completed. For a read transaction, the data is ready to be transferred to the microprocessor. For a write transaction, the data provided by the microprocessor has been written. This pin is an open drain output for an external wired OR logic implementation. An external pull-up resistor is required for this pin. MInt~ Microprocessor Interrupt Request B19 TTL 2 mA O When active low, the device needs servicing. It remains active until the pending interrupt is processed by the Interrupt Service Routine. This pin is an open drain output for an external wired OR logic implementation. See Section 2.4.6. An external pull-up resistor is required for this pin. 28228-DSH-001-C 28228-DSH-001-C Mindspeed TechnologiesTM Mindspeed Proprietary and Confidential 1-11 M02063 M02063 Non-Conformance Table 1-1. RS8228 RS8228 27 mm Pin Descriptions (8 of 11) Pin Label Signal Name No. Type Driver I/O Strength Description JTAG (see IEEE 1149.1a-1993) UTOPIA Transmit Test Reset B15 TTL - I When asserted, the internal boundary-scan logic is reset. This pin has a pull-up resistor. Do not assert this reset unless a clock is provided on TCK. TCK Test Clock D14 TTL - I Samples the value of TMS and TDI on its rising edge to control the boundary scan operations. TMS Test Mode Select C15 TTL - I Controls the boundary-scan Test Access Port (TAP) controller operation. This pin has a pull-up resistor. TDI Test Data Input A16 TTL - I The serial test data input. This pin has a pull-up resistor. TDO Test Data Output B16 TTL 4 mA O The serial test data output. UTxClk 27 mm BGA TRST~ UTOPIA Transmit Clock W13 TTL - I A clock input used to synchronize transmitted data. UTxEnb~ Transmit Enable Y13 TTL - I Enables data transmission when asserted low. UTxAddr[0] LSB V4 TTL - I U5 TTL I The address of the PHY device being selected for transmission. Address 11111 (31 decimal) indicates a null PHY port. Y3 TTL I Y4 TTL I V5 TTL I UTxAddr[1] UTxAddr[2] UTxAddr[3] UTxAddr[4] 28228-DSH-001-C 28228-DSH-001-C UTOPIA Transmit Address MSB Mindspeed TechnologiesTM Mindspeed Proprietary and Confidential 1-12 1.0 Product Description Table 1-1. RS8228 RS8228 27 mm Pin Descriptions (9 of 11) Pin Label Driver I/O Strength W5 TTL Y5 TTL - I V6 TTL I UTxData[3] UTOPIA Transmit Data U7 TTL I UTxData[4] W6 TTL I UTxData[5] Y6 TTL I UTxData[6] V7 TTL I UTxData[7] W7 TTL I UTxData[8] Y7 TTL I UTxData[9] W8 TTL I UTxData[10] Y8 TTL I UTxData[11] W9 TTL I UTxData[12] Y9 TTL I UTxData[13] W10 TTL I UTxData[14] Y10 TTL Description I UTxData[2] UTOPIA Transmit (Continued) LSB No. Type UTxData[1] Transmit data from the ATM layer. I I UTxData[15] MSB Y11 TTL UTxPrty UTOPIA Transmit Parity Input W11 TTL - I The parity calculated over the UTxData bus. BusWidth (bit 0) in the IOMODE register (0x0202) determines whether parity is checked over UTxData[7:0] or UTxData[15:0]. OddEven (bit 2) in the UTOP1 register (0x0D) determines whether this pin represents even or odd parity. UTxSOC UTOPIA Transmit Start of Cell W12 TTL - I Indicates the first byte of valid cell data transmitted when asserted high. UTxClAv UTOPIA Transmit Cell Available Y12 TTL 8 mA O Indicates a FIFO full condition or Cell Available condition, depending upon UTOPIA HandShake (bit 1) in the MODE register (0x0202). An external pull-down resistor is required for this pin. URxClk UTOPIA Receive Clock V13 TTL - I A clock input used to synchronize received data. URxEnb~ UTOPIA Receive 27 mm BGA UTxData[0] Signal Name Receive Enable Y14 TTL - I Enables data reception when asserted low. URxAddr[0] LSB V20 TTL - I U20 TTL I The address of the PHY device being selected for reception. The address range is 0­30. Address 11111 (31 decimal) indicates a null PHY port. UTOPIA Receive Address T18 TTL I T19 TTL I MSB T20 TTL I URxAddr[1] URxAddr[2] URxAddr[3] URxAddr[4] 28228-DSH-001-C 28228-DSH-001-C Mindspeed TechnologiesTM Mindspeed Proprietary and Confidential 1-13 M02063 M02063 Non-Conformance Table 1-1. RS8228 RS8228 27 mm Pin Descriptions (10 of 11) Pin Label URxData[0] Signal Name Driver I/O Strength Y16 TTL 8 mA O URxData[1] V15 TTL 8 mA URxData[2] W16 TTL 8 mA O Y17 TTL 8 mA O URxData[4] V16 TTL 8 mA O URxData[5] W17 TTL 8 mA O URxData[6] Y18 TTL 8 mA O URxData[7] U16 TTL 8 mA O URxData[8] W18 TTL 8 mA O URxData[9] Y19 TTL 8 mA O URxData[10] V18 TTL 8 mA O URxData[11] W19 TTL 8 mA O URxData[12] V19 TTL 8 mA O URxData[13] U19 TTL 8 mA O URxData[14] U18 TTL 8 mA UTOPIA Receive (Continued) 27 mm BGA Description O O URxData[3] LSB No. Type UTOPIA Receive Data Bus Output the received data to the ATM layer. URxData[15] MSB T17 TTL 8 mA O URxPrty UTOPIA Receive Parity V14 TTL 8 mA O The parity calculated over the URxData bus. BusWidth (bit 0) in the IOMODE register (0x0202) determines whether parity is calculated over URxData[7:0] or URxData[15:0]. OddEven (bit 2) in the UTOP1 register (0x0D) determines whether this pin represents even or odd parity. URxSOC Receive Start of Cell Y15 TTL 8 mA O When active high, indicates the first byte of valid cell data received. An external pull-down resistor is required for this pin. URxClAv UTOPIA Receive Cell Available W14 TTL 8 mA O Indicates FIFO empty or Cell Buffer Available, depending upon HandShake (bit 1) in the MODE register (0x0202). An external pull-down resistor is required for this pin. 28228-DSH-001-C 28228-DSH-001-C Mindspeed TechnologiesTM Mindspeed Proprietary and Confidential 1-14 1.0 Product Description Table 1-1. RS8228 RS8228 27 mm Pin Descriptions (11 of 11) Pin Label Signal Name No. Type Driver I/O Strength Description D6 D11 D15 F4 F17 K4 L17 R4 R17 U6 U10 U15 - - - Power supply connections. Ground A1 D4 D8 D13 D17 H4 H17 J9 J10 J11 J12 K9 K10 K11 K12 L9 L10 L11 L12 M9 M10 M11 M12 N4 N17 U4 U8 U13 U17 - - - Ground connections. VGG Electrostatic Discharge (ESD) Supply Voltage Y1 - - - Provides ESD protection when interfacing with 5 V systems. If using this device in a system with 5 V logic, this pin must be connected to 5 V. If using 3.3 V system, leave this pin unconnected. Test 1 Manufacturing Test 1 B14 TTL - I Reserved, connect to ground. Test 2 Manufacturing Test 2 C14 TTL - I Reserved, connect to ground. Test 3 Manufacturing Test 3 A15 TTL - I Reserved, connect to ground. Testing Supply Voltage Supply Voltage GND 27 mm BGA PWR NOTE(S): All input and bi-directional pins have hysteresis. 28228-DSH-001-C 28228-DSH-001-C Mindspeed TechnologiesTM Mindspeed Proprietary and Confidential 1-15 M02063 M02063 Non-Conformance 1.4 17 mm Pin Diagram and Definitions Figure 1-3 illustrates a pinout diagram for the M28228 M28228. It is a single CMOS integrated circuit packaged in a 256-pin BGA. All unused input pins should be connected to ground or power. Unused outputs should be left unconnected. NOTE: The port numbers following the pin names in the Port Interface section represent each of the eight ports as follows: LTxSync[0]-Line transmit sync for port 0. LStatOut[3][0]-Line status output bit number 3 for port 0. Figure 1-4. M28228 M28228 17 mm Pinout Diagram (Top View) M28228 M28228 256 BGA Package (viewed from top of device) 1 2 3 4 LRxHld[5] 27 mm BGA A B LTxClk[5] LStatOut[3][4] LRxData[4] LTxSync[4] LStatOut[1][3] E F LStatOut[2][3] LTxClk[4] LStatOut[3][3] LRxHld[3] LStatOut[0][2] LStatOut[2][2] LTxData[2] LStatOut[1][1] LRxHld[1] 1 UTxData[10] 2 UTxData[3] UTxData[4] UTxData[5] 4 5 UTxPrty UTxData[9] UTxData[2] UTxData[15] 7 URxData[2] 9 10 11 URxAddr[0] R URxData[10] URxData[11] URxData[3] 13 P URxData[13] URxData[1] 12 N URxAddr[1] URxData[5] URxData[4] URxEnb~ M URxAddr[2] URxData[8] URxPrty UTxEnb~ MAs~ or MWr~ URxAddr[3] URxData[12] URxData[0] URxSOC UTxClAv 8 URxData[14] URxData[9] UTxClk UTxSOC UTxData[11] 6 URxData[7] URxClAv UTxData[13] UTxData[8] UTxData[0] 3 UTxData[12] UTxData[7] UTxData[1] UTxAddr[4] L MCs~ URxData[15] URxClk UTxData[14] UTxData[6] UTxAddr[1] LRxData[0] MAddr[1] MW/R~ or MRd~ UTxAddr[3] K MAddr[0] LTxClk[0] UTxAddr[2] T MRdy URxAddr[4] VGG LRxSync[0] MAddr[2] MAddr[4] MAddr[5] LTxSync[0] LStatOut[0][0] J MAddr[9] LTxSync[1] UTxAddr[0] H MAddr[6] MAddr[3] LStatOut[3][1] LRxHld[0] LRxClk[0] R MAddr[8] LTxData[0] LTxClk[1] G MAddr[10] MAddr[11] LTxData[1] LStatOut[3][0] P MData[0] T URxData[6] 14 F MAddr[12] MData[2] MData[1] LStatOut[2][1] LStatOut[1][0] N MData[5] MAddr[7] LStatOut[2][0] MData[3] LInt~[1] MData[4] LRxHld[2] LRxData[1] LRxClk[1] M MData[6] LCs[1] LTxClk[2] LRxSync[1] L LInt~[0] E LCs[0] LInt~[5] LRxData[2] LStatOut[0][1] K MData[7] LCs[4] LTxSync[2] LRxSync[2] D LCs[3] MInt~ LTxClk[3] LStatOut[1][2] C LCs[2] LInt~[7] LInt~[2] B LInt~[3] LInt~[4] LTxSync[3] LRxClk[2] J LCs[7] LRxClk[3] LRxData[3] LCs[5] Reset~ TDO A LInt~[6] OneSecOut LRxSync[3] LStatOut[3][2] H MClk OneSecIn LRxHld[7] LCs[6] TDI LStatOut[0][6] 16 MSyncMode TCK Test1 LRxHld[6] 15 8kHzIn LRxSync[6] LStatOut[0][3] LTxData[3] G LStatOut[1][7] 14 TMS Test2 LRxClk[7] LRxData[6] 13 TRST~ LStatOut[2][7] LStatOut[1][6] LStatOut[0][5] 12 Test3 LRxData[7] LRxClk[6] LTxData[5] LRxSync[4] 11 LStatOut[0][7] LTxClk[7] LRxData[5] LStatOut[1][4] 10 LStatOut[3][7] LStatOut[3][6] LRxClk[5] 9 LRxSync[7] LStatOut[1][5] LStatOut[0][4] 8 LTxData[7] LTxSync[6] LStatOut[2][4] LRxClk[4] 7 LStatOut[2][6] LStatOut[3][5] LTxData[4] D LTxData[6] LTxSync[5] LRxHld[4] C 6 LTxSync[7] LTxClk[6] LStatOut[2][5] LRxSync[5] 5 15 16 Ground - VSS Signal Power - VDD 3.3 V Spare/No Connect 28228-DSH-001-C 28228-DSH-001-C Mindspeed TechnologiesTM Mindspeed Proprietary and Confidential 1-16 1.0 Product Description Table 1-2. RS8228 RS8228 17 mm Pin Descriptions (1 of 10) Reset Pin Label Signal Name No. Type Driver I/O Strength Description TTL - I When asserted low, resets the device. One-Second Input D12 TTL - I When asserted high, the device may latch and hold its status, provided either EnStatLat (bit 5) or EnCntLat (bit 4) in the MODE register (0x0202) are written to a logic 1. This pin is typically strobed at one-second intervals. It is typically driven by OneSecOut (pin C16) but can also be driven by an external one-second source. OneSecOut One-Second Output C12 TTL 4 mA O When active high, indicates that 8000 periods of the 8kHzIn input (pin A18) have passed. Typically active at one second intervals. Remains active for one period of the 8kHzIn pin. It typically drives OneSecIn. One-Second A14 Reference Clock Input TTL - I A clock input used to derive OneSecOut (pin C16). Typically operates at a frequency of 8 kHz). LTxClk[0] LTxClk[1] LTxClk[2] LTxClk[3] LTxClk[4] LTxClk[5] LTxClk[6] LTxClk[7] Line Transmit Clock Input (ports 0­7) N4 N1 J4 G5 E3 B2 A4 B8 TTL - I Used for the framer (line) transmit timing source. The polarity is set by TxClkPol (bit 3) in the IOMODE register (0x05). LTxData[0] LTxData[1] LTxData[2] LTxData[3] LTxData[4] LTxData[5] LTxData[6] LTxData[7] Line Transmit Data Output (ports 0­7) M3 L4 K1 G2 D2 D5 A5 A7 TTL 4 mA O Used for serial transmit output data. LTxSync[0] LTxSync[1] LTxSync[2] LTxSync[3] LTxSync[4] LTxSync[5] LTxSync[6] LTxSync[7] Line Transmit Frame Synchronization (ports 0­7) N3 L5 J3 G4 D1 B3 B5 A6 TTL - I When transferring framed data, must be connected to the framer's start-of-frame output. In general purpose mode, this pin is ignored. The polarity is set by TxMrkPol (bit 4) in the IOMODE register (0x05). LRxClk[0] LRxClk[1] LRxClk[2] LRxClk[3] LRxClk[4] LRxClk[5] LRxClk[6] LRxClk[7] One Second Interface C13 8kHzIn Framer (Line) Interfaces (ports 0­7) Device Reset OneSecIn 17 mm BGA Reset* Line Receive Clock Input (ports 0­7) R2 M2 J2 F5 C1 C5 C7 C9 TTL - I Used for the framer (line) receive timing source. The polarity is set by RxClkPol (bit 5) in the IOMODE register (0x05). 28228-DSH-001-C 28228-DSH-001-C Mindspeed TechnologiesTM Mindspeed Proprietary and Confidential 1-17 M02063 M02063 Non-Conformance Table 1-2. RS8228 RS8228 17 mm Pin Descriptions (2 of 10) Pin Label Signal Name No. Type Driver I/O Strength Description Line Receive Data Input (ports 0­7) T1 K3 H4 G3 D3 D6 D7 B9 TTL - I Used for serial receive input data. LRxSync[0] LRxSync[1] LRxSync[2] LRxSync[3] LRxSync[4] LRxSync[5] LRxSync[6] LRxSync[7] Line Receive Frame Synchronization (ports 0-7) R1 L2 J1 F4 E4 A1 E7 A8 TTL - I When transferring framed data, must be connected to the framer's start-of-frame output. In general purpose mode, this pin is ignored. The polarity is set by RxSyncPol (bit 4) in the IOMODE register (0x05). LRxHld[0] LRxHld[1] LRxHld[2] LRxHld[3] LRxHld[4] LRxHld[5] LRxHld[6] LRxHld[7] Line Receiver Hold Input (ports 0-7) M4 M1 H5 F1 C2 A2 D8 D9 TTL - I Stops receive cell processing when asserted. The polarity is set by RxHldPol (bit 7) in the IOMODE register (0x05). When asserted, all receiver state machines are held in reset. Tie to Vss for normal operation. LCs[0] LCs[1] LCs[2] LCs[3] LCs[4] LCs[5] LCs[6] LCs[7] Line External Framer Chip Select (ports 0-7) E15 F13 D16 D15 E14 B16 A16 C14 TTL 4 mA O When asserted, the corresponding external framer will be selected. The polarity is set by CsPol (bit 2) in the IOMODE register (0x05). LInt*[0] LInt*[1] LInt*[2] LInt*[3] LInt*[4] LInt*[5] LInt*[6] LInt*[7] Framer (Line) Interfaces (ports 0-7) (Continued) 17 mm BGA LRxData[0] LRxData[1] LRxData[2] LRxData[3] LRxData[4] LRxData[5] LRxData[6] LRxData[7] Line Interrupt Request F12 (ports 0-7) F15 E12 C16 C15 E13 B15 D14 TTL - I When asserted low, the corresponding framer needs servicing. The RS8228 RS8228 may be used to transfer the interrupt request to the microprocessor via MInt* (pin B19) if it is enabled. These pins have pull-up resistors. 28228-DSH-001-C 28228-DSH-001-C Mindspeed TechnologiesTM Mindspeed Proprietary and Confidential 1-18 1.0 Product Description Table 1-2. RS8228 RS8228 17 mm Pin Descriptions (3 of 10) Pin Label LStatOut[3][0] LStatOut[3][1] LStatOut[3][2] LStatOut[3][3] LStatOut[3][4] LStatOut[3][5] LStatOut[3][6] LStatOut[3][7] Signal Name Line Status Output 3 (ports 0-7) No. Type P2 K5 H2 F2 B1 B4 B7 A9 TTL Driver I/O Strength 4 mA O Description Reflects port signals based on the value of StatSel (bits 0 and 1) in the IOMODE register (0x05): LStatOut RcvrHld[7:0] NonMatch[7:0] RxOvfl[7:0] OutStat[3][7:0](0x07, bit 3) StatSelect 00 01 10 11 Framer (Line) Interfaces (ports 0-7) (Continued) 17 mm BGA Eight RcvrHld, NonMatch, and RxOvfl signals (0­7) have numbers that correspond to the eight ports. LStatOut[2][0] LStatOut[2][1] LStatOut[2][2] LStatOut[2][3] LStatOut[2][4] LStatOut[2][5] LStatOut[2][6] LStatOut[2][7] Line Status Output 2 (ports 0-7) L3 K4 H1 E1 C3 A3 B6 B10 TTL 4 mA O Reflects various port signals based on the value of StatSel (0x05, bits 0 and 1): LStatOut[3] HECCorr[7:0] IdleRcvd[7:0] TxOvfl[7:0] OutStat[2][7:0](0x07, bit 2) StatSelect 00 01 10 11 Eight HECCorr, IDlRcvd, and TxOvfl signals (0­7) have numbers that correspond to the eight ports. LStatOut[1][0] LStatOut[1][1] LStatOut[1][2] LStatOut[1][3] LStatOut[1][4] LStatOut[1][5] LStatOut[1][6] LStatOut[1][7] Line Status Output 1 (ports 0-7) N2 L1 H3 E2 D4 C6 C8 C10 TTL 4 mA O This pin reflects various port signals depending on the value of StatSel (0x05, bits 0 and 1): LStatOut[3] StatSelect HECDet[7:0] 00 CellRcvd[7:0] 01 SOCErr[7:0] 10 OutStat[1][7:0](0x07, bit 1) 11 Eight HECDet, CellRcvd, and SOCErr signals (0­7) have numbers that correspond to the eight ports. LStatOut[0][0] LStatOut[0][1] LStatOut[0][2] LStatOut[0][3] LStatOut[0][4] LStatOut[0][5] LStatOut[0][6] LStatOut[0][7] Line Status Output 0 (ports 0-7) P1 K2 G1 F3 C4 E6 E8 A10 TTL 4 mA O This pin reflects various port signals depending on the value of StatSel (0x05, bits 0 and 1): LStatOut[3] LOCD[7:0] CellSent[7:0] ParErr[7:0] OutStat[0][7:0](0x07, bit 0) StatSelect 00 01 10 11 Eight LOCD, CellSent, and ParErr signals (0­7) have numbers that correspond to the eight ports. 28228-DSH-001-C 28228-DSH-001-C Mindspeed TechnologiesTM Mindspeed Proprietary and Confidential 1-19 M02063 M02063 Non-Conformance Table 1-2. RS8228 RS8228 17 mm Pin Descriptions (4 of 10) Pin Label Signal Name No. Type Driver I/O Strength Description TTL - I An 8­50 MHz clock signal input. The RS8228 RS8228 samples the microprocessor interface pins (MCs*, MW/R*, MAs*, MAddr[6:0], and MData[7:0]) on the rising edge of this signal. The microprocessor interface output pins (MData[7:0], MInt*) are clocked on the rising edge of MClk. Microprocessor Synchronous/ Asynchronous Bus Mode Select A15 TTL - I Selects synchronous or asynchronous bus mode, which determines the functions of two pins, MW/R*,MRd* (pin P17) and MAs*,MWr* (pin R20). A logic 1 selects the synchronous bus mode, compatible with Bt8230 and Bt8233. In this mode, these pins are defined as follows: MW/R* (P17) and MAs* (R20). A logic 0 selects the asynchronous SRAM-type bus mode. In this mode, the pins are defined as follows: MRd* (P17) and MWr* (R20). MCs* Microprocessor Chip Select M15 TTL - I When asserted low, the device is selected for read and write accesses. When asserted high, the device will not respond to input signal transitions on MClk, MW/R*, MRd*, or MAs*, MWr*. Additionally, when MCs* is asserted high, the MData[7:0] pins are in a high-impedance state but the MInt* pin remains operational. NOTE(S): MCs* must be asserted when using the LCs pins to select external framers. 17 mm BGA Microprocessor Clock B14 MSyncMode Microprocessor Interface MClk 28228-DSH-001-C 28228-DSH-001-C Mindspeed TechnologiesTM Mindspeed Proprietary and Confidential 1-20 1.0 Product Description Table 1-2. RS8228 RS8228 17 mm Pin Descriptions (5 of 10) Pin Label MW/R* Microprocessor Interface (Continued) 17 mm BGA or Signal Name No. Type Microprocessor Write/ M14 Read TTL Driver I/O Strength - I or MRd* Microprocessor Address Strobe or MWr* 28228-DSH-001-C 28228-DSH-001-C or Write Control When MSyncMode is asserted high, this pin is a read/write control pin. In this mode, when MW/R* is asserted high, a write access is enabled and the MData[7:0] pin values will be written to the memory location indicated by the MAddr[6:0] pins. Also, when MW/R* is asserted low in this mode, a read access is enabled and the memory location indicated by the MAddr[6:0] pins is read. Its value is placed on the MData[7:0] pins. Both read and write accesses assume the device is chip selected (MCs* = 0), the address is valid (MAs* = 0), and the device is not being reset (Reset* = 1). When MSyncMode is asserted low, this pin is a read control pin. In this mode, when MRd* is asserted low, a read access is enabled and the memory location indicated by the MAddr[6:0] pins is read. Its value is placed on the MData[7:0] pins. The read access assumes the device is chip selected (MCs* = 0), a write access is not being requested (MWr* = 1), and the device is not being reset (Reset* = 1). Read Control MAs* Description M16 TTL - I When MSyncMode is asserted high, this pin is an address strobe pin. When the MAs* pin is asserted low, it indicates a valid address, MAddr[6:0]. This signal is used to qualify read and write accesses. When MSyncMode is asserted low, this pin is a write control pin. When MWr* is asserted low, a write access is enabled and the MData[7:0] pin values will be written to the memory location indicated by the MAddr[6:0] pins. The write access assumes the device is chip selected (MCs* = 0), a read access is not being requested (MRd* = 1), and the device is not being reset (Reset* = 1). Mindspeed TechnologiesTM Mindspeed Proprietary and Confidential 1-21 M02063 M02063 Non-Conformance Table 1-2. RS8228 RS8228 17 mm Pin Descriptions (6 of 10) Signal Name No. Type Driver I/O Strength Description Microprocessor Interface (Continued) MAddr[12] MAddr[11] MAddr[10] MAddr[9] MAddr[8] MAddr[7] MAddr[6] MAddr[5] MAddr[4] MAddr[3] MAddr[2] MAddr[1] MAddr[0] Microprocessor Address Bus G16 H15 H16 J15 J14 J13 J16 K13 K15 K14 K16 L16 L15 TTL - MData[7] MData[6] MData[5] MData[4] MData[3] MData[2] MData[1] MData[0] Microprocessor Data Bus E16 F14 G14 G13 F16 G15 H14 H13 TTL 8 mA I/O A bidirectional data bus for transferring read and write data. MRdy Microprocessor Ready L14 TTL 4 mA O When active high, the current read or write transaction has been completed. For a read transaction, the data is ready to be transferred to the microprocessor. For a write transaction, the data provided by the microprocessor has been written. This pin is an open drain output for an external wired OR logic implementation. An external pull-up resistor is required for this pin. MInt* JTAG (see IEEE 1149.1a-1993) 17 mm BGA Pin Label Microprocessor Interrupt Request D13 TTL 2 mA O When active low, the device needs servicing. It remains active until the pending interrupt is processed by the Interrupt Service Routine. This pin is an open drain output for an external wired OR logic implementation. See Section 2.4.6. An external pull-up resistor is required for this pin. TRST* Test Reset A12 TTL - I When asserted, the internal boundary-scan logic is reset. This pin has a pull-up resistor. Do not assert this reset unless a clock is provided on TCK. TCK Test Clock B12 TTL - I Samples the value of TMS and TDI on its rising edge to control the boundary scan operations. TMS Test Mode Select A13 TTL - I Controls the boundary-scan Test Access Port (TAP) controller operation. This pin has a pull-up resistor. TDI Test Data Input B13 TTL - I The serial test data input. This pin has a pull-up resistor. TDO Test Data Output D11 TTL 4 mA O The serial test data output. 28228-DSH-001-C 28228-DSH-001-C I These 13 bits are an address input for identifying the register to access. Registers are mapped into the address space 0000­1FFF. Mindspeed TechnologiesTM Mindspeed Proprietary and Confidential 1-22 1.0 Product Description Table 1-2. RS8228 RS8228 17 mm Pin Descriptions (7 of 10) Pin Label Signal Name No. Type Driver I/O Strength Description UTOPIA Transmit UTxClk UTOPIA Transmit Clock R10 TTL - I A clock input used to synchronize transmitted data. UTxEnb* Transmit Enable T10 TTL - I Enables data transmission when asserted low. UTxAddr[0] LSB P4 TTL - I R3 TTL I The address of the PHY device being selected for transmission. Address 11111 (31 decimal) indicates a null PHY port. T2 TTL I R4 TTL I I UTxAddr[1] UTxAddr[2] UTxAddr[3] UTOPIA Transmit Address T3 TTL LSB T4 TTL UTxData[1] R5 TTL I UTxData[2] T5 TTL I UTxData[3] UTOPIA Transmit Data P6 TTL I UTxData[4] P5 TTL I UTxData[5] P7 TTL I UTxData[6] N7 TTL I UTxData[7] R6 TTL I UTxData[8] UTOPIA Transmit (Continued) MSB UTxData[0] 17 mm BGA UTxAddr[4] T6 TTL I UTxData[9] R7 TTL I UTxData[10] N8 TTL I UTxData[11] T7 TTL I UTxData[12] P8 TTL I UTxData[13] R8 TTL I UTxData[14] N9 TTL I I - I Transmit data from the ATM layer. UTxData[15] MSB T8 TTL UTxPrty UTOPIA Transmit Parity Input P9 TTL - I The parity calculated over the UTxData bus. BusWidth (bit 0) in the IOMODE register (0x0202) determines whether parity is checked over UTxData[7:0] or UTxData[15:0]. OddEven (bit 2) in the UTOP1 register (0x0D) determines whether this pin represents even or odd parity. UTxSOC UTOPIA Transmit Start of Cell R9 TTL - I Indicates the first byte of valid cell data transmitted when asserted high. UTxClAv UTOPIA Transmit Cell Available T9 TTL 8 mA O Indicates a FIFO full condition or Cell Available condition, depending upon UTOPIA HandShake (bit 1) in the MODE register (0x0202). An external pull-down resistor is required for this pin. 28228-DSH-001-C 28228-DSH-001-C Mindspeed TechnologiesTM Mindspeed Proprietary and Confidential 1-23 M02063 M02063 Non-Conformance Table 1-2. RS8228 RS8228 17 mm Pin Descriptions (8 of 10) Pin Label Signal Name No. Type Driver I/O Strength Description UTOPIA Receive Clock N10 TTL - I A clock input used to synchronize received data. URxEnb* Receive Enable T11 TTL - I Enables data reception when asserted low. URxAddr[0] LSB R16 TTL - I P16 TTL I The address of the PHY device being selected for reception. The address range is 0­30. Address 11111 (31 decimal) indicates a null PHY port. UTOPIA Receive Address N15 TTL I N16 TTL I URxAddr[4] MSB M13 TTL I URxData[0] LSB R12 TTL 8 mA O URxData[1] T13 TTL 8 mA O URxData[2] P11 TTL 8 mA O T14 TTL 8 mA O URxData[4] R13 TTL 8 mA O URxData[5] R14 TTL 8 mA O URxData[6] T15 TTL 8 mA O URxData[7] UTOPIA Receive URxClk N11 TTL 8 mA O URxData[8] P13 TTL 8 mA O URxData[9] P12 TTL 8 mA O URxData[10] R15 TTL 8 mA O URxData[11] T16 TTL 8 mA O URxData[12] P14 TTL 8 mA O URxData[13] P15 TTL 8 mA O URxData[14] N13 TTL 8 mA O URxAddr[1] URxAddr[2] URxData[3] UTOPIA Receive (Continued) 17 mm BGA URxAddr[3] UTOPIA Receive Data Bus Output the received data to the ATM layer. URxData[15] MSB N14 TTL 8 mA O URxPrty UTOPIA Receive Parity T12 TTL 8 mA O The parity calculated over the URxData bus. BusWidth (bit 0) in the IOMODE register (0x0202) determines whether parity is calculated over URxData[7:0] or URxData[15:0]. OddEven (bit 2) in the UTOP1 register (0x0D) determines whether this pin represents even or odd parity. URxSOC Receive Start of Cell R11 TTL 8 mA O When active high, indicates the first byte of valid cell data received. An external pull-down resistor is required for this pin. URxClAv UTOPIA Receive Cell Available P10 TTL 8 mA O Indicates FIFO empty or Cell Buffer Available, depending upon HandShake (bit 1) in the MODE register (0x0202). An external pull-down resistor is required for this pin. 28228-DSH-001-C 28228-DSH-001-C Mindspeed TechnologiesTM Mindspeed Proprietary and Confidential 1-24 1.0 Product Description Table 1-2. RS8228 RS8228 17 mm Pin Descriptions (9 of 10) Pin Label Supply Voltage 17 mm BGA PWR 28228-DSH-001-C 28228-DSH-001-C Signal Name Supply Voltage No. Type D10 E5 E9 E10 E11 F6 F7 F8 F11 G6 G11 G12 H6 H12 J5 J6 J12 K6 K12 L6 L12 L13 M5 M6 M7 M8 M9 M10 M11 M12 N5 N6 N12 - Driver I/O Strength - Description - Power supply connections. Mindspeed TechnologiesTM Mindspeed Proprietary and Confidential 1-25 M02063 M02063 Non-Conformance Table 1-2. RS8228 RS8228 17 mm Pin Descriptions (10 of 10) Pin Label Signal Name No. Type Driver I/O Strength Description Ground F9 F10 G7 G8 G9 G10 H7 H8 H9 H10 H11 J7 J8 J9 J10 J11 K7 K8 K9 K10 K11 L7 L8 L9 L10 L11 - - - Ground connections. VGG Electrostatic Discharge (ESD) Supply Voltage P3 - - - Provides ESD protection when interfacing with 5 V systems. If using this device in a system with 5 V logic, this pin must be connected to 5 V. If using 3.3 V system, leave this pin unconnected. Test 1 Manufacturing Test 1 C11 TTL - I Reserved, connect to ground. Test 2 Manufacturing Test 2 B11 TTL - I Reserved, connect to ground. Test 3 Manufacturing Test 3 A11 TTL - I Reserved, connect to ground. Testing Supply Voltage GND NOTE(S): All input and bi-directional pins have hysteresis. 28228-DSH-001-C 28228-DSH-001-C Mindspeed TechnologiesTM Mindspeed Proprietary and Confidential 1-26 1.0 Product Description 1.5 Block Diagram and Descriptions Figure 1-5 illustrates a detailed block diagram of the RS8228/M28228 RS8228/M28228 device. Traffic is transmitted from the ATM layer device via the UTOPIA bus, in either an 8- or 16-bit format. The ATM cells are then formatted for serial-line transmission by one of the RS8228 RS8228 transmit ports. In the receive direction, serial network data is packed into octets by the receive port and passed to the ATM cell receiver module. Octet data is then delineated into ATM cells, checked, and sent to the UTOPIA port. The UTOPIA interface communicates with the next layer of ATM processing. Figure 1-5. RS8228 RS8228 Block Diagram LCs[7:0] LInt~[7:0] LStatOut[3:0][7:0] MData[7:0] MAddr[12:0] Control Lines MInt~ Microprocessor Interface Interrupt Control UTOPIA Level 2 Interface Framer (Line) Interface Status and Control LTxClk LTxSync LTxData Line Transmitter LRxClk LRxSync Control ATM Cell Receiver Loopback LRxData 4-cell FIFO ATM Cell Transmitter Line Receiver LRxHold Cell Alignment Cell Validation VPI/VCI Screening 4-cell FIFO Host Interface Transmit UTOPIA Level 2 Host Interface Receive UTOPIA Level 2 UTxClk UTxClav UTxEnb~ UTxSOC UTxData[15:0] UTxPrty UTxAddr[4:0] URxClk URxClav URxEnb~ URxSOC URxData[15:0] URxPrty URxAddr[4:0] This segment is replicated for Ports 0 - 7 JTAG Controller TCK 28228-DSH-001-C 28228-DSH-001-C TMS TDO TRST~ TDI One Second Interface 8kHzIn OneSecOut OneSecIn Mindspeed TechnologiesTM Mindspeed Proprietary and Confidential 1-27 2 2.0 Functional Description This chapter describes the primary functions of the RS8228 RS8228, including the ATM cell processor, the UTOPIA interface, and the microprocessor interface. 2.1 ATM Cell Processor The RS8228 RS8228's ATM cell receiver block is responsible for recovering cell alignment using the HEC octet, performing detection/correction, and descrambling the payload octets. The resulting ATM cells are then passed to the ATM layer via the UTOPIA interface. Simultaneously, the ATM transmitter block is receiving data from the ATM layer, optionally inserting header fields, optionally calculating the HEC, and sending the cells to the framers. If no data is being received from the ATM layer, the cell processor generates idle cells based on the data programmed into the associated registers. The RS8228 RS8228 has all counters needed for capturing ATM error events and performs payload CRC calculations as required by the AAL formats. It generates cell status events, cell counts, and error counts. 2.1.1 ATM Cell Transmitter The ATM cell transmitter controls the generation and formatting of 53-octet ATM cells that are sent to the Framer (Line) Transmit Ports. This block formats an octet stream containing ATM data cells from the ATM layer device when those cells are available. All 53 octets of the data cells may be obtained from the external data source and formatted into the outgoing octet stream. This block calculates the HEC octet in the outgoing cell from the header field. The calculated HEC octet can be inserted in place of the incoming data octet by writing DisHEC (bit 7) in the CGEN register (0x08) to a logic 0. For testing purposes, this HEC octet can be corrupted by XORing the calculated value with a specific error pattern input set in the ERRPAT register (0x0B). This HEC error is achieved by writing ErrHEC (bit 4) in the CGEN register (0x08) to a logic 1. The remaining 48-octet payload field of the outgoing cell is obtained from the external data source. The payload can be scrambled. When there is no data from the ATM layer device, the RS8228 RS8228 inserts idle cells automatically in the outgoing octet stream. The 4-octet header field for these idle cells comes from the TXIDL1­4 registers (0x14­17). The HEC octet is calculated and inserted automatically. The payload field is filled with the octet contained in the IDLPAY register (0x0A). In normal operation, the 4-octet header field in the outgoing cell is passed on from the ATM layer device. Header patterns can be modified in the TXHDR1­4 registers (0x10­13) and inserted into outgoing cells in place of header bytes received from the ATM layer. Whether the original header cells or replacement cells are sent is controlled by bits 0­4 in the HDRFIELD (0x09) register. 28228-DSH-001-C 28228-DSH-001-C Mindspeed TechnologiesTM Mindspeed Proprietary and Confidential 2-1 2.0 Functional Description 2.1.1.1 HEC Generation In normal operation, the RS8228 RS8228 calculates the HEC for the four header bytes of each cell coming from the ATM layer. It then adds the HEC coset (55 hex, by ATM standards) and inserts the result in octet 5 of the outgoing cell. HEC calculation can be disabled by setting bit 7 of CGEN (0x08) to a 1. When HEC is disabled, the RS8228 RS8228 leaves the contents of the HEC field unchanged and transmits whatever data is placed in that field by the ATM layer. The HEC coset is used to maintain a value other than zero in the HEC field. If the first four bytes in the header are zero, the HEC derived from these bytes is also zero. When this occurs and there are strings of zeros in the data, the receiver cannot determine cell boundaries. Therefore, it is recommended that the value 55 hex be added to the HEC before transmission. To enable the HEC coset on the transmit side, set bit 6 in register CGEN (0x08) to one. To enable the receive HEC coset, set bit 5 in register CVAL (0x0C) to one. 2.1.2 ATM Cell Receiver The ATM cell receiver performs cell delineation on incoming data cells by searching for the position of a valid HEC field within the cell. The HEC coset can be either active or inactive; this is determined in bit 5 in the CVAL (0x0C) register. 2.0.0.1 Cell Delineation The ATM block receives octets from the framers and recovers ATM cells by means of cell delineation. Cell delineation is achieved by aligning ATM cell boundaries using the HEC algorithm. Four consecutive bytes are chosen and the HEC value is calculated. The result is compared with the value of the following byte. This "hunt" is continued by shifting this four-byte window, one byte at a time, until the calculated HEC value equals the received HEC value. When this occurs, a pre-sync state is declared and the next 48 bytes are assumed to be payload. The ATM block calculates HEC on the four bytes following this payload, assuming that a new cell has begun. If seven consecutive header blocks are found, synchronization is declared. If any HEC calculation fails in the pre-sync state, the process begins again (see Figure 2-1). Synchronization will be held until seven consecutive incorrect HECs are received. At this time, the "hunt" state is reinitiated. Figure 2-1. Cell Delineation Process 1 Correct HEC Pre-Sync Hunt 1 Errored HEC 6 Correct HECs Sync 7 Errored HECs 28228-DSH-001-C 28228-DSH-001-C Mindspeed TechnologiesTM Mindspeed Proprietary and Confidential 2-2 M02063 M02063 Non-Conformance During the sync state of cell delineation, cells are passed to the UTOPIA interface if the HEC is valid. If a single-bit error in the header is detected, the error is corrected (optionally), and the cell is passed to the UTOPIA interface. If HEC checking is enabled and HEC correcting is disabled (bit 3 in the CVAL register [0x0C]), cells with single-bit HEC errors are discarded. If a multi-bit error is detected, the cell is dropped. Once either type of error is noted, all subsequent errored cells are dropped until a valid cell is received. This rule applies even for single-bit errors that could be corrected. Once a valid cell is detected, the process begins again. (See Figure 2-2.) When LOCD occurs, an interrupt is generated and the RS8228 RS8228 automatically enters the "hunt" mode. However, the cell is still being scrambled by the far-end transmitter, leaving only the headers (or just the HEC byte in Distributed Sample Scrambler [DSS]) unscrambled. This means that the only repetitive byte patterns in the data stream that meet the cell delineation criteria are valid headers (or just the HEC bytes in DSS). Figure 2-2. Header Error Check Process Cell Delineation in Sync State Errors Detected (Drop Cell) No Errors Detected (Pass Cell) Detection Mode Apparent Single-bit Error (Correct Error and Pass Cell) No Errors Detected (Pass Cell) Correction Mode Apparent Multi-bit Error (Drop Cell) When the RS8228 RS8228 is in general purpose mode, a synchronization pulse from the framer interface is not always available. In this mode, the RS8228 RS8228 performs a bit serial search to find byte and cell alignment. The RS8228 RS8228 selects a starting window of 32 sequential bits and calculates the HEC over this window. This HEC is then compared to the next eight incoming bits. If they do not match, the RS8228 RS8228 shifts the 32-bit window by 1 bit and recalculates the HEC until a valid HEC position is found. Once byte-alignment is achieved, cell delineation is performed. 2.0.0.2 Cell Screening The RS8228 RS8228 provides two optional types of cell screening. The first type, idle cell rejection, prevents idle cells from being passed on. The second type, user traffic screening, compares incoming bits to the values in the receive cell header registers. Cells are rejected or accepted based on the bit patterns of their headers. Idle cell rejection is enabled in bit 6 of the CVAL register (0x0C). If this bit is set to 1, all incoming cells that match the contents of the Receive Idle Cell Header Control Registers, RXIDL1­4 (0x20­23), are rejected. Individual bits in the Receive Idle Cell Mask Control Registers, IDLMSK1­4 (0x24­27), can be set to 1 or Don't Care, causing the corresponding bits of the incoming cell to be treated as matching, regardless of their value. If idle cell rejection is disabled, cells pass directly to user traffic screening. 28228-DSH-001-C 28228-DSH-001-C Mindspeed TechnologiesTM Mindspeed Proprietary and Confidential 2-3 2.0 Functional Description User traffic cell screening is similar to idle cell screening in that the incoming cells are compared to the Receive Cell Header Control Registers, RXHDR1­4 (0x18­1B). Individual bits in the Receive Cell Mask Control Registers, RXMSK1­4 (0x1C­1F), can be set to 1 or Don't Care, causing the corresponding bits of the incoming cell to be treated as matching, regardless of their values. The RejHdr bit (bit 7) in the CVAL register (0x0C) determines whether matching cells are rejected or accepted. If it is set to 0, matching cells are accepted. If it is set to 1, matching cells are rejected. See Table 2-1 and Table 2-2. Table 2-1. Cell Screening-Matching Receive Cell Mask Bit Receive Cell Header Bit Incoming Bit 0 0 0 Match 0 0 1 Fail 0 1 0 Fail 0 1 1 Match 1 x x Match Table 2-2. Result Cell Screening-Accept/Reject Cell Cell Reject Header Match 0 Accept Cell Match 1 Reje