RS5C313 EA-034-9803 RS5C314 RS5C313-E1 RS5C313-E2 - Datasheet Archive

 

REAL-TIME-CLOCK RS5C313 APPLICATION MANUAL ELECTRONIC DEVICES DIVISION NO.EA-034-9803 NOTICE 1. The products and the product

 

ULTRA-COMPACT REAL-TIME-CLOCK RS5C313 RS5C313 APPLICATION MANUAL ELECTRONIC DEVICES DIVISION NO.EA-034-9803 EA-034-9803 NOTICE 1. The products and the product specifications described in this application manual are subject to change or discontinuation of production without notice for reasons such as improvement. Therefore, before deciding to use the products, please refer to Ricoh sales representatives for the latest information thereon. 2. This application manual may not be copied or otherwise reproduced in whole or in part without prior written consent of Ricoh. 3. Please be sure to take any necessary formalities under relevant laws or regulations before exporting or otherwise taking out of your country the products or the technical information described herein. 4. The technical information described in this application manual shows typical characteristics of and example application circuits for the products. The release of such information is not to be construed as a warranty of or a grant of license under Ricoh's or any third party's intellectual property rights or any other rights. 5. The products listed in this application manual are intended and designed for use as general electronic components in standard applications (office equipment, computer equipment, measuring instruments, consumer electronic products, amusement equipment etc.). Those customers intending to use a product in an application requiring extreme quality and reliability, for example, in a highly specific application where the failure or misoperation of the product could result in human injury or death (aircraft, spacevehicle, nuclear reactor control system, traffic control system, automotive and transportation equipment, combustion equipment, safety devices, life support system etc.) should first contact us. 6. We are making our continuous effort to improve the quality and reliability of our products, but semiconductor products are likely to fail with certain probability. In order prevent any injury to persons or damages to property resulting from such failure, customers should be careful enough to incorporate safety measures in their design, such as redundancy feature, fire-containment feature and fail-safe feature. We do not assume any liability or responsibility for any loss or damage arising from misuse or inappropriate use of the products. 7. Anti-radiation design is not implemented in the products described in this application manual. 8. Please contact Ricoh sales representatives should you have any questions or comments concerning the products or the technical information. June 1995 RS5C313 RS5C313 APPLICATION MANUAL CONTENTS Outline.1 Features .1 Block Diagrams .2 Applications .2 Pin Configuration.2 PIN DESCRIPTIONS .3 ABSOLUTE MAXIMUM RATINGS .4 RECOMMENDED OPERATING CONDITIONS .5 DC CHARACTERISTICS .5 AC CHARACTERISTICS .6 TIMING CHART .6 FUNCTIONAL DESCRIPTION.7 1) Addressing .7 2) Registers .8 3) Counters .12 OPERATION .14 1) Read Data .14 2) Write Data .15 3) CE Pin .16 4) Configuration of Oscillating Circuit .17 5) Oscillator Halt Sensing .18 6) Typical Power Supply Circuit .18 7) Oscillation Frequency Adjustment .19 8) Interrupt Operation .20 9) Typical Application .21 10) Typical Characteristic Measurements .22 11) Typical Software-based Operations .24 PACKAGE DIMENSIONS .28 PACKAGE SPECIFICATIONS .28 ULTRA-COMPACT REAL-TIME-CLOCK RS5C313 RS5C313 OUTLINE The RS5C313 RS5C313 is a CMOS type real-time clock which is connected to the CPU via three signal lines and capable of serial transmission of clock and calendar data to the CPU. The RS5C313 RS5C313 can generate various interrupt clock pulses lasting for long periods (one month). Driving an oscillation circuit at constant voltage, the circuit undergoes few voltage fluctuations and consequently realizes low current consumption (TYP. 0.7 µA at 3 V). It also provides an oscillator halt sensing function for application to data validity at power-on and other occasions. Integrated into an ultra-compact and ultra-thin 8pin SSOP (0.65mm pitch), the RS5C313 RS5C313 is the optimum choice for equipment requiring small size and low power consumption. There is RS5C314 RS5C314 reversing the logic of serial clock for series goods. FEATURES · Time Keeping Supply Voltage: 1.6 to 6.0 V · Operating Supply Voltage: 2.7 to 6.0 V · Low Current Consumption: TYP. 0.7µA (MAX. of 1.5µA) at 3V · Connection to the CPU via only three pins: CE, SCLK, and SIO (for addressing and data read and write operations) · A clock counter (counting hours, minutes, and seconds) and a calendar counter (counting leap years, years, months, days, and days of the week) in binary-coded decimal (BCD) code · Generation of interrupt pulses to the CPU with cycles ranging from 1 month to 1/1024 Hz, interrupt flags, and interrupt halt · Software-based alarming through clock-interlocked interrupt operation · Oscillator halt sensing to judge internal data validity · Second digit adjustment by ±30 seconds · 12-hour or 24-hour time display selectable · Automatic leap year recognition up to the year 2099 · CMOS logic · Package: 8pin SSOP (0.65mm pitch) 1 RS5C313 RS5C313 BLOCK DIAGRAMS OSCIN OSCOUT OSC SEC. DIV MIN. HOUR WEEK DAY MONTH YEAR TIME COUNTER OSC DETECT VDD SCLK VOLTAGE REGULATOR ADDRESS DECODER ADDRESS REGISTER VSS INTR SIO I/O CONTROL INTERRUPT CONTROL CE SHIFT REGISTER APPLICATIONS · Communication equipment (Multi-function telephone, portable telephone, PHS, Pager) · Office automation (Facsimile, portable facsimile) · Personal computer (Desk top type, notebook type, word proccesor, PDA, electronic notebook, TV games) · Audio visual equipment (Portable audio equipment, video camera, camera, digital camera, remote control equipment) · Home use (Rice cooker, microwave range) PIN CONFIGURATION · 8pin SSOP (0.65mm pitch) CE 8 VDD 2 7 OSCIN SIO 3 6 OSCOUT VSS 2 1 SCLK 4 5 INTR RS5C313 RS5C313 PIN DESCRIPTIONS Pin No. Symbol 1 CE Name Chip enable input Description The CE pin is used to interface with the CPU and is accessible when held at the high level. This pin incorporates a pull-down resistor. It should be switched to the low level or opened when not accessed or when powering off the system. Holding the CE pin at the high level for more than 2.5 seconds forces 1Hz interrupt pulses to be output from the INTR pin for oscillation frequency measurement . (No pulse is output for less than 1.5 seconds.) 2 SCLK Shift clock input The SCLK pin is used to input shift clock pulses to synchronize data input to, and output from, the SIO pin. 3 SIO Serial input The SIO pin inputs and outputs written or read data in synchronization with and out- and output put shift clock pulses from the SCLK pin. The SIO pin causes high impedance when the CE pin is held at the low level. After the CE pin is switched to the high level and the control bits and the address bits are input from the SIO, the SIO pin performs serial input and output operations 5 INTR Interrupt output The INTR pin outputs cyclic interrupt pulses to the CPU. This pin functions as an Nch open drain output even when the CE pin is held at the low level. 7 OSCIN Oscillation circuit These pins configure an oscillation circuit by connecting a 32.768 kHz crystal 6 OSCOUT input and output oscillator between the OSCIN and OSCOUT pins and by connecting a capacitor between the OSCIN and VSS pins. (Any other oscillation circuit components are built into the RS5C313 RS5C313.) 8 VDD Positive power supply input 4 VSS The VDD pin is connected to a power supply and the VSS pin is connected to the Negative power ground. supply input 3 RS5C313 RS5C313 ABSOLUTE MAXIMUM RATINGS Symbol VDD VI Item (VSS=0V) Conditions V ­0.3 to +VDD+0.3 Input voltage Unit ­0.3 to +7.0 Supply voltage Ratings V VO1 Output voltage1 SIO ­0.3 to +VDD+0.3 V VO2 Output voltage2 INTR ­0.3 to +12 V PD Maximum power consumption Topt=25°C 300 mW Topt Ambient operating temperature ­30 to +80 °C Tstg Storage temperature ­40 to +125 °C ABSOLUTE MAXIMUM RATINGS Absolute Maximum ratings are threshold limit values that must not be exceeded even for an instant under any conditions. Moreover, such values for any two items must not be reached simultaneously. Operation above these absolute maximum ratings may cause degradation or permanent damage to the device. These are stress ratings only and do not necessarily imply functional operation below these limits. 4 RS5C313 RS5C313 RECOMMENDED OPERATING CONDITIONS (VSS=0V, Topt=­30 to +80°C) Symbol Item Conditions MIN. TYP. MAX. Unit 5.0 6.0 V 6.0 V VDD Operating supply voltage 2.7 VCLK Time Keeping supply voltage 1.6 fXT Oscillation frequency CG External oscillator capacitance VPUP 32.768 CL value of crystal=6 to 8pF Applied voltage at OFF 5 10 kHz pF 10 INTR 24 V DC CHARACTERISTICS Unless otherwise specified:VSS=0V, VDD=5V±10%, Topt=­30 to +80°C, oscillation frequency=32.768kHz (CL=6pF, R1=30k½), CG=10pF Symbol Item Pin name Conditions MIN. TYP. MAX. Unit VIH "H" input voltage CE, SCLK, SIO 0.8VDD VDD V VIL "L" input voltage CE, SCLK, SIO 0 0.2VDD V IOH "H" output current SIO VOH=VDD­0.5V ­1 mA SIO VOL1=0.5V 1 INTR VOL2=0.4V 2 IOL 1 "L" output current IOL 2 RDN Pull-down resistance CE 45 IILK Input leakage current SCLK VI =VDD or V SS IOZ 1 Output off-state SIO IOZ 2 leakage current INTR IDD1 Power consumption 1 VDD mA 130 450 k½ ­1 1 µA VO=VDD or V SS ­2 2 VO=10V ­5 5 µA VDD=3V 0.7 1.5 µA 2 µA I/O=OPEN IDD2 Power consumption 2 VDD VDD=5.5V I/O=OPEN CD Internal oscillator capacitance OSCOUT 10 pF 5 RS5C313 RS5C313 AC CHARACTERISTICS (VSS=0V, Topt=­30 to +80°C, CL=50pF) VDD=5V±10% Symbol VDD=3V±10% MIN. Item MIN. MAX. MAX. VDD=5V±20% MIN. MAX. Unit tCES CE set-up time 175 300 200 ns tCEH CE hold time 175 300 200 ns tCR CE recovery time 350 600 400 ns tSCK SCLK clock cycle 350 600 400 ns tCKH SCLK "H" clock time 175 300 200 ns tCKL SCLK "L" clock time 175 300 200 ns tCKS SCLK clock set-up time 60 100 80 ns tRE Data output start time (from tRR Data output delay time (from tRZ Output floating time tDS Input data set-up time 50 80 60 ns tDH Input data hold time 50 50 50 ns of SCLK) 120 135 ns 120 200 135 ns 120 of SCLK) 200 200 135 ns TIMING CHART tCES CE tCKS tCEH tSCK SCLK tCKH tCKL tRE Read cycle Read Data SIO tDS Write cycle Write Data SIO Input/output conditions VIH = 0.8 ´ VDD VIL = 0.2 ´ VDD VOH = 0.8 ´ VDD VOL = 0.2 ´ VDD *) The ability that is fair in "H" or 6 tDH "L" slanted line department tRR tRZ tCR RS5C313 RS5C313 FUNCTIONAL DESCRIPTION 1. Addressing Address Description Data*1 D3 D2 D1 D0 1-second counter S8 S4 S2 S1 1 10-second counter -*2 S40 S20 S10 1 0 1-minute counter M8 M4 M2 M1 0 1 1 10-minute counter - M40 M20 M10 0 1 0 0 1-hour counter H8 H4 H2 H1 5 0 1 0 1 10-hour counter - - P/A or H20 H10 6 0 1 1 0 Day-of-the-week counter - W4 W2 W1 7 0 1 1 1 Interrupt cycle register CT3 CT2 CT1 CT0 8 1 0 0 0 1-day counter D8 D4 D2 D1 9 1 0 0 1 10-day counter - - D20 D10 A 1 0 1 0 1-month counter MO 8 MO4 MO2 MO1 B 1 0 1 1 10-month counter - - - MO10 C 1 1 0 0 1-year counter Y8 Y4 Y2 Y1 D 1 1 0 1 10-year counter Y80 Y40 Y20 Y10 E 1 1 1 0 Control register CTFG 12/24 WTEN/XSTP*3 ADJ/BSY*4 F 1 1 1 1 Test register - - - TEST A3 A2 A1 A0 0 0 0 0 0 1 0 0 0 2 0 0 3 0 4 *1) *2) *3) *4) All the listed data can be read and written . The "-" mark indicates data which can be read only and set to "0" when read . The WTEN/XSTP bit of the control register is set to WTEN for write operation and XSTP for read operation. The ADJ/BSY bit of the control register is set to ADJ for write operation and BSY for read operation. 7 RS5C313 RS5C313 2. Register 2.1 Control Register (at Eh) D3 D2 D1 D0 CTFG 12/24 WTEN ADJ (For write operation) CTFG 12/24 XSTP BSY (For read operation) ±30-second Adjustment Bit ADJ Description 0 Ordinary operation 1 Second digit adjustment Clock/Calendar Counter Busy-state Indication Bit BSY Description 0 Ordinary operation 1 Second digit carry or adjustment Clock Counter Enable/Disable Setting Bit WTEN Description 0 Disabling of 1-second digit carry for clock counter 1 Enabling of 1-second digit carry for clock counter Oscillator Halt Sensing Bit XSTP Description 0 Ordinary oscillation 1 Oscillator halt sensing 12/24-hour Time Display System Selection Bit 12/24 Description 0 12-hour time display system (separate for mornings and afternoons) 1 24-hour time display system Interrupt Flag Bit CTFG Description 0 INTR=H(Nch Open Drain). Enabling of write operation when the CT3 bit is set to 1. 1 INTR=L (Nch Open Drain). Enabling of write operation when the CT3 bit is set to 1. 2.1-1 (ADJ) When the ADJ bit is set to 1: (If the WTEN bit is 0, adjustment of second digits is started after the WTEN bit is set to 1.) 1) For second digits ranging from 00 to 29 seconds: Time counts smaller than seconds are reset to set second digits to "00". 2) For second digits ranging from 30 to 59 seconds: Time counts smaller than seconds are reset to set second digits to "00" and increment minute digits by 1. After the ADJ bit is set to 1, the BSY bit is set to 1 for the maximum duration of 122.1µs. 8 RS5C313 RS5C313 2.1-2 (BSY) When the BSY bit is 1, the clock and calendar counters are being updated. Consequently, write operation should be performed for the counters when the BSY bit is 0. Meanwhile, read operation is normally performed for the counters when the BSY bit is 0, but can be performed without checking the BSY bit as long as appropriate software is provided for preventing read errors(Refer to the item 11.3 Read Operation from Clock and Calendar Counters). The BSY bit is set to 1 in the following three cases: (1) Adjustment of second digits by ±30 seconds MAX. 122.1µs Setting of the ADJ bit to 1 (2) Second digit increment by 1 (Subject to 1-second digit carry when the WTEN bit is switched from 0 to 1) (3) Ordinary 1-second digit carry Completion of second digit adjustment MAX.91.6µs Setting of the WTEN bit to 1 End of second digit increment by 1 91.6µs End of second digit carry pulse 2.1-3 (WTEN) The WTEN bit should be set to 0 to check that the BSY bit is 0 when performing read and write operations for the clock and calendar counters. For read operation, the WTEN bit may be left as 1 without checking the BSY bit as long as appropriate measures such as read repetition are provided for preventing read errors(Refer to the item 11.3 Read Operation from Clock and Calendar Counters). The WTEN bit should be set to 1 after completing read and write operations, or will automatically be set to 1 by switching the CE pin to the low level. If 1-second digit carry occurs when the WTEN bit is 0, a second digit increment by 1 occurs when the WTEN bit is set to 1. Note If the WTEN bit is 0 for 1/1024 second and more, second digit increment by 1 may not occur. (Refer to the item 11.3 Read Operation from Clock and Calendar Counters). 2.1-4 (XSTP) The XSTP bit senses the ocilllator halt. When the CE pin is held at the low level, the XSTP bit is set to 1 once the crystal oscillator is stopped after initial power-on or supply voltage drop and left to be 1 after it is restarted. When the CE pin is held at the high level, the XSTP bit is left as it was when the CE pin was held at the low level without checking oscillation stop. As such, the XSTP bit can be used to validate clock and calendar count data after power-on or supply voltage drop. The XSTP bit is set to 0 when write operation is performed for the control register (at Eh) (during normal oscillation). 2.1-5 (12/24) The 12/24 bit specifies time digit display in BCD code. 24-hour time display system 12-hour time display system 24-hour time display system 12-hour time display system 00 01 02 03 04 05 06 07 08 09 10 11 12(AM12) 01(AM 1) 02(AM 2) 03(AM 3) 04(AM 4) 05(AM 5) 06(AM 6) 07(AM 7) 08(AM 8) 09(AM 9) 10(AM10) 11(AM11) 12 13 14 15 16 17 18 19 20 21 22 23 32(PM12) 21(PM 1) 22(PM 2) 23(PM 3) 24(PM 4) 25(PM 5) 26(PM 6) 27(PM 7) 28(PM 8) 29(PM 9) 30(PM10) 31(PM11) Either the 12-hour or 24-hour time display system should be selected before time setting (e.g. during initialization after power-on). 9 RS5C313 RS5C313 2.1-6 (CTFG) The CTFG bit is set to 1 when interrupt pulses are output from the INTR pin held at the low level. There are two interrupt modes selectable: the pulse mode (when the CT3 bit is set to 0) and the level mode (when the CT3 bit is set to 1). The CTFG bit can be set only when the CT3 is set to 1. Setting the CTFG bit to 1 switches the INTR pin to the low level while setting the CTFG bit to 0 turns off the INTR pin. Interrupt cycle register Remarks CT0 0 0 OFF Interrupt disabling 0 1 ON Fixing INTR pin at low level 1 0 0.977ms Cycle: 0.977 ms (1/1024 Hz), Duty: 50% *2 0 *1 * * * 1 1 0.5s Cycle: 0.5 s (1/2 Hz)*3 1 0 0 0 1 second Every second*4 1 0 0 1 10 seconds Every 10 seconds (For display of second digits: 00, 10, 20, 30, 40, and 50)*4 1 0 1 0 1 minute Every minute (00 second)*4 1 0 1 1 10 minutes Every 10 minutes (00 second) (For display of minute digits: 00, 10, 20, 30, 40, and 50)*4 1 1 0 0 1 hour Every hour (00 minute and 00 second)*4 1 1 0 1 1 day Every day (0 hour, 00 minute, and 00 second a.m.)*4 1 1 1 0 1 week Every week (0 week, 0 hour, 00 minute, and 00 second a.m.)*4 1 1 1 1 1 month Every month (1st day, 0 hour, 00 minute, and 00 second a.m.)*4 0 0 0 *1) *2) CT2 Outputs from CT1 CT3 INTR pin The symbol " " in the above table indicates 0 or 1. * 0.977ms CTFG INTR *3) 0.5s CTFG INTR 0.488ms 4) * CTFG INTR Interrupt (Second count-up) 10 Setting CTFG bit to 0 Interrupt (Second count-up) RS5C313 RS5C313 2.2 Interrupt Cycle Register (at 7h) D3 D2 D1 D0 CT3 CT2 CT1 CT0 (For write operation) CT3 CT2 CT1 CT0 (For read operation) Bits for selecting the interrupt cycle and output mode at the INTR pin*1 *1) (CT3 to CT0) The CT3 to CT0 bits are used to select the interrupt cycle and output mode at the INTR pin. There are two interrupt modes selectable: the pulse mode (when the CT3 bit is set to 0) and the level mode (when the CT3 bit is set to 1). The interrupt cycle and output mode at the INTR pin are shown in detail in the section on the CTFG bit in "2.1 Control Register (at Eh)". 2.3 Test Register (at Fh) D3 D2 D1 D0 * * * TEST (For write operation) 0 0 0 0 (For read operation)*1 Bit For Testing*2 TEST Description 0 1 *1) *2) Testing mode Ordinary operating mode The TEST bit is write-only and set to 0 when read. The TEST bit should be fixed at 1 for ordinary operation and will automatically be set to 1 when the CE pin is at the low level. 11 RS5C313 RS5C313 3. Counters 3.1 Clock Counter (at 0h to 5h) D3 D2 D1 D0 S8 S4 S2 S1 ( read and write cycle) 1-second time digit (at 0h) * S40 S20 S10 (read and write cycle) 10-second time digit (at 1h) M8 M4 M2 M1 (read and write cycle) 1-minute time digit (at 2h) * M40 M20 M10 (read and write cycle) 10-minute time digit (at 3h) H8 H4 H2 H1 (read and write cycle) 1-hour time digit (at 4h) * * P/A or H20 H10 (read and write cycle) 10-hour time digit (at 5h) 1) The " " mark in the above table indicates data which are set to 0 for read cycle and not set for write cycle. * 2) Any carry to 1-second digits from the second counter is disabled when the WTEN bit (of the control register) is set to 0. 3) Time digit display ( BCD code): Second digits: Range from 00 to 59 and carried to minute digits when incremented from 59 to 00. Minute digits: Range from 00 to 59 and carried to hour digits when incremented from 59 to 00. Hour digits: Range as shown in the section on the 12/24 bit and carried to day and day-of-the-week. digits when incremented from 11 p.m. to 12 a.m. or 23 to 00. 4) Any registered imaginary time should be replaced with actual time as carrying to such registered imaginary time digits from lower-order ones cause the clock counter to malfunction. 3.2 Day-of-the-week Counter (at 6h) D3 D2 D1 D0 * W4 W2 W1 ( read and write cycle) Day-of-the-week counter 1) The " " mark in the above table indicates data which are set to 0 for read cycle and not set for write cycle. * 2) Day-of-the-week digits are incremented by 1 when carried to 1-day digits. 3) Day-of-the-week digit display (incremented in septimal notation): (W4W2W1)=(000)® (001)® - - - - - - ® (110) ® (000) The relation between days of the week and day-of-the-week digits is user changeable (e.g. Sunday=000). 4) The (W4W2W1) should not be set to (111). 12 RS5C313 RS5C313 3.3 Calendar Counter (at 8h to Dh) D3 D2 D1 D0 D8 D4 D2 D1 (read and write cycle) 1-day calendar digit (at 8h) * * D20 D10 (read and write cycle) 10-day calendar digit (at 9h) MO8 MO4 MO2 MO1 (read and write cycle) 1-month calendar digit (at Ah) * * * MO10 (read and write cycle) 10-month calendar digit (at Bh) Y8 Y4 Y2 Y1 (read and write cycle) 1-year calendar digit (at Ch) Y80 Y40 Y20 Y10 (read and write cycle) 10-year calendar digit (at Dh) 1) The " " mark in the above table indicates data which are set to 0 for read cycle and not set for write cycle. * 2) The automatic calendar function provides the following calendar digit displays in BCD code: Day digits: Range from 1 to 31 (for January, March, May, July, August, October, and December). Range from 1 to 30 (for April, June, September, and November). Range from 1 to 29 (for February in leap years). Range from 1 to 28 (for February in ordinary years). Carried to month digits when cycled to 1. Month digits: Range from 1 to 12 and carried to year digits when cycled to 1. Year digits: Range from 00 to 99 and counted as 00, 04, 08, - - - - -, 92, and 96 in leap years. 3) Any registered imaginary time should be replaced with actual time as carrying to such registered imaginary time digits from lower-order ones cause the clock counter to malfunction. 13 RS5C313 RS5C313 OPERATION 1. Read Data The real-time clock becomes accessible by switching the CE pin from the low level to high level to enable interfacing with the CPU and then inputting setting data (control bits and address bits) to the SIO pin in synchronization with shift clock pulses from the SCLK pin. The input data are registered in synchronization with the falling edge of the SCLK. When the data is read, the read cycle shall be set by control bits. · Control bits R/W: Establishes the read mode when set to 1, and the write mode when set to 0. AD: Writes succeeding address bits (A3 to A0) to the address register when set to 1 with the DT bit set to 0 and performs no such write operation in any other case. DT: Writes data bits (D3 to D0) to the counter or register specified by the address register which has written just before when set to 1 with the R/W and AD bits set equally to 0 and performs no such write operation in any other case. A3 to A0: Inputs the bits MSB to LSB in the address table describing the functions. · Address bits 1.1 Read Cycle Flow 1. The CE pin is switched from the low level to the high level. 2. Four control bits (with the first bit ignored) and four read address bits are input from the SIO pin. At this time, control bits R/W and AD are set equally to 1 while a control bit DT is set to 0. 3. The SIO pin enters the output mode at the rising edge of the shift clock pulse 2B from the SCLK pin while the four read bits (MSB®LSB) at designated addresses are output at the rising edge of the shift clock pulse 5B (see the figure below). 4. Then, the SIO pin returns to the input mode at the rising edge of the shift clock pulse 1C. Afterwards control bits and address bits are input at the shift clock pulses 1C in the same manner as at the shift clock pulse 1A. 5. At the end of read cycle, the CE pin is switched from the high level to the low level (after tCEH from the falling edge of the eighth shift clock pulse from the SCLK pin). (Following on read cycle, write operation can be performed by setting control bits in the write mode at the shift clock pulse 1C and later with the CE pin held at the high level.) CE 1A 2A 3A 4A 5A 6A 7A 8A 1B 2B 3B 4B 5B 6B 7B 8B 1C 2C 3C SCLK Setting of Shifting data SIO pin in output mode Reading to shift register Input to SIO pin * * R/W AD DT Control bits A3 A2 A1 Setting of SIO pin in input mode (Hi-z) A0 R/W AD Address bits Output from SIO pin - - - D3 D2 D1 (Hi-z) (Internal processing) *) 14 D0 (Hi-z) Read data Setting of control bits Writing to address register In the above figure, the " "mark indicates arbitrary data; the "-" mark indicates unknown data; * the " " mark indicates data which are available when the SIO pin is held at the high, low, or Hiz level ; and the diagonaliy shaded area indicates high or low. RS5C313 RS5C313 2. Write Data Writing data to the real-time clock requires inputting setting data (control bits and address bits) to the SIO pin and then establishing the write mode by using a control bit R/W in the same manner as in read operation. *) Control bits and address bits are described in the previous section on read cycle. · Data bits D3 to D0 : inputs writing data to the counter or the register describing the functions in order of MSB to LSB. 2.1 Write Cycle Flow 1. The CE pin is switched from the low level to the high level. 2. Four control bits (with the first bit ignored) and four write address bits are input from the SIO pin. At this time, control bits R/W and DT are set equally to 0 while a control bit AD is set to 1 (at the shift clock pulses 1A to 8A from the SCLK pin). 3. Four control bits and four bits of data to be written are input in the descending order of their significance. At this time, control bits R/W and AD are set equally to 0 while a control bit DT is set to 1 (at the shift clock pulses 1B to 8B from the SCLK pin). 4. When write cycle is continued, control bits and address bits are input at the shift clock pulse 1C and later in the same manner as at the shift clock pulse 1A. 5. At the end of write operation, control bits R/W, AD, and DT are set equally to 0 (at the falling edge of the fifth shift clock pulse and later from the SCLK pin) or the CE pin is switched from the high level to the low level (after tCEH from the falling edge of the eighth shift clock pulse from the SCLK pin). CE 1A 2A 3A 4A 5A 6A 7A 8A 1B 2B 3B 4B 5B 6B 7B 8B 1C 2C 3C SCLK Reading from shift register Input to SIO pin * * R/W AD DT Control bits Output from SIO pin A2 A1 A0 Address bits * R/W AD DT Control bits D3 D2 D1 D0 * R/W AD Data bits (Hi-z) (Hi-z) (Internal processing) *) A3 Setting of control bits Writing to address register Setting of control bits End of write operation In the above figure, the " " mark indicates arbitrary data; and the diagonally shaded area indicates the high or low level. * 15 RS5C313 RS5C313 3. CE Pin SCLK SIO Shift clock pulses Address & Write data Read data CE Reading control bits Control bits 1) Switching the CE pin to the high level enables both the SCLK and SIO pins, allowing data to be serially read from and written to the SIO pin in synchronization with shift clock pulses input from the SCLK pin. 2) Switching the CE pin to the low level or opening it disables both the SCLK and SIO pins, causing high impedance and resetting the internal interfacing circuits such as the shift register. 3) The CE pin should be held at the low level or open state when no access is made to the RS5C313 RS5C313. The CE pin incorporates a pull-down resistor. 4) During system power-down (being back-up battery powered), the low-level input of the CE pin should be brought as close as possible to the VSS level to minimize the loss of charge in the battery. 5) Holding the CE pin at the high level for more than 2.5 seconds mainly forces 1Hz interrupt pulses to be output from the INTR pin for oscillation frequency measurement. When the CE pin is held at the high level for less than 1.5 seconds, no pulse is output. 6) The CE pin should be held at the low level in order to enable oscillator halt sensing. Holding the CE pin at the high level, therefore, disables oscillator halt sensing, retaining the value of the XSTP (oscillator halt sensing) bit which exists immediately before the CE pin is switched to the high level. Considerations When the power turns on from 0V, the CE pin should be set low or open once. 16 RS5C313 RS5C313 4. Configuration of Oscillating Circuit VDD VDD 8 7 CG OSCIN 32kHz RF RD 6 OSCOUT CD A VSS Typical external device: X'tal : 32.768kHz (R1=30k½) (CL=6pF to 8pF) CG=8pF to 20pF Standard values of internal devices: RF=15M½ (TYP.) RD=60k½ (TYP.) CD=10pF (TYP.) The oscillation circuit is driven at a constant voltage of about 1.5 V relative to the VSS level. Consequently, it generates a waveform having a peak-to-peak amplitude of about 1.5 V on the positive side of the VSS level. Considerations in Mounting Components Surrounding Oscillating Circuit 1) Mount the crystal oscillators and CG in the closest possible position to the IC. 2) Avoid laying any signal or power line close to the oscillation circuit (particularly in the area marked with "¬A ®" in the above figure). 3) Apply the highest possible insulation resistance between the OSCIN or OSCOUT pin and the PCB. 4) Avoid using any long parallel line to wire the OSCIN or OSCOUT pin. 5) Take extreme care not to cause condensation, which leads to various problems such as oscillation halt. Other Relevant Considerations 1) When applying an external input of clock pulses (32.768 kHz) to the OSCIN pin: DC coupling - - - - - Prohibited due to mismatching input levels. AC coupling - - - - - Permissible except that unpredictable results may occur in oscillator halt sensing due to possible sensing errors caused by noises, etc. 2) Avoid using the oscillator output of the RS5C313 RS5C313 (from the OSCOUT pin) to drive any other IC for the purpose of ensuring stable oscillation. 17 RS5C313 RS5C313 5. Oscillator Halt Sensing Oscillation Halt can be sensed by setting the XSTP (oscillator halt sensing) bit to 0 (after writing data to the control register) and then monitoring the XSTP bit. Upon oscillator halt sensing, the XSTP bit is switched from 0 to 1. This function can be applied to judge clock data validity. XSTP Power-on from 0V*1 Oscillation restart*2 Writing of data to Oscillation halt control register (in the presence of oscillation) *1) While the CE pin is held at the low level the XSTP bit is set to 1 upon power-on from 0 V. Note that any instantaneous power disconnection may cause operational failure. When the CE pin is held at the high level oscillation halt is not sensed and the value of the XSTP bit when the CE pin is held at the low level is retained. *2) Once oscillation halt has been sensed, the XSTP bit is held at 1 even if oscillation is restarted. Considerations in Use of XSTP Bit Ensure error-free oscillation halt sensing by preventing the following: 1) Instantaneous disconnection of VDD 2) Condensation on the crystal oscillator 3) Generation of noise on the PCB in the crystal oscillator 4) Application of voltage exceeding prescribed maximum ratings to the individual pins of the IC 6. Typical Power Supply Circuit 1) Connect the capacitance of the oscillation circuit to the VSS pin. System supply voltage 2) Mount the high- and low-frequency by-pass capacitors in parallel and very close to the RS5C313 RS5C313. RS5C313 RS5C313 3) Connect the pull-up resistor of the INTR pin to two different posiA INTR B tions depending on whether the resistor is in use during battery back-up. · When not in use during battery back-up OSCIN - - - - - Position A in the left figure OSCOUT VDD · When in use during battery back-up - - - - - Position B in the left figure 4) Timing of power supply on / off and CE terminal refer to lower part plan. C VSS System supply voltage D E Battery voltage VDD 0V CE 0.2VDD MIN. 0µs 0.2VDD MIN. 0µs C,D,E : The lower limit voltage for CPU operation 18 0.2VDD MIN. 0µs RS5C313 RS5C313 7. Oscillation Frequency Adjustment 7.1 Oscillation Frequency Measurement +5V or +3V VDD OSCIN 32kHz CG OSCOUT Frequency counter INTR CE 1) When switch the CE pin to the high level after low level or open state, a 1-Hz interrupt pulse is output from the INTR pin about 2.5 seconds later. Measure this interrupt pulse by using a frequency counter 2) Ensure that the frequency counter has more than six digits (on the order of 1 ppm). 3) Place the CG between the OSCIN pin and the VSS level and pull up the INTR pin output to the VDD . VSS 7.2 Oscillation Frequency Adjustment Select crystal oscillator (For fixed capacitance) (For variable capacitance) Fix CG. Change CL value of crystal. Optimize CG. NG OK End *1 Fix the capacitance of CG. *2 Optimize central variable capacitance value *3 *3 Change the CL value of crystal. NG OK Make fine frequency adjustment with variable capacitance. End *1) To ensure that the crystal is matched to the IC, inquire its crystal supplier about its CL (load capacitance) and R1 (equivalent series resistance) values. It is recommended that the crystal should have the CL value range of 6 to 8pF and the typical R1 value of 30k ohms. 2) To allow for the possible effects of floating capacitance, select the optimum capacitance of the CG on the mounted PCB. The standard and recom* mendable capacitance values of the CG range from 5 to 24pF and 8 to 20pF, respectively. When you need to change the frequency to get higher accuracy, change the CL value of the crystal. *3) Collate the central variable capacitance value of the CG with its oscillation frequency by adjusting the angle of rotation of the variable capacitance of the CG in such a manner that the actual variable capacitance value is slightly smaller than the central variable capacitance value. (It is recommended that the central variable capacitance value should be slightly less than one half of the actual variable capacitance value because the smaller is variable capacitance, the greater are fluctuations in oscillation frequency.) In the case of an excessive deviation of the oscillation frequency from its required value, change the CL value of the crystal. 19 RS5C313 RS5C313 After adjustment, oscillation frequency is subject to fluctuations of an ambient temperature and supply voltage. See "10. Typical Characteristic Measurements". Note Any rise or fall in ambient temperature from its reference value ranging from 20 to 25 degrees Celsius causes a time delay for a 32kHz crystal oscillator. It is recommendable, therefore, to set slightly high oscillation frequency at room temperature. 8. Interrupt Operation The INTR pin output, the interrupt cycle register, and the CTFG bit can be used to interrupt the CPU in a certain cycle. (The INTR pin functions as an Nch open drain output.) 8.1 Selection of Interrupt Cycle The interrupt cycle register can be used to select either one of two interrupt output modes: the pulse mode (when the CT3 bit is set to 0) and the level mode (when the CT3 bit is set to 1). Interrupt cycle register CT3 INTR pin output Remarks CT1 CT0 *1 * * * 0 0 OFF Interrupt halt 0 1 ON Fixing the INTR pin at the low level 1 0 0.977ms Cycle: 0.977ms (1/1024Hz) Duty: 50% 1 1 0.5s Cycle: 0.5s (1/2Hz) 1 0 0 0 1 second Every second 1 0 0 1 10 seconds Every 10 seconds (For display of second digits: 00, 10, 20, 30, 40, and 50) 1 0 1 0 1 minute Every minute (00 second) 1 0 1 1 10 minutes Every 10 minutes (00 second) (For display of minute digits: 00, 10, 20, 30, 40, and 50) 1 1 0 0 1 hour Every hour (00 minute and 00 second) 1 1 0 1 1 day Every day (0 hour, 00 minute, and 00 second a.m.) 1 1 1 0 1 week Every week (0 week, 0 hour, 00 minute, and 00 second a.m.) 1 1 1 1 1 month Every month (1st day, 0 hour, 00 minute, and 00 second a.m.) 0 0 0 0 *1) 20 CT2 The symbol " " in the above table indicates 0 or 1. * RS5C313 RS5C313 8.2 Pulse Mode Interrupt When the CT3 bit is set to 0 and provides four interrupt cycles, off, on, 1024 Hz, and 2 Hz can be selected. The CTFG bit cannot be set because it is used for output monitoring. 1024Hz : T1=0.977ms 2Hz : T1=500ms T1 CTFG INTR 0.488ms 8.3 Level Mode Interrupt When the CT3 bit is set to 1, clock-interlocked cycles in increments of 1 second to 1 month can be selected. The CTFG bit can be written; writing the CTFG bit switches the INTR pin to the low level while writing 0 to the CTFG bit turns off the INTR pin. CTFG INTR Interrupt (Second count-up) Interrupt Writing 0 to CTFG bit (Second count-up) 9. Typical Application CPU System supply voltage System supply voltage RS5C313 RS5C313 B VCC A OSCIN INTR CE OSCOUT VDD SCLK SIO VSS VSS 1) Connect the capacitance of the oscillation circuit to the VSS pin. 2) Mount the high- and low-frequency by-pass capacitors in parallel and very close to the RS5C313 RS5C313. 3) Connect the pull-up resistor of the INTR pin to two different positions depending on whether the resistor is in use during battery back-up. When not in use during battery back-up - - - - - Position A in the above figure When in use during battery back-up - - - - - - - Position B in the above figure 21 RS5C313 RS5C313 10. Typical Characteristic Measurements VDD CG VDD CG=10pF X'tal : R1=30k½, CL=6pF Topt=25°C Input pin : VDD or VSS Output pin : Open OSCIN A X'tal OSCOUT VSS INTR Frequency counter 10.1 Standby Current vs. CG (VDD=3V) Topt=25°C 1.0 VDD=3V 0.0 1.0 0.0 0 10 30 20 Topt=25°C 2.0 Standby Current IDD (µA) 2.0 Standby Current IDD (µA) 10.2 Standby Current vs. VDD(CG=10pF) CG=10pF 0 10.3 Operational Current vs. SCLK Frequency VDD=5V 0.001 0.01 22 6 VDD=3V 1 0.1 SCLK Frequency (MHz) 10 CG=10pF 2 Standby Current IDD (µA) Operational Current IOPR (mA) 0.1 0.01 4 10.4 Standby Current vs. Temperature (VDD=3V, 5V) Topt=25°C 1 2 VDD (V) CG (pF) 1 VDD=5V VDD=3V 0 ­40 ­20 20 40 60 80 0 Temperature Topt (°C) 100 RS5C313 RS5C313 VDD=3V, Topt=25°C 80 60 40 20 0 ­20 ­40 10.6 Oscillation Frequency Deviation vs. VDD (f0: VDD=4V reference) Oscillation Frequency Deviation f/f0 (ppm) Oscillation Frequency Deviation f/f0 (ppm) 10.5 Oscillation Frequency Deviation vs. CG (f0: CG=10pF reference) 0 10 20 CG (pF) 0 ­1 ­2 ­3 ­4 30 CG=10pF, Topt=25°C 1 0 1 2 4 3 VDD (V) 5 6 10.7 Oscillation Frequency Deviation vs. Temperature 10.8 Oscillation Start Time vs. VDD (f0: Topt=25°C reference) VDD=3V, CG=10pF CG=10pF, Topt=25°C 1.0 0 Oscillation Start Time (s) Oscillation Frequency Deviation f/f0 (ppm) 10 ­10 ­20 ­30 ­40 ­50 ­60 0.5 CG=20pF ­70 CG=10pF ­80 ­40 ­20 0 20 40 60 80 100 Temperature Topt (°C) 0.0 0 1 2 3 4 VDD (V) 5 6 10.9 VDS vs. IDS for Nch Open Drain Output Topt=25°C Nch Open Drain Output IDS (mA) 50 40 30 VDD=5V 20 VDD=3V 10 0 0.0 0.5 1.0 VDS (V) 1.5 2.0 23 RS5C313 RS5C313 11. Typical Software-based Operations 11.1 Initialization upon Power-on *1) Power-on YES XSTP=0? No Interrupt cycle register¬0h Control register¬3h, 7h Set the XSTP bit to 0 by writing data to the control register. 0h for the 12-hour time display system. 4h for the 24-hour time display system. NO BSY=0? YES It takes 0.1-2 seconds to be set the BSY bit to 0 from oscillation starting upon power-on from 0V. Provide an exit from an oscillation start loop to prepare for oscillation failure. *6) *4 Write to control register 3h for 12-hour format or 7h for 24-hour format. Set the ADJ bit to 1 for checking oscillaiton. *5) *3 Turn off the INTR pin, whose output is uncertain at power-on. *4) *2 When not making oscillation halt sensing (data validity), the XSTP bit need not be checked. *3) *1 Switch the CE pin to the low level immediately after power-on. *2) Start *6 Control register¬0h, 4h Set clock and calendar counters and interrupt cycles. When using the XSTP bit *5 Wait or other operations. Ensure stable oscillation by preventing the following: 1) Condensation on the crystal oscillator 2) Instantaneous disconnection of power 3) Generation of clock noises, etc. in the crystal oscillator 4) Charge of voltage exceeding prescribed maximum ratings to the individual pins of the IC 11.2 Write Operation to Clock and Calendar Counters *1) *2) CE=H Control register¬0h, 4h BSY=0? YES Write to clock and calendar counters. *4 24 CE=L After switching the CE pin to the high level, hold it at the high level until any subsequent operation requires switching it to the low level. (Note that switching the CE pin to the low level sets the WTEN bit to 1.) Write 0h for the 12-hour format or 4h for the 24-hour time display system. *3) The BSY bit is held at 1 for a maximum duration of 122.1 us. *4) Switch the CE pin to the low level to set the WTEN bit to 1. During write operation to the clock and calendar counters, one 1-second digit carry causes a 1-second increment while two 1-second digit carries also cause only a 1-second increment, which, in turn, causes a time delay. *1 *2 NO CE=L *3 Wait or other operations. RS5C313 RS5C313 11.3 Read Operation from Clock and Calendar Counters 11.3-1 11.3-2 CE=H *1 Control register ¬0h, 4h *2 * Again read 1-second digit of clock counter. CE=L Read from clock and calendar counters. *5 Read from clock and calendar counters. NO BSY=0? YES 4 Read 1-second digit of clock counter. *5 Two1-second digit readings match? *5 *3 Wait or other operations. CE=L NO YES Note Read data as described in 11.3-2 or 11.3-3 when it takes (1/1024) sec or more to set the WTEN bit from 0 to 1 (CE=L), the read operation described in 11.3-1 is prohibited as such a case. 11.3-3 *1) Interrupt to CPU CTFG=1? YES *2) NO *7 Control register ¬2h, 6h *8 Read from clock calendar counter Write 0h for the 12-hour format or 4h for the 24-hour time display system. *3) The BSY bit is held at 1 for a maximum duration of 122.1 us. *4) *6 After switching the CE pin to the high level, hold it at the high level until any subsequent operation requires switching it to the low level. (Note that switching the CE pin to the low level sets the WTEN bit to 1.) Switch the CE pin to the low level to set the WTEN bit to 1. During write operation to the clock and calendar counters, one 1-second digit carry causes a 1-second increment while two 1-second digit carries also cause only a 1-second increment, which, in turn, causes a time delay. *5) When needing any higher-order digits than the minute digits, replace second digits with minute digits. (Reading LSD one of the required digits twice.) *6) Select the level mode as an interrupt mode by setting the CT3 bit to 1. *7) Write 2h for the 12-hour format or 6h for the 24-hour format. *8) Complete read operation within an interrupt cycle after interrupt generation (e.g. within 1 second). Interrupt operation from any other IC 25 RS5C313 RS5C313 11.4 Second-digit Adjustment by ±30 seconds *1) Write 3h for the 12-hour format or 7h for the 24-hour format and then set the ADJ bit to 1. (The BSY bit is held at 1 for a maximum duration of 122.1µs after the ADJ bit is set to 1.) *2) The XSTP bit is set to 1 upon power-on from 0V. *3) It takes approximately 0.1 to 2 seconds to start oscillation. Provide an exit from an oscillation start loop to prepare for oscillation failure. *4) Control register ¬3h, 7h Write 2h for the 12-hour format or 6h for the 24-hour format. 1 * 11.5 Oscillation Start Judgment Power-on YES *3 *2 XSTP=0? Wait or other operations NO *4 Control register ¬2h, 6h When using the XSTP bit Ensure stable oscillation by preventing the following: 1) Condensation on the crystal oscillator 2) Instantaneous disconnection of power Oscillation start 3) Generation of clock noises, etc. in the crystal oscillator 4) Charge of voltage exceeding prescribed maximum ratings to the individual pins of the IC 11.6 Interrupt Operation (a) Cyclic Interrupt Operation (Every 1 Second to 1 Month) *5) Set interrupt cycle register *6) *5 Interrupt to CPU CTFG=1? YES NO *6 Control register ¬2h, 6h Cyclic interrupt operation 26 Interrupt operation from any other IC Set the interrupt cycle register to the level mode by setting the CT3 bit to 1. Write 2h for the 12-hour format or 6h for the 24-hour format. RS5C313 RS5C313 (b) Daily Time (Hour or Minute) Alarm Operation*1 *1) Interrupt cycle register ¬ h *2) Initially set address h to Ch (every 1 hour) and change it in the following sequence for every matching of clock counter readings in Ch ® Bh ® Ah ® (9h ® 8h) Every Every Every (Every Every) 1 hour 10 mins. 1 min. (10 secs. 1 sec.) In this manner, change the settings of the interrupt cycle register. *3) Write 2h for the 12-hour format or 6h for the 24-hour format. *4) *2 In this typical operation, alarm time is stored in the CPU and collated with clock time through interrupt operation. Collate alarm time with clock time through interrupt operation. Interrupt Setting Time Digit for Collation Ch 10-hour and 1-hour digits Bh 10-minute digit (10-hour and 1-hour digits) Ah 1-minute digit (10-hour, 1-hour, and 10-minute digits) (9h) 10-second digit (10-hour digit to 1-minute digit) (8h) 1-second digit (10-hour digit to 10-second digit) Interrupt to CPU NO CTFG=1? YES *3 Control register ¬2h, 6h Interrupt operatin from any other IC Read from clock counter Readings match? *4 NO YES Note In the above typical operation, alarm time (hour and minute) is collated with clock time by making interrupt operation a maximum of 37 times per day as shown by the following calculation: 23(1-hour digit)+5(10-minute digit)+9(1-minute digit)=37 times In this connection, a total current consumption increase resulting from interrupt operation can also be calculated as follows: Assuming, for example, that interrupt operation to the CPU takes 50 ms and consumes 10mA of current, an average current consumption increase resulting from interrupt operation can be calculated as follows: (50 ms ´ 10mA ´ 37 times) / (60 seconds ´ 60 minutes ´ 24 hours)=0.21µA Counting in a standard current consumption of about 0.91µA when the RS5C313 RS5C313 is set to 3V, a total current consumption can be calculated at about 1.1µA. 27 RS5C313 RS5C313 PACKAGE DIMENSIONS (Unit:mm) · 8pin SSOP (0.65mm pitch) 3.5±0.3 1 4 6.4±0.3 5 4.4±0.2 8 0.65 0.15 0° 0° to1 0.1±0.1 0.15 0.22±0.1 +0.1 0.15 -0.05 1.15±0.1 0.775 TYP. 0.5±0.3 M TAPING SPECIFICATION (Unit:mm) 3.9 2.0±0.05 6.7 2.7 MAX. Direction of taping RS5C313-E1 RS5C313-E1 28 8.0±0.1 RS5C313-E2 RS5C313-E2 12.0±0.3 4.0±0.1 5.5±0.05 +0.1 ø1.5 ­0 0.3±0.1 1.75±0.1 · 8pin SSOP (0.65mm pitch) RICOH COMPANY, LTD. ELECTRONIC DEVICES DIVISION HEADQUARTERS 13-1, Himemuro-cho, Ikeda City, Osaka 563-8501, JAPAN Phone 81-727-53-1111 Fax 81-727-53-6011 YOKOHAMA OFFICE (International Sales) 3-2-3, Shin-Yokohama, Kohoku-ku, Yokohama City, Kanagawa 222-8530, JAPAN Phone 81-45-477-1697 Fax 81-45-477-1694 · 1695 http://www.ricoh.co.jp/LSI/english/ RICOH CORPORATION ELECTRONIC DEVICES DIVISION SAN JOSE OFFICE 3001 Orchard Parkway, San Jose, CA 95134-2088, U.S.A. Phone 1-408-432-8800 Fax 1-408-432-8375