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HFBR-RUS500Z Broadcom Limited Wire And Cable visit Digikey Buy
HFBR-RUS100Z Broadcom Limited Wire And Cable visit Digikey Buy

RRUS 32 b2

Catalog Datasheet MFG & Type PDF Document Tags

RRUS 32 b2

Abstract: RRUS 32 CONNECTION DIAGRAMS Top View 32-Pin DIP CI, C 1 â'¢ 32 D C3,/E< C2i C 2 31 : C5i/INs C4,/INe [ 3 30 , I 11 35 â¡ DCL Vcc* C 12 34 â¡ RSRVD RSRVD E 13 33 â¡ Vcc V0UT2 Q 14 32 â¡ S2 VEE2 C 15 31 , = 15% to 85%) PACKAGE TYPE P = 32-Pin Plastic DIP (PD 032) J = 44-Pin Plastic Leaded Chip Carrier , separate for each channel. The IOM 2 DSLAC device is available in a 32-pin DIP or a 44-pin PLCC. This , slot is used with a 256 kb/s bit rate. In this case the same 32-bit time slot is sent for every frame
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RRUS 32 b2

Abstract: RRUS 32 32-Pin DIP Z 32 : C3i/Ei 31 : C5,/INs 3 30 : DET./IN4 4 29 : FSC , 34 ⡠RSRVD 13 33 "~1 Vcc 14 32 ⡠S2 15 31 ⡠S1 ⡠so s 3 , TYPE P = 32-Pin Plastic DIP (PD 032) J = 44-Pin Plastic Leaded Chip Carrier (PL 044) DEVICE OPTIONS , available in a 32-pin DIP or a 44-pin PLCC. This section describes the operation of the IOM 2 in , I/O programming and an M byte used for signal processor programming. case the same 32-bit time
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RRUS 01 B1

Abstract: RRUS 01 B2 AMD CONNECTION DIAGRAMS Top View 32-Pin DIP C l, C 1 · 32 : 31 C 3 i/E i C5,/IN s d e , S2 S1 SO RSRVD Q > a: (/) cc Q > o cc O C O C LL cc 37 36 35 34 33 32 31 V oU TI , a tio n of the e le m e n ts below . AM79C04 _A _ P C P = 32-P in Plastic DIP (P D , PIN DESCRIPTION A G ND A nalog G round C l, C2, C3./E, C12 , C22, C 32 /CHCLK SLIC Outputs These , available in a 32-pin DIP o r a 44-pin PLCC. This section describes the operation of the IOM 2 in terface
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RRUS 01 B1 RRUS 01 B2 M25C22 RRUS 32 RRUS 32 b2 YLE relay 79C04 096-M 79C04/A

RRUS 32 b2

Abstract: RRUS 01 B2 Adjustable System Sampling Rates - including 32 kHz, 44.1 kHz & 48 kHz · Digital De-emphasis for 32 kHz, 44.1 , -60 dB (Note 2) THD+N -90 -78 -38 (Note 3) (Note 3) (Note 3) (Note 3) (Note 4) Fs = 32 kHz Fs = 44.1 , / LRCK = 256 Fs 1 10 10 21 21 31 32 " - 50 " - kHz ns ns ns ns ns ns ns ns ns ns ns ns ns , input sample rate between 1 and 50 kHz, including the standard audio rates of 48, 44.1 and 32 kHz. The , 1 Format 0 1 2 3 4 5 6 Calibrate Figure 3 3 3 4 5 6 7 - 32 44.1 48 8.1920 11.2896 12.2880
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RRUS 01 CS4329 CS4390 CS4329-KP CS4329-KS CDB4329 28BMH

RRUS 01 B1

Abstract: RRUS 01 B2 of an overflow, the END signal will not be issued. The width of the ENC) signal is 32 DCLK cycles , is 65,312. Each entry consists of two bytes; therefore, Section III can support up to 32,656 blocks , 35 1 4 8 11 19 22 34 36 5 7 12 18 23 33 37 48 6 13 17 24 32 38 47 49 14 16 25 31 39 46 50 57 15 26 30 , leastsignificant bits (b1 ,b0) define the access time of the Auxiliary Memory, and the next two bits (b3,b2) define , these three values cannot exceed 32,656. g. In Encodel and Encode2, write the contents of BCV to the
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AD012 zoran zr ZR36031 ZR36020 OOS-O15 DS36020-0391

RRUS 01 B1

Abstract: RRUS 32 b2 /pipeline Harvard architecture â'¢ 3 data-bus structure â  3 data types : 16-bit real, 32-bit real : 16 , â'¢ 32-bit instruction bus â'¢ 84k x 32-bit external program space â'¢ 68000 family compatibility , 12 37 :aio vssc 13 36 :a9 xtalc 14 35 3 as extalc 15 34 3 ad7 CLKOUTC 16 33 3 ad6 BSC 17 32 :ad6 , .32 Section 7 Instruction set 36 7.1 Operating code formats , bus R5 1 22 32 Register Select Used by a master to gain access to the mailbox and system bus SDS t
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TS68930 TS68931 ocular lcd 3BS1 e purse TS68930/1 CB-229 LCCC84 C8-229

RRUS 32

Abstract: RRUS 32 b2 -bit real, 32-bit real : 16 + 16-bit complex number · 2 versions : TS68930 (internal ROMs) 48-pin : TS68931 , 32-bit instruction bus · 64 k x 32-bit external program space · 68000 family compatibility · Dual , 33 3 A D 6 32 3 A D S 31 3 A D 4 30 3 A D 3 29 3 A D 2 28 3A D 1 27 3 A D O 26 3 B E 5 /B A 25 3 B E , . Application examples Section 7 Instruction set 26 28 28 29 30 31 32 36 7.1 7.2 7.3 , 24 31 32 30 29 43 44 34 EXTERNAL BRANCH CONDITIONS Name BS (0:2) BE (3:6) Pin Pin nb. Pin nb
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2101S TS68930VC TS68931CE TS68931VE TS68931CR CB-33 CB-34

68488 gpib

Abstract: MC68848 Voltage (lLoad= 1.6mA) (lLoac) = 3.2 mA) DO-07 SRQ. IRQ "OL - - VSS-0 4 VSS^0 4 V Output Leakage Current , state transition. Time values specified by an upper case T indicate the minimum time that a fur,con rrus , rsv R6R B7 B6 B5 84 B3 B2 81 BO R6W PPR8 PPR7 PPR6 PPR5 PPR4 PPR3 PPR2 PPR1 R7R DI7 OI6 DI5 , inspection. Command Pass-Through Register (Read Only) B7 B6 B5 B4 B3 B2 81 BO An 8-bit input port used to
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MC68488 M6800 MC68488CP 68488 gpib MC68848 G6G 6 pin ic 68488 IB0-I87 mc8040 64-SZP IEEE-488 MC68A488P MC684S8P

RRUS 01 B2

Abstract: RRUS 32 b2 . 32 14. ORDERING INFORMATION , .) Parameters High-Level Output Voltage (IOH = -3.2 mA), except TXP/TXN Low-Level Output Voltage (IOH = 3.2 mA
Cirrus Logic
Original
d 2037 CS8406 CP1201 IEC-60958 IEC60958 CDB8416 DS580F6

RRUS 32 b2

Abstract: CL-GD620 expansion for 8 bits-per-pixel graphics - 32 x 32 hardware cursor (2 bits-per-pixel) â  S upports 3.3 , control and Standby Mode - Dedicated Suspend Mode Pin - 32-kHz DRAM refresh clock in Suspend Mode â , directly with '386SX microprocessors. Connections to 32-bit buses, such as '386DX or '486 microprocessors , .30 2.8 Power Management Support. 31 2.9 LCD Panel class="hl">32 , . 36 Data Bus Interface for 32
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CL-GD620 CL-GD6205 CL-GD6215 CL-GD6225 386SL CL-GD62XX

rsn 3404

Abstract: texas instruments data guide manual , integration, and per formance with the industries fastest 32- and 16-bit error detection and correction , Am29000TM Family of 32-bit RISC processors. AMD also offers a line of iAPX microprocessors and related , functions are present, with two relay drivers (32-pin PLCC package). n = 5 indicates that both EO and E1 functions are present, with a ground-key filter pin and one relay driver (32-pin PLCC package). All these , 28-pin DIP 22-pin DIP 32-pin PLCC · · · · · · · · · · · · · ·
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rsn 3404 texas instruments data guide manual cf -mh 22 e 103 m-c Transistor AND DIODE Equivalent list HIGH VOLTAGE ISOLATION DZ 2101 PEAK DETECTOR CIRC ZLN 7901 CD022 CD3022 PD022 CD024 PD024 CD028

CL-SH360

Abstract: lro 07   Supports host- and disk-interrupt pins Formatter Interface m Supports NRZ disk data rates up to 32 Mbits , memory manager. It supports disk data rates up to 32 Mbits/second, and simultaneously provides the , . 3.1 Buffer Manager Registers. 3.2 , internal pull-up resistor. The resistor is disabled when the pin is configured as an output. INDEX 32 81 I , Local Microcontroller Power-Down Bit is unlocked (Register 4FH, Bit 5). 3.2 PC Interface Registers
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CL-SH360 68HC11 lro 07 bd 9893 DSI-T10 BA 4213 winchester wdc 88 16-MH ST506/412 100-P SH360

TNY 176 PN EQUIVALENT

Abstract: AY-5-8100 Y -5 -1 2 0 0 A . 3-2 A Y -5 -1 2 0 2 A . 3-2 A Y -5 -1 2 0 3 A . 3-2 A Y -5 -1 2 0 4 A . 3-2 A Y -5 -1 2 2 4 A . 3-5 A Y -5 -1 2 3 0 , . 4C -24 M E M 636 . .4C -28 M E M 655 . . . .4C -32 M E , Operates directly from a 3,58MHz TV crystal. Direct drive oi l ë d display P A G E N O . 3-2 3-2 3-2 1
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TNY 176 PN EQUIVALENT AY-5-8100 TFK 7 segment displays AY5-8100 7-segment display tfk TNY 177 PN EQUIVALENT