NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: ROE bit in the command register or the external REQEN pin. Request enable input. REQEN ='0' enables , aperiodic signal (representing the noise of the speech) is fed to a series of resor .¡tors. Every resonator , finishes. This leaves the control circuit (e.g. microprocessor) enougi time to use polling, instead of , STOP CONT enable CONT ROE enable ROE NOT USED '0'= INVALID '1' := STOP 00= INVALID 01 = INVALID 10 = , results in an immediate reset of the synthesizer to the STOP mode. The ROE and CO NT are not affec ted by ... | OCR Scan |
14 pages, |
MEA8000 mea8 MAB8048 IEC134 BC558 mullard mea8000 M4242 MEA8000 abstract |
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| Abstract: represent all possible configurations, e.g., SCKx and FS don't have to be in the same direction. Note that , A/MU FSD0 OF1 OF0 SHFD SCKP SCKD FSD1 7 6 5 4 3 2 1 TDE ROE , (PSR) Bit 15 The Prescaler Range controls a fixed divide-by-8 prescaler in series with the variable , on the following condition: RIE=1 and RDF=1 and ROE=1 2. Receive Data without exceptions - This interrupt is generated on the following condition: RIE=1 and RDF=1 and ROE=0 8.13 SSI STATUS REGISTER ... | Original |
28 pages, |
CRB 432 datasheet abstract |
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| Abstract: modes.These figures do not represent all possible configurations, e.g., SCKx and FS don't have to be in the , 6 5 4 3 2 1 TDE ROE TUE RFS TFS IF1 READ-WRITE SSIx CONTROL , Range controls a fixed divide-by-8 prescaler in series with the variable prescaler. It is used to , on the following condition: RIE=1 and RDF=1 and ROE=1 2. Receive Data without exceptions - This interrupt is generated on the following condition: RIE=1 and RDF=1 and ROE=0 8.13 SSI STATUS REGISTER ... | Original |
28 pages, |
DSP56156 CRB 432 datasheet abstract |
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| Abstract: This document assumes all other pins (e.g., Address, Data, etc.) are connected in such a way as to , processor series provides higher performance levels while maintaining backward compatibility with the i960 , D31:0 TOV1 W/R#-OE# NOTE: The address line labels in this diagram refer to the labels on the , CE0 W9 W3 W3 W12 WE# TOH1 TOV1 TOV1 W/R#-OE# TOV1 TOV1 TOH1 TOV1 TOH1 ... | Original |
12 pages, |
Intel i960 architecture INTEL application notes FF000000 298130 28F640J3A 28F320J3A 28F128J3A INTEL STRATAFLASH AP-646 datasheet abstract |
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| Abstract: RXE 24 receiver circuit enable output ROE 25 receiver oscillator enable output ZSD 26 synthesizer , (respectively RXE and ROE) according to the code structure and the synchronization algorithm. Data received , circuit (at output ROE) before activating the rest of the receiver. This is possible with the UAA2082 UAA2082 , operation. To allow easy oscillator adjustment (e.g. by means of a variable capacitor) a 32.768 kHz , when a valid data sequence has been detected (e.g. preamble or sync word). Synchronization strategy ... | OCR Scan |
37 pages, |
UAA2082 UAA2080 ROE d3 PCD5003H PCD5003 matrix tv m21 service mode manual LQFP32 POCSAG Receiver PCD5003 abstract |
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| Abstract: received POCSAG data input RXE 24 receiver circuit enable output ROE 25 receiver oscillator enable output , enable outputs (respectively RXE and ROE) according to the code structure and the synchronization , oscillator circuit (at output ROE) before activating the rest of the receiver. This is possible with the , proper operation. To allow easy oscillator adjustment (e.g. by means of a variable capacitor) a 32.768 , when a valid data sequence has been detected (e.g. preamble or sync word). Synchronization strategy ... | OCR Scan |
37 pages, |
V100 UAA2082 UAA2080 POCSAG Receiver POCSAG PCD5003H PCD5003 LQFP32 power supply CIRCUIT DIAGRAM irfp 460 a PCD5003 abstract |
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| Abstract: connected RDI 23 received POCSAG data input RXE 24 receiver circuit enable output ROE 25 receiver , ROE) according to the code structure and the synchronization algorithm. Data received serially at the , complete pager can be minimized by separately activating the RF oscillator circuit (at output ROE) before , easy oscillator adjustment (e.g. by means of a variable capacitor) a 32.768 kHz reference frequency can , been detected (e.g. preamble or sync word). Synchronization strategy In ON status the PCD5003 PCD5003 ... | OCR Scan |
38 pages, |
UAA2082 DO25 PCD5003 PCD5003H POCSAG out of range CXO 049 S524 TQFP32 UAA2080 POCSAG TQFP32 footprint POCSAG Receiver PCD5003 abstract |
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| Abstract: receiver circuit enable output ROE 25 receiver oscillator enable output ZSD 26 synthesizer serial data , receiver and oscillator enable outputs (respectively RXE and ROE) according to the code structure and the , adjustment (e.g. by means of a variable capacitor) a 32.768 kHz reference frequency can be selected at output , detected (e.g. preamble or sync word). m TllOÛEb 0003474 MAT â- 561 This Material Copyrighted By Its , Oscillator Enable outputs (respectively FIXE and ROE) are switched accordingly, with the appropriate ... | OCR Scan |
37 pages, |
UAA2080 TQFP32 spf 316 PCD5003H PCD5003 00S34 CCIR Radiopaging Code NO.1 PCD5003 abstract |
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| Abstract: divide-by-eight prescaler in series with the variable prescaler. This bit extends the prescaler range for those , receive data interrupts. Therefore, if an exception occurs (the ROE bit is set) and REIE is set, the SSI , ) control bit is set, the DSP is interrupted when both the RDF and ROE bits in the SSISR are set. When the , data register clears the ROE bit, thus clearing the pending interrupt. Hardware and software reset , 5 4 3 2 RDF TDE ROE TUE RFS TFS 1 0 IF1 IF0 * Indicates reserved bits ... | Original |
26 pages, |
DSP56602 AA0741 datasheet abstract |
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| Abstract: Range (PSR)-Bit 15 The Prescaler Range (PSR) bit controls a fixed divide-by-eight prescaler in series , interrupts. Therefore, if an exception occurs (the ROE bit is set) and REIE is set, the SSI requests an SSI , ) control bit is set, the DSP is interrupted when both the RDF and ROE bits in the SSISR are set. When the , data register clears the ROE bit, thus clearing the pending interrupt. Hardware and software reset , * * * * * * * * 7 6 5 4 3 2 RDF TDE ROE TUE RFS TFS 1 0 IF1 IF0 * Indicates ... | Original |
28 pages, |
DSP56603 datasheet abstract |
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| SINGLE SUPPLY APPLICATIONS; E.G. VCC+ = 5 V, * VCC- = 0 V, VSAT+ = 3 V, VSAT- = 5 MV; POWER NOT CONNECTED + TT = 0 + CJO = 0 + VJ = 1 + M = .5 + EG = 1.11 + XTI = 3 + M = .5 + EG = 1.11 + XTI = 3 + KF = 0 + AF = 1 + FC = .5 = 1 + TT = 0 + CJO = 0 + VJ = 1 + M = .5 + EG = 1 + CJS = 0 + VJS = .75 + MJS = 0 + XTB = 0 + EG = 1.11 + XTI = 3 www.datasheetarchive.com/files/spicemodels/misc/opamp.lib |
Spice Models | 07/08/2009 | 299.04 Kb | LIB | opamp.lib |
| MODELS SINGLE SUPPLY APPLICATIONS; E.G. VCC+ = 5 V, * VCC- = 0 V, VSAT+ = 3 V, VSAT- = 5 MV; POWER NOT + CJO = 0 + VJ = 1 + M = .5 + EG = 1.11 + XTI = 3 + KF = 0 + M = .5 + EG = 1.11 + XTI = 3 + KF = 0 + AF = 1 + FC = .5 + N = 1 + TT = 0 + CJO = 0 + VJ = 1 + M = .5 + EG = 1 + EG = 1.11 + XTI = 3 + KF = 0 + AF = 1 + FC = .5 + NK = .5 www.datasheetarchive.com/files/spicemodels/misc/spice_model_cd/mixed part list/spice-models-collection/opamp.lib |
Spice Models | 29/07/2012 | 301.82 Kb | LIB | opamp.lib |
| +@'(* # YV4DGYM1?7Y&]5GTPF?3"Y]5+WQVO24 WQVO24 WQVO24 WQVO24@^\EG;B06 O0W&M#A M:$"/HP%=CN0S;RX!=0SJ0NCWX3;T6(7N*A5Z/9L TBP6-O1H ; !T>T,@[@V#N#?@W=YPB'M#(NX-4K\(A[ ]7M#9.8'0EG M=E2 M94>TF!UU YY7>P2V+4=;%_;@1ZV'?1AVT'3M1T$8MO! M85U www.datasheetarchive.com/download/32843250-960428ZC/4kefixhp.uue |
Xilinx | 05/09/1996 | 1743.89 Kb | UUE | 4kefixhp.uue |