RN-01052-1 EP4CGX30 EP4CGX50 EP4CGX75 EP4CGX110 EP4CGX150 EP4CE10 EP4CE15 - Datasheet Archive

 

RN-01052-1.0 February 2010 This document provides late-breaking information about the following areas of the Altera®

 

Quartus II Software Release Notes RN-01052-1 RN-01052-1.0 February 2010 This document provides late-breaking information about the following areas of the Altera® Quartus®II software version 9.1 SP1. For information about disk space and system requirements, refer to the readme.txt file in your altera//quartus directory. For information about device support in this version of the Quartus II software, along with the latest information about timing and power models, refer to the Quartus II Device Support Release Notes. For the latest information about the MegaCore® IP Library, refer to the MegaCore IP Library Release Notes and Errata. Both documents are available on the Altera website at http://www.altera.com/literature/lit-rn.jsp. This document contains the following sections: "New Features & Enhancements" on page 1 "EDA Interface Information" on page 3 "Changes to Software Behavior" on page 4 "Known Issues & Workarounds" on page 6 "Platform-Specific Issues" on page 8 "Device Family Issues" on page 9 "SOPC Builder Issues" on page 18 "EDA Integration Issues" on page 19 "Memory Interface Issues" on page 20 "Simulation Model Changes" on page 21 "Latest Known Quartus II Software Issues" on page 22 "Software Issues Resolved" on page 22 New Features & Enhancements The Quartus II software version 9.1 includes the following new features and enhancements: You can use non-rectangular LogicLock regions to create more compact and efficient floorplans. Avalon Verification IP components in SOPC Builder allow you to simulate the behavior of IP created for SOPC Builder systems and to monitor Avalon interface traffic. You can also perform Avalon Memory Map or Avalon Streaming Protocol assertion checking. The Quartus II software version 9.1 provides VHDL 2008 initial support. February 2010 The Rapid Recompile option, which reduces compilation time and improves timing preservation when making small design changes. You can use the Rapid Recompile option in place of or together with creating design partitions to preserve placement and routing results from a previous compilation. The IP library includes improved DDR2, DDR3, QDR II+, and RLDRAM II memory controllers. Altera Corporation Quartus II Software Release Notes Page 2 New Features & Enhancements The Pin Advisor has been enhanced to include information on how to use the Quartus II software to generate more accurate and less pessimistic Simultaneous Switching Noise (SSN) results. The Quartus II software version 9.1 supports the following new megafunctions: altotp megafunction altfp_matrix_inv megafunction The Quartus II software version 9.1 SP1 adds support for the following devices: Initial information support for these Cyclone IV GX devices: EP4CGX30 EP4CGX30, EP4CGX50 EP4CGX50, EP4CGX75 EP4CGX75, EP4CGX110 EP4CGX110, EP4CGX150 EP4CGX150 Advance support for these Cyclone IV E devices: EP4CE6, EP4CE10 EP4CE10, EP4CE15 EP4CE15, EP4CE22 EP4CE22, EP4CE30 EP4CE30, EP4CE40 EP4CE40, EP4CE55 EP4CE55, EP4CE75 EP4CE75, EP4CE115 EP4CE115 Full support for these Arria II GX devices: EP2AGX190 EP2AGX190, EP2AGX260 EP2AGX260 Full support for these Stratix IV devices: EP4SGX290 EP4SGX290, EP4SGX360 EP4SGX360, EP4SGX530 EP4SGX530 Compilation support for these HardCopy IV E devices: HC4E25 HC4E25, HC4E35 HC4E35 Compilation support for these HardCopy IV GX devices: HC4GX15 HC4GX15, HC4GX25 HC4GX25, HC4GX35 HC4GX35 The Quartus II software version 9.1 adds support for the following devices: Initial information support for these Cyclone IV GX devices: EP4CGX15 EP4CGX15, EP4CGX22 EP4CGX22, EP4CGX30 EP4CGX30 Advance support for these Cyclone III LS devices: EP3CLS70 EP3CLS70, EP3CLS100 EP3CLS100 Advance support for these HardCopy IV GX devices: HC4GX15 HC4GX15, HC4GX25 HC4GX25, HC4GX35 HC4GX35 Advance support for these Stratix IV devices: EP4SE360 EP4SE360, EP4SE820 EP4SE820, EP4S40G5 EP4S40G5, EP4S100G3 EP4S100G3, EP4S100G4 EP4S100G4, EP4S100G5 EP4S100G5, EP4SGX70HF35 EP4SGX70HF35, EP4SGX110HF35 EP4SGX110HF35, EP4SGX290KF43 EP4SGX290KF43, EP4SGX290NF45 EP4SGX290NF45, EP4SGX360KF43 EP4SGX360KF43, EP4SGX360NF45 EP4SGX360NF45, EP4SGX530KF43 EP4SGX530KF43 Full support for these Arria II GX devices: EP2AGX45 EP2AGX45, EP2AGX65 EP2AGX65, EP2AGX125ES EP2AGX125ES Full support for these Cyclone III LS devices: EP3CLS150 EP3CLS150, EP3CLS200 EP3CLS200 Full support for these HardCopy III devices: HC325 HC325, HC335 HC335 Full support for these Stratix IV devices: EP4SE530ES EP4SE530ES, EP4SGX180 EP4SGX180, EP4SGX230 EP4SGX230, EP4SGX530ES EP4SGX530ES, EP4S40G2 EP4S40G2, EP4S100G2 EP4S100G2 Quartus II Software Release Notes February 2010 Altera Corporation EDA Interface Information Page 3 EDA Interface Information The Quartus II software version 9.1 SP1 supports the following EDA tools: Synthesis Tools Version Synopsys Synplify & Synplify Pro 2009a Mentor Graphics LeonardoSpectrum 2009a Synopsys Design Compiler 2004.12-SP4 12-SP4 Mentor Graphics DK Design Suite C-2009 C-2009.06 Mentor Graphics Precision RTL Synthesis 5.0 SP5 Simulation Tools Version NativeLink Support Mentor Graphics ModelSim 6.5b Mentor Graphics ModelSim-Altera 6.5b Mentor Graphics ModelSim-Altera Starter Edition 6.5b Cadence NC-Sim 8.2 (Linux only) Synopsys VCS / VCS MX Y-2009 Y-2009.06-SP1 06-SP1 Aldec Active-HDL 8.1-SP2 (Windows only) Aldec Riviera-PRO 2009.06 Cadence Encounter Conformal Altera Corporation NativeLink Support Z-2007 Z-2007.06 Version NativeLink Support Version NativeLink Support 3.7 Board Level Symbol/Pin-out Management Mentor Graphics I/O Designer NativeLink Support Version Board Level Static Timing Analysis Mentor Graphics TAU 8.1 Chip Level Static Timing Analysis Synopsys PrimeTime Version Formal Verification Tools (Equivalence Checking) February 2010 NativeLink Support 7.3 Quartus II Software Release Notes Page 4 Changes to Software Behavior Changes to Software Behavior This section documents instances in which the behavior and default settings of this release of the Quartus II software have been changed from earlier releases of the software. Items listed in the following table represent cases in which the behavior of the current release of the Quartus II software is different from a previous version. Description Workaround Version 9.1 SP1 The following Cyclone IV GX devices are not supported in the Quartus II software version 9.1 SP1 and later: EP4CGX15BN11C6 EP4CGX15BN11C6 EP4CGX15BN11C7 EP4CGX15BN11C7 EP4CGX15BN11I7 EP4CGX15BN11I7 For the Cyclone IV GX device family, the RESERVE_ASDO_AFTER_CONFIGURATION assignment is not available. In the Quartus II software version 9.1, you could use a RESERVE_ASDO_AFTER_CONFIGURATION assignment to reserve both ASDO/DATA1 and nCSO pins in Bank 9 as user I/O pins in user mode. In the Quartus II software version 9.1 SP1, the RESERVE_ASDO_AFTER_CONFIGURATION assignment is not available for the Cyclone IV GX device family. This change enables Fast Passive Parallel (FPP) configuration for some Cyclone IV GX devices, allowing you to reserve the ASDO/DATA1 pin while keeping the nCSO pin available for general purpose I/O. In the Quartus II software version 9.1, RX PCS and TX PCS clock names reported by the TimeQuest Timing Analyzer are incorrect. For example, in the Quartus II software version 9.1, the TimeQuest Timing Analyzer might report xcvr_alt4gxb_component|receive_pcs0|clkout as xcvr_alt4gxb_component|receive_pcs0|recove redclk To reserve a ASDO/DATA1 pin, use a RESERVE_DATA1_AFTER_CONFIGURATION assignment. To reserve a nCSO pin, use a RESERVE_FLASH_NCE_AFTER_CONFIGURATION assignment. If you are using SDC assignments written for the Quartus II software version 9.1 in the Quartus II software version 9.1 SP1 or later, verify that your RX PCS and TX PCS clock names are correct. In the Quartus II software version 9.1 SP1 and later, the clock names reported by the TimeQuest Timing Analyzer are correct. Version 9.1 ACEX, APEX, FLEX, and HardCopy Stratix device families are not provided with the Quartus II software version 9.1 and later. Use the Quartus II software version 9.0 SP2 or earlier to support those devices. The Quartus II software version 9.0 and the associated service packs will remain available on the Altera website (http://www.altera.com). The Simulator and the Waveform Editor will not be provided in future versions of the Quartus II software beginning with version 10.0 Use the Quartus II software version 9.1 SP1 or earlier, Mentor Graphics ModelSim Altera Edition, or a third-party EDA simulator and waveform editor. Quartus II Software Release Notes February 2010 Altera Corporation Changes to Software Behavior Page 5 Description For Arria II GX, Cyclone III, Cyclone IV, HardCopy III, HardCopy IV, Stratix III, and Stratix IV devices, Analysis and Synthesis performs timing-driven synthesis by default. Workaround To turn off timing-driven synthesis, Turn off Timing-Driven Synthesis on the Analysis and Synthesis page of the Settings dialog box. Changes to the default assignment settings in the Quartus II software include the following: The default value of PARALLEL_SYNTHESIS has changed to On. For Arria II GX, Cyclone III, Cyclone IV GX, HardCopy III, HardCopy IV, Stratix III, and Stratix IV devices, the default value of SYNTH_TIMING_DRIVEN_SYNTHESIS has changed to On. Changes to TimeQuest Timing Analyzer behavior in the Quartus II software version 9.1 include the following: set_max_skew now includes utsu, uth, utco, from_clock, to_clock, and clock_uncertainty. In designs that target Stratix III devices, if ENA_REGISTER_MODE of the ena port is set to DOUBLE_REGISTER, the internal register-to-register timing of the enable signal is guaranteed by design and is excluded from timing analysis. Stratix III I4 timing models have been updated in the Quartus II software versions 9.0 SP2 and 9.1. Only timing delays in Low Power mode LABs and Low Power mode MLABs in I4 industrial speed grade devices are affected. This change in the timing models may affect your static timing analysis and fitting result. Existing designs that target Stratix III I4 devices might exhibit some degradation in performance after timing analysis with the TimeQuest Timing Analyzer in the Quartus II software version 9.1. However, a full recompilation of the design removes any degradation in performance. Other speed grade devices (I3 and I4L at 1.1V; I4L at 0.9V; and all commercial speed grades) are not affected. If your design works correctly in your hardware system, Altera recommends that you take no action. Otherwise, Altera recommends that you fully recompile the design. Mentor Graphics ModelSim-Altera Edition no longer includes the alt_vtl library used to simulate MAX+PLUS II designs. Use the alt_vtl library from the Mentor Graphics ModelSim-Altera Edition version 6.4a. In designs that target Stratix IV devices, ALTGX megafunction instances created with the Use external termination option turned on in the Quartus II software version 9.0 and earlier did not disable internal termination. The Quartus II software version 9.1 disables internal termination when the Use external termination option is turned on. This change in software behavior decreases the resistance in designs that use external termination and may change measured signal characteristics compared to those measured in previous versions of the Quartus II software. This change in software behavior does not affect designs that use internal termination. Starting in the Quartus II software version 9.1, an ALTGX megafunction generates only a 1-bit rateswitch port for PCIE Gen 2 x4/x8 configurations. In previous versions of the Quartus II software, an ALTGX megafunction generated 4- or 8-bit rateswitch ports, of which only bit 0 was used. February 2010 Altera Corporation Quartus II Software Release Notes Page 6 Known Issues & Workarounds Known Issues & Workarounds General Quartus II Software Issues Issue Workaround Version 9.1 SP1 Quartus II Help in the Quartus II software version 9.1 SP1 and earlier incorrectly states that the Fitter does not include set_max_skew constraints in design optimization, however, set_max_skew constraints are optimized by the Fitter. The set_max_skew command is available in the :quartus:sdc_ext_1.0 Tcl package. If you use the Remote System Upgrade configuration scheme to create a Programmer Object File (.pof) to update a device programmed with a .pof from a previous version of the Quartus II software, the Quartus II software version 9.1 SP1 might generate an internal error similar to the following: Use the version of the Quartus II software you used to generate the original .pof to create the updated .pof. Internal Error: Sub-system: PGMIO, File: /quartus/pgm/pgmio/pgmio_pof_diff.cpp, Line: 635 data do not match If you implement an ALTCLKCTRL megafunction and then run the Design Assistant, the Design Assistant might generate a message similar to the following: You may safely ignore this message. Critical Warning: (Critical) Rule C101: Gated clock should be implemented according to the Altera standard scheme. Found 1 node(s) related to this rule. Version 9.1 If you use variable part select with two-dimensional arrays, the Quartus II software version 9.1 SP1 generates an error similar to the following: Do not use variable part select with two-dimensional arrays. Use multiple constant part selects such as m[2+:1], and then choose from them. no support for variable part select of multidimensional arrays (System Verilog) The Quartus II software version 9.1 does not correctly synthesize variable part select with two-dimensional arrays. For example, the following Verilog statements are not synthesized correctly: logic s[3:0] ; logic [0:w-1][3:0]m ; s = m[i+1]; Quartus II Software Release Notes February 2010 Altera Corporation Known Issues & Workarounds Page 7 Issue Workaround The Quartus II software version 9.1 does not correctly synthesize disable statements when the disable statement refers to a labeled statement. For example, the following Verilog statements are not synthesized correctly: Rewrite your code so that the statement is surrounded by a begin-end block and name the block after the begin keyword. For example, the following is synthesized correctly: lbl: out1 ,=r1^r2; begin: lbl disable lbl; out1