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HS1-82C85RH-Q Intersil Corporation 15MHz, PROC SPECIFIC CLOCK GENERATOR, CDIP24 visit Intersil
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8406801VA Intersil Corporation 8MHz, PROC SPECIFIC CLOCK GENERATOR, CDIP18, CERAMIC, DIP-18 visit Intersil

RMII Specification revision 1.2

Catalog Datasheet MFG & Type PDF Document Tags

RMII Specification revision 1.2

Abstract: IC 7809 pin diagram specifics of this signal are available in the RMII Specification Revision 1.2. I TRANSMIT ERROR: - , RMII Specification Revision 1.2. RECEIVE DATA VALID: - RXDVn is asserted high to indicate that valid , on the specifics of this signal are available in the RMII Specification Revision 1.2. RECEIVE , RMII Specification published by the RMII Consortium. The intent of the RMII is to provide a reduced , false carrier event. Details on the specifics of this signal are available in the RMII Specification
TDK
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RMII Specification revision 1.2

Abstract: "RMII Specification revision 1.2" · RMII Specification Revision 1.2, RMII Consortium, March 20, 1998 · POS-PHY Saturn , L IM IN A R Y Revision 1.1 Entridia Corporation 131 Theory, Suite 150 Irvine, CA 92612 , respective owners. R E Revision History L 1.1 10/30/00 Description of Changes Update for Revision EB design: - Subnet broadcasts for Ethernet and OC-3 ports - TTL0/1 handling for , Ethernet port - Flow Table Layer 1 transaction revision - Layer 2 Tx/Rx Tag mode for Ethernet port - Tx
Entridia
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RMII Specification revision 1.2

Abstract: 100base ) . 74 Package Specification . 75 Revision History , .166 specification. This interface is suitable for driving a fiber-optic coupler. Network I/F RMII DATA I/F , Data Sheet MARCH, 2000 Revision 1.1 LXT9761 / 9781 General Description The LXT9781 is an , and 100 Mbps. It provides a Reduced Media Independent Interface (RMII) for switching and other , requires only a single 3.3V power supply. Fast Ethernet 10/100 Multi-Port Transceiver with RMII
Intel
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RMII Specification revision 1.2 100base duplex clock led display LXT9781HC duplex display led 30 PIN duplex led display LXT97 10/100BASE-TX 100BASE-FX 10BASE-T 100BASE-TX ISLXT9761/81DS

RMII Specification revision 1.2

Abstract: LXT9781HC LXT9761/9781 Fast Ethernet 10/100 Multi-Port Transceiver with RMII Datasheet The LXT9781 is an , Mbps and 100 Mbps. It provides a Reduced Media Independent Interface (RMII) for switching and other , auto-negotiation capability JTAG boundary scan Multiple Reduced MII (RMII) ports for independent PHY port , Multi-Port Transceiver with RMII. Order Number: 249048-001 January 2001 Information in this document , Multi-Port Transceiver with RMII - LXT9761/9781 Contents 1.0 Pin Assignments and Signal Descriptions
Intel
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100BASE-T 10/100-TX 208-P LXT9761HC 272-L LXT9781BC
Abstract: ) . 74 Package Specification . 75 Revision History , .166 specification. This interface is suitable for driving a fiber-optic coupler. Network I/F RMII DATA I/F , Data Sheet - Preliminary Information OCTOBER, 1999 Revision 1.0 LXT9761 / 9781 General , layer applications at both 10 Mbps and 100 Mbps. It provides a Reduced Media Independent Interface (RMII , Multi-Port Transceiver with RMII Features · Six or eight IEEE 802.3-compliant 10BASE-T or 100BASE-TX ports Intel
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HBLXT9785HE.D0

Abstract: LXT9785EHC Serial Media Independent Interfaces (SMII/SS-SMII) and Reduced Media Independent Interface (RMII) for , . Multiple RMII or SMII/SS-SMII ports for independent PHY port operation. Auto MDI/MDIX crossover , Extended temperature operation of -40oC to +85oC (LXT9785HE). Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH , Datasheet Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 Contents
Intel
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LXT9785 LXT9785E HBLXT9785HE GDLXT9785MBC HBLXT9785HE.D0 LXT9785EHC TS-42 reset FWLXT9785BC.D0 HBLXT9785EHC LXT97985E LXT9785/LXT9785E FWLXT9785EBC

1000base-t MDI

Abstract: HBLXT9785HE.D0 Synchronous Serial Media Independent Interfaces (SMII/SS-SMII) and Reduced Media Independent Interface (RMII , typical. Multiple RMII or SMII/SS-SMII ports for independent PHY port operation. Auto MDI/MDIX , of -40 oC to +85 oC (LXT9785E only). LXT9785/LXT9785E Datasheet 249241, Revision 11.0 16 , .20 3.1.1 PQFP Pin Assignments ­ RMII Configuration , .36 3.2.2 PQFP Signal Descriptions ­ RMII, SMII, and SS-SMII Configurations
Cortina Systems
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1000base-t MDI BGA 31 x 31 tray LXT9785HC IP168 785HC WBLXT9785HE 9785E LXT9785MBC

lxt9785

Abstract: HBLXT9785HE.D0 Interfaces (SMII/SS-SMII) and Reduced Media Independent Interface (RMII) for switching and other independent , power consumption; 250 mW per port typical. Multiple RMII or SMII/SS-SMII ports for independent PHY port , +85 oC (LXT9785E only). Document Number: 249241 Revision Number: 010 Revision Date: 30 , Datasheet Document Number: 249241 Revision Number: 010 Revision Date: 30-May-2006 Contents Contents , . 19 3.1.1 PQFP Pin Assignments ­ RMII Configuration
Intel
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FWLXT9785BC.C2V HBLXT9785 WBLXT9785HC.D0 WBLXT9785HE.D0 WBLXT9785HC B3408

LXT9785EHC

Abstract: HBLXT9785HE Independent Interfaces (SMII/SS-SMII) and Reduced Media Independent Interface (RMII) for switching and other , . 2.5 V operation. Low power consumption; 250 mW per port typical. Multiple RMII or SMII/SS-SMII , only). Document Number: 249241 Revision Number: 009 Revision Date: April 30, 2004 INFORMATION , Corporation 2 Datasheet Document Number: 249241 Revision Number: 009 Revision Date: April 30, 2004 , . 19 3.1.1 PQFP Pin Assignments ­ RMII Configuration
Intel
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B3408-01 n14 167 SL ENHANCED I486 HBLXT9785HC.D0 LXT9785EBC c 4744 RJ 49 CONNECTORS

WBLXT9785HC

Abstract: T3 SL 100B Synchronous Serial Media Independent Interfaces (SMII/SS-SMII) and Reduced Media Independent Interface (RMII , ; 250 mW per port typical. Multiple RMII or SMII/SS-SMII ports for independent PHY port operation. Auto , temperature operation of -40 oC to +85 oC (LXT9785E only). 249241, Revision 12.0 LXT9785/LXT9785E Datasheet 249241, Revision 12.0 04 November 2011 Legal Disclaimers INFORMATION IN THIS DOCUMENT IS , Transceivers Page 2 LXT9785/LXT9785E Datasheet 249241, Revision 12.0 04 November 2011 Contents
Cortina Systems
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T3 SL 100B PRLXT9785C B3368-01 PRLXT9785BC

865114

Abstract: GWLXT9785BC Media Independent Interfaces (SMII/SS-SMII) and Reduced Media Independent Interface (RMII) for switching , typical. Multiple RMII or SMII/SS-SMII ports for independent PHY port operation. Auto MDI/MDIX crossover , +85 oC (LXT9785E only). LXT9785/LXT9785E Datasheet 249241, Revision 11.0 16 April 2007 Contents , .20 3.1.1 PQFP Pin Assignments ­ RMII Configuration , .36 3.2.2 PQFP Signal Descriptions ­ RMII, SMII, and SS-SMII Configurations.36 BGA23
Cortina Systems
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GWLXT9785BC 865114 level one and bob smith termination GDLXT9785MBC.D0-854705 D0-865114 D0-865115 D0-865112 D0-865113 WBLXT9785EHC D0-865110

WBLXT9785EHC

Abstract: LXT9785 Synchronous Serial Media Independent Interfaces (SMII/SS-SMII) and Reduced Media Independent Interface (RMII , typical. Multiple RMII or SMII/SS-SMII ports for independent PHY port operation. Auto MDI/MDIX , of -40 oC to +85 oC (LXT9785E only). LXT9785/LXT9785E Datasheet 249241, Revision 11.0 16 , .20 3.1.1 PQFP Pin Assignments ­ RMII Configuration , .36 3.2.2 PQFP Signal Descriptions ­ RMII, SMII, and SS-SMII Configurations
Cortina Systems
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SMII-10BASE-T Balun Transformers bga236-1

LXT9785

Abstract: SMII-10BASE-T provides both Serial/Source Synchronous (SMII/SS-SMII) and Reduced Media Independent (RMII) Interfaces for , auto-negotiation capability. s s s s s s s JTAG boundary scan. Multiple RMII or SMII/SS-SMII ports , 2.3.3 RMII , . 68 2.7.5.1 Source Synchronous SMII. 70 RMII , . 74 2.8.1 RMII Reference Clock
Intel
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LXT9785BC 8029 l2 circuit RJ-45 241-B

line diagram for hp dv6 dc power connector

Abstract: 249241 /SS-SMII) and Reduced Media Independent Interface (RMII) for switching and other independent port , operation. Low power consumption; 250 mW per port typical. Multiple RMII or SMII/SS-SMII ports for , respective owners. 2 Datasheet Document #: 249241 Revision #: 005 Rev. Date: January 24, 2002 , . 55 2.3.3 RMII Data Interface , . 63 Datasheet Document #: 249241 Revision #: 005 Rev. Date: January 24, 2002 3
Intel
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line diagram for hp dv6 dc power connector 249241 hp dv6 4939n LXT9785/9785E HBLXT9785HC FWLXT9785BC

line diagram for hp dv6 dc power connector

Abstract: LXT9785EHC /SS-SMII) and Reduced Media Independent Interface (RMII) for switching and other independent port , operation. Low power consumption; 250 mW per port typical. Multiple RMII or SMII/SS-SMII ports for , Datasheet Document #: 249241 Revision #: 003 Rev. Date: 04/19/01 Contents Contents 1.0 Pin , . 54 2.3.3 RMII Data Interface , . 62 Datasheet Document #: 249241 Revision #: 003 Rev. Date: 04/19/01 3 Contents 2.7
Intel
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ss smii aui isolation transformer bob smith termination MAC data and non-data symbols sl r7 LXT9785BC/
Abstract: ) Master/Slave Interface Conforms to PCI Specification 2.3 One Inter-Integrated Circuit (I2C) Bus Two , '" Supports Multiple Media Independent Interfaces (MII, GMII, RMII, and RGMII) â'" 8 Independent Transmit , ) MII RMII L1P Memory Controller (Memory Protect/Bandwidth Mgmt) GMII RMGII(E) MDIO 16 L1D , . 2.9 Device Silicon Revision . Device Configurations , /Output (GPIO) . 175 6.26 IEEE 1149.1 JTAG . 178 Revision Texas Instruments
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TMS320C6455 SPRS276A C6455 850-MH TMS320C64 32-/16-B

TMS320C6455 rapid io

Abstract: SPRAAA8 Interface Conforms to PCI Specification 2.3 One Inter-Integrated Circuit (I2C) Bus Two Multichannel Buffered , Media Independent Interfaces (MII, GMII, RMII, and RGMII) ­ 8 Independent Transmit (TX) and 8 , /1000 MII RMII GMII RMGII(E) MDIO GPIO16(C) I2C Timer1(D) HI LO Timer0(D) HI LO Switched Central , 175 6.26 IEEE 1149.1 JTAG . 178 Revision History , . 2.9 Device Silicon Revision . Device Configurations
Texas Instruments
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TMS320C6455 rapid io SPRAAA8 125-G IEEE-1149 697-P
Abstract: Specification 2.3 · · · · · · · · · · · · Please be aware that an important notice concerning , (EMAC) ­ IEEE 802.3 Compliant ­ Supports Multiple Media Independent Interfaces (MII, RMII) ­ Management , ) External Clock Input From MXI/CLKIN Pin Revision History . , www.ti.com Revision History This data manual revision history highlights the technical changes made to the SPRS347 device-specific data manual to make it an SPRS347A revision. Scope: Applicable updates to Texas Instruments
Original
TMS320C6424 C6424 600-MH 32-/40-B 8-/16-/32-/64-B

TMS320C642x

Abstract: aeg td Interface Conforms to PCI Specification 2.3 Please be aware that an important notice concerning , Interfaces (MII, RMII) ­ Management Data Input/Output (MDIO) Module VLYNQTM Interface (FPGA Interface , Behavior. 128 6.3 6.4 Revision History , Fixed-Point Digital Signal Processor www.ti.com SPRS347A ­ MARCH 2007 ­ REVISED APRIL 2007 Revision History This data manual revision history highlights the technical changes made to the SPRS347
Texas Instruments
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TMS320C642x aeg td AC97 AIC12 C6000 TMS320C6000

SPRS276

Abstract: rgmii timing Interconnect (PCI) Master/Slave Interface Conforms to PCI Local Bus Specification (version 2.3) One , Supports Multiple Media Independent Interfaces (MII, GMII, RMII, and RGMII) ­ 8 Independent Transmit (TX , ) PCI66(B) UTOPIA(B) EMAC 10/100/1000 MII RMII GMII RMGII(D) MDIO 16 Primary Switched Central Resource , . 5.5 Megamodule Resets . 5.6 Megamodule Revision , JTAG . Revision History . 8
Texas Instruments
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SPRS276 rgmii timing DEA10 SPRS276E 720-MH 256K-B 32K-B 16M-B 2096K-B
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