500 MILLION PARTS FROM 12000 MANUFACTURERS

DATASHEET SEARCH ENGINE

Top Results

Part Manufacturer Description Datasheet BUY
CS5371A-ISZ Cirrus Logic Telecom Circuit, 1-Func, PDSO24, LEAD FREE, SSOP-24 visit Digikey
CS5372A-ISZ Cirrus Logic Telecom Circuit, 1-Func, PDSO24, LEAD FREE, SSOP-24 visit Digikey
CS5371-BSZ Cirrus Logic Telecom Circuit, 1-Func, PDSO24, LEAD FREE, SSOP-24 BUY
CS61884-IB Cirrus Logic PCM Transceiver, 1-Func, CEPT PCM-30/E-1, CMOS, PBGA160, FBGA-160 BUY
CS5374-CNZ Cirrus Logic Telecom Circuit, 2-Func, 7 X 7 MM, LEAD FREE, QFN-48 BUY
CS6422-CSZ Cirrus Logic Speaker Phone Circuit, PDSO20, 0.300 INCH, LEAD FREE, MS-013, SOIC-20 BUY

RMII Specification revision 1.2

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: specifics of this signal are available in the RMII Specification Revision 1.2. I TRANSMIT ERROR: - , RMII Specification Revision 1.2. RECEIVE DATA VALID: - RXDVn is asserted high to indicate that valid , on the specifics of this signal are available in the RMII Specification Revision 1.2. RECEIVE , RMII Specification published by the RMII Consortium. The intent of the RMII is to provide a reduced , false carrier event. Details on the specifics of this signal are available in the RMII Specification TDK
Original
IC 7809 pin diagram datasheet ic 7809 sd 7809 ic 7809 datasheet RMII Specification the RMII Consortium Specification 78Q2124/R 10/100BASE-TX/FX 78Q2124 78Q2124R IEEE-802 10BASE-T/100BASE-TX
Abstract: · RMII Specification Revision 1.2, RMII Consortium, March 20, 1998 · POS-PHY Saturn , L IM IN A R Y Revision 1.1 Entridia Corporation 131 Theory, Suite 150 Irvine, CA 92612 , respective owners. R E Revision History L 1.1 10/30/00 Description of Changes Update for Revision EB design: - Subnet broadcasts for Ethernet and OC-3 ports - TTL0/1 handling for , Ethernet port - Flow Table Layer 1 transaction revision - Layer 2 Tx/Rx Tag mode for Ethernet port - Tx Entridia
Original
ENT3041 PMC-971147 RFC-1042 RFC1042 RMII PHY
Abstract: ) . 74 Package Specification . 75 Revision History , .166 specification. This interface is suitable for driving a fiber-optic coupler. Network I/F RMII DATA I/F , Data Sheet MARCH, 2000 Revision 1.1 LXT9761 / 9781 General Description The LXT9781 is an , and 100 Mbps. It provides a Reduced Media Independent Interface (RMII) for switching and other , requires only a single 3.3V power supply. Fast Ethernet 10/100 Multi-Port Transceiver with RMII Intel
Original
100base 30 PIN duplex led display duplex clock led display duplex display led LXT9781HC LXT97 10/100BASE-TX 100BASE-FX 10BASE-T 100BASE-TX ISLXT9761/81DS
Abstract: LXT9761/9781 Fast Ethernet 10/100 Multi-Port Transceiver with RMII Datasheet The LXT9781 is an , Mbps and 100 Mbps. It provides a Reduced Media Independent Interface (RMII) for switching and other , auto-negotiation capability JTAG boundary scan Multiple Reduced MII (RMII) ports for independent PHY port , Multi-Port Transceiver with RMII. Order Number: 249048-001 January 2001 Information in this document , Multi-Port Transceiver with RMII - LXT9761/9781 Contents 1.0 Pin Assignments and Signal Descriptions Intel
Original
100BASE-T 10/100-TX 208-P LXT9761HC 272-L LXT9781BC
Abstract: ) . 74 Package Specification . 75 Revision History , .166 specification. This interface is suitable for driving a fiber-optic coupler. Network I/F RMII DATA I/F , Data Sheet - Preliminary Information OCTOBER, 1999 Revision 1.0 LXT9761 / 9781 General , layer applications at both 10 Mbps and 100 Mbps. It provides a Reduced Media Independent Interface (RMII , Multi-Port Transceiver with RMII Features · Six or eight IEEE 802.3-compliant 10BASE-T or 100BASE-TX ports Intel
Original
Abstract: Serial Media Independent Interfaces (SMII/SS-SMII) and Reduced Media Independent Interface (RMII) for , . Multiple RMII or SMII/SS-SMII ports for independent PHY port operation. Auto MDI/MDIX crossover , Extended temperature operation of -40oC to +85oC (LXT9785HE). Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH , Datasheet Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 Contents Intel
Original
LXT9785 LXT9785E HBLXT9785HE GDLXT9785MBC LXT9785EHC HBLXT9785HE.D0 TS-42 reset FWLXT9785BC.D0 HBLXT9785EHC LXT97985E LXT9785/LXT9785E FWLXT9785EBC
Abstract: Synchronous Serial Media Independent Interfaces (SMII/SS-SMII) and Reduced Media Independent Interface (RMII , typical. Multiple RMII or SMII/SS-SMII ports for independent PHY port operation. Auto MDI/MDIX , of -40 oC to +85 oC (LXT9785E only). LXT9785/LXT9785E Datasheet 249241, Revision 11.0 16 , .20 3.1.1 PQFP Pin Assignments ­ RMII Configuration , .36 3.2.2 PQFP Signal Descriptions ­ RMII, SMII, and SS-SMII Configurations Cortina Systems
Original
1000base-t MDI LXT9785HC IP168 BGA 31 x 31 tray 785HC WBLXT9785HE 9785E LXT9785MBC
Abstract: Interfaces (SMII/SS-SMII) and Reduced Media Independent Interface (RMII) for switching and other independent , power consumption; 250 mW per port typical. Multiple RMII or SMII/SS-SMII ports for independent PHY port , +85 oC (LXT9785E only). Document Number: 249241 Revision Number: 010 Revision Date: 30 , Datasheet Document Number: 249241 Revision Number: 010 Revision Date: 30-May-2006 Contents Contents , . 19 3.1.1 PQFP Pin Assignments ­ RMII Configuration Intel
Original
FWLXT9785BC.C2V WBLXT9785HC.D0 WBLXT9785HC PRLXT9785BC HBLXT9785 B3408
Abstract: Independent Interfaces (SMII/SS-SMII) and Reduced Media Independent Interface (RMII) for switching and other , . 2.5 V operation. Low power consumption; 250 mW per port typical. Multiple RMII or SMII/SS-SMII , only). Document Number: 249241 Revision Number: 009 Revision Date: April 30, 2004 INFORMATION , Corporation 2 Datasheet Document Number: 249241 Revision Number: 009 Revision Date: April 30, 2004 , . 19 3.1.1 PQFP Pin Assignments ­ RMII Configuration Intel
Original
B3408-01 n14 167 LXT9785EBC i386 SL c 4744 GDLXT9785MBC.D0
Abstract: Synchronous Serial Media Independent Interfaces (SMII/SS-SMII) and Reduced Media Independent Interface (RMII , ; 250 mW per port typical. Multiple RMII or SMII/SS-SMII ports for independent PHY port operation. Auto , temperature operation of -40 oC to +85 oC (LXT9785E only). 249241, Revision 12.0 LXT9785/LXT9785E Datasheet 249241, Revision 12.0 04 November 2011 Legal Disclaimers INFORMATION IN THIS DOCUMENT IS , Transceivers Page 2 LXT9785/LXT9785E Datasheet 249241, Revision 12.0 04 November 2011 Contents Cortina Systems
Original
T3 SL 100B PRLXT9785C B3368-01
Abstract: Media Independent Interfaces (SMII/SS-SMII) and Reduced Media Independent Interface (RMII) for switching , typical. Multiple RMII or SMII/SS-SMII ports for independent PHY port operation. Auto MDI/MDIX crossover , +85 oC (LXT9785E only). LXT9785/LXT9785E Datasheet 249241, Revision 11.0 16 April 2007 Contents , .20 3.1.1 PQFP Pin Assignments ­ RMII Configuration , .36 3.2.2 PQFP Signal Descriptions ­ RMII, SMII, and SS-SMII Configurations.36 BGA23 Cortina Systems
Original
GWLXT9785BC 865114 level one and bob smith termination GDLXT9785MBC.D0-854705 WBLXT9785HE.D0 D0-865114 D0-865115 D0-865112 D0-865113 WBLXT9785EHC D0-865110
Abstract: Synchronous Serial Media Independent Interfaces (SMII/SS-SMII) and Reduced Media Independent Interface (RMII , typical. Multiple RMII or SMII/SS-SMII ports for independent PHY port operation. Auto MDI/MDIX , of -40 oC to +85 oC (LXT9785E only). LXT9785/LXT9785E Datasheet 249241, Revision 11.0 16 , .20 3.1.1 PQFP Pin Assignments ­ RMII Configuration , .36 3.2.2 PQFP Signal Descriptions ­ RMII, SMII, and SS-SMII Configurations Cortina Systems
Original
SMII-10BASE-T bga236-1 Balun Transformers
Abstract: provides both Serial/Source Synchronous (SMII/SS-SMII) and Reduced Media Independent (RMII) Interfaces for , auto-negotiation capability. s s s s s s s JTAG boundary scan. Multiple RMII or SMII/SS-SMII ports , 2.3.3 RMII , . 68 2.7.5.1 Source Synchronous SMII. 70 RMII , . 74 2.8.1 RMII Reference Clock Intel
Original
LXT9785BC 8029 l2 circuit RJ-45 241-B
Abstract: /SS-SMII) and Reduced Media Independent Interface (RMII) for switching and other independent port , operation. Low power consumption; 250 mW per port typical. Multiple RMII or SMII/SS-SMII ports for , respective owners. 2 Datasheet Document #: 249241 Revision #: 005 Rev. Date: January 24, 2002 , . 55 2.3.3 RMII Data Interface , . 63 Datasheet Document #: 249241 Revision #: 005 Rev. Date: January 24, 2002 3 Intel
Original
hp dv6 249241 4939n LXT9785/9785E HBLXT9785HC FWLXT9785BC
Abstract: /SS-SMII) and Reduced Media Independent Interface (RMII) for switching and other independent port , operation. Low power consumption; 250 mW per port typical. Multiple RMII or SMII/SS-SMII ports for , Datasheet Document #: 249241 Revision #: 003 Rev. Date: 04/19/01 Contents Contents 1.0 Pin , . 54 2.3.3 RMII Data Interface , . 62 Datasheet Document #: 249241 Revision #: 003 Rev. Date: 04/19/01 3 Contents 2.7 Intel
Original
ss smii sl r7 MAC data and non-data symbols bob smith termination aui isolation transformer PIN assignments of UTP cables LXT9785BC/
Abstract: ) Master/Slave Interface Conforms to PCI Specification 2.3 One Inter-Integrated Circuit (I2C) Bus Two , '" Supports Multiple Media Independent Interfaces (MII, GMII, RMII, and RGMII) â'" 8 Independent Transmit , ) MII RMII L1P Memory Controller (Memory Protect/Bandwidth Mgmt) GMII RMGII(E) MDIO 16 L1D , . 2.9 Device Silicon Revision . Device Configurations , /Output (GPIO) . 175 6.26 IEEE 1149.1 JTAG . 178 Revision Texas Instruments
Original
TMS320C6455 SPRS276A C6455 850-MH TMS320C64 32-/16-B
Abstract: Interface Conforms to PCI Specification 2.3 One Inter-Integrated Circuit (I2C) Bus Two Multichannel Buffered , Media Independent Interfaces (MII, GMII, RMII, and RGMII) ­ 8 Independent Transmit (TX) and 8 , /1000 MII RMII GMII RMGII(E) MDIO GPIO16(C) I2C Timer1(D) HI LO Timer0(D) HI LO Switched Central , 175 6.26 IEEE 1149.1 JTAG . 178 Revision History , . 2.9 Device Silicon Revision . Device Configurations Texas Instruments
Original
SPRAAA8 TMS320C6455 rapid io 125-G IEEE-1149 697-P
Abstract: Specification 2.3 · · · · · · · · · · · · Please be aware that an important notice concerning , (EMAC) ­ IEEE 802.3 Compliant ­ Supports Multiple Media Independent Interfaces (MII, RMII) ­ Management , ) External Clock Input From MXI/CLKIN Pin Revision History . , www.ti.com Revision History This data manual revision history highlights the technical changes made to the SPRS347 device-specific data manual to make it an SPRS347A revision. Scope: Applicable updates to Texas Instruments
Original
TMS320C6424 C6424 600-MH 32-/40-B 8-/16-/32-/64-B
Abstract: Interface Conforms to PCI Specification 2.3 Please be aware that an important notice concerning , Interfaces (MII, RMII) ­ Management Data Input/Output (MDIO) Module VLYNQTM Interface (FPGA Interface , Behavior. 128 6.3 6.4 Revision History , Fixed-Point Digital Signal Processor www.ti.com SPRS347A ­ MARCH 2007 ­ REVISED APRIL 2007 Revision History This data manual revision history highlights the technical changes made to the SPRS347 Texas Instruments
Original
aeg td TMS320C642x AC97 AIC12 C6000 gp-105
Abstract: Interconnect (PCI) Master/Slave Interface Conforms to PCI Local Bus Specification (version 2.3) One , Supports Multiple Media Independent Interfaces (MII, GMII, RMII, and RGMII) ­ 8 Independent Transmit (TX , ) PCI66(B) UTOPIA(B) EMAC 10/100/1000 MII RMII GMII RMGII(D) MDIO 16 Primary Switched Central Resource , . 5.5 Megamodule Resets . 5.6 Megamodule Revision , JTAG . Revision History . 8 Texas Instruments
Original
DEA10 rgmii timing SPRS276 SPRS276E 720-MH 256K-B 32K-B 16M-B 2096K-B
Showing first 20 results.