REJ09B0413-0200 H8SX/1658R H8SX/1658M H8SX/1600 H8SX/1654R H8SX/1653R - Datasheet Archive

 

The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and

 

REJ09B0413-0200 REJ09B0413-0200 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. 32 H8SX/1658R H8SX/1658R Group, H8SX/1658M H8SX/1658M Group Hardware Manual Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 H8SX/1600 Series H8SX/1658R H8SX/1658R H8SX/1654R H8SX/1654R H8SX/1653R H8SX/1653R H8SX/1658M H8SX/1658M H8SX/1654M H8SX/1654M H8SX/1653M H8SX/1653M R5F61658R R5F61658R R5F61654R R5F61654R R5F61653R R5F61653R R5F61658M R5F61658M R5F61654M R5F61654M R5F61653M R5F61653M All information contained in this material, including products and product specifications at the time of publication of this material, is subject to change by Renesas Technology Corp. without notice. Please review the latest information published by Renesas Technology Corp. through various means, including the Renesas Technology Corp. website (http://www.renesas.com). Rev.2.00 Revision Date: Sep. 25, 2008 Rev. 2.00 Sep. 25, 2008 Page ii of xxx Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. Rev. 2.00 Sep. 25, 2008 Page iii of xxx General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited. The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized. When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different type number, confirm that the change will not lead to problems. The characteristics of MPU/MCU in the same group but having different type numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different type numbers, implement a system-evaluation test for each of the products. Rev. 2.00 Sep. 25, 2008 Page iv of xxx How to Use This Manual 1. Objective and Target Users This manual was written to explain the hardware functions and electrical characteristics of this LSI to the target users, i.e. those who will be using this LSI in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logic circuits, and microcomputers. This manual is organized in the following items: an overview of the product, descriptions of the CPU, system control functions, and peripheral functions, electrical characteristics of the device, and usage notes. When designing an application system that includes this LSI, take all points to note into account. Points to note are given in their contexts and at the final part of each section, and in the section giving usage notes. The list of revisions is a summary of major points of revision or addition for earlier versions. It does not cover all revised items. For details on the revised points, see the actual locations in the manual. The following documents have been prepared for the H8SX/1658R H8SX/1658R Group and the H8SX/1658M H8SX/1658M Group. Before using any of the documents, please visit our web site to verify that you have the most up-to-date available version of the document. Document Type Contents Document Title Document No. Data Sheet Overview of hardware and electrical characteristics Hardware Manual Hardware specifications (pin assignments, memory maps, peripheral specifications, electrical characteristics, and timing charts) and descriptions of operation H8SX/1658R H8SX/1658R, H8SX/1658M H8SX/1658M Group Hardware Manual This manual Software Manual Detailed descriptions of the CPU and instruction set H8SX Family Software Manual REJ09B0102 REJ09B0102 Application Note Examples of applications and sample programs The latest versions are available from our web site. Renesas Technical Update Preliminary report on the specifications of a product, document, etc. Rev. 2.00 Sep. 25, 2008 Page v of xxx 2. Description of Numbers and Symbols Aspects of the notations for register names, bit names, numbers, and symbolic names in this manual are explained below. (1) Overall notation In descriptions involving the names of bits and bit fields within this manual, the modules and registers to which the bits belong may be clarified by giving the names in the forms "module name"."register name"."bit name" or "register name"."bit name". (2) Register notation The style "register name"_"instance number" is used in cases where there is more than one instance of the same function or similar functions. [Example] CMCSR_0: Indicates the CMCSR register for the compare-match timer of channel 0. (3) Number notation Binary numbers are given as B'nnnn (B' may be omitted if the number is obviously binary), hexadecimal numbers are given as H'nnnn or 0xnnnn, and decimal numbers are given as nnnn. [Examples] Binary: B'11 or 11 Hexadecimal: H'EFA0 or 0xEFA0 Decimal: 1234 (4) Notation for active-low An overbar on the name indicates that a signal or pin is active-low. [Example] WDTOVF (4) (2) 14.2.2 Compare Match Control/Status Register_0, _1 (CMCSR_0, CMCSR_1) CMCSR indicates compare match generation, enables or disables interrupts, and selects the counter input clock. Generation of a WDTOVF signal or interrupt initializes the TCNT value to 0. 14.3 Operation 14.3.1 Interval Count Operation When an internal clock is selected with the CKS1 and CKS0 bits in CMCSR and the STR bit in CMSTR is set to 1, CMCNT starts incrementing using the selected clock. When the values in CMCNT and the compare match constant register (CMCOR) match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1. When the CKS1 and CKS0 bits are set to B'01 at this time, a f/4 clock is selected. Rev. 0.50, 10/04, page 416 of 914 (3) Note: The bit names and sentences in the above figure are examples and have nothing to do with the contents of this manual. Rev. 2.00 Sep. 25, 2008 Page vi of xxx 3. Description of Registers Each register description includes a bit chart, illustrating the arrangement of bits, and a table of bits, describing the meanings of the bit settings. The standard format and notation for bit charts and tables are described below. [Bit Chart] Bit: 15 Initial value: R/W: 14 13 12 11 ASID2 ASID1 ASID0 10 9 8 7 6 5 4 Q 3 2 1 ACMP2 ACMP1 ACMP0 0 IFE 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W (1) [Table of Bits] Bit (2) (3) (4) (5) Bit Name - - Initial Value R/W 0 0 R R Reserved These bits are always read as 0. 13 to 11 ASID2 to ASID0 All 0 R/W Address Identifier These bits enable or disable the pin function. 10 - 0 R Reserved This bit is always read as 0. 9 - 1 R Reserved This bit is always read as 1. - 0 15 14 Description Note: The bit names and sentences in the above figure are examples, and have nothing to do with the contents of this manual. (1) Bit Indicates the bit number or numbers. In the case of a 32-bit register, the bits are arranged in order from 31 to 0. In the case of a 16-bit register, the bits are arranged in order from 15 to 0. (2) Bit name Indicates the name of the bit or bit field. When the number of bits has to be clearly indicated in the field, appropriate notation is included (e.g., ASID[3:0]). A reserved bit is indicated by "-". Certain kinds of bits, such as those of timer counters, are not assigned bit names. In such cases, the entry under Bit Name is blank. (3) Initial value Indicates the value of each bit immediately after a power-on reset, i.e., the initial value. 0: The initial value is 0 1: The initial value is 1 -: The initial value is undefined (4) R/W For each bit and bit field, this entry indicates whether the bit or field is readable or writable, or both writing to and reading from the bit or field are impossible. The notation is as follows: R/W: The bit or field is readable and writable. R/(W): The bit or field is readable and writable. However, writing is only performed to flag clearing. R: The bit or field is readable. "R" is indicated for all reserved bits. When writing to the register, write the value under Initial Value in the bit chart to reserved bits or fields. W: The bit or field is writable. (5) Description Describes the function of the bit or field and specifies the values for writing. Rev. 2.00 Sep. 25, 2008 Page vii of xxx 4. Description of Abbreviations The abbreviations used in this manual are listed below. · Abbreviations specific to this product Abbreviation Description BSC Bus controller CPG DTC INTC PPG SCI TMR Clock pulse generator Data transfer controller Interrupt controller Programmable pulse generator Serial communications interface 8-bit timer TPU WDT 16-bit timer pulse unit Watchdog timer · Abbreviations other than those listed above Abbreviation Description ACIA Asynchronous communications interface adapter bps CRC DMA DMAC GSM Hi-Z IEBus I/O IrDA LSB MSB NC PLL Bits per second Cyclic redundancy check Direct memory access Direct memory access controller Global System for Mobile Communications High impedance Inter Equipment Bus (IEBus is a trademark of NEC Electronics Corporation.) Input/output Infrared Data Association Least significant bit Most significant bit No connection Phase-locked loop PWM SFR SIM UART VCO Pulse width modulation Special function register Subscriber Identity Module Universal asynchronous receiver/transmitter Voltage-controlled oscillator All trademarks and registered trademarks are the property of their respective owners. Rev. 2.00 Sep. 25, 2008 Page viii of xxx Contents Section 1 Overview.1 1.1 1.2 1.3 1.4 Features. 1 1.1.1 Applications . 1 1.1.2 Overview of Functions. 2 List of Products. 9 Block Diagram. 11 Pin Assignments . 12 1.4.1 Pin Assignments . 12 1.4.2 Correspondence between Pin Configuration and Operating Modes . 13 1.4.3 Pin Functions . 19 Section 2 CPU.25 2.1 2.2 2.3 2.4 2.5 2.6 2.7 Features. 25 CPU Operating Modes. 27 2.2.1 Normal Mode. 27 2.2.2 Middle Mode. 29 2.2.3 Advanced Mode. 30 2.2.4 Maximum Mode . 31 Instruction Fetch . 33 Address Space. 33 Registers . 34 2.5.1 General Registers. 35 2.5.2 Program Counter (PC) . 36 2.5.3 Condition-Code Register (CCR). 37 2.5.4 Extended Control Register (EXR) . 38 2.5.5 Vector Base Register (VBR). 39 2.5.6 Short Address Base Register (SBR). 39 2.5.7 Multiply-Accumulate Register (MAC) . 39 2.5.8 Initial Values of CPU Registers . 39 Data Formats. 40 2.6.1 General Register Data Formats . 40 2.6.2 Memory Data Formats . 42 Instruction Set . 43 2.7.1 Instructions and Addressing Modes. 45 2.7.2 Table of Instructions Classified by Function . 49 2.7.3 Basic Instruction Formats . 59 Rev. 2.00 Sep. 25, 2008 Page ix of xxx 2.8 2.9 Addressing Modes and Effective Address Calculation. 60 2.8.1 Register Direct-Rn . 60 2.8.2 Register Indirect-@ERn. 61 2.8.3 Register Indirect with Displacement -@(d:2, ERn), @(d:16, ERn), or @(d:32, ERn). 61 2.8.4 Index Register Indirect with Displacement-@(d:16,RnL.B), @(d:32,RnL.B), @(d:16,Rn.W), @(d:32,Rn.W), @(d:16,ERn.L), or @(d:32,ERn.L) . 61 2.8.5 Register Indirect with Post-Increment, Pre-Decrement, Pre-Increment, or Post-Decrement-@ERn+, @-ERn, @+ERn, or @ERn-. 62 2.8.6 Absolute Address-@aa:8, @aa:16, @aa:24, or @aa:32. 63 2.8.7 Immediate-#xx . 64 2.8.8 Program-Counter Relative-@(d:8, PC) or @(d:16, PC) . 64 2.8.9 Program-Counter Relative with Index Register-@(RnL.B, PC), @(Rn.W, PC), or @(ERn.L, PC). 64 2.8.10 Memory Indirect-@@aa:8 . 65 2.8.11 Extended Memory Indirect-@@vec:7 . 66 2.8.12 Effective Address Calculation . 66 2.8.13 MOVA Instruction. 68 Processing States . 69 Section 3 MCU Operating Modes . 71 3.1 3.2 3.3 3.4 Operating Mode Selection . 71 Register Descriptions. 73 3.2.1 Mode Control Register (MDCR) . 73 3.2.2 System Control Register (SYSCR). 75 Operating Mode Descriptions . 77 3.3.1 Mode 1. 77 3.3.2 Mode 2. 77 3.3.3 Mode 3. 77 3.3.4 Mode 4. 77 3.3.5 Mode 5. 78 3.3.6 Mode 6. 78 3.3.7 Mode 7. 78 3.3.8 Pin Functions . 79 Address Map. 79 3.4.1 Address Map. 79 Section 4 Reset . 87 4.1 Types of Reset . 87 Rev. 2.00 Sep. 25, 2008 Page x of xxx 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 Input/Output Pin . 89 Register Descriptions. 90 4.3.1 Reset Status Register (RSTSR). 90 4.3.2 Reset Control/Status Register (RSTCSR). 92 Pin Reset . 93 Power-on Reset (POR) (H8SX/1658M H8SX/1658M Group) . 93 Power Supply Monitoring Reset (H8SX/1658M H8SX/1658M Group). 94 Deep Software Standby Reset. 95 Watchdog Timer Reset . 95 Determination of Reset Generation Source. 95 Section 5 Voltage Detection Circuit (LVD) .97 5.1 5.2 5.3 Features. 97 Register Descriptions. 98 5.2.1 Voltage Detection Control Register (LVDCR). 98 5.2.2 Reset Status Register (RSTSR). 99 Voltage Detection Circuit . 101 5.3.1 Voltage Monitoring Reset. 101 5.3.2 Voltage Monitoring Interrupt. 102 5.3.3 Release from Deep Software Standby Mode by the Voltage-Detection Circuit . 104 5.3.4 Voltage Monitor. 104 Section 6 Exception Handling .105 6.1 6.2 6.3 6.4 6.5 6.6 6.7 Exception Handling Types and Priority. 105 Exception Sources and Exception Handling Vector Table . 106 Reset . 108 6.3.1 Reset Exception Handling. 108 6.3.2 Interrupts after Reset. 109 6.3.3 On-Chip Peripheral Functions after Reset Release . 109 Traces. 111 Address Error. 112 6.5.1 Address Error Source. 112 6.5.2 Address Error Exception Handling . 114 Interrupts. 116 6.6.1 Interrupt Sources. 116 6.6.2 Interrupt Exception Handling . 116 Instruction Exception Handling . 117 6.7.1 Trap Instruction. 117 6.7.2 Sleep Instruction Exception Handling . 118 Rev. 2.00 Sep. 25, 2008 Page xi of xxx 6.8 6.9 6.7.3 Exception Handling by Illegal Instruction . 119 Stack Status after Exception Handling . 120 Usage Note . 121 Section 7 Interrupt Controller. 123 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 Features. 123 Input/Output Pins. 125 Register Descriptions. 125 7.3.1 Interrupt Control Register (INTCR) . 126 7.3.2 CPU Priority Control Register (CPUPCR) . 127 7.3.3 Interrupt Priority Registers A to C, E to O, Q, and R (IPRA to IPRC, IPRE to IPRO, IPRQ, and IPRR). 129 7.3.4 IRQ Enable Register (IER) . 131 7.3.5 IRQ Sense Control Registers H and L (ISCRH, ISCRL). 133 7.3.6 IRQ Status Register (ISR). 138 7.3.7 Software Standby Release IRQ Enable Register (SSIER) . 140 Interrupt Sources. 141 7.4.1 External Interrupts . 141 7.4.2 Internal Interrupts . 142 Interrupt Exception Handling Vector Table. 143 Interrupt Control Modes and Interrupt Operation. 149 7.6.1 Interrupt Control Mode 0. 149 7.6.2 Interrupt Control Mode 2. 151 7.6.3 Interrupt Exception Handling Sequence . 153 7.6.4 Interrupt Response Times . 154 7.6.5 DTC and DMAC Activation by Interrupt . 155 CPU Priority Control Function Over DTC, DMAC, and EXDMAC . 158 Usage Notes . 161 7.8.1 Conflict between Interrupt Generation and Disabling . 161 7.8.2 Instructions that Disable Interrupts. 162 7.8.3 Times when Interrupts are Disabled . 162 7.8.4 Interrupts during Execution of EEPMOV Instruction . 162 7.8.5 Interrupts during Execution of MOVMD and MOVSD Instructions. 162 7.8.6 Interrupts of Peripheral Modules . 163 Section 8 User Break Controller (UBC). 165 8.1 8.2 8.3 Features. 165 Block Diagram. 166 Register Descriptions. 167 8.3.1 Break Address Register n (BARA, BARB, BARC, BARD) . 168 Rev. 2.00 Sep. 25, 2008 Page xii of xxx 8.4 8.5 8.3.2 Break Address Mask Register n (BAMRA, BAMRB, BAMRC, BAMRD) . 169 8.3.3 Break Control Register n (BRCRA, BRCRB, BRCRC, BRCRD) . 170 Operation . 172 8.4.1 Setting of Break Control Conditions. 172 8.4.2 PC Break. 172 8.4.3 Condition Match Flag . 173 Usage Notes . 174 Section 9 Bus Controller (BSC).177 9.1 9.2 9.3 9.4 9.5 9.6 Features. 177 Register Descriptions. 180 9.2.1 Bus Width Control Register (ABWCR). 181 9.2.2 Access State Control Register (ASTCR) . 182 9.2.3 Wait Control Registers A and B (WTCRA, WTCRB) . 183 9.2.4 Read Strobe Timing Control Register (RDNCR) . 188 9.2.5 CS Assertion Period Control Registers (CSACR) . 189 9.2.6 Idle Control Register (IDLCR) . 192 9.2.7 Bus Control Register 1 (BCR1) . 194 9.2.8 Bus Control Register 2 (BCR2) . 196 9.2.9 Endian Control Register (ENDIANCR). 197 9.2.10 SRAM Mode Control Register (SRAMCR) . 198 9.2.11 Burst ROM Interface Control Register (BROMCR). 199 9.2.12 Address/Data Multiplexed I/O Control Register (MPXCR) . 201 Bus Configuration. 202 Multi-Clock Function and Number of Access Cycles . 203 External Bus. 207 9.5.1 Input/Output Pins. 207 9.5.2 Area Division. 210 9.5.3 Chip Select Signals . 211 9.5.4 External Bus Interface. 212 9.5.5 Area and External Bus Interface . 216 9.5.6 Endian and Data Alignment. 221 Basic Bus Interface . 224 9.6.1 Data Bus. 224 9.6.2 I/O Pins Used for Basic Bus Interface . 224 9.6.3 Basic Timing. 225 9.6.4 Wait Control . 231 9.6.5 Read Strobe (RD) Timing. 233 9.6.6 Extension of Chip Select (CS) Assertion Period. 234 9.6.7 DACK and EDACK Signal Output Timings . 236 Rev. 2.00 Sep. 25, 2008 Page xiii of xxx 9.7 9.8 9.9 9.10 9.11 9.12 9.13 Byte Control SRAM Interface . 237 9.7.1 Byte Control SRAM Space Setting. 237 9.7.2 Data Bus . 237 9.7.3 I/O Pins Used for Byte Control SRAM Interface . 238 9.7.4 Basic Timing. 239 9.7.5 Wait Control . 241 9.7.6 Read Strobe (RD) . 243 9.7.7 Extension of Chip Select (CS) Assertion Period. 243 9.7.8 DACK and EDACK Signal Output Timings . 243 Burst ROM Interface . 245 9.8.1 Burst ROM Space Setting. 245 9.8.2 Data Bus . 245 9.8.3 I/O Pins Used for Burst ROM Interface. 246 9.8.4 Basic Timing. 247 9.8.5 Wait Control . 249 9.8.6 Read Strobe (RD) Timing. 249 9.8.7 Extension of Chip Select (CS) Assertion Period. 249 Address/Data Multiplexed I/O Interface. 250 9.9.1 Address/Data Multiplexed I/O Space Setting . 250 9.9.2 Address/Data Multiplex. 250 9.9.3 Data Bus . 250 9.9.4 I/O Pins Used for Address/Data Multiplexed I/O Interface. 251 9.9.5 Basic Timing. 252 9.9.6 Address Cycle Control. 254 9.9.7 Wait Control . 255 9.9.8 Read Strobe (RD) Timing. 255 9.9.9 Extension of Chip Select (CS) Assertion Period. 257 9.9.10 DACK and EDACK Signal Output Timings . 259 Idle Cycle. 260 9.10.1 Operation . 260 9.10.2 Pin States in Idle Cycle. 269 Bus Release. 270 9.11.1 Operation . 270 9.11.2 Pin States in External Bus Released State . 271 9.11.3 Transition Timing . 272 Internal Bus. 273 9.12.1 Access to Internal Address Space . 273 Write Data Buffer Function . 274 9.13.1 Write Data Buffer Function for External Data Bus . 274 9.13.2 Write Data Buffer Function for Peripheral Modules . 275 Rev. 2.00 Sep. 25, 2008 Page xiv of xxx 9.14 9.15 9.16 Bus Arbitration . 276 9.14.1 Operation . 276 9.14.2 Bus Transfer Timing . 277 Bus Controller Operation in Reset . 280 Usage Notes . 280 Section 10 DMA Controller (DMAC) .283 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 Features. 283 Input/Output Pins. 286 Register Descriptions. 287 10.3.1 DMA Source Address Register (DSAR). 288 10.3.2 DMA Destination Address Register (DDAR). 289 10.3.3 DMA Offset Register (DOFR). 290 10.3.4 DMA Transfer Count Register (DTCR) . 291 10.3.5 DMA Block Size Register (DBSR) . 292 10.3.6 DMA Mode Control Register (DMDR). 293 10.3.7 DMA Address Control Register (DACR) . 302 10.3.8 DMA Module Request Select Register (DMRSR) . 308 Transfer Modes . 309 Operations. 310 10.5.1 Address Modes . 310 10.5.2 Transfer Modes . 314 10.5.3 Activation Sources. 319 10.5.4 Bus Access Modes . 321 10.5.5 Extended Repeat Area Function . 323 10.5.6 Address Update Function using Offset . 326 10.5.7 Register during DMA Transfer . 330 10.5.8 Priority of Channels . 335 10.5.9 DMA Basic Bus Cycle. 337 10.5.10 Bus Cycles in Dual Address Mode . 338 10.5.11 Bus Cycles in Single Address Mode. 347 DMA Transfer End . 352 Relationship among DMAC and Other Bus Masters . 355 10.7.1 CPU Priority Control Function Over DMAC . 355 10.7.2 Bus Arbitration among DMAC and Other Bus Masters . 356 Interrupt Sources. 357 Usage Notes . 360 Section 11 EXDMA Controller (EXDMAC) .361 11.1 Features. 361 Rev. 2.00 Sep. 25, 2008 Page xv of xxx 11.2 11.3 Input/Output Pins. 364 Registers Descriptions . 365 11.3.1 EXDMA Source Address Register (EDSAR). 367 11.3.2 EXDMA Destination Address Register (EDDAR). 368 11.3.3 EXDMA Offset Register (EDOFR). 369 11.3.4 EXDMA Transfer Count Register (EDTCR). 370 11.3.5 EXDMA Block Size Register (EDBSR). 371 11.3.6 EXDMA Mode Control Register (EDMDR) . 372 11.3.7 EXDMA Address Control Register (EDACR) . 381 11.3.8 Cluster Buffer Registers 0 to 7 (CLSBR0 to CLSBR7). 387 11.4 Transfer Modes. 388 11.4.1 Ordinary Modes . 388 11.4.2 Cluster Transfer Modes . 389 11.5 Mode Operation . 390 11.5.1 Address Modes . 390 11.5.2 Transfer Modes. 394 11.5.3 Activation Sources. 399 11.5.4 Bus Mode. 400 11.5.5 Extended Repeat Area Function . 401 11.5.6 Address Update Function Using Offset . 404 11.5.7 Registers during EXDMA Transfer Operation . 408 11.5.8 Channel Priority Order. 413 11.5.9 Basic Bus Cycles . 414 11.5.10 Bus Cycles in Dual Address Mode . 415 11.5.11 Bus Cycles in Single Address Mode. 424 11.5.12 Operation Timing in Each Mode . 429 11.6 Operation in Cluster Transfer Mode . 440 11.6.1 Address Mode. 440 11.6.2 Setting of Address Update Mode. 445 11.6.3 Caution for Combining with Extended Repeat Area Function . 446 11.6.4 Bus Cycles in Cluster Transfer Dual Address Mode . 446 11.6.5 Operation Timing in Cluster Transfer Mode . 449 11.7 Ending EXDMA Transfer. 457 11.8 Relationship among EXDMAC and Other Bus Masters. 460 11.8.1 CPU Priority Control Function Over EXDMAC . 460 11.8.2 Bus Arbitration with Another Bus Master . 461 11.9 Interrupt Sources. 462 11.10 Usage Notes . 465 Rev. 2.00 Sep. 25, 2008 Page xvi of xxx Section 12 Data Transfer Controller (DTC) .467 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 Features. 467 Register Descriptions. 469 12.2.1 DTC Mode Register A (MRA) . 470 12.2.2 DTC Mode Register B (MRB). 471 12.2.3 DTC Source Address Register (SAR). 472 12.2.4 DTC Destination Address Register (DAR). 473 12.2.5 DTC Transfer Count Register A (CRA) . 473 12.2.6 DTC Transfer Count Register B (CRB). 474 12.2.7 DTC enable registers A to F (DTCERA to DTCERF). 474 12.2.8 DTC Control Register (DTCCR) . 475 12.2.9 DTC Vector Base Register (DTCVBR). 477 Activation Sources. 477 Location of Transfer Information and DTC Vector Table . 477 Operation . 482 12.5.1 Bus Cycle Division . 484 12.5.2 Transfer Information Read Skip Function . 486 12.5.3 Transfer Information Writeback Skip Function . 487 12.5.4 Normal Transfer Mode . 487 12.5.5 Repeat Transfer Mode. 488 12.5.6 Block Transfer Mode . 490 12.5.7 Chain Transfer . 491 12.5.8 Operation Timing. 492 12.5.9 Number of DTC Execution Cycles . 494 12.5.10 DTC Bus Release Timing . 495 12.5.11 DTC Priority Level Control to the CPU . 495 DTC Activation by Interrupt. 496 Examples of Use of the DTC . 497 12.7.1 Normal Transfer Mode . 497 12.7.2 Chain Transfer . 497 12.7.3 Chain Transfer when Counter = 0. 498 Interrupt Sources. 500 Usage Notes . 500 12.9.1 Module Stop State Setting . 500 12.9.2 On-Chip RAM . 500 12.9.3 DMAC Transfer End Interrupt. 500 12.9.4 DTCE Bit Setting. 500 12.9.5 Chain Transfer . 501 Rev. 2.00 Sep. 25, 2008 Page xvii of xxx 12.9.6 12.9.7 12.9.8 12.9.9 Transfer Information Start Address, Source Address, and Destination Address . 501 Transfer Information Modification . 501 Endian Format . 501 Points for Caution when Overwriting DTCER . 502 Section 13 I/O Ports. 503 13.1 13.2 13.3 Register Descriptions. 510 13.1.1 Data Direction Register (PnDDR) (n = 1, 2, 6, A, B, D to F, H to K, and M). 511 13.1.2 Data Register (PnDR) (n = 1, 2, 6, A, B, D to F, H to K, and M). 512 13.1.3 Port Register (PORTn) (n = 1, 2, 5, 6, A, B, D to F, H to K, and M) . 512 13.1.4 Input Buffer Control Register (PnICR) (n = 1, 2, 5, 6, A, B, D to F, H to K, and M). 513 13.1.5 Pull-Up MOS Control Register (PnPCR) (n = D to F, and H to K). 514 13.1.6 Open-Drain Control Register (PnODR) (n = 2 and F). 515 Output Buffer Control. 516 13.2.1 Port 1. 516 13.2.2 Port 2. 520 13.2.3 Port 5. 524 13.2.4 Port 6. 525 13.2.5 Port A. 528 13.2.6 Port B. 532 13.2.7 Port D. 534 13.2.8 Port E . 535 13.2.9 Port F . 536 13.2.10 Port H. 538 13.2.11 Port I . 539 13.2.12 Port J . 540 13.2.13 Port K. 544 13.2.14 Port M . 548 Port Function Controller . 557 13.3.1 Port Function Control Register 0 (PFCR0). 558 13.3.2 Port Function Control Register 1 (PFCR1). 559 13.3.3 Port Function Control Register 2 (PFCR2). 560 13.3.4 Port Function Control Register 4 (PFCR4). 562 13.3.5 Port Function Control Register 6 (PFCR6). 563 13.3.6 Port Function Control Register 7 (PFCR7). 564 13.3.7 Port Function Control Register 8 (PFCR8). 565 13.3.8 Port Function Control Register 9 (PFCR9). 566 Rev. 2.00 Sep. 25, 2008 Page xviii of xxx 13.4 13.3.9 Port Function Control Register A (PFCRA) . 567 13.3.10 Port Function Control Register B (PFCRB). 569 13.3.11 Port Function Control Register C (PFCRC). 571 13.3.12 Port Function Control Register D (PFCRD) . 572 Usage Notes . 573 13.4.1 Notes on Input Buffer Control Register (ICR) Setting . 573 13.4.2 Notes on Port Function Control Register (PFCR) Settings. 573 Section 14 16-Bit Timer Pulse Unit (TPU) .575 14.1 14.2 14.3 Features. 575 Input/Output Pins. 582 Register Descriptions. 584 14.3.1 Timer Control Register (TCR). 589 14.3.2 Timer Mode Register (TMDR) . 594 14.3.3 Timer I/O Control Register (TIOR) . 596 14.3.4 Timer Interrupt Enable Register (TIER) . 630 14.3.5 Timer Status Register (TSR). 631 14.3.6 Timer Counter (TCNT). 635 14.3.7 Timer General Register (TGR) . 635 14.3.8 Timer Start Register (TSTR) . 636 14.3.9 Timer Synchronous Register (TSYR). 637 14.4 Operation . 638 14.4.1 Basic Operation. 638 14.4.2 Synchronous Operation. 644 14.4.3 Buffer Operation . 646 14.4.4 Cascaded Operation . 650 14.4.5 PWM Modes . 652 14.4.6 Phase Counting Mode . 658 14.5 Interrupt Sources. 665 14.6 DTC Activation. 667 14.7 DMAC Activation. 667 14.8 A/D Converter Activation. 667 14.9 Operation Timing. 668 14.9.1 Input/Output Timing . 668 14.9.2 Interrupt Signal Timing. 672 14.10 Usage Notes . 676 14.10.1 Module Stop Function Setting . 676 14.10.2 Input Clock Restrictions . 676 14.10.3 Caution on Cycle Setting . 677 14.10.4 Conflict between TCNT Write and Clear Operations. 677 Rev. 2.00 Sep. 25, 2008 Page xix of xxx 14.10.5 14.10.6 14.10.7 14.10.8 14.10.9 14.10.10 14.10.11 14.10.12 14.10.13 14.10.14 Conflict between TCNT Write and Increment Operations . 678 Conflict between TGR Write and Compare Match. 678 Conflict between Buffer Register Write and Compare Match . 679 Conflict between TGR Read and Input Capture . 679 Conflict between TGR Write and Input Capture . 680 Conflict between Buffer Register Write and Input Capture. 681 Conflict between Overflow/Underflow and Counter Clearing . 682 Conflict between TCNT Write and Overflow/Underflow . 682 Multiplexing of I/O Pins . 683 Interrupts in the Module Stop State . 683 Section 15 Programmable Pulse Generator (PPG). 685 15.1 15.2 15.3 15.4 15.5 Features. 685 Input/Output Pins. 688 Register Descriptions. 689 15.3.1 Next Data Enable Registers H, L (NDERH, NDERL) . 690 15.3.2 Output Data Registers H, L (PODRH, PODRL). 692 15.3.3 Next Data Registers H, L (NDRH, NDRL) . 695 15.3.4 PPG Output Control Register (PCR) . 699 15.3.5 PPG Output Mode Register (PMR) . 701 Operation . 705 15.4.1 Output Timing . 705 15.4.2 Sample Setup Procedure for Normal Pulse Output. 706 15.4.3 Example of Normal Pulse Output (Example of 5-Phase Pulse Output). 708 15.4.4 Non-Overlapping Pulse Output. 709 15.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output. 711 15.4.6 Example of Non-Overlapping Pulse Output (Example of 4-Phase Complementary Non-Overlapping Pulse Output). 713 15.4.7 Inverted Pulse Output . 715 15.4.8 Pulse Output Triggered by Input Capture . 716 Usage Notes . 717 15.5.1 Module Stop State Setting . 717 15.5.2 Operation of Pulse Output Pins. 717 15.5.3 TPU Setting when PPG1 is in Use. 717 Section 16 8-Bit Timers (TMR) . 719 16.1 16.2 16.3 Features. 719 Input/Output Pins. 724 Register Descriptions. 725 16.3.1 Timer Counter (TCNT). 727 Rev. 2.00 Sep. 25, 2008 Page xx of xxx 16.4 16.5 16.6 16.7 16.8 16.3.2 Time Constant Register A (TCORA). 727 16.3.3 Time Constant Register B (TCORB) . 728 16.3.4 Timer Control Register (TCR). 728 16.3.5 Timer Counter Control Register (TCCR) . 730 16.3.6 Timer Control/Status Register (TCSR). 735 Operation . 739 16.4.1 Pulse Output. 739 16.4.2 Reset Input . 740 Operation Timing. 741 16.5.1 TCNT Count Timing . 741 16.5.2 Timing of CMFA and CMFB Setting at Compare Match. 742 16.5.3 Timing of Timer Output at Compare Match . 742 16.5.4 Timing of Counter Clear by Compare Match . 743 16.5.5 Timing of TCNT External Reset*. 743 16.5.6 Timing of Overflow Flag (OVF) Setting . 744 Operation with Cascaded Connection. 744 16.6.1 16-Bit Counter Mode . 744 16.6.2 Compare Match Count Mode. 745 Interrupt Sources. 745 16.7.1 Interrupt Sources and DTC Activation . 745 16.7.2 A/D Converter Activation. 746 Usage Notes . 747 16.8.1 Notes on Setting Cycle. 747 16.8.2 Conflict between TCNT Write and Counter Clear. 747 16.8.3 Conflict between TCNT Write and Increment. 748 16.8.4 Conflict between TCOR Write and Compare Match . 748 16.8.5 Conflict between Compare Matches A and B. 749 16.8.6 Switching of Internal Clocks and TCNT Operation. 749 16.8.7 Mode Setting with Cascaded Connection . 751 16.8.8 Module Stop State Setting . 751 16.8.9 Interrupts in Module Stop State . 751 Section 17 Watchdog Timer (WDT).753 17.1 17.2 17.3 17.4 Features. 753 Input/Output Pin . 754 Register Descriptions. 755 17.3.1 Timer Counter (TCNT). 755 17.3.2 Timer Control/Status Register (TCSR). 755 17.3.3 Reset Control/Status Register (RSTCSR). 757 Operation . 758 Rev. 2.00 Sep. 25, 2008 Page xxi of xxx 17.5 17.6 17.4.1 Watchdog Timer Mode. 758 17.4.2 Interval Timer Mode. 760 Interrupt Source . 760 Usage Notes . 761 17.6.1 Notes on Register Access . 761 17.6.2 Conflict between Timer Counter (TCNT) Write and Increment. 762 17.6.3 Changing Values of Bits CKS2 to CKS0. 762 17.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode. 762 17.6.5 Internal Reset in Watchdog Timer Mode. 763 17.6.6 System Reset by WDTOVF Signal. 763 17.6.7 Transition to Watchdog Timer Mode or Software Standby Mode. 763 Section 18 Serial Communication Interface (SCI, IrDA, CRC) . 765 18.1 18.2 18.3 18.4 18.5 18.6 Features. 765 Input/Output Pins. 770 Register Descriptions. 771 18.3.1 Receive Shift Register (RSR) . 773 18.3.2 Receive Data Register (RDR). 773 18.3.3 Transmit Data Register (TDR). 774 18.3.4 Transmit Shift Register (TSR) . 774 18.3.5 Serial Mode Register (SMR) . 774 18.3.6 Serial Control Register (SCR) . 778 18.3.7 Serial Status Register (SSR) . 783 18.3.8 Smart Card Mode Register (SCMR). 792 18.3.9 Bit Rate Register (BRR) . 793 18.3.10 Serial Extended Mode Register (SEMR_2) . 800 18.3.11 Serial Extended Mode Register 5 and 6 (SEMR_5 and SEMR_6). 802 18.3.12 IrDA Control Register (IrCR). 809 Operation in Asynchronous Mode . 810 18.4.1 Data Transfer Format. 811 18.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode. 812 18.4.3 Clock. 813 18.4.4 SCI Initialization (Asynchronous Mode). 814 18.4.5 Serial Data Transmission (Asynchronous Mode) . 815 18.4.6 Serial Data Reception (Asynchronous Mode) . 817 Multiprocessor Communication Function . 821 18.5.1 Multiprocessor Serial Data Transmission . 823 18.5.2 Multiprocessor Serial Data Reception . 824 Operation in Clocked Synchronous Mode (SCI_0, 1, 2, and 4 only). 827 Rev. 2.00 Sep. 25, 2008 Page xxii of xxx 18.6.1 18.6.2 18.6.3 Clock. 827 SCI Initialization (Clocked Synchronous Mode) (SCI_0, 1, 2, and 4 only). 828 Serial Data Transmission (Clocked Synchronous Mode) (SCI_0, 1, 2, and 4 only). 829 18.6.4 Serial Data Reception (Clocked Synchronous Mode) (SCI_0, 1, 2, and 4 only). 831 18.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) (SCI_0, 1, 2, and 4 only) . 832 18.7 Operation in Smart Card Interface Mode. 834 18.7.1 Sample Connection . 834 18.7.2 Data Format (Except in Block Transfer Mode) . 835 18.7.3 Block Transfer Mode . 836 18.7.4 Receive Data Sampling Timing and Reception Margin. 837 18.7.5 Initialization . 838 18.7.6 Data Transmission (Except in Block Transfer Mode) . 839 18.7.7 Serial Data Reception (Except in Block Transfer Mode). 842 18.7.8 Clock Output Control (Only SCI_0, 1, 2, and 4) . 843 18.8 IrDA Operation . 845 18.9 Interrupt Sources. 848 18.9.1 Interrupts in Normal Serial Communication Interface Mode . 848 18.9.2 Interrupts in Smart Card Interface Mode . 849 18.10 Usage Notes . 851 18.10.1 Module Stop Function Setting . 851 18.10.2 Break Detection and Processing . 851 18.10.3 Mark State and Break Detection . 851 18.10.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only). 851 18.10.5 Relation between Writing to TDR and TDRE Flag . 852 18.10.6 Restrictions on Using DTC or DMAC. 852 18.10.7 SCI Operations during Power-Down State . 853 18.11 CRC Operation Circuit . 856 18.11.1 Features. 856 18.11.2 Register Descriptions . 857 18.11.3 CRC Operation Circuit Operation. 859 18.11.4 Note on CRC Operation Circuit. 862 Section 19 USB Function Module (USB).863 19.1 19.2 19.3 Features. 863 Input/Output Pins. 864 Register Descriptions. 865 Rev. 2.00 Sep. 25, 2008 Page xxiii of xxx 19.4 19.5 19.6 19.7 19.3.1 Interrupt Flag Register 0 (IFR0) . 866 19.3.2 Interrupt Flag Register 1 (IFR1) . 868 19.3.3 Interrupt Flag Register 2 (IFR2) . 869 19.3.4 Interrupt Select Register 0 (ISR0). 871 19.3.5 Interrupt Select Register 1 (ISR1). 872 19.3.6 Interrupt Select Register 2 (ISR2). 873 19.3.7 Interrupt Enable Register 0 (IER0) . 874 19.3.8 Interrupt Enable Register 1 (IER1) . 875 19.3.9 Interrupt Enable Register 2 (IER2) . 875 19.3.10 EP0i Data Register (EPDR0i). 876 19.3.11 EP0o Data Register (EPDR0o) . 877 19.3.12 EP0s Data Register (EPDR0s) . 877 19.3.13 EP1 Data Register (EPDR1) . 878 19.3.14 EP2 Data Register (EPDR2) . 878 19.3.15 EP3 Data Register (EPDR3) . 879 19.3.16 EP0o Receive Data Size Register (EPSZ0o) . 879 19.3.17 EP1 Receive Data Size Register (EPSZ1) . 880 19.3.18 Trigger Register (TRG) . 880 19.3.19 Data Status Register (DASTS). 882 19.3.20 FIFO Clear Register (FCLR) . 883 19.3.21 DMA Transfer Setting Register (DMA) . 884 19.3.22 Endpoint Stall Register (EPSTL). 887 19.3.23 Configuration Value Register (CVR) . 888 19.3.24 Control Register (CTLR) . 888 19.3.25 Endpoint Information Register (EPIR) . 890 19.3.26 Transceiver Test Register 0 (TRNTREG0) . 894 19.3.27 Transceiver Test Register 1 (TRNTREG1) . 896 Interrupt Sources. 898 Operation . 900 19.5.1 Cable Connection. 900 19.5.2 Cable Disconnection . 901 19.5.3 Suspend and Resume Operations. 901 19.5.4 Control Transfer. 910 19.5.5 EP1 Bulk-Out Transfer (Dual FIFOs). 916 19.5.6 EP2 Bulk-In Transfer (Dual FIFOs) . 917 19.5.7 EP3 Interrupt-In Transfer. 919 Processing of USB Standard Commands and Class/Vendor Commands . 920 19.6.1 Processing of Commands Transmitted by Control Transfer. 920 Stall Operations . 921 19.7.1 Overview . 921 Rev. 2.00 Sep. 25, 2008 Page xxiv of xxx 19.7.2 Forcible Stall by Application . 921 19.7.3 Automatic Stall by USB Function Module . 923 19.8 DMA Transfer. 924 19.8.1 Overview. 924 19.8.2 DMA Transfer for Endpoint 1 . 924 19.8.3 DMA Transfer for Endpoint 2 . 925 19.9 Example of USB External Circuitry . 926 19.10 Usage Notes . 928 19.10.1 Receiving Setup Data. 928 19.10.2 Clearing the FIFO . 928 19.10.3 Overreading and Overwriting the Data Registers . 928 19.10.4 Assigning Interrupt Sources to EP0 . 929 19.10.5 Clearing the FIFO When DMA Transfer is Enabled . 929 19.10.6 Notes on TR Interrupt . 929 19.10.7 Restrictions on Peripheral Module Clock (P) Operating Frequency. 930 19.10.8 Notes on Deep Software Standby Mode when USB is Used . 930 Section 20 I2C Bus Interface 2 (IIC2) .931 20.1 20.2 20.3 20.4 20.5 20.6 Features. 931 Input/Output Pins. 933 Register Descriptions. 934 20.3.1 I2C Bus Control Register A (ICCRA) . 935 20.3.2 I2C Bus Control Register B (ICCRB). 937 20.3.3 I2C Bus Mode Register (ICMR). 939 20.3.4 I2C Bus Interrupt Enable Register (ICIER) . 940 20.3.5 I2C Bus Status Register (ICSR). 943 20.3.6 Slave Address Register (SAR). 946 20.3.7 I2C Bus Transmit Data Register (ICDRT). 947 20.3.8 I2C Bus Receive Data Register (ICDRR). 947 20.3.9 I2C Bus Shift Register (ICDRS). 947 Operation . 948 20.4.1 I2C Bus Format. 948 20.4.2 Master Transmit Operation . 949 20.4.3 Master Receive Operation. 951 20.4.4 Slave Transmit Operation . 953 20.4.5 Slave Receive Operation. 956 20.4.6 Noise Canceler. 957 20.4.7 Example of Use. 958 Interrupt Request. 962 Bit Synchronous Circuit. 962 Rev. 2.00 Sep. 25, 2008 Page xxv of xxx 20.7 Usage Notes . 963 Section 21 A/D Converter . 965 21.1 21.2 21.3 21.4 21.5 21.6 21.7 Features. 965 Input/Output Pins. 968 Register Descriptions. 969 21.3.1 A/D Data Registers A to H (ADDRA to ADDRH) . 970 21.3.2 A/D Control/Status Register for Unit 0 (ADCSR_0). 971 21.3.3 A/D Control/Status Register for Unit 1 (ADCSR_1). 973 21.3.4 A/D Control Register for Unit 0 (ADCR_0). 975 21.3.5 A/D Control Register for Unit 1 (ADCR_1). 977 Operation . 979 21.4.1 Single Mode. 979 21.4.2 Scan Mode . 980 21.4.3 Input Sampling and A/D Conversion Time . 983 21.4.4 External Trigger Input Timing. 985 Interrupt Source . 987 A/D Conversion Accuracy Definitions . 988 Usage Notes . 990 21.7.1 Module Stop Function Setting . 990 21.7.2 A/D Input Hold Function in Software Standby Mode . 990 21.7.3 Notes on A/D Activation by an External Trigger . 990 21.7.4 Permissible Signal Source Impedance . 991 21.7.5 Influences on Absolute Accuracy . 992 21.7.6 Setting Range of Analog Power Supply and Other Pins. 992 21.7.7 Notes on Board Design . 993 21.7.8 Notes on Noise Countermeasures . 993 Section 22 D/A Converter . 995 22.1 22.2 22.3 22.4 22.5 Features. 995 Input/Output Pins.