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REJ09B0394-0200 SH7101 HD6437101 REJ09B0171-0500 REJ10B0047-0100 - Datasheet Archive
The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and
REJ09B0394-0200 REJ09B0394-0200 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. SH7101 SH7101 32 Hardware Manual Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7100 Series SH7101 SH7101 Rev.2.00 Revision date: Sep. 27, 2007 HD6437101 HD6437101 www.renesas.com Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. Rev.2.00 Sep. 27, 2007 Page ii of xxxiv REJ09B0394-0200 REJ09B0394-0200 General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions may occur due to the false recognition of the pin state as an input signal. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited. The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized. When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different type number, confirm that the change will not lead to problems. The characteristics of MPU/MCU in the same group but having different type numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different type numbers, implement a system-evaluation test for each of the products. Rev.2.00 Sep. 27, 2007 Page iii of xxxiv REJ09B0394-0200 REJ09B0394-0200 Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules · CPU and System-Control Modules · On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. List of Registers 8. Electrical Characteristics 9. Appendix 10. Index Rev.2.00 Sep. 27, 2007 Page iv of xxxiv REJ09B0394-0200 REJ09B0394-0200 Preface The SH7101 SH7101 single-chip RISC (Reduced Instruction Set Computer) microcomputer includes a Renesas Technology-original RISC CPU as its core, and the peripheral functions required to configure a system. Target Users: This manual was written for users who will be using this LSI in the design of application systems. Users of this manual are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of this LSI to the above users. Refer to the SH-1/SH-2/SH-DSP Software Manual for a detailed description of the instruction set. Notes on reading this manual: · Product names The following products are covered in this manual. Product Classifications and Abbreviations Basic Classification On-Chip ROM Classification Part No. SH7101 SH7101 (80-pin version) Mask ROM version (ROM: 32 kbytes) HD6437101 HD6437101 In this manual, the product abbreviations are used to distinguish products. For example, products are collectively referred to as the SH7101 SH7101. · In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics. · In order to understand the details of the CPU's functions Read the SH-1/SH-2/SH-DSP Software Manual. · In order to understand the details of a register when the user knows its name Read the index that is the final part of the manual to find the page number of the entry on the register. The addresses, bit names, and initial values of the registers are summarized in section 18, List of Registers. Rev.2.00 Sep. 27, 2007 Page v of xxxiv REJ09B0394-0200 REJ09B0394-0200 Rules: Register name: The following notation is used for cases when the same or a similar function, e.g. serial communication, is implemented on more than one channel: XXX_N (XXX is the register name and N is the channel number) Bit order: The MSB (most significant bit) is on the left and the LSB (least significant bit) is on the right. Related Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/ SH7101 SH7101 manuals: Document Title Document No. SH7101 SH7101 Hardware Manual This manual SH-1/SH-2/SH-DSP Software Manual REJ09B0171-0500 REJ09B0171-0500 Users manuals for development tools: Document Title Document No. SuperH C/C+ Compiler, Assembler, Optimizing Linkage Editor User's Manual REJ10B0047-0100 REJ10B0047-0100 SuperH RISC engine Simulator/Debugger (for Windows) User's Manual REJ10B0210-0300 REJ10B0210-0300 High-performance Embedded Workshop User's Manual REJ10J1554-0100 REJ10J1554-0100 Application Notes: Document Title Document No. SuperH RISC engine C/C+ Compiler Package Application Note REJ05B0463-0400 REJ05B0463-0400 Rev.2.00 Sep. 27, 2007 Page vi of xxxiv REJ09B0394-0200 REJ09B0394-0200 Main Revisions for This Edition Item Page Revision (See Manual for Details) All · 6.5 Interrupt Exception Processing Vectors Table 79 Table amended Company name and brand names amended (Before) Hitachi, Ltd. (After) Renesas Technology Corp. Interrupt Source Table 6.2 Interrupt Exception Processing Vectors and Priorities Name MTU channel 3 TGIA_3 TGIB_3 TGIC_3 TGID_3 TCIV_3 7.5.1 Bus Control Register 1 (BCR1) 89 Bit table amended Bit Bit Name Initial Value R/W Description 14 1 R Reserved These bits are always read as 1 and should always be written to 1. 8.1 Features 94 Title and figure amended Figure 8.1 Block Diagram of MTU Interrupt request signals Channel 3: TGI3A TGI3B TGI3C TGI3D TCI3V Channel 4: TGI4A TGI4B TGI4C TGI4D TCI4V 8.3.3 Timer I/O Control 109 Register (TIOR) Table amended Description Bit 3 IOC3 Bit 2 IOC2 Bit 1 IOC1 Bit 0 IOC0 TGRC_0 Function 0 Table 8.13 TIORL_0 (channel 0) 0 0 0 Output compare register* 1 8.4.4 Cascaded Operation Table 8.30 Cascaded Combinations 149 TIOC0C Pin Function Output disable Initial output is 0 0 output at compare match Note amended Note: When phase counting mode is set for channel 1 or 2, the counter clock setting is invalid and the counters operates independently in phase counting mode. Rev.2.00 Sep. 27, 2007 Page vii of xxxiv REJ09B0394-0200 REJ09B0394-0200 Item Page Revision (See Manual for Details) 8.4.4 Cascaded Operation 149 Figure amended [1] Set bits TPSC2 to TPSC0 in the channel 1 TCR to B'111 to select TCNT_2 overflow/ underflow counting. Figure 8.18 Cascaded Operation Setting Procedure 8.4.8 Complementary PWM Mode 170 Example of Complementary PWM Mode Setting Procedure: 11. Set bits CST3 and CST4 in TSTR to 1 simultaneously to start the count operation. Complementary PWM 192 Mode Output Protection Function: 8.5.1 Interrupts and Priorities Underflow Interrupt: Description amended 10. Set enabling/disabling of PWM waveform output pin output in the timer output master enable register (TOER). 194 Description amended · Register and counter miswrite prevention function With the exception of the buffer registers, which can be rewritten at any time, access by the CPU can be enabled or disabled for the mode registers, control registers, compare registers, and counters used in complementary PWM mode by means of bit 13 in the bus controller's bus control register 1 (BCR1). Some registers in channels 3 and 4 concerned are listed below: total 21 registers of TCR_3 and TCR_4; TMDR_3 and TMDR_4; TIORH_3 and TIORH_4; TIORL_3 and TIORL_4; TIER_3 and TIER_4; TCNT_3 and TCNT_4; TGRA_3 and TGRA_4; TGRB_3 and TGRB_4; TOER; TOCR; TGCR; TCDR; and TDDR. This function enables the CPU to prevent miswriting due to the CPU runaway by disabling CPU access to the mode registers, control registers, and counters. In access disabled state, an undefined value is read from the registers concerned, and cannot be modified. Description amended An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel. The interrupt request is cleared by clearing the TCFU flag to 0. The MTU has two underflow interrupts, one each for channels 1 and 2. Rev.2.00 Sep. 27, 2007 Page viii of xxxiv REJ09B0394-0200 REJ09B0394-0200 Item Page 8.7.15 Overflow Flags in 216 Reset Sync PWM Mode Figure 8.81 Reset Sync PWM Mode Overflow Flag Revision (See Manual for Details) Figure amended Counter cleared by compare match 3A TGRA_3 (H'FFFF) TCNT_3 = TCNT_4 H'0000 TCFV_3 TCFV_4 8.7.21 Simultaneous 219 Input Capture of TCNT_1 and TCNT_2 in Cascade Connection Not set Not set Description amended When timer counters 1 and 2 (TCNT_1 and TCNT_2) are operated as a 32-bit counter in cascade connection, the cascade counter value cannot be captured successfully even if input-capture input is simultaneously done to TIOC1A and TIOC2A or to TIOC1B and TIOC2B. This is because the input timing of TIOC1A and TIOC2A or of TIOC1B and TIOC2B may not be the same when external input-capture signals to be input into TCNT_1 and TCNT_2 are taken in synchronization with the internal clock. For example, TCNT_1 (the counter for upper 16 bits) does not capture the count-up value by overflow from TCNT_2 (the counter for lower 16 bits) but captures the count value before the count-up. In this case, the values of TCNT_1 = H'FFF1 and TCNT_2 = H'0000 should be transferred to TGRA_1 and TGRA_2 or to TGRB_1 and TGRB_2, but the values of TCNT_1 = H'FFF0 and TCNT_2 = H'0000 are erroneously transferred. Rev.2.00 Sep. 27, 2007 Page ix of xxxiv REJ09B0394-0200 REJ09B0394-0200 Item Page Revision (See Manual for Details) 8.9.5 Usage Note 262 Description added (1) Symptom (a) Regarding the POEnF*1 bits If setting of the POEnF bits in the input level control/status registers (ICSR1 and ICSR2) by the hardware*2 and reading from these bits occur simultaneously, "0" will be read, where "1" should be read. Furthermore, if clearing of these bits is attempted subsequent to the above condition, the clearing should be ignored*3 but it will be carried out. Notes: *1 For the SH7046-Series and SH7047-Series, n = 0 to 6; for the SH7144-Series, n = 0 to 3. *2 The POEnF bits are set when the signals input to the respective POEn pins satisfy the conditions that are specified by the POEnM1 and POEnM0 of the ICSR1 and ICSR2. *3 The correct operation is that clearing of the POEnF bits is only possible after "1" is read from them in order to prevent accidental clearing. (b) Regarding the OSF bit The same symptom applies to the OSF bits of the output level control/status register (OCSR). (2) To Avoid This Problem Please clear the POEnF bits or the OSF bit in these steps: first execute a read for ICSR1, ICSR2, or OCSR, then write "0" to the bits that had a read value of "1" to clear them while writing "1" to other bits. If this procedure is not followed, the POEnF bits and the OSF bit may be cleared unexpectedly if their setting by hardware and reading occur simultaneously. 10.3.2 Receive Data Register (RDR) 280 10.3.4 Transmit Data Register (TDR) 280 Description added . RDR cannot be written to by the CPU. The initial value of RDR is H'00. Description added . Although TDR can be read or written to by the CPU at all times, to achieve reliable serial transmission, write transmit data to TDR for only once after confirming that the TDRE bit in SSR is set to 1. The initial value of TDR is H'FF. Rev.2.00 Sep. 27, 2007 Page x of xxxiv REJ09B0394-0200 REJ09B0394-0200 Item Page Revision (See Manual for Details) 11.1 Features 325 Description added · Conversion time: 6.7 s per channel (at P = 20-MHz operation) 5.4 s per channel (at P = 25-MHz operation) 11.7.2 Permissible Signal Source Impedance 340 17.3.1 Sleep Mode 395 Notes on Using Sleep Mode Description amended This LSI's analog input is designed such that conversion accuracy is guaranteed for an input signal for which the signal source impedance is 1 k or less, or 3 k or less. This specification is provided to enable the A/D converter's sampleand-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 1 k or 3 k, charging may be insufficient and it may not be possible to guarantee A/D conversion accuracy. . Description added · There are 4 conditions to clear sleep mode. (1) Clearing by an interrupt (2) Clearing by DTC address error (3) Clearing by the power-on reset (4) Clearing by the manual reset When clearing sleep mode by (1) or (2), CPU may run out of control. Please clear sleep mode by (3) or (4), don't use (1) or (2). · Do not use DTC module or AUD module during sleep mode. Rev.2.00 Sep. 27, 2007 Page xi of xxxiv REJ09B0394-0200 REJ09B0394-0200 All trademarks and registered trademarks are the property of their respective owners. Rev.2.00 Sep. 27, 2007 Page xii of xxxiv REJ09B0394-0200 REJ09B0394-0200 Contents Section 1 Overview. 1 1.1 1.2 1.3 1.4 1.5 Features . 1 Internal Block Diagram. 3 Pin Arrangement . 4 Pin Functions . 5 Differences from SH7046 SH7046 Group . 9 Section 2 CPU. 11 2.1 2.2 2.3 2.4 2.5 2.6 Features . 11 Register Configuration . 11 2.2.1 General Registers (Rn). 13 2.2.2 Control Registers . 13 2.2.3 System Registers . 14 2.2.4 Initial Values of Registers. 15 Data Formats . 15 2.3.1 Data Format in Registers. 15 2.3.2 Data Formats in Memory . 16 2.3.3 Immediate Data Format . 16 Instruction Features. 17 2.4.1 RISC-Type Instruction Set. 17 2.4.2 Addressing Modes . 20 2.4.3 Instruction Format. 24 Instruction Set . 26 2.5.1 Instruction Set by Classification . 26 Processing States. 41 2.6.1 State Transitions. 41 Section 3 MCU Operating Modes. 43 3.1 3.2 3.3 3.4 3.5 Selection of Operating Modes. 43 Input/Output Pins . 44 Explanation of Operating Modes . 44 3.3.1 Mode 3 (Single chip mode). 44 3.3.2 Clock Mode. 44 Address Map . 45 Initial State of This LSI. 46 Section 4 Clock Pulse Generator . 47 4.1 Oscillator. 47 Rev.2.00 Sep. 27, 2007 Page xiii of xxxiv REJ09B0394-0200 REJ09B0394-0200 4.2 4.3 4.1.1 Connecting Crystal Resonator . 47 4.1.2 External Clock Input Method. 49 Function for Detecting Oscillator Halt. 49 Usage Notes . 50 4.3.1 Note on Crystal Resonator . 50 4.3.2 Notes on Board Design . 50 Section 5 Exception Processing.53 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 Overview. 53 5.1.1 Types of Exception Processing and Priority . 53 5.1.2 Exception Processing Operations. 54 5.1.3 Exception Processing Vector Table . 55 Resets . 57 5.2.1 Types of Reset . 57 5.2.2 Power-On Reset . 57 5.2.3 Manual Reset . 58 Address Errors . 59 5.3.1 Cause of Address Error Exception. 59 5.3.2 Address Error Exception Processing. 60 Interrupts. 60 5.4.1 Interrupt Sources. 60 5.4.2 Interrupt Priority Level . 61 5.4.3 Interrupt Exception Processing . 61 Exceptions Triggered by Instructions . 62 5.5.1 Types of Exceptions Triggered by Instructions . 62 5.5.2 Trap Instructions . 62 5.5.3 Illegal Slot Instructions . 63 5.5.4 General Illegal Instructions. 63 Cases when Exception Sources are Not Accepted . 64 5.6.1 Immediately after Delayed Branch Instruction . 64 5.6.2 Immediately after Interrupt-Disabled Instruction . 64 Stack Status after Exception Processing Ends . 65 Usage Notes . 66 5.8.1 Value of Stack Pointer (SP) . 66 5.8.2 Value of Vector Base Register (VBR) . 66 5.8.3 Address Errors Caused by Stacking of Address Error Exception Processing. 66 Section 6 Interrupt Controller (INTC).67 6.1 6.2 Features. 67 Input/Output Pins . 68 Rev.2.00 Sep. 27, 2007 Page xiv of xxxiv REJ09B0394-0200 REJ09B0394-0200 6.3 6.4 6.5 6.6 6.7 Register Descriptions . 68 6.3.1 Interrupt Control Register 1 (ICR1) . 69 6.3.2 Interrupt Control Register 2 (ICR2) . 70 6.3.3 IRQ Status Register (ISR). 72 6.3.4 Interrupt Priority Registers A, D to I (IPRA, IPRD to IPRI) . 73 Interrupt Sources . 75 6.4.1 External Interrupts . 75 6.4.2 On-Chip Peripheral Module Interrupts . 77 Interrupt Exception Processing Vectors Table. 77 Operation. 81 6.6.1 Interrupt Sequence . 81 6.6.2 Stack after Interrupt Exception Processing . 83 Interrupt Response Time . 84 Section 7 Bus State Controller (BSC). 87 7.1 7.2 7.3 7.4 7.5 7.6 Features . 87 Input/output Pin. 87 Register . 87 Address Map . 88 Register Description. 89 7.5.1 Bus Control Register 1 (BCR1) . 89 On-chip Peripheral I/O Register Access . 90 Section 8 Multi-Function Timer Pulse Unit (MTU) . 91 8.1 8.2 8.3 Features . 91 Input/Output Pins . 95 Register Descriptions . 96 8.3.1 Timer Control Register (TCR) . 98 8.3.2 Timer Mode Register (TMDR) . 102 8.3.3 Timer I/O Control Register (TIOR) . 104 8.3.4 Timer Interrupt Enable Register (TIER) . 122 8.3.5 Timer Status Register (TSR). 124 8.3.6 Timer Counter (TCNT). 126 8.3.7 Timer General Register (TGR) . 127 8.3.8 Timer Start Register (TSTR). 127 8.3.9 Timer Synchro Register (TSYR) . 128 8.3.10 Timer Output Master Enable Register (TOER) . 130 8.3.11 Timer Output Control Register (TOCR) . 131 8.3.12 Timer Gate Control Register (TGCR). 133 8.3.13 Timer Subcounter (TCNTS) . 135 Rev.2.00 Sep. 27, 2007 Page xv of xxxiv REJ09B0394-0200 REJ09B0394-0200 8.4 8.5 8.6 8.7 8.3.14 Timer Dead Time Data Register (TDDR). 135 8.3.15 Timer Period Data Register (TCDR) . 135 8.3.16 Timer Period Buffer Register (TCBR). 135 8.3.17 Bus Master Interface . 136 Operation . 137 8.4.1 Basic Functions. 137 8.4.2 Synchronous Operation. 142 8.4.3 Buffer Operation . 145 8.4.4 Cascaded Operation . 149 8.4.5 PWM Modes . 150 8.4.6 Phase Counting Mode. 156 8.4.7 Reset-Synchronized PWM Mode. 163 8.4.8 Complementary PWM Mode. 167 Interrupt Sources. 192 8.5.1 Interrupts and Priorities. 192 8.5.2 A/D Converter Activation. 194 Operation Timing. 195 8.6.1 Input/Output Timing . 195 8.6.2 Interrupt Signal Timing. 200 Usage Notes . 204 8.7.1 Module Standby Mode Setting . 204 8.7.2 Input Clock Restrictions . 204 8.7.3 Caution on Period Setting . 205 8.7.4 Contention between TCNT Write and Clear Operations. 205 8.7.5 Contention between TCNT Write and Increment Operations. 206 8.7.6 Contention between TGR Write and Compare Match . 207 8.7.7 Contention between Buffer Register Write and Compare Match . 208 8.7.8 Contention between TGR Read and Input Capture. 210 8.7.9 Contention between TGR Write and Input Capture. 211 8.7.10 Contention between Buffer Register Write and Input Capture . 212 8.7.11 TCNT_2 Write and Overflow/Underflow Contention in Cascade Connection . 212 8.7.12 Counter Value during Complementary PWM Mode Stop . 214 8.7.13 Buffer Operation Setting in Complementary PWM Mode . 214 8.7.14 Reset Sync PWM Mode Buffer Operation and Compare Match Flag . 215 8.7.15 Overflow Flags in Reset Sync PWM Mode. 216 8.7.16 Contention between Overflow/Underflow and Counter Clearing. 217 8.7.17 Contention between TCNT Write and Overflow/Underflow. 218 8.7.18 Cautions on Transition from Normal Operation or PWM Mode 1 to Reset-Synchronous PWM Mode. 218 Rev.2.00 Sep. 27, 2007 Page xvi of xxxiv REJ09B0394-0200 REJ09B0394-0200 8.8 8.9 8.7.19 Output Level in Complementary PWM Mode and Reset-Synchronous PWM Mode. 219 8.7.20 Interrupts in Module Standby Mode . 219 8.7.21 Simultaneous Input Capture of TCNT_1 and TCNT_2 in Cascade Connection. 219 MTU Output Pin Initialization . 220 8.8.1 Operating Modes. 220 8.8.2 Reset Start Operation . 220 8.8.3 Operation in Case of Re-Setting Due to Error During Operation, Etc. . 221 8.8.4 Overview of Initialization Procedures and Mode Transitions in Case of Error during Operation, Etc. . 222 Port Output Enable (POE). 252 8.9.1 Features. 252 8.9.2 Pin Configuration. 254 8.9.3 Register Configuration. 254 8.9.4 Operation . 259 8.9.5 Usage Note. 262 Section 9 Watchdog Timer . 263 9.1 9.2 9.3 9.4 9.5 9.6 Features . 263 Input/Output Pin. 264 Register Descriptions . 265 9.3.1 Timer Counter (TCNT). 265 9.3.2 Timer Control/Status Register (TCSR) . 266 9.3.3 Reset Control/Status Register (RSTCSR) . 268 Operation. 269 9.4.1 Watchdog Timer Mode . 269 9.4.2 Interval Timer Mode . 271 9.4.3 Clearing Software Standby Mode . 271 9.4.4 Timing of Setting the Overflow Flag (OVF) . 272 9.4.5 Timing of Setting the Watchdog Timer Overflow Flag (WOVF). 272 Interrupt Source. 273 Usage Notes . 273 9.6.1 Notes on Register Access. 273 9.6.2 TCNT Write and Increment Contention. 275 9.6.3 Changing CKS2 to CKS0 Bit Values. 275 9.6.4 Changing between Watchdog Timer/Interval Timer Modes. 275 9.6.5 System Reset by WDTOVF Signal. 276 9.6.6 Internal Reset in Watchdog Timer Mode. 276 9.6.7 Manual Reset in Watchdog Timer Mode . 276 9.6.8 Notes on Using WDTOVF pin. 276 Rev.2.00 Sep. 27, 2007 Page xvii of xxxiv REJ09B0394-0200 REJ09B0394-0200 Section 10 Serial Communication Interface (SCI) .277 10.1 Features. 277 10.2 Input/Output Pins . 279 10.3 Register Descriptions . 279 10.3.1 Receive Shift Register (RSR) . 280 10.3.2 Receive Data Register (RDR) . 280 10.3.3 Transmit Shift Register (TSR) . 280 10.3.4 Transmit Data Register (TDR). 280 10.3.5 Serial Mode Register (SMR) . 281 10.3.6 Serial Control Register (SCR). 283 10.3.7 Serial Status Register (SSR) . 285 10.3.8 Serial Direction Control Register (SDCR). 287 10.3.9 Bit Rate Register (BRR) . 287 10.4 Operation in Asynchronous Mode . 296 10.4.1 Data Transfer Format. 296 10.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode . 298 10.4.3 Clock. 299 10.4.4 SCI Initialization (Asynchronous Mode) . 300 10.4.5 Data Transmission (Asynchronous Mode). 301 10.4.6 Serial Data Reception (Asynchronous Mode). 303 10.5 Multiprocessor Communication Function. 307 10.5.1 Multiprocessor Serial Data Transmission . 309 10.5.2 Multiprocessor Serial Data Reception . 310 10.6 Operation in Clocked Synchronous Mode . 313 10.6.1 Clock. 313 10.6.2 SCI Initialization (Clocked Synchronous Mode) . 314 10.6.3 Serial Data Transmission (Clocked Synchronous Mode) . 315 10.6.4 Serial Data Reception (Clocked Synchronous Mode). 318 10.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) . 320 10.7 Interrupts Sources . 322 10.7.1 Interrupts in Normal Serial Communication Interface Mode . 322 10.8 Usage Notes . 323 10.8.1 TDR Write and TDRE Flag . 323 10.8.2 Module Standby Mode Setting . 323 10.8.3 Break Detection and Processing (Asynchronous Mode Only). 323 10.8.4 Sending a Break Signal (Asynchronous Mode Only) . 323 10.8.5 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) . 324 Rev.2.00 Sep. 27, 2007 Page xviii of xxxiv REJ09B0394-0200 REJ09B0394-0200 10.8.6 Cautions on Clocked Synchronous External Clock Mode . 324 10.8.7 Caution on Clocked Synchronous Internal Clock Mode. 324 Section 11 A/D Converter. 325 11.1 Features . 325 11.2 Input/Output Pins . 327 11.3 Register Descriptions . 328 11.3.1 A/D Data Registers 8 to 15 (ADDR8 to ADDR15 ADDR15) . 328 11.3.2 A/D Control/Status Registers_0 and _1 (ADCSR_0 and ADCSR_1) . 329 11.3.3 A/D Control Registers_0 and _1 (ADCR_0 and ADCR_1). 330 11.3.4 A/D Trigger Select Register (ADTSR) . 332 11.4 Operation. 333 11.4.1 Single Mode. 333 11.4.2 Continuous Scan Mode . 333 11.4.3 Single-Cycle Scan Mode. 335 11.4.4 Input Sampling and A/D Conversion Time. 335 11.4.5 A/D Converter Activation by MTU . 337 11.4.6 External Trigger Input Timing . 337 11.5 Interrupt Sources . 338 11.6 Definitions of A/D Conversion Accuracy . 338 11.7 Usage Notes . 340 11.7.1 Module Standby Mode Setting . 340 11.7.2 Permissible Signal Source Impedance . 340 11.7.3 Influences on Absolute Accuracy . 340 11.7.4 Range of Analog Power Supply and Other Pin Settings . 341 11.7.5 Notes on Board Design . 341 11.7.6 Notes on Noise Countermeasures . 341 Section 12 Compare Match Timer (CMT). 343 12.1 Features . 343 12.2 Register Descriptions . 344 12.2.1 Compare Match Timer Start Register (CMSTR) . 344 12.2.2 Compare Match Timer Control/Status Register_0 and _1 (CMCSR_0, CMCSR_1) . 345 12.2.3 Compare Match Timer Counter_0 and _1 (CMCNT_0, CMCNT_1). 346 12.2.4 Compare Match Timer Constant Register_0 and _1 (CMCOR_0, CMCOR_1). 346 12.3 Operation. 346 12.3.1 Cyclic Count Operation . 346 12.3.2 CMCNT Count Timing. 347 12.4 Interrupts . 347 Rev.2.00 Sep. 27, 2007 Page xix of xxxiv REJ09B0394-0200 REJ09B0394-0200 12.4.1 Interrupt Sources. 347 12.4.2 Compare Match Flag Set Timing. 347 12.4.3 Compare Match Flag Clear Timing . 348 12.5 Usage Notes . 349 12.5.1 Contention between CMCNT Write and Compare Match. 349 12.5.2 Contention between CMCNT Word Write and Incrementation . 350 12.5.3 Contention between CMCNT Byte Write and Incrementation . 351 Section 13 Pin Function Controller (PFC) .353 13.1 Register Descriptions . 360 13.1.1 Port A I/O Register L (PAIORL). 360 13.1.2 Port A Control Registers L3 to L1 (PACRL3 to PACRL1). 361 13.1.3 Port B I/O Register (PBIOR) . 364 13.1.4 Port B Control Registers 1 and 2 (PBCR1 and PBCR2). 365 13.1.5 Port E I/O Registers L and H (PEIORL and PEIORH). 366 13.1.6 Port E Control Registers L1, L2, and H (PECRL1, PECRL2, and PECRH) . 366 13.2 Usage Notes . 370 13.2.1 Note on PFC Setting . 370 13.2.2 Note on PFC Setting Order . 370 Section 14 I/O Ports.371 14.1 Port A 14.1.1 14.1.2 14.2 Port B 14.2.1 14.2.2 14.3 Port E 14.3.1 14.3.2 14.4 Port F 14.4.1 14.4.2 14.5 Port G 14.5.1 14.5.2 . 371 Register Description. 372 Port A Data Register L (PADRL) . 372 . 374 Register Description. 374 Port B Data Register (PBDR) . 374 . 376 Register Descriptions . 377 Port E Data Registers H and L (PEDRH and PEDRL) . 377 . 379 Register Description. 379 Port F Data Register (PFDR) . 379 . 381 Register Description. 381 Port G Data Register (PGDR). 381 Section 15 Mask ROM .383 15.1 Usage Note. 383 Rev.2.00 Sep. 27, 2007 Page xx of xxxiv REJ09B0394-0200 REJ09B0394-0200 Section 16 RAM . 385 16.1 Usage Note. 385 Section 17 Power-Down Modes . 387 17.1 Input/Output Pins . 389 17.2 Register Descriptions . 390 17.2.1 Standby Control Register (SBYCR) . 390 17.2.2 System Control Register (SYSCR) . 392 17.2.3 Module Standby Control Register 1 and 2 (MSTCR1 and MSTCR2). 393 17.3 Operation. 395 17.3.1 Sleep Mode . 395 17.3.2 Software Standby Mode. 396 17.3.3 Module Standby Mode. 398 17.4 Usage Notes . 399 17.4.1 I/O Port Status. 399 17.4.2 Current Consumption during Oscillation Stabilization Wait Period . 399 17.4.3 On-Chip Peripheral Module Interrupt. 399 17.4.4 Writing to MSTCR1 and MSTCR2 . 399 Section 18 List of Registers . 401 18.1 Register Addresses (Order of Address). 401 18.2 Register Bits. 408 18.3 Register States in Each Operating Mode. 415 Section 19 Electrical Characteristics . 421 19.1 Absolute Maximum Ratings . 421 19.2 DC Characteristics . 422 19.3 AC Characteristics . 425 19.3.1 Test Conditions for the AC Characteristics. 425 19.3.2 Clock Timing . 426 19.3.3 Control Signal Timing . 428 19.3.4 Multi-Function Timer Pulse Unit (MPU) Timing. 431 19.3.5 I/O Port Timing. 432 19.3.6 Watchdog Timer (WDT) Timing . 433 19.3.7 Serial Communication Interface (SCI) Timing . 434 19.3.8 Output Enable (POE) Timing . 436 19.3.9 A/D Converter Timing . 436 19.4 A/D Converter Characteristics . 438 Appendix A Pin States . 439 Rev.2.00 Sep. 27, 2007 Page xxi of xxxiv REJ09B0394-0200 REJ09B0394-0200 Appendix B Product Lineup .441 Appendix C Package Dimensions .443 Index .445 Rev.2.00 Sep. 27, 2007 Page xxii of xxxiv REJ09B0394-0200 REJ09B0394-0200 Figures Section 1 Overview Figure 1.1 Internal Block Diagram of SH7101 SH7101. 3 Figure 1.2 SH7101 SH7101 Pin Arrangement . 4 Section 2 CPU Figure 2.1 CPU Internal Registers. 12 Figure 2.2 Data Format in Registers. 15 Figure 2.3 Data Formats in Memory . 16 Figure 2.4 Transitions between Processing States . 41 Section 3 MCU Operating Modes Figure 3.1 Address Map for SH7101 SH7101 Mask ROM Version . 45 Section 4 Clock Pulse Generator Figure 4.1 Block Diagram of Clock Pulse Generator . 47 Figure 4.2 Connection of Crystal Resonator (Example). 48 Figure 4.3 Crystal Resonator Equivalent Circuit . 48 Figure 4.4 Example of External Clock Connection . 49 Figure 4.5 Cautions for Oscillator Circuit System Board Design. 50 Figure 4.6 Recommended External Circuitry around PLL . 51 Section 6 Interrupt Controller (INTC) Figure 6.1 INTC Block Diagram . 67 Figure 6.2 Block Diagram of IRQ3 to IRQ0 Interrupts Control. 76 Figure 6.3 Interrupt Sequence Flowchart . 82 Figure 6.4 Stack after Interrupt Exception Processing . 83 Figure 6.5 Example of the Pipeline Operation when an IRQ Interrupt is Accepted. 85 Section 8 Multi-Function Timer Pulse Unit (MTU) Figure 8.1 Block Diagram of MTU . 94 Figure 8.2 Complementary PWM Mode Output Level Example . 132 Figure 8.3 Example of Counter Operation Setting Procedure . 137 Figure 8.4 Free-Running Counter Operation . 138 Figure 8.5 Periodic Counter Operation. 139 Figure 8.6 Example of Setting Procedure for Waveform Output by Compare Match. 139 Figure 8.7 Example of 0 Output/1 Output Operation . 140 Figure 8.8 Example of Toggle Output Operation . 140 Figure 8.9 Example of Input Capture Operation Setting Procedure . 141 Figure 8.10 Example of Input Capture Operation . 142 Figure 8.11 Example of Synchronous Operation Setting Procedure . 143 Figure 8.12 Example of Synchronous Operation. 144 Rev.2.00 Sep. 27, 2007 Page xxiii of xxxiv REJ09B0394-0200 REJ09B0394-0200 Figure 8.13 Figure 8.14 Figure 8.15 Figure 8.16 Figure 8.17 Figure 8.18 Figure 8.19 Figure 8.20 Figure 8.21 Figure 8.22 Figure 8.23 Figure 8.24 Figure 8.25 Figure 8.26 Figure 8.27 Figure 8.28 Figure 8.29 Figure 8.30 Figure 8.31 Figure 8.32 Figure 8.33 Figure 8.34 Figure 8.35 Figure 8.36 Figure 8.37 Figure 8.38 Figure 8.39 Figure 8.40 Figure 8.41 Figure 8.42 Figure 8.43 Figure 8.44 Figure 8.45 Figure 8.46 Figure 8.47 Figure 8.48 Figure 8.49 Figure 8.50 Figure 8.51 Compare Match Buffer Operation. 145 Input Capture Buffer Operation . 146 Example of Buffer Operation Setting Procedure. 146 Example of Buffer Operation (1) . 147 Example of Buffer Operation (2) . 148 Cascaded Operation Setting Procedure . 149 Example of Cascaded Operation . 150 Example of PWM Mode Setting Procedure . 152 Example of PWM Mode Operation (1) . 153 Example of PWM Mode Operation (2) . 154 Example of PWM Mode Operation (3) . 155 Example of Phase Counting Mode Setting Procedure. 157 Example of Phase Counting Mode 1 Operation . 157 Example of Phase Counting Mode 2 Operation . 158 Example of Phase Counting Mode 3 Operation . 159 Example of Phase Counting Mode 4 Operation . 160 Phase Counting Mode Application Example . 162 Procedure for Selecting the Reset-Synchronized PWM Mode. 165 Reset-Synchronized PWM Mode Operation Example (When the TOCR's OLSN = 1 and OLSP = 1). 166 Block Diagram of Channels 3 and 4 in Complementary PWM Mode . 169 Example of Complementary PWM Mode Setting Procedure. 171 Complementary PWM Mode Counter Operation. 173 Example of Complementary PWM Mode Operation . 175 Example of PWM Cycle Updating. 178 Example of Data Update in Complementary PWM Mode. 179 Example of Initial Output in Complementary PWM Mode (1). 180 Example of Initial Output in Complementary PWM Mode (2). 181 Example of Complementary PWM Mode Waveform Output (1) . 183 Example of Complementary PWM Mode Waveform Output (2) . 183 Example of Complementary PWM Mode Waveform Output (3) . 184 Example of Complementary PWM Mode 0% and 100% Waveform Output (1) . 184 Example of Complementary PWM Mode 0% and 100% Waveform Output (2) . 185 Example of Complementary PWM Mode 0% and 100% Waveform Output (3) . 185 Example of Complementary PWM Mode 0% and 100% Waveform Output (4) . 186 Example of Complementary PWM Mode 0% and 100% Waveform Output (5) . 186 Example of Toggle Output Waveform Synchronized with PWM Output. 187 Counter Clearing Synchronized with Another Channel . 188 Example of Output Phase Switching by External Input (1) . 189 Example of Output Phase Switching by External Input (2) . 190 Rev.2.00 Sep. 27, 2007 Page xxiv of xxxiv REJ09B0394-0200 REJ09B0394-0200 Figure 8.52 Figure 8.53 Figure 8.54 Figure 8.55 Figure 8.56 Figure 8.57 Figure 8.58 Figure 8.59 Figure 8.60 Figure 8.61 Figure 8.62 Figure 8.63 Figure 8.64 Figure 8.65 Figure 8.66 Figure 8.67 Figure 8.68 Figure 8.69 Figure 8.70 Figure 8.71 Figure 8.72 Figure 8.73 Figure 8.74 Figure 8.75 Figure 8.76 Figure 8.77 Figure 8.78 Figure 8.79 Figure 8.80 Figure 8.81 Figure 8.82 Figure 8.83 Figure 8.84 Figure 8.85 Figure 8.86 Figure 8.87 Figure 8.88 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (1). 190 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (2). 191 Count Timing in Internal Clock Operation. 195 Count Timing in External Clock Operation . 195 Count Timing in External Clock Operation (Phase Counting Mode). 196 Output Compare Output Timing (Normal Mode/PWM Mode). 196 Output Compare Output Timing (Complementary PWM Mode/Reset Synchronous PWM Mode) . 197 Input Capture Input Signal Timing. 197 Counter Clear Timing (Compare Match) . 198 Counter Clear Timing (Input Capture) . 198 Buffer Operation Timing (Compare Match) . 199 Buffer Operation Timing (Input Capture) . 199 TGI Interrupt Timing (Compare Match) . 200 TGI Interrupt Timing (Input Capture) . 201 TCIV Interrupt Setting Timing. 202 TCIU Interrupt Setting Timing. 202 Timing for Status Flag Clearing by the CPU . 203 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode . 204 Contention between TCNT Write and Clear Operations. 205 Contention between TCNT Write and Increment Operations . 206 Contention between TGR Write and Compare Match . 207 Contention between Buffer Register Write and Compare Match (Channel 0) . 208 Contention between Buffer Register Write and Compare Match (Channels 3 and 4). 209 Contention between TGR Read and Input Capture . 210 Contention between TGR Write and Input Capture . 211 Contention between Buffer Register Write and Input Capture. 212 TCNT_2 Write and Overflow/Underflow Contention with Cascade Connection. 213 Counter Value during Complementary PWM Mode Stop . 214 Buffer Operation and Compare-Match Flags in Reset Sync PWM Mode. 215 Reset Sync PWM Mode Overflow Flag . 216 Contention between Overflow and Counter Clearing . 217 Contention between TCNT Write and Overflow. 218 Error Occurrence in Normal Mode, Recovery in Normal Mode. 223 Error Occurrence in Normal Mode, Recovery in PWM Mode 1. 224 Error Occurrence in Normal Mode, Recovery in PWM Mode 2. 225 Error Occurrence in Normal Mode, Recovery in Phase Counting Mode . 226 Error Occurrence in Normal Mode, Recovery in Complementary PWM Mode . 227 Rev.2.00 Sep. 27, 2007 Page xxv of xxxiv REJ09B0394-0200 REJ09B0394-0200 Figure 8.89 Figure 8.90 Figure 8.91 Figure 8.92 Figure 8.93 Figure 8.94 Figure 8.95 Figure 8.96 Figure 8.97 Figure 8.98 Figure 8.99 Figure 8.100 Figure 8.101 Figure 8.102 Figure 8.103 Figure 8.104 Figure 8.105 Figure 8.106 Figure 8.107 Figure 8.108 Figure 8.109 Figure 8.110 Figure 8.111 Figure 8.112 Figure 8.113 Figure 8.114 Figure 8.115 Figure 8.116 Error Occurrence in Normal Mode, Recovery in Reset-Synchronous PWM Mode. 228 Error Occurrence in PWM Mode 1, Recovery in Normal Mode . 229 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 1 . 230 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 2 . 231 Error Occurrence in PWM Mode 1, Recovery in Phase Counting Mode. 232 Error Occurrence in PWM Mode 1, Recovery in Complementary PWM Mode. 233 Error Occurrence in PWM Mode 1, Recovery in Reset-Synchronous PWM Mode. 234 Error Occurrence in PWM Mode 2, Recovery in Normal Mode . 235 Error Occurrence in PWM Mode 2, Recovery in PWM Mode 1 . 236 Error Occurrence in PWM Mode 2, Recovery in PWM Mode 2 . 237 Error Occurrence in PWM Mode 2, Recovery in Phase Counting Mode. 238 Error Occurrence in Phase Counting Mode, Recovery in Normal Mode. 239 Error Occurrence in Phase Counting Mode, Recovery in PWM Mode 1. 240 Error Occurrence in Phase Counting Mode, Recovery in PWM Mode 2. 241 Error Occurrence in Phase Counting Mode, Recovery in Phase Counting Mode . 242 Error Occurrence in Complementary PWM Mode, Recovery in Normal Mode. 243 Error Occurrence in Complementary PWM Mode, Recovery in PWM Mode 1. 244 Error Occurrence in Complementary PWM Mode, Recovery in Complementary PWM Mode . 245 Error Occurrence in Complementary PWM Mode, Recovery in Complementary PWM Mode . 246 Error Occurrence in Complementary PWM Mode, Recovery in Reset-Synchronous PWM Mode. 247 Error Occurrence in Reset-Synchronous PWM Mode, Recovery in Normal Mode. 248 Error Occurrence in Reset-Synchronous PWM Mode, Recovery in PWM Mode 1. 249 Error Occurrence in Reset-Synchronous PWM Mode, Recovery in Complementary PWM Mode . 250 Error Occurrence in Reset-Synchronous PWM Mode, Recovery in Reset-Synchronous PWM Mode. 251 POE Block Diagram. 253 Low-Level Detection Operation. 259 Output-Level Detection Operation . 260 Falling Edge Detection Operation. 261 Section 9 Watchdog Timer Figure 9.1 Block Diagram of WDT. 264 Rev.2.00 Sep. 27, 2007 Page xxvi of xxxiv REJ09B0394-0200 REJ09B0394-0200 Figure 9.2 Figure 9.3 Figure 9.4 Figure 9.5 Figure 9.6 Figure 9.7 Figure 9.8 Figure 9.9 Operation in Watchdog Timer Mode . 270 Operation in Interval Timer Mode . 271 Timing of Setting OVF. 272 Timing of Setting WOVF. 272 Writing to TCNT and TCSR . 273 Writing to RSTCSR . 274 Contention between TCNT Write and Increment. 275 Example of System Reset Circuit Using WDTOVF Signal . 276 Section 10 Serial Communication Interface (SCI) Figure 10.1 Block Diagram of SCI. 278 Figure 10.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits). 296 Figure 10.3 Receive Data Sampling Timing in Asynchronous Mode . 298 Figure 10.4 Relation between Output Clock and Transmit Data Phase (Asynchronous Mode). 299 Figure 10.5 Sample SCI Initialization Flowchart . 300 Figure 10.6 Example of Operation in Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) . 301 Figure 10.7 Sample Serial Transmission Flowchart . 302 Figure 10.8 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity, One Stop Bit) . 303 Figure 10.9 Sample Serial Reception Data Flowchart (1) . 305 Figure 10.9 Sample Serial Reception Data Flowchart (2) . 306 Figure 10.10 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) . 308 Figure 10.11 Sample Multiprocessor Serial Transmission Flowchart . 309 Figure 10.12 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit). 310 Figure 10.13 Sample Multiprocessor Serial Reception Flowchart (1). 311 Figure 10.13 Sample Multiprocessor Serial Reception Flowchart (2). 312 Figure 10.14 Data Format in Clocked Synchronous Communication (For LSB-First) . 313 Figure 10.15 Sample SCI Initialization Flowchart . 314 Figure 10.16 Sample SCI Transmission Operation in Clocked Synchronous Mode . 316 Figure 10.17 Sample Serial Transmission Flowchart . 317 Figure 10.18 Example of SCI Operation in Reception . 318 Figure 10.19 Sample Serial Reception Flowchart . 319 Figure 10.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations . 321 Section 11 A/D Converter Figure 11.1 Block Diagram of A/D Converter (For One Module) . 326 Rev.2.00 Sep. 27, 2007 Page xxvii of xxxiv REJ09B0394-0200 REJ09B0394-0200 Figure 11.2 Figure 11.3 Figure 11.4 Figure 11.5 Figure 11.6 Figure 11.7 Figure 11.8 Figure 11.9 Operation Example in Continuous Scan Mode (Three Channels Selected) (AN8 to AN10) . 334 A/D Conversion Timing. 336 External Trigger Input Timing . 337 Definitions of A/D Conversion Accuracy . 339 Definitions of A/D Conversion Accuracy . 339 Example of Analog Input Circuit . 340 Example of Analog Input Protection Circuit. 342 Analog Input Pin Equivalent Circuit . 342 Section 12 Compare Match Timer (CMT) Figure 12.1 CMT Block Diagram. 343 Figure 12.2 Counter Operation. 346 Figure 12.3 Count Timing . 347 Figure 12.4 CMF Set Timing . 348 Figure 12.5 Timing of CMF Clear by CPU . 348 Figure 12.6 CMCNT Write and Compare Match Contention . 349 Figure 12.7 CMCNT Word Write and Increment Contention . 350 Figure 12.8 CMCNT Byte Write and Increment Contention. 351 Section 14 I/O Ports Figure 14.1 Port A . 371 Figure 14.2 Port B . 374 Figure 14.3 Port E. 376 Figure 14.4 Port F. 379 Figure 14.5 Port G . 381 Section 15 Mask ROM Figure 15.1 Mask ROM Block Diagram . 383 Section 17 Power-Down Modes Figure 17.1 Mode Transition Diagram . 389 Figure 17.2 NMI Timing in Software Standby Mode. 398 Section 19 Electrical Characteristics Figure 19.1 Output Load Circuit . 425 Figure 19.2 System Clock Timing. 427 Figure 19.3 EXTAL Clock Input Timing . 427 Figure 19.4 Oscillation Settling Time . 427 Figure 19.5 Reset Input Timing. 429 Figure 19.6 Reset Input Timing. 429 Figure 19.7 Interrupt Signal Input Timing. 430 Figure 19.8 Interrupt Signal Output Timing. 430 Rev.2.00 Sep. 27, 2007 Page xxviii of xxxiv REJ09B0394-0200 REJ09B0394-0200 Figure 19.9 Figure 19.10 Figure 19.11 Figure 19.12 Figure 19.13 Figure 19.14 Figure 19.15 Figure 19.16 MTU Input/Output Timing. 431 MTU Clock Input Timing . 432 I/O Port Input/Output Timing. 433 WDT Timing . 433 Input Clock Timing . 434 SCI Input/Output Timing . 435 POE Input/Output Timing . 436 External Trigger Input Timing . 437 Appendix C Package Dimensions Figure C.1 FP-80Q FP-80Q . 443 Rev.2.00 Sep. 27, 2007 Page xxix of xxxiv REJ09B0394-0200 REJ09B0394-0200 Rev.2.00 Sep. 27, 2007 Page xxx of xxxiv REJ09B0394-0200 REJ09B0394-0200 Tables Section 1 Overview Table 1.1 Pin Functions . 5 Table 1.2 Differences from SH7046 SH7046 Group . 9 Section 2 Table 2.1 Table 2.2 Table 2.3 Table 2.4 Table 2.5 Table 2.6 Table 2.7 Table 2.8 Table 2.9 Table 2.10 Table 2.11 Table 2.12 Table 2.13 Table 2.14 Table 2.15 Table 2.16 Table 2.17 CPU Initial Values of Registers. 15 Sign Extension of Word Data . 17 Delayed Branch Instructions. 17 T Bit . 18 Immediate Data Accessing. 18 Absolute Address Accessing. 19 Displacement Accessing . 19 Addressing Modes and Effective Addresses. 20 Instruction Formats . 24 Classification of Instructions . 27 Symbols Used in Instruction Code, Operation, and Execution States Tables . 30 Data Transfer Instructions. 31 Arithmetic Operation Instructions . 33 Logic Operation Instructions . 36 Shift Instructions. 37 Branch Instructions . 38 System Control Instructions. 39 Section 3 MCU Operating Modes Table 3.1 Selection of Operating Modes. 43 Table 3.2 Maximum Operating Clock Frequency for Each Clock Mode . 43 Table 3.3 Operating Mode Pin Configuration. 44 Section 4 Clock Pulse Generator Table 4.1 Damping Resistance Values. 48 Table 4.2 Crystal Resonator Characteristics . 48 Section 5 Exception Processing Table 5.1 Types of Exception Processing and Priority . 53 Table 5.2 Timing for Exception Source Detection and Start of Exception Processing. 54 Table 5.3 Exception Processing Vector Table . 55 Table 5.4 Calculating Exception Processing Vector Table Addresses. 56 Table 5.5 Reset Status. 57 Table 5.6 Bus Cycles and Address Errors. 59 Table 5.7 Interrupt Sources. 60 Rev.2.00 Sep. 27, 2007 Page xxxi of xxxiv REJ09B0394-0200 REJ09B0394-0200 Table 5.8 Interrupt Priority . 61 Table 5.9 Types of Exceptions Triggered by Instructions . 62 Table 5.10 Generation of Exception Sources Immediately after Delayed Branch Instruction or Interrupt-Disabled Instruction . 64 Table 5.11 Stack Status after Exception Processing Ends . 65 Section 6 Interrupt Controller (INTC) Table 6.1 Pin Configuration. 68 Table 6.2 Interrupt Exception Processing Vectors and Priorities . 78 Table 6.3 Interrupt Response Time. 84 Section 7 Bus State Controller (BSC) Table 7.1 Address Map . 88 Table 7.2 On-chip Peripheral I/O Register Access . 90 Section 8 Table 8.1 Table 8.2 Table 8.3 Table 8.4 Table 8.5 Table 8.6 Table 8.7 Table 8.8 Table 8.9 Table 8.10 Table 8.11 Table 8.12 Table 8.13 Table 8.14 Table 8.15 Table 8.16 Table 8.17 Table 8.18 Table 8.19 Table 8.20 Table 8.21 Table 8.22 Table 8.23 Table 8.24 Table 8.25 Table 8.26 Multi-Function Timer Pulse Unit (MTU) MTU Functions. 92 Pin configuration. 95 CCLR0 to CCLR2 (channels 0, 3, and 4) . 99 CCLR0 to CCLR2 (channels 1 and 2) . 99 TPSC0 to TPSC2 (channel 0) . 100 TPSC0 to TPSC2 (channel 1) . 100 TPSC0 to TPSC2 (channel 2) . 101 TPSC0 to TPSC2 (channels 3 and 4) . 101 MD0 to MD3 . 103 TIORH_0 (channel 0) . 106 TIORH_0 (channel 0) . 107 TIORL_0 (channel 0). 108 TIORL_0 (channel 0). 109 TIOR_1 (channel 1) . 110 TIOR_1 (channel 1) . 111 TIOR_2 (channel 2) . 112 TIOR_2 (channel 2) . 113 TIORH_3 (channel 3) . 114 TIORH_3 (channel 3) . 115 TIORL_3 (channel 3). 116 TIORL_3 (channel 3). 117 TIORH_4 (channel 4) . 118 TIORH_4 (channel 4) . 119 TIORL_4 (channel 4). 120 TIORL_4 (channel 4). 121 Output Level Select Function . 131 Rev.2.00 Sep. 27, 2007 Page xxxii of xxxiv REJ09B0394-0200 REJ09B0394-0200 Table 8.27 Table 8.28 Table 8.29 Table 8.30 Table 8.31 Table 8.32 Table 8.33 Table 8.34 Table 8.35 Table 8.36 Table 8.37 Table 8.38 Table 8.39 Table 8.40 Table 8.41 Table 8.42 Table 8.43 Table 8.44 Table 8.45 Output Level Select Function . 132 Output level Select Function. 134 Register Combinations in Buffer Operation . 145 Cascaded Combinations. 149 PWM Output Registers and Output Pins . 151 Phase Counting Mode Clock Input Pins . 156 Up/Down-Count Conditions in Phase Counting Mode 1. 158 Up/Down-Count Conditions in Phase Counting Mode 2. 159 Up/Down-Count Conditions in Phase Counting Mode 3. 160 Up/Down-Count Conditions in Phase Counting Mode 4. 161 Output P