REJ09B0353-0300 H8/3039 H8/3039F-ZTATTM H8/300H H8/3037 HD6433037F HD64F3039F - Datasheet Archive

 

The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and

 

REJ09B0353-0300 REJ09B0353-0300 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. 16 H8/3039 H8/3039 Group, H8/3039F-ZTATTM H8/3039F-ZTATTM Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H H8/300H Series H8/3037 H8/3037 HD6433037F HD6433037F H8/3039 H8/3039 HD64F3039F HD64F3039F HD6433037TE HD6433037TE HD64F3039TE HD64F3039TE HD6433037VF HD6433037VF HD64F3039VF HD64F3039VF HD6433037VTE HD6433037VTE HD64F3039VTE HD64F3039VTE H8/3036 H8/3036 HD6433036F HD6433036F HD6433039F HD6433039F HD6433036TE HD6433036TE HD6433039TE HD6433039TE HD6433036VF HD6433036VF HD6433039VF HD6433039VF HD6433036VTE HD6433036VTE HD6433039VTE HD6433039VTE H8/3038 H8/3038 HD6433038F HD6433038F HD6433038TE HD6433038TE HD6433038VF HD6433038VF HD6433038VTE HD6433038VTE Rev.3.00 Revision date: Mar. 26, 2007 www.renesas.com Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. Rev.3.00 Mar. 26, 2007 Page ii of xxii REJ09B0353-0300 REJ09B0353-0300 General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions may occur due to the false recognition of the pin state as an input signal. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited. The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized. When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different type number, confirm that the change will not lead to problems. The characteristics of MPU/MCU in the same group but having different type numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different type numbers, implement a system-evaluation test for each of the products. Rev.3.00 Mar. 26, 2007 Page iii of xxii REJ09B0353-0300 REJ09B0353-0300 Rev.3.00 Mar. 26, 2007 Page iv of xxii REJ09B0353-0300 REJ09B0353-0300 Preface The H8/3039 H8/3039 Group comprises high-performance single-chip microcomputers (MCUs) that integrate system supporting functions together with an H8/300H H8/300H CPU core. The H8/300H H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address space. The on-chip system supporting functions include ROM, RAM, a 16-bit integrated timer unit (ITU), a programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial communication interface (SCI), an A/D converter, I/O ports, and other facilities. Of the two SCI channels, one has been expanded to support the ISO/IEC 7816-3 smart card interface. Functions have also been added to reduce power consumption in battery-powered applications: individual modules can be placed in standby, and the frequency of the system clock supplied to the chip can be divided down under software control. The five MCU operating modes offer a choice of expanded mode, single-chip mode, and address space size, enabling the H8/3039 H8/3039 Group to adapt quickly and flexibly to a variety of conditions. In addition to its mask-ROM versions, the H8/3039 H8/3039 Group has an F-ZTATTM version with user programmable on-chip flash memory that can be programmed on-board. These versions enable users to respond quickly and flexibly to changing application specifications. This manual describes the H8/3039 H8/3039 Group hardware. For details of the instruction set, refer to the H8/300H H8/300H Series Software Manual. Note: F-ZTAT is a trademark of Renesas Technology Corp. Rev.3.00 Mar. 26, 2007 Page v of xxii REJ09B0353-0300 REJ09B0353-0300 Rev.3.00 Mar. 26, 2007 Page vi of xxii REJ09B0353-0300 REJ09B0353-0300 Main Revisions for This Edition Item Page Revision (See Manual for Details) All - · Notification of change in company name amended (Before) Hitachi, Ltd. (After) Renesas Technology Corp. · Product naming convention amended (Before) H8/3039 H8/3039 Series (After) H8/3039 H8/3039 Group 2.3 Address Space 20 Figure amended H'0000 Figure 2.2 Memory Map H'FFFF 1. Normal mode (64-Kbyte mode) 5.2.2 Interrupt Priority 91 Registers A and B (IPRA, IPRB) Description amended Bit 7 6 5 4 3 2 1 0 IPRB7 IPRB6 - - IPRB3 IPRB2 IPRB1 - Initial value 5.2.3 IRQ Status Register (ISR) 93 5.2.4 IRQ Enable Register (IER) 94 0 0 0 0 0 0 0 0 Read/Write Interrupt Priority Register B (IPRB) R/W R/W R/W R/W R/W R/W R/W R/W Description amended Bits 5, 4, 1 and 0-IRQ5, IRQ4, IRQ1 and IRQ0 Flags (IRQ5F, IRQ4F, IRQ1F, and IRQ0F): These bits indicate the status of IRQ5, IRQ4, IRQ1, and IRQ0 interrupt requests. Description amended Bit 7 6 - - Initial value 0 0 Read/Write R/W R/W Reserved bits Bits 5, 4, 1, and 0-IRQ5, IRQ4, IRQ1, and IRQ0 Enable (IRQ5E, IRQ4E, IRQ1E, IRQ0E): These bits enable or disable IRQ5 , IRQ4 , IRQ1 , IRQ0 interrupts. Rev.3.00 Mar. 26, 2007 Page vii of xxii REJ09B0353-0300 REJ09B0353-0300 Item Page Revision (See Manual for Details) 5.3.3 Interrupt Vector Table 98 Table amended WOVI (interval timer) Table 5.3 Interrupt Sources, Vector Addresses, and Priority 5.5.4 Usage Notes 109 Figure amended Figure 5.9 IRQnF Flag when Interrupt Exception Handling is not Executed 1 read 0 written 1 read 0 written (Inadvertent clearing) Generation condition (2) 6.4.2 Precautions on Setting ASTCR and ABWCR* 131 11.2.8 Bit Rate Register (BRR) 349 Table 11.3 Examples of Bit Rates and BRR Settings in Asynchronous Mode 351 Description amended Modes 5 and 7 ASTCR0 = 0 ABWCR = H'FC Description added The baud rate generator is controlled separately for the individual channels, so different values may be set for each. Table amended (MHz) 12 Bit Rate (bits/s) Clock 376 N Error (%) 300 11.3.4 Synchronous Operation n 2 77 0.16 Description amended An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected by clearing or setting the CKE1 and CKE0 bits in SCR and the C/A bit in SMR. See table 11.9. Rev.3.00 Mar. 26, 2007 Page viii of xxii REJ09B0353-0300 REJ09B0353-0300 Item Page Revision (See Manual for Details) 16.2.1 Connecting a Crystal Resonator 500 Preliminary deleted 532 Table amended Table 16.2 Crystal Resonator Parameters 18.1.3 AC Characteristics Condition A Table 18.5 Control Signal Timing Condition B 8 MHz 10 MHz Condition C 18 MHz Item Symbol Min Max Min Max Min Max Unit Test Conditions RES setup time tRESS 200 - 200 - 200 - ns Figure 18.10 RES pulse width tRESW 10 - 10 - 10 - tcyc 200 - 200 - 200 - ns Mode programming tMDS setup time (MD0, MD1, MD2) 18.1.4 A/D Conversion 535 Characteristics Newly added 18.2.2 DC Characteristics Table amended 541 Item Table 18.10 Permissible Output Currents A.1 Instruction List Total of 27 pins including ports 1, 2, 5 and B Permissible output low current (total) 576 Table amended Mnemonic EEPMOV. W A.3 Number of States 584 Required for Execution Table A.4 Number of Cycles per Instruction Operand Size 8. Block transfer instructions Operation - if R4 0 then repeat @R5 @R6 R5+1 R5 R6+1 R6 R4-1 R4 until R4=0 else next Table amended Instruction Mnemonic BSR BSR d:16 Word Data Access M Internal Operation N Normal 2 Advanced 2 Rev.3.00 Mar. 26, 2007 Page ix of xxii REJ09B0353-0300 REJ09B0353-0300 All trademarks and registered trademarks are the property of their respective owners. Rev.3.00 Mar. 26, 2007 Page x of xxii REJ09B0353-0300 REJ09B0353-0300 Contents Section 1 Overview . 1.1 1.2 1.3 1.4 1 Overview. 1 Block Diagram . 6 Pin Description. 7 1.3.1 Pin Arrangement . 7 1.3.2 Pin Functions . 8 Pin Functions . 12 Section 2 CPU . 17 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 Overview. 2.1.1 Features. 2.1.2 Differences from H8/300 H8/300 CPU. CPU Operating Modes . Address Space . Register Configuration . 2.4.1 Overview. 2.4.2 General Registers . 2.4.3 Control Registers . 2.4.4 Initial CPU Register Values . Data Formats . 2.5.1 General Register Data Formats . 2.5.2 Memory Data Formats . Instruction Set . 2.6.1 Instruction Set Overview . 2.6.2 Instructions and Addressing Modes . 2.6.3 Tables of Instructions Classified by Function. 2.6.4 Basic Instruction Formats . 2.6.5 Notes on Use of Bit Manipulation Instructions. Addressing Modes and Effective Address Calculation . 2.7.1 Addressing Modes . 2.7.2 Effective Address Calculation . Processing States. 2.8.1 Overview. 2.8.2 Program Execution State. 2.8.3 Exception-Handling State . 2.8.4 Exception-Handling Sequences . 2.8.5 Reset State. 17 17 18 19 20 21 21 22 23 24 25 25 27 28 28 29 31 40 41 41 41 45 49 49 49 50 51 53 Rev.3.00 Mar. 26, 2007 Page xi of xxii REJ09B0353-0300 REJ09B0353-0300 2.9 2.8.6 Power-Down State . Basic Operational Timing . 2.9.1 Overview. 2.9.2 On-Chip Memory Access Timing. 2.9.3 On-Chip Supporting Module Access Timing . 2.9.4 Access to External Address Space . 53 54 54 54 55 56 Section 3 MCU Operating Modes . 57 3.1 3.2 3.3 3.4 3.5 3.6 3.7 Overview. 3.1.1 Operating Mode Selection . 3.1.2 Register Configuration. Mode Control Register (MDCR) . System Control Register (SYSCR) . Operating Mode Descriptions . 3.4.1 Mode 1 . 3.4.2 Mode 3 . 3.4.3 Mode 5 . 3.4.4 Mode 6 . 3.4.5 Mode 7 . Pin Functions in Each Operating Mode . Memory Map in Each Operating Mode . Restrictions on Use of Mode 6. 57 57 58 59 60 62 62 62 62 62 62 63 63 72 Section 4 Exception Handling . 75 4.1 4.2 4.3 4.4 4.5 4.6 Overview. 4.1.1 Exception Handling Types and Priority. 4.1.2 Exception Handling Operation . 4.1.3 Exception Vector Table . Reset. 4.2.1 Overview. 4.2.2 Reset Sequence . 4.2.3 Interrupts after Reset. Interrupts. Trap Instruction. Stack Status after Exception Handling. Notes on Stack Usage . 75 75 75 76 78 78 78 80 80 81 81 82 Section 5 Interrupt Controller . 83 5.1 Overview. 83 5.1.1 Features. 83 5.1.2 Block Diagram. 84 Rev.3.00 Mar. 26, 2007 Page xii of xxii REJ09B0353-0300 REJ09B0353-0300 5.2 5.3 5.4 5.5 5.1.3 Pin Configuration. 5.1.4 Register Configuration. Register Descriptions . 5.2.1 System Control Register (SYSCR) . 5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB) . 5.2.3 IRQ Status Register (ISR). 5.2.4 IRQ Enable Register (IER) . 5.2.5 IRQ Sense Control Register (ISCR) . Interrupt Sources . 5.3.1 External Interrupts . 5.3.2 Internal Interrupts. 5.3.3 Interrupt Vector Table. Interrupt Operation. 5.4.1 Interrupt Handling Process. 5.4.2 Interrupt Sequence . 5.4.3 Interrupt Response Time. Usage Notes . 5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction . 5.5.2 Instructions that Inhibit Interrupts. 5.5.3 Interrupts during EEPMOV Instruction Execution . 5.5.4 Usage Notes . 85 85 86 86 88 93 94 95 96 96 97 97 100 100 105 106 107 107 108 108 108 Section 6 Bus Controller. 111 6.1 6.2 6.3 6.4 Overview. 6.1.1 Features. 6.1.2 Block Diagram . 6.1.3 Input/Output Pins . 6.1.4 Register Configuration. Register Descriptions . 6.2.1 Access State Control Register (ASTCR) . 6.2.2 Wait Control Register (WCR). 6.2.3 Wait State Controller Enable Register (WCER) . 6.2.4 Address Control Register (ADRCR). Operation. 6.3.1 Area Division . 6.3.2 Bus Control Signal Timing . 6.3.3 Wait Modes. 6.3.4 Interconnections with Memory (Example) . Usage Notes . 6.4.1 Register Write Timing . 6.4.2 Precautions on Setting ASTCR and ABWCR. 111 111 112 113 113 114 114 115 116 117 119 119 121 123 129 131 131 131 Rev.3.00 Mar. 26, 2007 Page xiii of xxii REJ09B0353-0300 REJ09B0353-0300 Section 7 I/O Ports . 133 7.1 7.2 Overview. Port 1. 7.2.1 Overview. 7.2.2 Register Descriptions . 7.2.3 Pin Functions in Each Mode . 7.3 Port 2. 7.3.1 Overview. 7.3.2 Register Descriptions . 7.3.3 Pin Functions in Each Mode . 7.3.4 Input Pull-Up Transistors. 7.4 Port 3. 7.4.1 Overview. 7.4.2 Register Descriptions . 7.4.3 Pin Functions in Each Mode . 7.5 Port 5. 7.5.1 Overview. 7.5.2 Register Descriptions . 7.5.3 Pin Functions in Each Mode . 7.5.4 Input Pull-Up Transistors. 7.6 Port 6. 7.6.1 Overview. 7.6.2 Register Descriptions . 7.6.3 Pin Functions in Each Mode . 7.7 Port 7. 7.7.1 Overview. 7.7.2 Register Description. 7.8 Port 8. 7.8.1 Overview. 7.8.2 Register Descriptions . 7.8.3 Pin Functions . 7.9 Port 9. 7.9.1 Overview. 7.9.2 Register Descriptions . 7.9.3 Pin Functions . 7.10 Port A. 7.10.1 Overview. 7.10.2 Register Descriptions . 7.10.3 Pin Functions . 7.11 Port B . 7.11.1 Overview. Rev.3.00 Mar. 26, 2007 Page xiv of xxii REJ09B0353-0300 REJ09B0353-0300 133 137 137 138 140 142 142 143 145 147 148 148 148 150 152 152 153 155 156 157 157 158 160 163 163 163 164 164 165 167 168 168 168 170 172 172 173 175 182 182 7.11.2 Register Descriptions . 182 7.11.3 Pin Functions . 184 Section 8 16-Bit Integrated Timer Unit (ITU) . 191 8.1 8.2 8.3 8.4 8.5 8.6 Overview. 8.1.1 Features. 8.1.2 Block Diagrams . 8.1.3 Input/Output Pins . 8.1.4 Register Configuration. Register Descriptions . 8.2.1 Timer Start Register (TSTR). 8.2.2 Timer Synchro Register (TSNC) . 8.2.3 Timer Mode Register (TMDR) . 8.2.4 Timer Function Control Register (TFCR). 8.2.5 Timer Output Master Enable Register (TOER) . 8.2.6 Timer Output Control Register (TOCR) . 8.2.7 Timer Counters (TCNT) . 8.2.8 General Registers (GRA, GRB) . 8.2.9 Buffer Registers (BRA, BRB). 8.2.10 Timer Control Registers (TCR) . 8.2.11 Timer I/O Control Register (TIOR) . 8.2.12 Timer Status Register (TSR). 8.2.13 Timer Interrupt Enable Register (TIER) . CPU Interface. 8.3.1 16-Bit Accessible Registers . 8.3.2 8-Bit Accessible Registers . Operation. 8.4.1 Overview. 8.4.2 Basic Functions. 8.4.3 Synchronization . 8.4.4 PWM Mode. 8.4.5 Reset-Synchronized PWM Mode. 8.4.6 Complementary PWM Mode . 8.4.7 Phase Counting Mode . 8.4.8 Buffering. 8.4.9 ITU Output Timing . Interrupts . 8.5.1 Setting of Status Flags. 8.5.2 Clearing of Status Flags . 8.5.3 Interrupt Sources. Usage Notes . 191 191 194 199 201 204 204 206 208 211 214 216 218 219 220 221 223 225 227 228 228 231 232 232 234 243 245 249 252 261 263 269 272 272 274 275 276 Rev.3.00 Mar. 26, 2007 Page xv of xxii REJ09B0353-0300 REJ09B0353-0300 Section 9 Programmable Timing Pattern Controller . 291 9.1 9.2 9.3 9.4 Overview. 9.1.1 Features. 9.1.2 Block Diagram. 9.1.3 TPC Pins . 9.1.4 Registers. Register Descriptions . 9.2.1 Port A Data Direction Register (PADDR) . 9.2.2 Port A Data Register (PADR). 9.2.3 Port B Data Direction Register (PBDDR) . 9.2.4 Port B Data Register (PBDR) . 9.2.5 Next Data Register A (NDRA) . 9.2.6 Next Data Register B (NDRB). 9.2.7 Next Data Enable Register A (NDERA). 9.2.8 Next Data Enable Register B (NDERB) . 9.2.9 TPC Output Control Register (TPCR) . 9.2.10 TPC Output Mode Register (TPMR) . Operation . 9.3.1 Overview. 9.3.2 Output Timing . 9.3.3 Normal TPC Output. 9.3.4 Non-Overlapping TPC Output. 9.3.5 TPC Output Triggering by Input Capture . Usage Notes . 9.4.1 Operation of TPC Output Pins . 9.4.2 Note on Non-Overlapping Output. 291 291 292 293 294 295 295 295 296 296 297 299 301 302 303 306 308 308 309 310 312 314 315 315 315 Section 10 Watchdog Timer . 317 10.1 Overview. 10.1.1 Features. 10.1.2 Block Diagram. 10.1.3 Pin Configuration. 10.1.4 Register Configuration. 10.2 Register Descriptions . 10.2.1 Timer Counter (TCNT). 10.2.2 Timer Control/Status Register (TCSR). 10.2.3 Reset Control/Status Register (RSTCSR) . 10.2.4 Notes on Register Access. 10.3 Operation . 10.3.1 Watchdog Timer Operation . 10.3.2 Interval Timer Operation . Rev.3.00 Mar. 26, 2007 Page xvi of xxii REJ09B0353-0300 REJ09B0353-0300 317 317 318 318 319 319 319 320 322 324 326 326 327 10.3.3 Timing of Setting of Overflow Flag (OVF) . 10.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST). 10.4 Interrupts . 10.5 Usage Notes . 328 329 329 330 Section 11 Serial Communication Interface . 331 11.1 Overview. 11.1.1 Features. 11.1.2 Block Diagram . 11.1.3 Input/Output Pins . 11.1.4 Register Configuration. 11.2 Register Descriptions . 11.2.1 Receive Shift Register (RSR). 11.2.2 Receive Data Register (RDR) . 11.2.3 Transmit Shift Register (TSR) . 11.2.4 Transmit Data Register (TDR). 11.2.5 Serial Mode Register (SMR). 11.2.6 Serial Control Register (SCR). 11.2.7 Serial Status Register (SSR). 11.2.8 Bit Rate Register (BRR) . 11.3 Operation. 11.3.1 Overview. 11.3.2 Operation in Asynchronous Mode . 11.3.3 Multiprocessor Communication. 11.3.4 Synchronous Operation. 11.4 SCI Interrupts. 11.5 Usage Notes . 331 331 333 334 335 336 336 336 337 337 338 341 345 349 358 358 360 369 376 384 385 Section 12 Smart Card Interface . 12.1 Overview. 12.1.1 Features. 12.1.2 Block Diagram . 12.1.3 Pin Configuration. 12.1.4 Register Configuration. 12.2 Register Descriptions . 12.2.1 Smart Card Mode Register (SCMR) . 12.2.2 Serial Status Register (SSR). 12.3 Operation. 12.3.1 Overview. 12.3.2 Pin Connections . 12.3.3 Data Format . 391 391 391 392 393 393 394 394 396 397 397 398 399 Rev.3.00 Mar. 26, 2007 Page xvii of xxii REJ09B0353-0300 REJ09B0353-0300 12.3.4 Register Settings . 12.3.5 Clock. 12.3.6 Data Transfer Operations. 12.4 Usage Note. 401 403 405 411 Section 13 A/D Converter . 415 13.1 Overview. 13.1.1 Features. 13.1.2 Block Diagram. 13.1.3 Input Pins . 13.1.4 Register Configuration. 13.2 Register Descriptions . 13.2.1 A/D Data Registers A to D (ADDRA to ADDRD) . 13.2.2 A/D Control/Status Register (ADCSR) . 13.2.3 A/D Control Register (ADCR) . 13.3 CPU Interface. 13.4 Operation . 13.4.1 Single Mode (SCAN = 0) . 13.4.2 Scan Mode (SCAN = 1). 13.4.3 Input Sampling and A/D Conversion Time . 13.4.4 External Trigger Input Timing. 13.5 Interrupts. 13.6 Usage Notes . 415 415 416 417 418 419 419 420 422 423 424 424 426 428 429 430 430 Section 14 RAM . 14.1 Overview. 14.1.1 Block Diagram. 14.1.2 Register Configuration. 14.2 System Control Register (SYSCR) . 14.3 Operation . 435 435 436 436 437 438 Section 15 ROM . 439 15.1 Overview. 439 15.2 Overview of Flash Memory . 440 15.2.1 Features. 440 15.2.2 Block Diagram. 441 15.2.3 Pin Configuration. 442 15.2.4 Register Configuration. 442 15.3 Register Descriptions . 443 15.3.1 Flash Memory Control Register (FLMCR). 443 15.3.2 Erase Block Register (EBR) . 447 Rev.3.00 Mar. 26, 2007 Page xviii of xxii REJ09B0353-0300 REJ09B0353-0300 15.4 15.5 15.6 15.7 15.8 15.9 15.10 15.11 15.3.3 RAM Control Register (RAMCR) . 15.3.4 Flash Memory Status Register (FLMSR). On-Board Programming Modes. 15.4.1 Boot Mode . 15.4.2 User Program Mode. Programming/Erasing Flash Memory . 15.5.1 Program Mode . 15.5.2 Program-Verify Mode. 15.5.3 Erase Mode . 15.5.4 Erase-Verify Mode. Flash Memory Protection. 15.6.1 Hardware Protection . 15.6.2 Software Protection. 15.6.3 Error Protection. 15.6.4 NMI Input Disable Conditions. Flash Memory Emulation by RAM. Flash Memory PROM Mode. 15.8.1 PROM Mode Setting. 15.8.2 Memory Map . 15.8.3 PROM Mode Operation . 15.8.4 Memory Read Mode . 15.8.5 Auto-Program Mode . 15.8.6 Auto-Erase Mode . 15.8.7 Status Read Mode . 15.8.8 PROM Mode Transition Time . 15.8.9 Notes on Memory Programming. Notes on Flash Memory Programming/Erasing. Mask ROM Overview . 15.10.1 Block Diagram . Notes on Ordering Mask ROM Version Chip. 449 451 452 455 460 462 463 464 466 466 468 468 470 471 473 474 475 475 476 476 479 482 484 485 487 488 488 494 494 495 Section 16 Clock Pulse Generator . 497 16.1 Overview. 16.1.1 Block Diagram . 16.2 Oscillator Circuit. 16.2.1 Connecting a Crystal Resonator. 16.2.2 External Clock Input . 16.3 Duty Adjustment Circuit . 16.4 Prescalers . 16.5 Frequency Divider. 16.5.1 Register Configuration. 497 498 498 499 501 504 504 504 504 Rev.3.00 Mar. 26, 2007 Page xix of xxii REJ09B0353-0300 REJ09B0353-0300 16.5.2 Division Control Register (DIVCR) . 505 16.5.3 Usage Notes . 506 Section 17 Power-Down State . 507 17.1 Overview. 507 17.2 Register Configuration. 509 17.2.1 System Control Register (SYSCR) . 509 17.2.2 Module Standby Control Register (MSTCR) . 511 17.3 Sleep Mode . 513 17.3.1 Transition to Sleep Mode. 513 17.3.2 Exit from Sleep Mode. 513 17.4 Software Standby Mode. 514 17.4.1 Transition to Software Standby Mode . 514 17.4.2 Exit from Software Standby Mode . 514 17.4.3 Selection of Oscillator Waiting Time after Exit from Software Standby Mode . 515 17.4.4 Sample Application of Software Standby Mode. 516 17.4.5 Usage Note. 516 17.5 Hardware Standby Mode . 517 17.5.1 Transition to Hardware Standby Mode. 517 17.5.2 Exit from Hardware Standby Mode . 517 17.5.3 Timing for Hardware Standby Mode . 518 17.6 Module Standby Function. 519 17.6.1 Module Standby Timing . 519 17.6.2 Read/Write in Module Standby . 519 17.6.3 Usage Notes . 519 17.7 System Clock Output Disabling Function. 520 Section 18 Electrical Characteristics. 18.1 Electrical Characteristics of Mask ROM Version. 18.1.1 Absolute Maximum Ratings . 18.1.2 DC Characteristics . 18.1.3 AC Characteristics . 18.1.4 A/D Conversion Characteristics. 18.2 Electrical Characteristics of Flash Memory Version . 18.2.1 Absolute Maximum Ratings . 18.2.2 DC Characteristics . 18.2.3 AC Characteristics . 18.2.4 A/D Conversion Characteristics. 18.2.5 Flash Memory Characteristics . 18.3 Operational Timing. 18.3.1 Bus Timing . Rev.3.00 Mar. 26, 2007 Page xx of xxii REJ09B0353-0300 REJ09B0353-0300 521 521 521 522 530 535 536 536 537 543 548 549 552 552 18.3.2 18.3.3 18.3.4 18.3.5 18.3.6 Control Signal Timing . Clock Timing . TPC and I/O Port Timing. ITU Timing . SCI Input/Output Timing . 556 558 558 559 560 Appendix A Instruction Set . 561 A.1 A.2 A.3 Instruction List . 561 Operation Code Maps . 577 Number of States Required for Execution . 580 Appendix B Internal I/O Register Field . 590 B.1 B.2 Addresses . 590 Function . 597 Appendix C I/O Block Diagrams . 655 C.1 C.2 C.3 C.4 C.5 C.6 C.7 C.8 C.9 C.10 Port 1 Block Diagram . Port 2 Block Diagram . Port 3 Block Diagram . Port 5 Block Diagram . Port 6 Block Diagram . Port 7 Block Diagram . Port 8 Block Diagram . Port 9 Block Diagram . Port A Block Diagram. Port B Block Diagram. 655 656 657 658 659 661 662 664 668 671 Appendix D Pin States . 674 D.1 D.2 Port States in Each Mode . 674 Pin States at Reset . 676 Appendix E Timing of Transition to and Recovery from Hardware Standby Mode. 679 Appendix F Product Lineup . 680 Appendix G Package Dimensions . 681 Rev.3.00 Mar. 26, 2007 Page xxi of xxii REJ09B0353-0300 REJ09B0353-0300 Rev.3.00 Mar. 26, 2007 Page xxii of xxii REJ09B0353-0300 REJ09B0353-0300 Section 1 Overview Section 1 Overview 1.1 Overview The H8/3039 H8/3039 Group comprises microcomputers (MCUs) that integrate system supporting functions together with an H8/300H H8/300H CPU core featuring an original Renesas Technology architecture. The H8/300H H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address space. Its instruction set is upward-compatible at the object-code level with the H8/300 H8/300 CPU, enabling easy porting of software from the H8/300 H8/300 Series. The on-chip system supporting functions include ROM, RAM, a 16-bit integrated timer unit (ITU), a programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial communication interface (SCI), an A/D converter, I/O ports, and other facilities. The H8/3039 H8/3039 Group consists of four models: the H8/3039 H8/3039 with 128 kbytes of ROM and 4 kbytes of RAM, the H8/3038 H8/3038 with 64 kbytes of ROM and 2 kbytes of RAM, the H8/3037 H8/3037 with 32 kbytes of ROM and 1 kbytes of RAM, and the H8/3036 H8/3036 with 16 kbytes of ROM and 512 bytes of RAM. The five MCU operating modes offer a choice of expanded mode, single-chip mode and address space size. In addition to the mask-ROM version of the H8/3039 H8/3039 Group, an F-ZTATTM version with an onchip flash memory that can be freely programmed and reprogrammed by the user after the board is installed is also available. This version enables users to respond quickly and flexibly to changing application specifications, growing production volumes, and other conditions. Table 1.1 summarizes the features of the H8/3039 H8/3039 Group. Note: F-ZTAT is a trademark of Renesas Technology Corp. Rev.3.00 Mar. 26, 2007 Page 1 of 682 REJ09B0353-0300 REJ09B0353-0300 Section 1 Overview Table 1.1 Features Feature Description CPU Upward-compatible with the H8/300 H8/300 CPU at the object-code level General-register machine · Sixteen 16-bit general registers (also useable as sixteen 8-bit registers or eight 32-bit registers) High-speed operation · Maximum clock rate: 18 MHz · Add/subtract: 111 ns · Multiply/divide: 778 ns Two CPU operating modes · Normal mode (64-kbyte address space) · Advanced mode (16-Mbyte address space) Instruction features · 8/16/32-bit data transfer, arithmetic, and logic instructions · Signed and unsigned multiply instructions (8 bits × 8 bits, 16 bits × 16 bits) · Signed and unsigned divide instructions (16 bits ÷ 8 bits, 32 bits ÷ 16 bits) · Bit accumulator function · Bit manipulation instructions with register-indirect specification of bit positions Rev.3.00 Mar. 26, 2007 Page 2 of 682 REJ09B0353-0300 REJ09B0353-0300 Section 1 Overview Feature Description Memory H8/3039 H8/3039 · ROM: 128 kbytes · RAM: 4 kbytes H8/3038 H8/3038 · ROM: 64 kbytes · RAM: 2 kbytes H8/3037 H8/3037 · ROM: 32 kbytes · RAM: 1 kbyte H8/3036 H8/3036 · Five external interrupt pins: NMI, IRQ0, IRQ1, IRQ4, IRQ5 25 internal interrupts Three selectable interrupt priority levels · Address space can be partitioned into eight areas, with independent bus specifications in each area · Two-state or three-state access selectable for each area · 16-bit integrated timer unit (ITU) · · Bus controller RAM: 512 bytes · Interrupt controller ROM: 16 kbytes · Selection of four wait modes · Five 16-bit timer channels, capable of processing up to 12 pulse outputs or 10 pulse inputs · 16-bit timer counter (channels 0 to 4) · Two multiplexed output compare/input capture pins (channels 0 to 4) · Operation can be synchronized (channels 0 to 4) · PWM mode available (channels 0 to 4) · Phase counting mode available (channel 2) · Buffering available (channels 3 and 4) · Reset-synchronized PWM mode available (channels 3 and 4) · Complementary PWM mode available (channels 3 and 4) Rev.3.00 Mar. 26, 2007 Page 3 of 682 REJ09B0353-0300 REJ09B0353-0300 Section 1 Overview Feature Description Programmable timing pattern controller (TPC) · Maximum 15-bit pulse output, using ITU as time base · Up to three 4-bit pulse output groups and one 3-bit pulse output group (or one 15-bit group, one 8-bit group, or one 7-bit group) · Non-overlap mode available Watchdog timer (WDT), 1 channel · Reset signal can be generated by overflow · Reset signal can be output externally (However, not available with the F-ZTAT version.) · Usable as an interval timer Serial communication interface (SCI), 2 channels · Selection of asynchronous or synchronous mode · Full duplex: can transmit and receive simultaneously · On-chip baud-rate generator · Smart card interface functions added (SCI0 only) · Resolution: 10 bits · Eight channels, with selection of single or scan mode · Variable analog conversion voltage range · Sample-and-hold function A/D converter · Operating modes Can be externally triggered · 55 input/output pins · I/O ports 8 input-only pins Five MCU operating modes Mode Address Space Address Pins Bus Width Mode 1 1 Mbyte A0 to A19 8 bits Mode 3 16 Mbytes A23 to A0 8 bits Mode 5 1 Mbyte A0 to A19 8 bits Mode 6 64 kbytes - - Mode 7 1 Mbyte - - · · Sleep mode · Software standby mode · Hardware standby mode · Module standby function · Power-down state On-chip ROM is disabled in modes 1 and 3 Programmable System clock frequency division Rev.3.00 Mar. 26, 2007 Page 4 of 682 REJ09B0353-0300 REJ09B0353-0300 Section 1 Overview Feature Description Other features · Product lineup Model (5 V) Model (3 V)* Package ROM HD64F3039F HD64F3039F HD64F3039VF HD64F3039VF 80-pin QFP (FP-80A FP-80A) Flash memory HD64F3039TE HD64F3039TE HD64F3039VTE HD64F3039VTE 80-pin TQFP (TFP-80C TFP-80C) HD6433039F HD6433039F HD6433039VF HD6433039VF 80-pin QFP (FP-80A FP-80A) HD6433039TE HD6433039TE HD6433039VTE HD6433039VTE 80-pin TQFP (TFP-80C TFP-80C) HD6433038F HD6433038F HD6433038VF HD6433038VF 80-pin QFP (FP-80A FP-80A) HD6433038TE HD6433038TE HD6433038VTE HD6433038VTE 80-pin TQFP (TFP-80C TFP-80C) HD6433037F HD6433037F HD6433037VF HD6433037VF 80-pin QFP (FP-80A FP-80A) HD6433037TE HD6433037TE HD6433037VTE HD6433037VTE 80-pin TQFP (TFP-80C TFP-80C) HD6433036F HD6433036F HD6433036VF HD6433036VF 80-pin QFP (FP-80A FP-80A) HD6433036TE HD6433036TE HD6433036VTE HD6433036VTE 80-pin TQFP (TFP-80C TFP-80C) On-chip clock oscillator Mask ROM Mask ROM Mask ROM Mask ROM Note: * There are two 3 V versions: one with VCC = 2.7 V to 5.5 V and = 2 to 8 MHz, and one with VCC = 3.0 V to 5.5 V and = 2 to 10 MHz. However, there is only one flash memory version, with VCC = 3.0 to 5.5 V and = 2 to 10 MHz. Rev.3.00 Mar. 26, 2007 Page 5 of 682 REJ09B0353-0300 REJ09B0353-0300 Section 1 Overview 1.2 Block Diagram VCC VCC VSS VSS VSS P37/D7 P37/D7 P36/D6 P36/D6 P35/D5 P35/D5 P34/D4 P34/D4 P33/D3 P33/D3 P32/D2 P32/D2 P31/D1 P31/D1 P30/D0 P30/D0 Figure 1.1 shows an internal block diagram of the H8/3039 H8/3039 Group. Port 3 Address bus Data bus (upper) MD2 MD1 MD0 EXTAL XTAL STBY RES RESO/FWE* NMI Port 5 Port 2 Port 1 Port 7 P77/AN7 P77/AN7 P76/AN6 P76/AN6 P75/AN5 P75/AN5 P74/AN4 P74/AN4 P73/AN3 P73/AN3 P72/AN2 P72/AN2 P71/AN1 P71/AN1 P70/AN0 P70/AN0 PA7/TP7/TIOCB2/A20 PA7/TP7/TIOCB2/A20 PA6/TP6/TIOCA2/A21 PA6/TP6/TIOCA2/A21 PA5/TP5/TIOCB1/A22 PA5/TP5/TIOCB1/A22 PA4/TP4/TIOCA1/A23 PA4/TP4/TIOCA1/A23 PA3/TP3/TIOCB0/TCLKD PA2/TP2/TIOCA0/TCLKC PA1/TP1/TCLKB PA0/TP0/TCLKA PB7/TP15/ADTRG PB7/TP15/ADTRG PB5/TP13/TOCXB4 PB5/TP13/TOCXB4 PB4/TP12/TOCXA4 PB4/TP12/TOCXA4 PB3/TP11/TIOCB4 PB3/TP11/TIOCB4 PB2/TP10/TIOCA4 PB2/TP10/TIOCA4 PB1/TP9/TIOCB3 PB0/TP8/TIOCA3 Port A Figure 1.1 Block Diagram Rev.3.00 Mar. 26, 2007 Page 6 of 682 REJ09B0353-0300 REJ09B0353-0300 P17/A7 P17/A7 P16/A6 P16/A6 P15/A5 P15/A5 P14/A4 P14/A4 P13/A3 P13/A3 P12/A2 P12/A2 P11/A1 P11/A1 P10/A0 P10/A0 P95/SCK1/IRQ5 P95/SCK1/IRQ5 P94/SCK0/IRQ4 P94/SCK0/IRQ4 P93/RxD1 P92/RxD0 P91/TxD1 P90/TxD0 A/D converter AVCC AVSS Port 8 Programmable timing pattern controller (TPC) Note: * Mask ROM: RESO Flash memory: FWE P27/A15 P27/A15 P26/A14 P26/A14 P25/A13 P25/A13 P24/A12 P24/A12 P23/A11 P23/A11 P22/A10 P22/A10 P21/A9 P21/A9 P20/A8 P20/A8 Port 9 Serial communication interface (SCI) × 2 channel 16-bit integrated timer unit (ITU) Port B Interrupt controller P53/A19 P53/A19 P52/A18 P52/A18 P51/A17 P51/A17 P50/A16 P50/A16 Watchdog timer (WDT) RAM P81/IRQ1 P81/IRQ1 P80/IRQ0 P80/IRQ0 Bus controller Clock osc. H8/300H H8/300H CPU ROM (Flash memory, mask ROM) Port 6 P65/WR P65/WR P64/RD P64/RD P63/AS P63/AS P60/WAIT P60/WAIT Data bus (lower) Section 1 Overview 1.3 Pin Description 1.3.1 Pin Arrangement PA3/TP3/TIOCB0/TCLKD PA1/TP1/TCLKB PA0/TP0/TCLKA P95/SCK1/IRQ5 P95/SCK1/IRQ5 P93/RxD1 P91/TxD1 P81/IRQ1 P81/IRQ1 P80/IRQ0 P80/IRQ0 AVcc P77/AN7 P77/AN7 P76/AN6 P76/AN6 P75/AN5 P75/AN5 P74/AN4 P74/AN4 P73/AN3 P73/AN3 P72/AN2 P72/AN2 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PA4/TP4/TIOCA1/A23 PA4/TP4/TIOCA1/A23 77 PA2/TP2/TIOCA0/TCLKC PA5/TP5/TIOCB1/A22 PA5/TP5/TIOCB1/A22 78 75 PA6/TP6/TIOCA2/A21 PA6/TP6/TIOCA2/A21 79 76 PA7/TP7/TIOCB2/A20 PA7/TP7/TIOCB2/A20 80 Figure 1.2 shows the pin arrangement of the H8/3039 H8/3039 Group. TIOCA3/TP8/PB0 1 60 P71/AN1 P71/AN1 TIOCB3/TP9/PB1 2 59 P70/AN0 P70/AN0 TIOCA4/TP10/PB2 TIOCA4/TP10/PB2 3 58 AVSS TIOCB4/TP11/PB3 TIOCB4/TP11/PB3 4 57 RESO/FWE* TOCXA4/TP12/PB4 5 56 P65/WR P65/WR TOCXB4/TP13/PB5 6 55 P64/RD P64/RD MD2 7 54 P63/AS P63/AS ADTRG/TP15/PB7 ADTRG/TP15/PB7 8 53 VCC TxD0/P90 9 52 XTAL RxD0/P92 10 51 EXTAL Top view (FP-80A FP-80A, TFP-80C TFP-80C) 34 35 36 37 38 39 40 A12/P24 A12/P24 A13/P25 A13/P25 A14/P26 A14/P26 A15/P27 A15/P27 A16/P50 A16/P50 A17/P51 A17/P51 P52/A18 P52/A18 A11/P23 A11/P23 41 A10/P22 A10/P22 20 33 P53/A19 P53/A19 D7/P37 D7/P37 32 42 A9/P21 A9/P21 19 31 P60/WAIT P60/WAIT D6/P36 D6/P36 A8/P20 A8/P20 43 30 18 VSS MD0 D5/P35 D5/P35 29 MD1 44 A7/P17 A7/P17 45 17 A6/P16 A6/P16 16 D4/P34 D4/P34 28 D3/P33 D3/P33 27 A5/P15 A5/P15 46 26 15 A4/P14 A4/P14 STBY D2/P32 D2/P32 25 47 A3/P13 A3/P13 14 24 RES D1/P31 D1/P31 A2/P12 A2/P12 48 A1/P11 A1/P11 13 23 NMI D0/P30 D0/P30 22 VSS 49 21 50 12 VCC 11 VSS A0/P10 A0/P10 IRQ4/SCK0/P94 IRQ4/SCK0/P94 Note: * Mask ROM: RESO Flash memory: FWE Figure 1.2 Pin Arrangement (FP-80A FP-80A, TFP-80C TFP-80C Top View) Rev.3.00 Mar. 26, 2007 Page 7 of 682 REJ09B0353-0300 REJ09B0353-0300 Section 1 Overview 1.3.2 Pin Functions Pin Assignments in Each Mode Table 1.2 lists the FP-80A FP-80A and TFP-80C TFP-80C pin assignments in each mode. Table 1.2 FP-80A FP-80A and TFP-80C TFP-80C Pin Assignments in Each Mode Pin Name Pin No. PROM Mode Flash memory Mode 1 Mode 3 Mode 5 Mode 6 Mode 7 1 PB0/TP8/ TIOCA3 PB0/TP8/ TIOCA3 PB0/TP8/ TIOCA3 PB0/TP8/ TIOCA3 PB0/TP8/ TIOCA3 NC 2 PB1/TP9/ TIOCB3 PB1/TP9/ TIOCB3 PB1/TP9/ TIOCB3 PB1/TP9/ TIOCB3 PB1/TP9/ TIOCB3 NC 3 PB2/TP10/ PB2/TP10/ TIOCA4 PB2/TP10/ PB2/TP10/ TIOCA4 PB2/TP10/ PB2/TP10/ TIOCA4 PB2/TP10/ PB2/TP10/ TIOCA4 PB2/TP10/ PB2/TP10/ TIOCA4 NC 4 PB3/TP11/ PB3/TP11/ TIOCB4 PB3/TP11/ PB3/TP11/ TIOCB4 PB3/TP11/ PB3/TP11/ TIOCB4 PB3/TP11/ PB3/TP11/ TIOCB4 PB3/TP11/ PB3/TP11/ TIOCB4 NC 5 PB4/TP12/ PB4/TP12/ TOCXA4 PB4/TP12/ PB4/TP12/ TOCXA4 PB4/TP12/ PB4/TP12/ TOCXA4 PB4/TP12/ PB4/TP12/ TOCXA4 PB4/TP12/ PB4/TP12/ TOCXA4 NC 6 PB5/TP13/ PB5/TP13/ TOCXB4 PB5/TP13/ PB5/TP13/ TOCXB4 PB5/TP13/ PB5/TP13/ TOCXB4 PB5/TP13/ PB5/TP13/ TOCXB4 PB5/TP13/ PB5/TP13/ TOCXB4 NC 7 MD2 MD2 MD2 MD2 MD2 VSS 8 PB7/TP15/ PB7/TP15/ ADTRG PB7/TP15/ PB7/TP15/ ADTRG PB7/TP15/ PB7/TP15/ ADTRG PB7/TP15/ PB7/TP15/ ADTRG PB7/TP15/ PB7/TP15/ ADTRG NC 9 P90/TxD0 P90/TxD0 P90/TxD0 P90/TxD0 P90/TxD0 NC 10 P92/RxD0 P92/RxD0 P92/RxD0 P92/RxD0 P92/RxD0 VSS 11 P94/SCK0/ P94/SCK0/ IRQ4 P94/SCK0/ P94/SCK0/ IRQ4 P94/SCK0/ P94/SCK0/ IRQ4 P94/SCK0/ P94/SCK0/ IRQ4 P94/SCK0/ P94/SCK0/ IRQ4 NC 12 VSS VSS VSS VSS VSS VSS 13 D0 D0 D0 P30 P30 I/O0 14 D1 D1 D1 P31 P31 I/O1 15 D2 D2 D2 P32 P32 I/O2 16 D3 D3 D3 P33 P33 I/O3 17 D4 D4 D4 P34 P34 I/O4 Rev.3.00 Mar. 26, 2007 Page 8 of 682 REJ09B0353-0300 REJ09B0353-0300 Section 1 Overview Pin Name Pin No. Mode 1 Mode 3 Mode 5 Mode 6 Mode 7 PROM Mode Flash memory 18 D5 D5 D5 P35 P35 I/O5 19 D6 D6 D6 P36 P36 I/O6 20 D7 D7 D7 P37 P37 I/O7 21 VCC VCC VCC VCC VCC VCC 22 A0 A0 P10/A0 P10/A0 P10 P10 A0 23 A1 A1 P11/A1 P11/A1 P11 P11 A1 24 A2 A2 P12/A2 P12/A2 P12 P12 A2 25 A3 A3 P13/A3 P13/A3 P13 P13 A3 26 A4 A4 P14/A4 P14/A4 P14 P14 A4 27 A5 A5 P15/A5 P15/A5 P15 P15 A5 28 A6 A6 P16/A6 P16/A6 P16 P16 A6 29 A7 A7 P17/A7 P17/A7 P17 P17 A7 30 VSS VSS VSS VSS VSS VSS 31 A8 A8 P20/A8 P20/A8 P20 P20 A8 32 A9 A9 P21/A9 P21/A9 P21 P21 A9 33 A10 A10 P22/A10 P22/A10 P22 P22 A10 34 A11 A11 P23/A11 P23/A11 P23 P23 A11 35 A12 A12 P24/A12 P24/A12 P24 P24 A12 36 A13 A13 P25/A13 P25/A13 P25 P25 A13 37 A14 A14 P26/A14 P26/A14 P26 P26 A14 38 A15 A15 P27/A15 P27/A15 P27 P27 A15 39 A16 A16 P50/A16 P50/A16 P50 P50 A16 40 A17 A17 P51/A17 P51/A17 P51 P51 VSS 41 A18 A18 P52/A18 P52/A18 P52 P52 VSS 42 A19 A19 P53/A19 P53/A19 P53 P53 VSS 43 P60/WAIT P60/WAIT P60/WAIT P60/WAIT P60/WAIT P60/WAIT P60 P60 NC 44 MD0 MD0 MD0 MD0 MD0 VSS 45 MD1 MD1 MD1 MD1 MD1 VSS 46 NC Rev.3.00 Mar. 26, 2007 Page 9 of 682 REJ09B0353-0300 REJ09B0353-0300 Section 1 Overview Pin Name Pin No. Mode 1 Mode 3 Mode 5 Mode 6 Mode 7 PROM Mode Flash memory 47 STBY STBY STBY STBY STBY VCC 48 RES RES RES RES RES RES 49 NMI NMI NMI NMI NMI VCC 50 VSS VSS VSS VSS VSS VSS 51 EXTAL EXTAL EXTAL EXTAL EXTAL EXTAL 52 XTAL XTAL XTAL XTAL XTAL XTAL 53 VCC VCC VCC VCC VCC VCC 54 AS AS AS P63 P63 NC 55 RD RD RD P64 P64 NC 56 WR WR WR P65 P65 VCC 57 RESO/ FWE* RESO/ FWE* RESO/ FWE* RESO/ FWE* RESO/ FWE* FWE 58 AVSS AVSS AVSS AVSS AVSS VSS 59 P70/AN0 P70/AN0 P70/AN0 P70/AN0 P70/AN0 P70/AN0 P70/AN0 P70/AN0 P70/AN0 P70/AN0 NC 60 P71/AN1 P71/AN1 P71/AN1 P71/AN1 P71/AN1 P71/AN1 P71/AN1 P71/AN1 P71/AN1 P71/AN1 NC 61 P72/AN2 P72/AN2 P72/AN2 P72/AN2 P72/AN2 P72/AN2 P72/AN2 P72/AN2 P72/AN2 P72/AN2 NC 62 P73/AN3 P73/AN3 P73/AN3 P73/AN3 P73/AN3 P73/AN3 P73/AN3 P73/AN3 P73/AN3 P73/AN3 NC 63 P74/AN4 P74/AN4 P74/AN4 P74/AN4 P74/AN4 P74/AN4 P74/AN4 P74/AN4 P74/AN4 P74/AN4 NC 64 P75/AN5 P75/AN5 P75/AN5 P75/AN5 P75/AN5 P75/AN5 P75/AN5 P75/AN5 P75/AN5 P75/AN5 NC 65 P76/AN6 P76/AN6 P76/AN6 P76/AN6 P76/AN6 P76/AN6 P76/AN6 P76/AN6 P76/AN6 P76/AN6 NC 66 P77/AN7 P77/AN7 P77/AN7 P77/AN7 P77/AN7 P77/AN7 P77/AN7 P77/AN7 P77/AN7 P77/AN7 NC 67 AVCC AVCC AVCC AVCC AVCC VCC 68 P80/IRQ0 P80/IRQ0 P80/IRQ0 P80/IRQ0 P80/IRQ0 P80/IRQ0 P80/IRQ0 P80/IRQ0 P80/IRQ0 P80/IRQ0 VSS 69 P81/IRQ1 P81/IRQ1 P81/IRQ1 P81/IRQ1 P81/IRQ1 P81/IRQ1 P81/IRQ1 P81/IRQ1 P81/IRQ1 P81/IRQ1 VSS 70 P91/TxD1 P91/TxD1 P91/TxD1 P91/TxD1 P91/TxD1 NC 71 P93/RxD1 P93/RxD1 P93/RxD1 P93/RxD1 P93/RxD1 NC 72 P95/SCK1/ P95/SCK1/ IRQ5 P95/SCK1/ P95/SCK1/ IRQ5 P95/SCK1/ P95/SCK1/ IRQ5 P95/SCK1/ P95/SCK1/ IRQ5 P95/SCK1/ P95/SCK1/ IRQ5 VCC 73 PA0/TP0/ TCLKA PA0/TP0/ TCLKA PA0/TP0/ TCLKA PA0/TP0/ TCLKA PA0/TP0/ TCLKA CE Rev.3.00 Mar. 26, 2007 Page 10 of 682 REJ09B0353-0300 REJ09B0353-0300 Section 1 Overview Pin Name Pin No. PROM Mode Flash memory Mode 1 Mode 3 Mode 5 Mode 6 Mode 7 74 PA1/TP1/ TCLKB PA1/TP1/ TCLKB PA1/TP1/ TCLKB PA1/TP1/ TCLKB PA1/TP1/ TCLKB OE 75 PA2/TP2/ TIOCA0/ TCLKC PA2/TP2/ TIOCA0/ TCLKC PA2/TP2/ TIOCA0/ TCLKC PA2/TP2/ TIOCA0/ TCLKC PA2/TP2/ TIOCA0/ TCLKC WE 76 PA3/TP3/ TIOCB0/ TCLKD PA3/TP3/ TIOCB0/ TCLKD PA3/TP3/ TIOCB0/ TCLKD PA3/TP3/ TIOCB0/ TCLKD PA3/TP3/ TIOCB0/ TCLKD NC 77 PA4/TP4/ TIOCA1 PA4/TP4/ TIOCA1/A23 TIOCA1/A23 PA4/TP4/ TIOCA1 PA4/TP4/ TIOCA1 PA4/TP4/ TIOCA1 NC 78 PA5/TP5/ TIOCB1 PA5/TP5/ TIOCB1/A22 TIOCB1/A22 PA5/TP5/ TIOCB1 PA5/TP5/ TIOCB1 PA5/TP5/ TIOCB1 NC 79 PA6/TP6/ TIOCA2 PA6/TP6/ TIOCA2/A21 TIOCA2/A21 PA6/TP6/ TIOCA2 PA6/TP6/ TIOCA2 PA6/TP6/ TIOCA2 NC 80 PA7/TP7/ TIOCB2 A20 PA7/TP7/ TIOCB2 PA7/TP7/ TIOCB2 PA7/TP7/ TIOCB2 NC Notes: Pins marked NC should be left unconnected. For details about PROM mode see section 15, ROM. * Mask ROM: RESO Flash Memory: FWE Rev.3.00 Mar. 26, 2007 Page 11 of 682 REJ09B0353-0300 REJ09B0353-0300 Section 1 Overview 1.4 Pin Functions Table 1.3 summarizes the pin functions. Table 1.3 Pin Functions Type Symbol Pin No. I/O Name and Function Power VCC 21, 53 Input Power: For connection to the power supply. Connect all VCC pins to the system power supply. VSS 12, 30, 50 Input Ground: For connection to ground (0 V). Connect all VSS pins to the 0-V system power supply. XTAL 52 Input For connection to a crystal resonator For examples of crystal resonator and external clock input, see section 16, Clock Pulse Generator. EXTAL 51 Input For connection to a crystal resonator or input of an external clock signal. For examples of crystal resonator and external clock input, see section 16, Clock Pulse Generator. 46 Output System clock: Supplies the system clock to external devices MD2, MD1, MD0 7, 45, 44 Input Mode 2 to mode 0: For setting the operating mode, as follows. These pins should not be changed during operation. Clock Operating mode control MD2 MD0 Operating Mode 0 0 0 - 0 0 1 Mode 1 0 1 0 - 0 1 1 Mode 3 1 0 0 - 1 0 1 Mode 5 1 1 0 Mode 6 1 Rev.3.00 Mar. 26, 2007 Page 12 of 682 REJ09B0353-0300 REJ09B0353-0300 MD1 1 1 Mode 7 Section 1 Overview Type Symbol Pin No. I/O Name and Function System control RES 48 Input Reset input: When driven low, this pin resets the chip RESO/ FWE 57 Output/ Input Reset output (Mask ROM version): Outputs WDT-generated reset signal to an external device. Write enable signal (F-ZTAT version): Flash memory write control signal. STBY 47 Input Standby: When driven low, this pin forces a transition to hardware standby mode NMI 49 Input Nonmaskable interrupt: Requests a nonmaskable interrupt IRQ5, IRQ4 72, 11, IRQ1, IRQ0 69, 68 Input Interrupt request 5, 4, 1, 0: Maskable interrupt request pins Address bus A23 to A20, A19 to A8, A7 to A0 77 to 80, 42 to 31, 29 to 22 Output Address bus: Outputs address signals Data bus D7 to D0 20 to 13 Input/ output Data bus: Bidirectional data bus Bus control AS 54 Output Address strobe: Goes low to indicate valid address output on the address bus RD 55 Output Read: Goes low to indicate reading from the external address space. WR 56 Output Write: Goes low to indicate writing to the external address space indicates valid data on the data bus. WAIT 43 Input Wait: Requests insertion of wait states in bus cycles during access to the external address space. TCLKD to TCLKA 76 to 73 Input Clock input A to D: External clock inputs TIOCA4 to TIOCA0 3, 1, 79, 77, 75 Input/ Output Input capture/output compare A4 to A0: GRA4 to GRA0 output compare or input capture, or PWM output TIOCB4 to TIOCB0 4, 2, 80, 78, 76 Input/ output Input capture/output compare B4 to B0 GRB4 to GRB0 output compare or input capture, or PWM output TOCXA4 5 Output Output compare XA4: PWM output TOCXB4 6 Output Output compare XB4: PWM output Interrupts 16-bit integrated timer unit (ITU) Rev.3.00 Mar. 26, 2007 Page 13 of 682 REJ09B0353-0300 REJ09B0353-0300 Section 1 Overview Type Symbol Pin No. I/O Name and Function Programmable TP15, 8, 6 to 1 timing pattern TP13 to TP0 80 to 73 controller (TPC) Output TPC output 15, 13 to 0 : Pulse output Serial communication interface (SCI) Output Transmit data:(channels 0 and 1): SCI data output RxD1, RxD0 71, 10 Input Receive data:(channels 0 and 1): SCI data input 72, 11 Input/ output Serial clock:(channels 0 and 1): SCI clock input/output AN7 to AN0 66 to 59 Input Analog 7 to 0: Analog input pins ADTRG 8 Input A/D trigger: External trigger input for starting A/D conversion AVCC 67 Input Power supply pin and reference voltage input pin for the A/D converter. Connect to the system power supply when not using the A/D converter. AVSS 58 Input Ground pin for the A/D converter. Connect to system power-supply (0 V). P17 to P10 29 to 22 Input/ output Port 1: Eight input/output pins. The direction of each pin can be selected in the port 1 data direction register (P1DDR). P27 to P20 38 to 31 Input/ output Port 2: Eight input/output pins. The direction of each pin can be selected in the port 2 data direction register (P2DDR). P37 to P30 20 to 13 Input/ output Port 3: Eight input/output pins. The direction of each pin can be selected in the port 3 data direction register (P3DDR). P53 to P50 42 to 39 Input/ output Port 5: Four input/output pins. The direction of each pin can be selected in the port 5 data direction register (P5DDR). P65 to P63, 56 to 54, P60 43 Input/ output Port 6: Four input/output pins. The direction of each pin can be selected in the port 6 data direction register (P6DDR). P77 to P70 66 to 59 Input Port 7: Eight input pins P81, P80 I/O ports 70, 9 SCK1, SCK0 A/D converter TxD1, TxD0 69, 68 Input/ output Port 8: Two input/output pins. The direction of each pin can be selected in the port 8 data direction register (P8DDR). Rev.3.00 Mar. 26, 2007 Page 14 of 682 REJ09B0353-0300 REJ09B0353-0300 Section 1 Overview Type Symbol Pin No. I/O Name and Function I/O ports P95 to P90 72, 11 71, 10 70, 9 Input/ output Port 9: Six input/output pins. The direction of each pin can be selected in the port 9 data direction register (P9DDR). PA7 to PA0 80 to 73 Input/ output Port A: Eight input/output pins. The direction of each pin can be selected in the port A data direction register (PADDR). PB7, PB5 to PB0 8, 6to1 Input/ output Port B: Seven input/output pins. The direction of each pin can be selected in the port B data direction register (PBDDR). Rev.3.00 Mar. 26, 2007 Page 15 of 682 REJ09B0353-0300 REJ09B0353-0300 Section 1 Overview Rev.3.00 Mar. 26, 2007 Page 16 of 682 REJ09B0353-0300 REJ09B0353-0300 Section 2 CPU Section 2 CPU 2.1 Overview The H8/300H H8/300H CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 H8/300 CPU. The H8/300H H8/300H CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. 2.1.1 Features The H8/300H H8/300H CPU has the following features. · Upward compatibility with H8/300 H8/300 CPU Can execute H8/300 H8/300 series object programs without alteration · General-register architecture Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) · Sixty-two basic instructions 8/16/32-bit arithmetic and logic instructions Multiply and divide instructions Powerful bit-manipulation instructions · Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16, ERn) or @(d:24, ERn)] Register indirect with post-increment or pre-decrement [@ERn+ or @­ERn] Absolute address [@aa:8, @aa:16, or @aa:24] Immediate [#xx:8, #xx:16, or #xx:32] Program-counter relative [@(d:8, PC) or @(d:16, PC)] Memory indirect [@@aa:8] · 16-Mbyte linear address space · High-speed operation All frequently-used instructions execute in two to four states Maximum clock frequency: 18 MHz 8/16/32-bit register-register add/subtract: 111 ns 8 × 8-bit register-register multiply: 778 ns 16 ÷ 8-bit register-register divide: 778 ns Rev.3.00 Mar. 26, 2007 Page 17 of 682 REJ09B0353-0300 REJ09B0353-0300 Section 2 CPU 16 × 16-bit register-register multiply: 1222 ns 32 ÷ 16-bit register-register divide: 1222 ns · Two CPU operating modes Normal mode Advanced mode · Low-power mode Transition to power-down state by SLEEP instruction 2.1.2 Differences from H8/300 H8/300 CPU In comparison to the H8/300 H8/300 CPU, the H8/300H H8/300H has the following enhancements. · More general registers Eight 16-bit registers have been added. · Expanded address space Advanced mode supports a maximum 16-Mbyte address space. Normal mode supports the same 64-kbyte address space as the H8/300 H8/300 CPU. · Enhanced addressing The addressing modes have been enhanced to make effective use of the 16-Mbyte address space. · Enhanced instructions Data transfer, arithmetic, and logic instructions can operate on 32-bit data. Signed multiply/divide instructions and other instructions have been added. Rev.3.00 Mar. 26, 2007 Page 18 of 682 REJ09B0353-0300 REJ09B0353-0300 Section 2 CPU 2.2 CPU Operating Modes The H8/300H H8/300H CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports up to 16 Mbytes. See figure 2.1. Unless specified otherwise, all descriptions in this manual refer to advanced mode. Normal mode Maximum 64 kbytes, program and data areas combined Advanced mode Maximum 16 Mbytes, program and data areas combined CPU operating modes Figure 2.1 CPU Operating Modes Rev.3.00 Mar. 26, 2007 Page 19 of 682 REJ09B0353-0300 REJ09B0353-0300 Section 2 CPU 2.3 Address Space The maximum address space of the H8/300H H8/300H CPU is 16 Mbytes. This LSI allows selection of a normal mode and advanced mode 1-Mbyte mode or 16-Mbyte mode for the address space depending on the MCU operation mode. Figure 2.2 shows the address ranges of the H8/3039 H8/3039 Group. For further details see section 3.6, Memory Map in Each Operating Mode. The 1-Mbyte operating mode uses 20-bit addressing. The upper 4 bits of effective addresses are ignored. H'0000 H'00000 H'000000 H'FFFF H'FFFFF H'FFFFFF (a) 1-Mbyte mode 1. Normal mode (64-Kbyte mode) (b) 16-Mbyte mode 2. Advanced mode Figure 2.2 Memory Map Rev.3.00 Mar. 26, 2007 Page 20 of 682 REJ09B0353-0300 REJ09B0353-0300 Section 2 CPU 2.4 Register Configuration 2.4.1 Overview The H8/300H H8/300H CPU has the internal registers shown in figure 2.3. There are two types of registers: general registers and control registers. General Registers (ERn) 15 0 7 0 7 0 ER0 E0 R0H R0L ER1 E1 R1H R1L ER2 E2 R2H R2L ER3 E3 R3H R3L ER4 E4 R4H R4L ER5 E5 R5H R5L ER6 E6 R6H R6L ER7 E7 R7H R7L (SP) Control Registers (CR) 23 0 PC 7 6 5 4 3 2 1 0 CCR I UI H U N Z V C Legend: SP: Stack pointer PC: Program counter CCR: Condition code register Interrupt mask bit I: User bit or interrupt mask bit UI: Half-carry flag H: User bit U: Negative flag N: Zero flag Z: Overflow flag V: Carry flag C: Figure 2.3 CPU Registers Rev.3.00 Mar. 26, 2007 Page 21 of 682 REJ09B0353-0300 REJ09B0353-0300 Section 2 CPU 2.4.2 General Registers The H8/300H H8/300H CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used without distinction between data registers and address registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or as address registers, they are designated by the letters ER (ER0 to ER7). The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit registers. Figure 2.4 illustrates the usage of the general registers. The usage of each register can be selected independently. · Address registers · 32-bit registers · 16-bit registers · 8-bit registers E registers (extended registers) E0 to E7 RH registers R0H to R7H ER registers ER0 to ER7 R registers R0 to R7 RL registers R0L to R7L Figure 2.4 Usage of General Registers Rev.3.00 Mar. 26, 2007 Page 22 of 682 REJ09B0353-0300 REJ09B0353-0300 Section 2 CPU General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.5 shows the stack. Free area SP (ER7) Stack area Figure 2.5 Stack 2.4.3 Control Registers The control registers are the 24-bit program counter (PC) and the 8-bit condition code register (CCR). Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word) or a multiple of 2 bytes, so the least significant PC bit is ignored. When an instruction is fetched, the least significant PC bit is regarded as 0. Condition Code Register (CCR) This 8-bit register contains internal CPU status information, including the inter