REJ09B0123-0110 M32R/ECU M32192F8VWG M32192F8UWG M32192F8TWG PLBG0224GA-A - Datasheet Archive

 

32 32192/32195/32196 Group Hardware Manual RENESAS MCU M32R FAMILY / M32R/ECU SERIES All information contained in these

 

REJ09B0123-0110 REJ09B0123-0110 32 32192/32195/32196 Group Hardware Manual RENESAS MCU M32R FAMILY / M32R/ECU M32R/ECU SERIES All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Technology Corp. without notice. Please review the latest information published by Renesas Technology Corp. through various means, including the Renesas Technology Corp. website (http://www.renesas.com). Rev. 1.10 Revision date: Apr. 06, 2007 www.renesas.com Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited. The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized. When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems. The characteristics of MPU/MCU in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different part numbers, implement a system-evaluation test for each of the products. 32192/32195/32196 Group Hardware Manual REVISION HISTORY Rev. Date Description Page Summary 1.01 Jul 22, 2005 - First edition issued 1.10 Apr 06, 2007 - Add the 32195 Group Add M32192F8VWG M32192F8VWG, M32192F8UWG M32192F8UWG, and M32192F8TWG M32192F8TWG 2-3 Add Note 1 to IE bit of PSW register 5-6 Correct notes of IMASK register Incorrect) the Interrupt Request Mask Register (IMASK) in the EIT handler Correct) the Interrupt Request Mask Register (IMASK) 5-7 Add a note for SBI Control Register 6-15 Add a description for FAENS bit of FMOD Register 6-16 Add descriptions for ERASE bit and WRERR bit. 6-19 to 21 Correct descriptions of FCNOT3 Register Add Table 6.5.2 and correct Figure 6.5.2 6-34 Add Figure 6.6.7 6-36 6-55 Correct the description of 4 Halfword Program command Add a note to 6.11 Notes on the Internal RAM 8-33 Correct functions of b4 (12) WFnSEL bit in the Port Group n Input Level Setting Regsiter 8-35 Correct R/W status of GnDSEL bits in the Port Group n Output Drive Capability Setting Register 8-39 Replace Figure 8.7.1 8-40 Replace Figure 8.7.2 8-41 8-42 Replace Figure 8.7.3 Replace Figure 8.7.4 8-43 Replace Figure 8.7.5 8-44 Add a note about using input/output ports in input mode Add a note about the peripheral function input when it is set to the generalpurpose port 9-26 Correct functions of RINGSEL bit 9-27 9-28 Correct descriptions of TREQFn bit and TENLn bit Correct the description of SELFEN bit 10-114 Add descriptions to Reload register uptdates in TIO PWM output mode 10-157 Correct a note of TOU Counters 10-160 10-171 Correct a note of TOU Registers Correct read status of PO0LVSELGA bit and PO1LVSELGA bit 10-176 Add descriptions to Reload register updates in TOUP PWM output mode 11-21 Add Note 3 to ADSEL2 bit 12-4 Replace Figure 12.1.1 12-8 Correct the description of notes on using transmit interrupts 12-45,62 Add a note about switching from general-purpose to serial interface pin 13-27 Correct the description of RBO bit 13-28 Add descriptions to LBM bit and RST bit (REVISION HISTORY-1) 32192/32195/32196 Group Hardware Manual REVISION HISTORY Rev. Date 1.10 Apr 06, 2007 Description Page 13-31 Add a description to CRS bit Summary 13-118 Add Note 1 to Figure 13.3.4 14-3 Replace Figure 14.1.1 14-24 Replace Figure 14.2.7 14-27 Correct the decription of DRI Transfer Counter 14-35 Add notes to Continuous Operation Mode 14-36 19-2 Correct the description of DRI Event Counters Replace Figure 19.1.1 20-2 Replace Figure 20.1.1 20-3 Correct the description of XIN Oscillation Stoppage Detection Circuit Replace Figure 20.1.2 Chap. 23 Add electrical characteristics of the 32195 and 32196 23-3, 4, Correct parameters of VIH and VIL 7, 8, 11, 12, 15, 16 23-5, 9, 13, 17 23-24 Correct parameters of VT+ and VT- (hysteresis) Add Note 1 to TIN 23-25, 47 Correct rated values of TCLK Add Note 1 to TCLK 23-29, 51 Add Note 1 to tw(WAITH) and tw(WAITL) 23-30, 52 Correct the note of Read Timing 23-46 Correct Note 1 of TIN Appendix Replace Dimensional Outline Drawing 1-2 Appendix Add 224 pin FBGA (PLBG0224GA-A PLBG0224GA-A) 1-3 Appendix4 Add correction of notes (REVISION HISTORY-2) Before Use · Guide to Understanding the Register Table (1) Bit number: Indicates a register's bit number. (2) Register border: The registers enclosed with thick border lines must be accessed in halfwords or words. (3) Status after reset: The initial state of each register after reset is indicated in hexadecimal or binary. (4) Status after reset: The initial state of each register after reset is indicated bitwise. 0: This bit is "0" after reset. 1: This bit is "1" after reset. ?: This bit is undefined after reset. (5) The shaded bits mean that they have no functions assigned. (6) Read conditions: R: This bit can be accessed for read. ?: The value read from this bit is undefined. (Reading this bit has no effect.) 0: The value read from this bit is always "0". 1: The value read from this bit is always "1". (7) Write conditions: W: This bit can be accessed for write. N: This bit is write protected. 0: To write to this bit, always write "0". 1: To write to this bit, always write "1". ­: Writing to this bit has no effect. (It does not matter whether this bit is set to "0" or "1" by writing in software.) Note: Care must be taken when writing to this bit. See Note in each register table. (1) XXXRegister(XXX) Function bit · · · b15 R · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · W bit bit R W bit bit R W bit bit R (Note 1) No function assigned. Fix to "0". 0 0 Note 1: Only writing "0" is effective. Writing "1" has no effect, in which case the bit retains the value it had before the write. (6) (7) · Notation of active-low pins (signals) The symbol "#" suffixed to the pin (or signal) names means that the pins (or signals) are active-low. Table of Contents CHAPTER 1 OVERVIEW 1.1 Outline of the 32192/32195/32196 Group - 1-2 1.1.1 M32R Family CPU Core with Built-in FPU (M32R-FPU M32R-FPU) - 1-2 1.1.2 Built-in Multiplier/Accumulator - 1-3 1.1.3 Built-in Single-precision FPU - 1-3 1.1.4 Built-in Flash Memory and RAM - 1-3 1.1.5 Built-in Clock Frequency Multiplier - 1-5 1.1.6 Powerful Peripheral Functions Built-in - 1-5 1.2 Block Diagram - 1-6 1.3 Pin Functions - 1-10 1.4 Pin Assignments - 1-15 CHAPTER 2 CPU 2.1 CPU Registers - 2-2 2.2 General-purpose Registers - 2-2 2.3 Control Registers - 2-2 2.3.1 Processor Status Word Register: PSW (CR0) - 2-3 2.3.2 Condition Bit Register: CBR (CR1) - 2-4 2.3.3 Interrupt Stack Pointer: SPI (CR2) and User Stack Pointer: SPU (CR3) - 2-4 2.3.4 Backup PC: BPC (CR6) - 2-4 2.3.5 Floating-point Status Register: FPSR (CR7) - 2-5 2.4 Accumulator - 2-7 2.5 Program Counter - 2-7 2.6 Data Formats - 2-8 2.6.1 Data Types - 2-8 2.6.2 Data Formats - 2-9 2.7 Supplementary Explanation for BSET, BCLR, LOCK and UNLOCK Instruction Execution - 2-14 CHAPTER 3 ADDRESS SPACE 3.1 Outline of the Address Space - 3-2 3.2 Operation Modes - 3-3 3.3 Internal ROM and External Extension Areas - 3-7 3.3.1 Internal ROM Area - 3-7 3.3.2 External Extension Area - 3-7 3.4 Internal RAM and SFR Areas - 3-8 3.4.1 Internal RAM Area - 3-8 3.4.2 SFR (Special Function Register) Area - 3-8 3.5 EIT Vector Entry - 3-48 3.6 ICU Vector Table - 3-49 3.7 Notes on Address Space - 3-52 32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 REJ09B0123-0110 Apr.06.07 Contents-1 CHAPTER 4 EIT 4.1 Outline of EIT - 4-2 4.2 EIT Events - 4-3 4.2.1 Exception - 4-3 4.2.2 Interrupt - 4-5 4.2.3 Trap - 4-6 4.3 EIT Processing Procedure - 4-6 4.4 EIT Processing Mechanism - 4-7 4.5 Acceptance of EIT Events - 4-8 4.6 Saving and Restoring the PC and PSW - 4-8 4.7 EIT Vector Entry - 4-10 4.8 Exception Processing - 4-11 4.8.1 Reserved Instruction Exception (RIE) - 4-11 4.8.2 Address Exception (AE) - 4-12 4.8.3 Floating-Point Exception (FPE) - 4-13 4.9 Interrupt Processing - 4-15 4.9.1 Reset Interrupt (RI) - 4-15 4.9.2 System Break Interrupt (SBI) - 4-15 4.9.3 External Interrupt (EI) - 4-17 4.10 Trap Processing - 4-18 4.10.1 Trap - 4-18 4.11 EIT Priority Levels - 4-19 4.12 Example of EIT Processing - 4-20 4.13 Notes on EIT - 4-22 CHAPTER 5 INTERRUPT CONTROLLER (ICU) 5.1 Outline of the Interrupt Controller - 5-2 5.2 ICU Related Registers - 5-4 5.2.1 Interrupt Vector Register - 5-5 5.2.2 Interrupt Request Mask Register - 5-6 5.2.3 SBI (System Break Interrupt) Control Register - 5-7 5.2.4 Interrupt Control Registers - 5-8 5.3 Interrupt Request Sources in Internal Peripheral I/O - 5-11 5.4 ICU Vector Table - 5-12 5.5 Description of Interrupt Operation - 5-13 5.5.1 Acceptance of Internal Peripheral I/O Interrupts - 5-13 5.5.2 Processing by Internal Peripheral I/O Interrupt Handlers - 5-14 5.6 Description of System Break Interrupt (SBI) Operation - 5-17 5.6.1 Acceptance of SBI - 5-17 5.6.2 SBI Processing by Handler - 5-17 32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 REJ09B0123-0110 Apr.06.07 Contents-2 CHAPTER 6 INTERNAL MEMORY 6.1 6.2 6.3 6.4 6.5 Outline of the Internal Memory - 6-2 Internal RAM - 6-2 Internal RAM Protect Function - 6-2 Internal Flash Memory - 6-11 Registers Associated with the Internal Flash Memory - 6-14 6.5.1 Flash Mode Register - 6-15 6.5.2 Flash Status Register - 6-16 6.5.3 Flash Control Registers - 6-17 6.5.4 Virtual Flash L Bank Registers - 6-24 6.6 Programming the Internal Flash Memory - 6-25 6.6.1 Outline of Internal Flash Memory Programming - 6-25 6.6.2 Controlling Operation Modes during Flash Programming - 6-31 6.6.3 Procedure for Programming/Erasing the Internal Flash Memory - 6-35 6.6.4 Flash Programming Time (Reference) - 6-43 6.7 Virtual Flash Emulation Function - 6-44 6.7.1 Virtual Flash Emulation Area - 6-46 6.7.2 Entering Virtual Flash Emulation Mode - 6-49 6.8 Connecting to A Serial Programmer (CSIO Mode) - 6-50 6.9 Connecting to A Serial Programmer (UART Mode) - 6-52 6.10 Internal Flash Memory Protect Function - 6-54 6.11 Notes on the Internal RAM - 6-55 6.12 Notes on the Internal Flash Memory - 6-55 CHAPTER 7 RESET 7.1 Outline of Reset - 7-2 7.2 Reset Operation - 7-2 7.2.1 Reset at Power-on - 7-3 7.2.2 Reset during Operation - 7-3 7.2.3 Reset Vector Relocation during Flash Programming - 7-3 7.3 Internal State upon Exiting Reset - 7-4 7.4 Things to Be Considered upon Exiting Reset - 7-4 CHAPTER 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.1 Outline of Input/Output Ports - 8-2 8.2 Selecting Pin Functions - 8-3 8.3 Input/Output Port Related Registers - 8-9 8.3.1 Port Data Registers - 8-12 8.3.2 Port Direction Registers - 8-13 8.3.3 Port Operation Mode and Port Peripheral Function Select Registers - 8-14 8.3.4 Port Input Special Function Control Register - 8-29 8.4 Port Input Level Switching Function - 8-32 8.5 Port Output Drive Capability Setting Function - 8-34 8.6 Noise Canceller Control Function - 8-37 8.7 Port Peripheral Circuits - 8-39 8.8 Notes on Input/Output Ports - 8-44 32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 REJ09B0123-0110 Apr.06.07 Contents-3 CHAPTER 9 DMAC 9.1 Outline of the DMAC - 9-2 9.2 DMAC Related Registers - 9-4 9.2.1 DMA Channel Control Registers - 9-6 9.2.2 DMA Software Request Generation Registers - 9-29 9.2.3 DMA Source Address Registers - 9-30 9.2.4 DMA Destination Address Registers - 9-31 9.2.5 DMA Transfer Count Registers - 9-32 9.2.6 DMA Interrupt Related Registers - 9-33 9.3 Functional Description of the DMAC - 9-38 9.3.1 DMA Transfer Request Sources - 9-38 9.3.2 DMA Transfer Processing Procedure - 9-44 9.3.3 Starting DMA - 9-45 9.3.4 DMA Channel Priority - 9-45 9.3.5 Gaining and Releasing Control of the Internal Bus - 9-45 9.3.6 Transfer Units - 9-46 9.3.7 Transfer Counts - 9-46 9.3.8 Address Space - 9-46 9.3.9 Transfer Operation - 9-46 9.3.10 End of DMA and Interrupt - 9-48 9.3.11 Each Register Status after Completion of DMA Transfer - 9-48 9.4 Notes on the DMAC - 9-49 CHAPTER 10 MULTIJUNCTION TIMERS 10.1 Outline of Multijunction Timers - 10-2 10.2 Common Units of Multijunction Timers - 10-9 10.2.1 MJT Common Unit Register Map - 10-10 10.2.2 Common Count Clock Select Function - 10-12 10.2.3 Prescaler Unit - 10-13 10.2.4 Clock Bus and Input/Output Event Bus Control Unit - 10-14 10.2.5 Input Processing Control Unit - 10-18 10.2.6 Output Flip-flop Control Unit - 10-26 10.2.7 Interrupt Control Unit - 10-34 10.3 TOP (Output-Related 16-Bit Timer) - 10-60 10.3.1 Outline of TOP - 10-60 10.3.2 Outline of Each Mode of TOP - 10-62 10.3.3 TOP Related Register Map - 10-64 10.3.4 TOP Control Registers - 10-66 10.3.5 TOP Counters (TOP0CT­TOP10CT) - 10-71 10.3.6 TOP Reload Registers (TOP0RL­TOP10RL) - 10-72 10.3.7 TOP Correction Registers (TOP0CC­TOP10CC) - 10-73 10.3.8 TOP Enable Control Registers - 10-74 10.3.9 Operation in TOP Single-shot Output Mode (with Correction Function) - 10-76 10.3.10 Operation in TOP Delayed Single-shot Output Mode (with Correction Function) - 10-82 10.3.11 Operation in TOP Continuous Output Mode (without Correction Function) - 10-87 32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 REJ09B0123-0110 Apr.06.07 Contents-4 10.4 TIO (Input/Output-Related 16-Bit Timer) - 10-90 10.4.1 Outline of TIO - 10-90 10.4.2 Outline of Each Mode of TIO - 10-92 10.4.3 TIO Related Register Map - 10-95 10.4.4 TIO Control Registers - 10-97 10.4.5 TIO Counters (TIO0CT­TIO9CT) - 10-105 10.4.6 TIO Reload 0/ Measure Registers (TIO0RL0­TIO9RL0) - 10-106 10.4.7 TIO Reload 1 Registers (TIO0RL1­TIO9RL1) - 10-107 10.4.8 TIO Enable Control Registers - 10-108 10.4.9 Operation in TIO Measure Free-Run/Clear Input Modes - 10-110 10.4.10 Operation in TIO Noise Processing Input Mode - 10-112 10.4.11 Operation in TIO PWM Output Mode - 10-113 10.4.12 Operation in TIO Single-shot Output Mode (without Correction Function) - 10-117 10.4.13 Operation in TIO Delayed Single-shot Output Mode (without Correction Function) - 10-119 10.4.14 Operation in TIO Continuous Output Mode (without Correction Function) - 10-121 10.5 TMS (Input-Related 16-Bit Timer) - 10-123 10.5.1 Outline of TMS - 10-123 10.5.2 Outline of TMS Operation - 10-123 10.5.3 TMS Related Register Map - 10-125 10.5.4 TMS Control Registers - 10-126 10.5.5 TMS Counters (TMS0CT, TMS1CT) - 10-127 10.5.6 TMS Measure Registers (TMS0MR3­0, TMS1MR3­0) - 10-127 10.5.7 Operation of TMS Measure Input - 10-128 10.6 TML (Input-Related 32-Bit Timer) - 10-129 10.6.1 Outline of TML - 10-129 10.6.2 Outline of TML Operation - 10-130 10.6.3 TML Related Register Map - 10-130 10.6.4 TML Control Registers - 10-131 10.6.5 TML Counters - 10-132 10.6.6 TML Measure Registers - 10-132 10.6.7 Operation of TML Measure Input - 10-133 10.7 TID (Input-Related 16-Bit Timer) - 10-135 10.7.1 Outline of TID - 10-135 10.7.2 TID Related Register Map - 10-137 10.7.3 TID Control & Prescaler Enable Registers - 10-138 10.7.4 TID Counters (TID0CT and TID1CT) - 10-140 10.7.5 TID Reload Registers (TID0RL and TID1RL) - 10-140 10.7.6 Outline of Each Mode of TID - 10-141 10.8 TOU (Output-Related 24-Bit Timer) - 10-146 10.8.1 Outline of TOU - 10-146 10.8.2 Outline of Each Mode of TOU - 10-148 10.8.3 TOU Related Register Map - 10-150 10.8.4 TOU Control Registers - 10-153 10.8.5 Shorting Prevention Function Registers - 10-155 10.8.6 TOU Counters - 10-157 10.8.7 TOU Reload Registers - 10-160 10.8.8 TOU Enable Protect Registers - 10-163 32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 REJ09B0123-0110 Apr.06.07 Contents-5 10.8.9 10.8.10 10.8.11 10.8.12 10.8.13 10.8.14 10.8.15 10.8.16 10.8.17 10.8.18 10.8.19 10.8.20 10.8.21 10.8.22 TOU Count Enable Registers - 10-164 PWMOFF Input Processing Control Registers - 10-166 PWM Output Disable Control Registers - 10-168 PWM Output Disable Level Control Registers - 10-171 PWMOFF Function Enable Registers - 10-173 Operation in TOU PWM Output Mode (without Correction Function) - 10-174 Operation in TOU Single-shot PWM Output Mode (without Correction Function) - 10-180 Operation in TOU Delayed Single-shot Output Mode (without Correction Function) - 10-182 Operation in TOU Single-shot Output Mode (without Correction Function) - 10-184 Operation in TOU Continuous Output Mode (without Correction Function) - 10-186 0% or 100% Duty-Cycle Wave Output during PWM Output and Single-shot PWM Output Modes - 10-188 PWM Output Disable Function - 10-193 Shorting Prevention Function - 10-197 Example Application for Using the 32192/32195/32196 in Motor Control - 10-201 CHAPTER 11 A/D CONVERTER 11.1 Outline of A/D Converter - 11-2 11.1.1 Conversion Modes - 11-6 11.1.2 Operation Modes - 11-6 11.1.3 Special Operation Modes - 11-9 11.1.4 A/D Converter Interrupt and DMA Transfer Requests - 11-12 11.1.5 Sample-and-Hold Function - 11-12 11.1.6 Simultaneous Sampling Function - 11-13 11.2 A/D Converter Related Registers - 11-15 11.2.1 A/D Single Mode Register 0 - 11-17 11.2.2 A/D Single Mode Register 1 - 11-19 11.2.3 A/D Single Mode Register 2 - 11-21 11.2.4 A/D Scan Mode Register 0 - 11-22 11.2.5 A/D Scan Mode Register 1 - 11-24 11.2.6 A/D Conversion Speed Control Register - 11-26 11.2.7 A/D Disconnection Detection Assist Function Control Register - 11-27 11.2.8 A/D Disconnection Detection Assist Method Select Register - 11-28 11.2.9 A/D Successive Approximation Register - 11-31 11.2.10 A/D Comparate Data Register - 11-32 11.2.11 10-bit A/D Data Registers - 11-33 11.2.12 8-bit A/D Data Registers - 11-34 11.3 Functional Description of A/D Converter - 11-35 11.3.1 How to Find Analog Input Voltages - 11-35 11.3.2 A/D Conversion by Successive Approximation Method - 11-36 11.3.3 Comparator Operation - 11-37 11.3.4 Calculating the A/D Conversion Time - 11-38 11.3.5 Accuracy of A/D Conversion - 11-43 11.4 Inflow Current Bypass Circuit - 11-45 11.5 Notes on the A/D Converter - 11-47 32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 REJ09B0123-0110 Apr.06.07 Contents-6 CHAPTER 12 SERIAL INTERFACE 12.1 Outline of Serial Interface - 12-2 12.2 Serial Interface Related Registers - 12-5 12.2.1 SIO Interrupt Related Registers - 12-6 12.2.2 SIO Transmit Control Registers - 12-14 12.2.3 SIO Transmit/Receive Mode Registers - 12-15 12.2.4 SIO Transmit Buffer Registers - 12-19 12.2.5 SIO Receive Buffer Registers - 12-20 12.2.6 SIO Receive Control Registers - 12-21 12.2.7 SIO Baud Rate Registers - 12-24 12.2.8 SIO Special Mode Registers - 12-27 12.3 Transmit Operation in CSIO Mode - 12-29 12.3.1 Setting the CSIO Baud Rate - 12-29 12.3.2 Initializing CSIO Transmission - 12-30 12.3.3 Starting CSIO Transmission - 12-32 12.3.4 Successive CSIO Transmission - 12-32 12.3.5 Processing at End of CSIO Transmission - 12-33 12.3.6 Transmit Interrupts - 12-33 12.3.7 Transmit DMA Transfer Request - 12-33 12.3.8 Example of CSIO Transmit Operation - 12-35 12.4 Receive Operation in CSIO Mode - 12-37 12.4.1 Initialization for CSIO Reception - 12-37 12.4.2 Starting CSIO Reception - 12-39 12.4.3 Processing at End of CSIO Reception - 12-39 12.4.4 About Successive Reception - 12-40 12.4.5 Flags Showing the Status of CSIO Receive Operation - 12-41 12.4.6 Example of CSIO Receive Operation - 12-42 12.5 Notes on Using CSIO Mode - 12-44 12.6 Transmit Operation in UART Mode - 12-46 12.6.1 Setting the UART Baud Rate - 12-46 12.6.2 UART Transmit/Receive Data Formats - 12-46 12.6.3 Initializing UART Transmission - 12-48 12.6.4 Starting UART Transmission - 12-50 12.6.5 Successive UART Transmission - 12-50 12.6.6 Processing at End of UART Transmission - 12-50 12.6.7 Transmit Interrupts - 12-50 12.6.8 Transmit DMA Transfer Request - 12-51 12.6.9 Example of UART Transmit Operation - 12-52 12.7 Receive Operation in UART Mode - 12-54 12.7.1 Initialization for UART Reception - 12-54 12.7.2 Starting UART Reception - 12-56 12.7.3 Processing at End of UART Reception - 12-56 12.7.4 Example of UART Receive Operation - 12-58 12.7.5 Start Bit Detection and Data Sampling during UART Reception - 12-60 12.8 Fixed Period Clock Output Function - 12-61 12.9 Notes on Using UART Mode - 12-62 32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 REJ09B0123-0110 Apr.06.07 Contents-7 CHAPTER 13 CAN MODULE 13.1 Outline of the CAN Module - 13-2 13.2 CAN Module Related Registers - 13-4 13.2.1 CAN Bus Mode Control Register - 13-23 13.2.2 CAN Control Registers - 13-26 13.2.3 CAN Status Registers - 13-29 13.2.4 CAN Configuration Registers - 13-32 13.2.5 CAN Timestamp Count Registers - 13-35 13.2.6 CAN Error Count Registers - 13-36 13.2.7 CAN Baud Rate Prescalers - 13-37 13.2.8 CAN Interrupt Related Registers - 13-38 13.2.9 CAN Cause of Error Registers - 13-67 13.2.10 CAN Mode Registers - 13-69 13.2.11 CAN DMA Transfer Request Select Registers - 13-70 13.2.12 CAN Message Slot Number Registers - 13-71 13.2.13 CAN Clock Select Registers - 13-72 13.2.14 CAN Frame Format Select Registers - 13-74 13.2.15 CAN Mask Registers - 13-76 13.2.16 CAN Single-Shot Mode Control Registers - 13-80 13.2.17 CAN Message Slot Control Registers - 13-82 13.2.18 CAN Message Slots - 13-86 13.3 CAN Protocol - 13-116 13.3.1 CAN Protocol Frames - 13-116 13.3.2 Data Formats during CAN Transmission/Reception - 13-117 13.3.3 CAN Controller Error States - 13-118 13.4 Initializing the CAN Module - 13-119 13.4.1 Initializing the CAN Module - 13-119 13.5 Transmitting Data Frames - 13-122 13.5.1 Data Frame Transmit Procedure - 13-122 13.5.2 Data Frame Transmit Operation - 13-123 13.5.3 Transmit Abort Function - 13-124 13.6 Receiving Data Frames - 13-125 13.6.1 Data Frame Receive Procedure - 13-125 13.6.2 Data Frame Receive Operation - 13-126 13.6.3 Reading Out Received Data Frames - 13-128 13.7 Transmitting Remote Frames - 13-130 13.7.1 Remote Frame Transmit Procedure - 13-130 13.7.2 Remote Frame Transmit Operation - 13-131 13.7.3 Reading Out Received Data Frames when Set for Remote Frame Transmission - 13-133 13.8 Receiving Remote Frames - 13-135 13.8.1 Remote Frame Receive Procedure - 13-135 13.8.2 Remote Frame Receive Operation - 13-136 13.9 Notes on CAN Module - 13-139 32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 REJ09B0123-0110 Apr.06.07 Contents-8 CHAPTER 14 DIRECT RAM INTERFACE (DRI) 14.1 Outline of the Direct RAM Interface (DRI) - 14-2 14.2 DRI Related Registers - 14-4 14.2.1 DD Input Pin Select Register - 14-6 14.2.2 DRI Interrupt Related Registers - 14-7 14.2.3 DRI Transfer Control Register - 14-13 14.2.4 DRI Special Mode Control Register - 14-15 14.2.5 DRI Data Capture Control Register - 14-18 14.2.6 DRI Data Interleave Control Register - 14-22 14.2.7 DD Input Event Select Register - 14-22 14.2.8 DD Input Enable Registers - 14-23 14.2.9 DRI Data Capture Event Count Setting Register - 14-25 14.2.10 DRI Capture Event Counter - 14-26 14.2.11 DRI Transfer Counter - 14-27 14.2.12 DRI Address Counters - 14-28 14.2.13 DRI Address Reload Registers - 14-29 14.2.14 DIN Input Processing Control Register - 14-30 14.2.15 DRI Event Counter (DEC) Control Registers - 14-31 14.2.16 DRI Event Counters (DEC Counters) - 14-36 14.2.17 DRI Event Counter (DEC) Reload Registers - 14-36 14.3 Notes on DRI - 14-37 CHAPTER 15 REAL TIME DEBUGGER (RTD) 15.1 Outline of the Real-Time Debugger (RTD) - 15-2 15.2 Pin Functions of the RTD - 15-3 15.3 RTD Related Register - 15-3 15.3.1 RTD Write Function Disable Register - 15-3 15.4 Functional Description of the RTD - 15-4 15.4.1 Outline of the RTD Operation - 15-4 15.4.2 Operation of RDR (Real-time RAM Content Output) - 15-4 15.4.3 Operation of the WRR (RAM Content Forcible Rewrite) - 15-6 15.4.4 Operation of VER (Continuous Monitor) - 15-7 15.4.5 Operation of VEI (Interrupt Request) - 15-7 15.4.6 Operation of RCV (Recover from Runaway) - 15-8 15.4.7 Method for Setting a Specified Address when Using the RTD - 15-9 15.4.8 Resetting the RTD - 15-10 15.5 Typical Connection with the Host - 15-11 CHAPTER 16 NON-BREAK DEBUG (NBD) 16.1 Outline of the Non-Break Debug (NBD) - 16-2 16.2 Pin Functions of NBD - 16-4 16.2.1 NBD Pin Control Register - 16-4 16.3 NBD Related Registers - 16-6 16.3.1 NBD Enable Register - 16-6 16.4 Communication Protocol - 16-7 32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 REJ09B0123-0110 Apr.06.07 Contents-9 16.5 RAM Monitor Function - 16-8 16.5.1 Description of NBD Operation - 16-8 16.5.2 NBDD Data Format - 16-9 16.6 Event Detection Function - 16-11 16.6.1 Event Address Setting Register - 16-11 16.6.2 Event Condition Setting Register - 16-12 16.6.3 Event Generation Register - 16-12 CHAPTER 17 EXTERNAL BUS INTERFACE 17.1 Outline of the External Bus Interface - 17-2 17.1.1 External Bus Interface Related Signals - 17-2 17.2 External Bus Interface Related Registers - 17-5 17.2.1 Port Operation Mode and Port Peripheral Function Select Registers - 17-5 17.2.2 Bus Mode Control Register - 17-15 17.2.3 CLKOUT Select Register - 17-16 17.3 Read/Write Operations - 17-19 17.4 Bus Arbitration - 17-25 17.5 Typical Connection of External Extension Memory - 17-27 17.6 Example of Bus Voltage Settings Using VCC-BUS - 17-30 CHAPTER 18 WAIT CONTROLLER 18.1 Outline of the Wait Controller - 18-2 18.2 Wait Controller Related Registers - 18-4 18.2.1 CS Area Wait Control Registers - 18-4 18.2.2 Flash E/W Wait Select Register - 18-6 18.3 Typical Operation of the Wait Controller - 18-7 CHAPTER 19 RAM BACKUP MODE 19.1 Outline of RAM Backup Mode - 19-2 19.2 Example of RAM Backup when Power is Off - 19-3 19.2.1 Normal Operating State - 19-3 19.2.2 RAM Backup State - 19-4 19.3 Example of RAM Backup for Saving Power Consumption - 19-5 19.3.1 Normal Operating State - 19-6 19.3.2 RAM Backup State - 19-7 19.3.3 Precautions to Be Observed at Power-On - 19-8 19.3.4 Power-On Limitation - 19-8 19.4 Exiting RAM Backup Mode (Wakeup) - 19-9 CHAPTER 20 OSCILLATOR CIRCUIT 20.1 Oscillator Circuit - 20-2 20.1.1 Example of an Oscillator Circuit - 20-2 20.1.2 XIN Oscillation Stoppage Detection Circuit - 20-3 20.1.3 Oscillation Drive Capability Select Function - 20-5 20.1.4 System Clock Output Function - 20-7 20.1.5 Oscillation Stabilization Time at Power-On - 20-11 20.2 Clock Generator Circuit - 20-12 32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 REJ09B0123-0110 Apr.06.07 Contents-10 CHAPTER 21 JTAG 21.1 Outline of JTAG - 21-2 21.2 Configuration of JTAG Circuit - 21-3 21.3 JTAG Registers - 21-4 21.3.1 Instruction Register (JTAGIR) - 21-4 21.3.2 Data Register - 21-5 21.4 Basic Operation of JTAG - 21-6 21.4.1 Outline of JTAG Operation - 21-6 21.4.2 IR Path Sequence - 21-8 21.4.3 DR Path Sequence - 21-9 21.4.4 Inspecting and Setting Data Registers - 21-10 21.5 Boundary Scan Description Language - 21-11 21.6 Notes on Board Design when Connecting JTAG - 21-12 21.7 Processing Pins when Not Using JTAG - 21-13 CHAPTER 22 POWER SUPPLY CIRCUIT 22.1 Configuration of the Power Supply Circuit - 22-2 22.2 Power-On Sequence - 22-3 22.2.1 Power-On Sequence when Not Using RAM Backup - 22-3 22.2.2 Power-On Sequence when Using RAM Backup - 22-4 22.3 Power-Off Sequence - 22-5 22.3.1 Power-Off Sequence when Not Using RAM Backup - 22-5 22.3.2 Power-Off Sequence when Using RAM Backup - 22-6 CHAPTER 23 ELECTRICAL CHARACTERISTICS 23.1 Adapted Table - 23-2 23.2 Absolute Maximum Ratings - 23-2 23.3 Electrical Characteristics when VCCE = 5 V, f(XIN) = 20 MHz - 23-3 23.3.1 Recommended Operating Conditions (when VCCE = 5 V ± 0.5 V, f(XIN) = 20 MHz) - 23-3 23.3.2 D.C. Characteristics (when VCCE = 5 V ± 0.5 V, f(XIN) = 20 MHz) - 23-5 23.3.3 A/D Conversion Characteristics (when VCCE = 5 V ± 0.5 V, f(XIN) = 20 MHz) - 23-6 23.4 Electrical Characteristics when VCCE = 5 V, f(XIN) = 16 MHz - 23-7 23.4.1 Recommended Operating Conditions (when VCCE = 5 V ± 0.5 V, f(XIN) = 16 MHz) - 23-7 23.4.2 D.C. Characteristics (when VCCE = 5 V ± 0.5 V, f(XIN) = 16 MHz) - 23-9 23.4.3 A/D Conversion Characteristics (when VCCE = 5 V ± 0.5 V, f(XIN) = 16 MHz) - 23-10 23.5 Electrical Characteristics when VCCE = 3.3 V, f(XIN) = 20 MHz - 23-11 23.5.1 Recommended Operating Conditions (when VCCE = 3.3 V ± 0.3 V, f(XIN) = 20 MHz) - 23-11 23.5.2 D.C. Characteristics (when VCCE = 3.3 V ± 0.3 V, f(XIN) = 20 MHz) - 23-13 23.5.3 A/D Conversion Characteristics (when VCCE = 3.3 V ± 0.3 V, f(XIN) = 20 MHz) - 23-14 23.6 Electrical Characteristics when VCCE = 3.3 V, f(XIN) = 16 MHz - 23-15 23.6.1 Recommended Operating Conditions (when VCCE = 3.3 V ± 0.3 V f(XIN) = 16 MHz) - 23-15 23.6.2 D.C. Characteristics (when VCCE = 3.3 V ± 0.3 V, f(XIN) = 16 MHz) - 23-17 23.6.3 A/D Conversion Characteristics (when VCCE = 3.3 V ± 0.3 V, f(XIN) = 8 MHz) - 23-18 23.7 Flash Memory Related Characteristics - 23-19 23.8 External Capacitance for Power Supply - 23-19 23.9 A.C. Characteristics (when VCCE = 5 V) - 23-20 23.10 A.C. Characteristics (when VCCE = 3.3 V) - 23-42 32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 REJ09B0123-0110 Apr.06.07 Contents-11 APPENDIX 1 MECHANICAL SPECIFICAITONS Appendix 1.1 Dimensional Outline Drawing - Appendix 1-2 APPENDIX 2 INSTRUCTION PROCESSING TIME Appendix 2.1 32192/32195/32196 Instruction Processing Time - Appendix 2-2 APPENDIX 3 PROCESSING OF UNUSED PINS Appendix 3.1 Example Processing of Unused Pins - Appendix 3-2 APPENDIX 4 SUMMARY OF PRECAUTIONS Appendix 4.1 Notes on the CPU -Appendix 4.2 Notes on Address Space -Appendix 4.3 Notes on EIT -Appendix 4.4 Notes on the Internal RAM -Appendix 4.5 Notes on the Internal Flash Memory -Appendix 4.6 Things to Be Considered upon Exiting Reset -Appendix 4.7 Notes on Input/Output Ports -Appendix 4.8 Notes on the DMAC -Appendix 4.9 Notes on Multijunction Timers -Appendix 4.9.1 Notes on using TOP single-shot output mode -Appendix 4.9.2 Notes on using TOP delayed single-shot output mode -Appendix 4.9.3 Notes on using TOP continuous output mode -Appendix 4.9.4 Notes on using TIO measure free-run/ clear input modes -Appendix 4.9.5 Notes on using TIO PWM output mode -Appendix 4.9.6 Notes on using TIO single-shot output mode -Appendix 4.9.7 Notes on using TIO delayed single-shot output mode -Appendix 4.9.8 Notes on using TIO continuous output mode -Appendix 4.9.9 Notes on using TMS measure input -Appendix 4.9.10 Notes on using TML measure input -Appendix 4.9.11 Notes on using TOU PWM output mode -Appendix 4.9.12 Notes on using TOU single-shot PWM output mode -Appendix 4.9.13 Notes on using TOU delayed single-shot output mode -Appendix 4.9.14 Notes on using TOU single-shot output mode -Appendix 4.9.15 Notes on using TOU continuous output mode -Appendix 4.9.16 0% or 100% Duty-Cycle Wave Output during PWM Output and Single-shot PWM Output Modes -Appendix 4.10 Notes on the A/D Converter -Appendix 4.11 Notes on Serial Interface -Appendix 4.11.1 Notes on Using CSIO Mode -Appendix 4.11.2 Notes on Using UART Mode -Appendix 4.12 Notes on CAN Module -Appendix 4.13 Notes on DRI -Appendix 4.14 Notes on RAM Backup Mode -Appendix 4.14.1 Precautions to Be Observed at Power-On -Appendix 4.14.2 Power-On Limitation - 32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 REJ09B0123-0110 Apr.06.07 Appendix 4-2 Appendix 4-3 Appendix 4-3 Appendix 4-3 Appendix 4-4 Appendix 4-4 Appendix 4-5 Appendix 4-6 Appendix 4-7 Appendix 4-7 Appendix 4-9 Appendix 4-10 Appendix 4-10 Appendix 4-10 Appendix 4-10 Appendix 4-11 Appendix 4-11 Appendix 4-11 Appendix 4-12 Appendix 4-13 Appendix 4-16 Appendix 4-16 Appendix 4-16 Appendix 4-17 Appendix 4-17 Appendix 4-22 Appendix 4-25 Appendix 4-25 Appendix 4-26 Appendix 4-28 Appendix 4-29 Appendix 4-29 Appendix 4-29 Appendix 4-29 Contents-12 Appendix 4.15 Notes on JTAG -Appendix 4.15.1 Notes on Board Design when Connecting JTAG -Appendix 4.15.2 Processing Pins when Not Using JTAG -Appendix 4.16 Notes on Noise -Appendix 4.16.1 Reduction of Wiring Length -Appendix 4.16.2 Inserting a Bypass Capacitor between VSS and VCC Lines -Appendix 4.16.3 Processing Analog Input Pin Wiring -Appendix 4.16.4 Consideration about the Oscillator -Appendix 4.16.5 Processing Input/Output Ports - 32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 REJ09B0123-0110 Apr.06.07 Appendix 4-30 Appendix 4-30 Appendix 4-31 Appendix 4-32 Appendix 4-32 Appendix 4-34 Appendix 4-34 Appendix 4-35 Appendix 4-39 Contents-13 To be written at a later time. 32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 REJ09B0123-0110 Apr.06.07 Contents-14 CHAPTER 1 OVERVIEW 1.1 1.2 Outline of the 32192/32195/32196 Group Block Diagram 1.3 Pin Functions 1.4 Pin Assignments OVERVIEW 1 1.1 Outline of the 32192/32195/32196 Group 1.1 Outline of the 32192/32195/32196 Group The 32192/32195/32196 Group (hereinafter simply the 32192/32195/32196) belongs to the M32R/ECU M32R/ECU Series in the M32R Family of Renesas microcomputers. For details about the current development status of the 32192/32195/32196, please contact your nearest office of Renesas or its distributor. Table 1.1.1 Product List Type Name M32192F8VFP M32192F8VFP ROM RAM capacity capacity 1 Mbytes 176 Kbytes Frequency Power supply voltage at single-supply 128 MHz at double-supply 3.3V 5V, 3.3V Temperature Range (Note 1) ­40°C to 125°C M32192F8UFP M32192F8UFP 1 Mbytes 176 Kbytes 160 MHz 3.3V 5V, 3.3V ­40°C to 105°C M32192F8TFP M32192F8TFP 1 Mbytes 176 Kbytes 160 MHz 5V or 3.3V 5V, 3.3V ­40°C to 85°C M32192F8VWG M32192F8VWG 1 Mbytes 176 Kbytes 128 MHz 3.3V 5V, 3.3V ­40°C to 125°C M32192F8UWG M32192F8UWG 1 Mbytes 176 Kbytes 160 MHz 3.3V 5V, 3.3V ­40°C to 105°C M32192F8TWG M32192F8TWG 1 Mbytes 176 Kbytes 160 MHz 5V or 3.3V 5V, 3.3V ­40°C to 85°C M32195F4VFP M32195F4VFP 512 Kbytes 32 Kbytes 128 MHz 3.3V 5V, 3.3V ­40°C to 125°C M32195F4UFP M32195F4UFP 512 Kbytes 32 Kbytes 160 MHz 3.3V 5V, 3.3V ­40°C to 105°C M32195F4TFP M32195F4TFP 512 Kbytes 32 Kbytes 160 MHz 5V or 3.3V 5V, 3.3V ­40°C to 85°C M32196F8VFP M32196F8VFP 1 Mbytes 64 Kbytes 128 MHz 3.3V 5V, 3.3V ­40°C to 125°C M32196F8UFP M32196F8UFP 1 Mbytes 64 Kbytes 160 MHz 3.3V 5V, 3.3V ­40°C to 105°C M32196F8TFP M32196F8TFP 1 Mbytes 64 Kbytes 160 MHz 5V or 3.3V 5V, 3.3V ­40°C to 85°C Note 1: This does not guarantee continuous operation and there is a limitation on the length of use (temperature profile). 1.1.1 M32R Family CPU Core with Built-in FPU (M32R-FPU M32R-FPU) (1) Based on a RISC architecture · The 32192/32195/32196 is a group of 32-bit RISC single-chip microcomputers. The M32R-FPU M32R-FPU in this group of microcomputers incorporates a fully IEEE 754-compliant, single-precision FPU in order to materialize the common instruction set and the high-precision arithmetic operation of the M32R CPU. The 32192/32195/32196 products listed in the above table are built around the M32R-FPU M32R-FPU and incorporates flash memory, RAM and various peripheral functions, all integrated into a single chip. · The M32R-FPU M32R-FPU is constructed based on a RISC architecture. Memory is accessed using load/store instructions, and various arithmetic/logic operations are executed using register-to-register operation instructions. · The M32R-FPU M32R-FPU internally contains sixteen 32-bit general-purpose registers. The instruction set consists of 100 discrete instructions in total (83 instructions common to the M32R Family plus 17 FPU and extended instructions). These instructions are either 16 bits or 32 bits long. · In addition to the ordinary load/store instructions, the M32R-FPU M32R-FPU supports compound instructions such as Load & Address Update and Store & Address Update. These instructions help to speed up data transfers. (2) Six-stage pipelined processing · The M32R-FPU M32R-FPU supports six-stage pipelined instruction processing. Not just load/store instructions and register-to-register operation instructions, but also floating-point arithmetic instructions and compound instructions such as Load & Address Update and Store & Address Update are executed in one CPUCLK period (which is equivalent to 6.25 ns when f(CPUCLK) = 160 MHz). · Although instructions are supplied to the execution stage in the order in which they were fetched, it is possible that if the load/store instruction supplied first is extended by wait cycles inserted in memory access, the subsequent register-to-register operation instruction will be executed before that instruction. Using such a facility, which is known as the "out-of-order-completion" mechanism, the M32R-FPU M32R-FPU is able to control instruction execution without wasting clock cycles. 32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 REJ09B0123-0110 Apr.06.07 1-2 OVERVIEW 1 1.1 Outline of the 32192/32195/32196 Group (3) Compact instruction code · The M32R-FPU M32R-FPU supports two instruction formats: one 16 bits long, and one 32 bits long. Use of the 16-bit instruction format especially helps to suppress the code size of a program. · Moreover, the availability of 32-bit instructions makes programming easier and provides higher performance at the same clock speed than in architectures where the address space is segmented. For example, some 32-bit instructions allow control to jump to an address 32 Mbytes forward or backward from the currently executed address in one instruction, making programming easy. 1.1.2 Built-in Multiplier/Accumulator (1) Built-in high-speed multiplier · The M32R-FPU M32R-FPU contains a 32 bits × 16 bits high-speed multiplier which enables the M32R-FPU M32R-FPU to execute a 32 bits × 32 bits integral multiplication instruction in three CPUCLK periods. (2) DSP-comparable multiply-accumulate instructions · The M32R-FPU M32R-FPU supports the following four types of multiply-accumulate instructions (or multiplication instructions) which each can be executed in one CPUCLK period using a 56-bit accumulator. (1) (2) (3) (4) 16 16 All All high-order bits of register × 16 high-order bits of register low-order bits of register × 16 low-order bits of register 32 bits of register × 16 high-order bits of register 32 bits of register × 16 low-order bits of register · The M32R-FPU M32R-FPU has some special instructions to round the value stored in the accumulator to 16 or 32 bits or shift the accumulator value before storing in a register to have its digits adjusted. Because these instructions too are executed in one CPUCLK period, when used in combination with highspeed data transfer instructions such as Load & Address Update or Store & Address Update, they enable the M32R-FPU M32R-FPU to exhibit superior data processing capability comparable to that of a DSP. 1.1.3 Built-in Single-precision FPU · The M32R-FPU M32R-FPU supports single-precision floating-point arithmetic fully compliant with IEEE 754 standards. Specifically, five exceptions specified in IEEE 754 standards (Inexact, Underflow, Division by Zero, Overflow and Invalid Operation) and four rounding modes (round to nearest, round toward 0, round toward + Infinity and round toward ­ Infinity) are supported. What's more, because general-purpose registers are used to perform floating-point arithmetic, the overhead associated with transferring the operand data can be reduced. 1.1.4 Built-in Flash Memory and RAM · The 32192/32195/32196 contains a RAM that can be accessed with zero wait state, allowing to design a high-speed embedded system. · The internal flash memory can be written to while mounted on a printed circuit board (on-board writing). Use of flash memory facilitates development work, because the chip used at the development stage can be used directly in mass-production, allowing for a smooth transition from prototype to mass-production without the need to change the printed circuit board. · The internal flash memory can be rewritten as many as 100 times. 32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 REJ09B0123-0110 Apr.06.07 1-3 OVERVIEW 1 1.1 Outline of the 32192/32195/32196 Group · The internal flash memory has a virtual flash emulation function, allowing the internal RAM to be superficially mapped into part of the internal flash memory. When combined with the internal RealTime Debugger (RTD) and the M32R family's common debug interface (Scalable Debug Interface or SDI), this function makes the ROM table data tuning easy. · The internal RAM can be accessed for reading or rewriting data from an external device independently of the M32R-FPU M32R-FPU by using the Real-Time Debugger. The external device is communicated using the Real-Time Debugger's exclusive clock-synchronous serial interface. 32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 REJ09B0123-0110 Apr.06.07 1-4 OVERVIEW 1 1.1 Outline of the 32192/32195/32196 Group 1.1.5 Built-in Clock Frequency Multiplier · The 32192/32195/32196 contains a clock frequency multiplier, which is schematically shown in Figure 1.1.1 below. XIN pin (16MHz-20MHz) CPUCLK (CPU clock) (128MHz-160MHz) X8 PLL BCLK (peripheral clock) (32MHz-40MHz) 1/4 1/2 CLKO SEL CLKOUT(external bus clock) (32MHz-40MHz or 16MHz-20MHz) Figure 1.1.1 Conceptual Diagram of the Clock Frequency Multiplier Table 1.1.2 Clock Functional Block Features CPUCLK · CPU clock: Defined as f(CPUCLK) when it indicates the operating clock frequency for the M32R-FPU M32R-FPU core, internal flash memory and internal RAM. BCLK · Peripheral clock: Defined as f(BCLK) when it indicates the operating clock frequency for the internal peripheral I/O and external data bus. Clock output · BCLK pin output: A clock with the same frequency as f(BCLK) is output from this pin. · CLKOUT pin output: A clock with the same or half frequency as f(BCLK) is output from this pin. 1.1.6 Powerful Peripheral Functions Built-in (1) 8-level interrupt controller (ICU) (2) 10-channel DMAC (3) 55-channel multijunction timer (MJT) (4) 16-channel A/D converter (ADC) (5) 6-channel serial interface (SIO) (6) 2-channel Full-CAN (7) Direct RAM interface (DRI) (8) Real-time debugger (RTD) (9) Non-break debug (NBD) (10) Wait controller (11) M32R Family's common debug function (Scalable Debug Interface or SDI) 32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 REJ09B0123-0110 Apr.06.07 1-5 OVERVIEW 1 1.2 Block Diagram 1.2 Block Diagram Figure 1.2.1 shows a block diagram of the 32192/32195/32196. The features of each block are described in Table 1.2.1. Internal Bus Interface M32R-FPU M32R-FPU Core (Max. 160MHz) DMAC (10 channels) (M32192F8 M32192F8: 1 Mbyte) (M32195F4 M32195F4: 512 Kbytes) (M32196F8 M32196F8: 1 Mbyte) Non-Break Debug (NBD) Internal RAM (M32192F8 M32192F8: 176 Kbytes) (M32195F4 M32195F4: 32 Kbytes) (M32196F8 M32196F8: 64 Kbytes) A/D Converter (A/D0: 10-bit converter, 16 channels) Internal 16-bit bus Internal Flash Memory Multijunction Timer (MJT: 55 channels) Internal 32-bit bus Single-precision FPU (fully IEEE 754 compliant) Internal 32-bit bus Multiplier/Accumulator (32 bits x 16 bits + 56 bits) Serial Interface (6 channels) Interrupt Controller (8 levels) Wait Controller Real-Time Debugger (RTD) Direct RAM Interface (DRI) Full CAN (2 channels) PLL Clock Generator Internal Power Supply Generator (VDC) External Bus Interface Data Address Input/output ports, 97 lines Figure 1.2.1 Block Diagram of the 32192/32195/32196 32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 REJ09B0123-0110 Apr.06.07 1-6 OVERVIEW 1 1.2 Block Diagram Table 1.2.1 Features of the 32192/32195/32196 (1/3) Functional Block Features M32R-FPU M32R-FPU CPU core · Implementation: Six-stage pipelined instruction processing · Internal 32-bit structure of the core · Register configuration General-purpose registers: 32 bits × 16 registers Control registers: 32 bits × 6 registers · Instruction set 16-bit and 32-bit instruction formats 100 discrete instructions and six addressing modes · Internal multiplier/accumulator (32 bits × 16 bits + 56 bits) · Internal single-precision floating-point arithmetic unit (FPU) Internal Flash memory · Capacity: M32192F8 M32192F8 : 1 Mbyte M32195F4 M32195F4 : 512 Kbytes M32196F8 M32196F8 : 1 Mbyte · One wait access · Durability: Rewritable 100 times Internal RAM · Capacity: M32192F8 M32192F8 : 176 Kbytes M32195F4 M32195F4 : 32 Kbytes M32196F8 M32196F8 : 64 Kbytes ·Zero wait access · The internal RAM can be accessed for reading or rewriting data from the outside independently of the M32R-FPU M32R-FPU by using the Real-Time Debugger, without ever causing the CPU performance to decrease. · By using RAM backup mode, a part of internal RAM area can be backed up when turn off the power supply. Bus specification · Fundamental bus cycle : 6.25 ns (when f(CPUCLK) = 160 MHz) · Logical address space : 4 Gbytes linear · Internal bus specification : Internal 32-bit data bus (for CPU internal flash memory and RAM access) (or accessed in 64 bits when accessing the internal flash memory for instructions) : Internal 16-bit data bus (for internal peripheral I/O access) · External extension area: During processor mode: maximum 32 Mbytes During external extension mode: maximum 31 Mbytes (7 Mbytes + 8 Mbytes × 3 blocks) · External data address: 22-bit address · External data bus: 16-bit data bus · Shortest external bus access: 1 CLKOUT during read, 1 CLKOUT during write Multijunction timer (MJT) · 55-channel multi-functional timer 16-bit output related timer × 11 channels, 16-bit input/output related timer × 10 channels, 16-bit input related timer × 8 channels, 32-bit input related timer × 8 channels, 16-bit input related up/down timer × 2 channels, and 24-bit output related timer × 16 channels · Flexible timer configuration is possible by interconnecting these timer channels. · Interrupt request: Counter underflow or overflow and rising or falling or both edges or "H" or "L" level from the TIN pin (TIN pin can be used as external interrupt inputs irrespective of timer operation.) · DMA transfer request: Counter underflow or overflow and rising or falling or both edges or "H" or "L" level from the TIN pin (TIN pin can be used as DMA transfer request inputs irrespective of timer operation.) DMAC · Number of channels: 10 · Transfers between internal peripheral I/Os or internal RAMs or between internal peripheral I/O and internal RAM are supported. · Capable of advanced DMA transfers when used in combination with internal peripheral I/O · Transfer request: Software or internal peripheral I/O (A/D converter, MJT, serial interface or CAN) · DMA channels can be cascaded. (DMA transfer on a channel can be started by completion of a transfer on another channel.) · Interrupt request: DMA transfer counter register underflow 32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 REJ09B0123-0110 Apr.06.07 1-7 OVERVIEW 1 1.2 Block Diagram Table 1.2.1 Features of the 32192/32195/32196 (2/3) Functional Block Features A/D Converter (ADC) · 16 channels: 10-bit resolution A/D converter × 1 block · Conversion modes: In addition to ordinary A/D conversion mode, comparator mode and 2-channel simultaneous sampling mode. · Operation modes: Single conversion mode and n-channel scan mode (n = 1­16) · Sample-and-hold function: Performs A/D conversion with the analog input voltages sampled at start of A/D conversion. · A/D disconnection detection assist function: Suppresses effects of the analog input voltage leakage from the preceding channel during A/D conversion. · An inflow current bypass circuit is built-in. · Can generate an interrupt or start DMA transfer upon completion of A/D conversion. · Either 8-bit or 10-bit conversion results can be read out. · Interrupt request: Completion of A/D conversion · DMA transfer request: Completion of A/D conversion Serial Interface (SIO) · 6-channel serial interface · Can be chosen to be clock-synchronous serial interface or clock-asynchronous serial interface. · Data can be transferred at high speed (5 Mbits per second during clock-synchronous mode or 2.5 Mbits per second during clock-asynchronous mode when f(BCLK) = 40 MHz). · Interrupt request: Reception completed, receive error, transmit buffer empty or transmission completed · DMA transfer request: Reception completed or transmit buffer empty CAN · 32 message slots × 2 blocks · Compliant with CAN specification 2.0B active. · Interrupt request: Transmission completed, reception completed, bus error, error-passive, bus-off or single shot · DMA transfer request: Failed to send, transmission completed or reception completed Real-Time Debugger (RTD) · Internal RAM can be rewritten or monitored independently of the CPU by entering a command from the outside. · Comes with exclusive clock-synchronous serial ports. · Interrupt request: RTD interrupt command input Non-Break Debug (NBD) · Can access to all resources on the address map from the outside · Clock-synchronous parallel interface (4-bit) · Event output function · RAM monitor function Direct RAM Interface (DRI) · Can control capture of clock-synchronous parallel data to the internal RAM independently of the CPU · Clock-synchronous parallel input (8-bit, 16-bit or 32-bit) · Maximum transfer rate: 40 Mbytes/s (when f(CPUCLK)=160 MHz) Interrupt Controller (ICU) · Controls interrupt requests from the internal peripheral I/O. · Supports 8-level interrupt priority including an interrupt disabled state. · External interrupt: 27 sources (SBI#, TIN0, TIN3­TIN11 TIN11, TIN16 TIN16­TIN27 TIN27, TIN30 TIN30­TIN33 TIN33) · TIN pin input sensing: Rising, falling or both edges or "H" or "L" level Wait Controller · Controls wait states for access to the external extension area. · Insertion of 0­15 wait states by setting up in software + wait state extension by entering WAIT# signal PLL · A multiply-by-8 clock generating circuit Clock · Maximum external input clock frequency (XIN) is 20.0 MHz. (Note 1) · CPUCLK: Operating clock for the M32R-FPU M32R-FPU core, internal flash memory and internal RAM The maximum CPU clock is 160 MHz (when f(XIN) = 20 MHz). · BCLK: Operating clock for the internal peripheral I/O and external data bus The maximum peripheral clock is 40 MHz (peripheral module access when f(XIN) = 20 MHz). · BCLK pin output: A clock with the same frequency as f(BCLK) is output from this pin. · CLKOUT pin output: A clock with the same or half frequency as f(BCLK) is output from this pin. 32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 REJ09B0123-0110 Apr.06.07 1-8 OVERVIEW 1 1.2 Block Diagram Table 1.2.1 Features of the 32192/32195/32196 (3/3) Functional Block Features JTAG · Boundary scan function VDC · Internal power supply generating circuit: Generates the internal power supply from an external power supply (5 or 3.3 V). Ports · Input/output pin: 97 pins · The port input threshold can be set in a program to one of three levels individually for each port group (with or without Schmitt circuit, selectable). Note 1: The maximum external input clock frequency (XIN) for the M32192F8VFP M32192F8VFP, M32195F4VFP M32195F4VFP, and M32196F8VFP M32196F8VFP are 16.0 MHz. 32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 REJ09B0123-0110 Apr.06.07 1-9 OVERVIEW 1 1.3 Pin Functions 1.3 Pin Functions VCC-BUS Figure 1.3.1 and Figure 1.3.2 show the 32192/32195/32196's pin function diagram. Pin functions are described in Table 1.3.1. XIN Clock Reset XOUT RESET# P93/TO16/SCLKI5/SCLKO5 P93/TO16/SCLKI5/SCLKO5 P95/TO18/RXD5/DD14 P95/TO18/RXD5/DD14 MOD0 MOD1 MOD2 (Note 1) Flash Interrupt controller P100/TO8 P100/TO8 P101/TO9/CRX0 P101/TO9/CRX0 SBI# P103/TO11/TIN24 P103/TO11/TIN24 Multijunction timer Port 3 VCCE 8 8 8 4 4 P41/BLW P41/BLW#/BLE# P42/BHW P42/BHW#/BHE# Bus control Port 4 Address bus P43/RD P43/RD# P44/CS0 P44/CS0#/TIN8, P45/CS1 P45/CS1#/TIN9 P46/A13/TIN10 P46/A13/TIN10, P47/A14/TIN11 P47/A14/TIN11 Multijunction timer Port 6 P61-P63 P61-P63 2 2 3 P70/CLKOUT/WR P70/CLKOUT/WR#/BCLK P71/WAIT P71/WAIT# Multijunction timer P72/HREQ P72/HREQ#/TIN27 /TIN27 Port 7 NBD Real time debugger P73/HACK P73/HACK#/TIN26 /TIN26 P74/RTDTXD/TXD3/NBDD0 P74/RTDTXD/TXD3/NBDD0 Serial Interface P75/RTDRXD/RXD3/NBDD1 P75/RTDRXD/RXD3/NBDD1 VCCE Bus control/ Clock P76/RTDACK/CTX1/NBDD2 P76/RTDACK/CTX1/NBDD2 CAN P77/RTDCLK/CRX1/NBDD3 P77/RTDCLK/CRX1/NBDD3 P107/TO15/RXD4/DD0 P107/TO15/RXD4/DD0 8 P110/TO0/TO29/DD11P117/TO7/TO36/DD4 P110/TO0/TO29/DD11P117/TO7/TO36/DD4 P125/TCLK1/A10/DD2 P125/TCLK1/A10/DD2 Address bus Bus control DRI P130/TIN16/PWMOFF0/DIN0 P130/TIN16/PWMOFF0/DIN0 P131/TIN17/PWMOFF1/DIN1 P131/TIN17/PWMOFF1/DIN1 P132/TIN18/DIN2 P132/TIN18/DIN2 P133/TIN19/DIN3 P133/TIN19/DIN3 P134/TIN20/TXD3/DIN4 P134/TIN20/TXD3/DIN4 Port 13 Serial Interface P135/TIN21/RXD3 P135/TIN21/RXD3 P136/TIN22/CRX1 P136/TIN22/CRX1 CAN P137/TIN23/CTX1 P137/TIN23/CTX1 P150/TIN0/CLKOUT/WR P150/TIN0/CLKOUT/WR# Port 15 Bus control/ Clock Port 17 Serial Interface P153/TIN3/WAIT P153/TIN3/WAIT# P174/TXD2/TO28 P174/TXD2/TO28 P220/CTX0/HACK P220/CTX0/HACK# P175/RXD2/TO27 P175/RXD2/TO27 P221/CRX0/HREQ P221/CRX0/HREQ# CAN/ Bus control Port 22 Address bus/ Bus control P224/A11/CS2 P224/A11/CS2# P225/A12/CS3 P225/A12/CS3# JTRST P84/SCLKI0/SCLKO0/TO24 P84/SCLKI0/SCLKO0/TO24 JTMS VCCE Port 8 Multijunction timer Port 12 P127/TCLK3/CS3 P127/TCLK3/CS3#/DD0 P83/RXD0/TO25 P83/RXD0/TO25 Serial Interface Port 11 P126/TCLK2/CS2 P126/TCLK2/CS2#/DD1 P82/TXD0/TO26 P82/TXD0/TO26 Multijunction timer DRI Serial Interface P124/TCLK0/A9/DD3 P124/TCLK0/A9/DD3 VCC-BUS Address bus P00/DB0/TO21/DD0P07/DB7/TO28/DD7 P00/DB0/TO21/DD0P07/DB7/TO28/DD7 P10/DB8/TO29/DD8P17/DB15/TO36/DD15 P10/DB8/TO29/DD8P17/DB15/TO36/DD15 P20/A23/DD24P27/A30/DD31 P20/A23/DD24P27/A30/DD31 P30/A15/TIN4/DD16P33/A18/TIN7/DD19 P30/A15/TIN4/DD16P33/A18/TIN7/DD19 P34/A19/TIN30/DD20P37/A22/TIN33/DD23 P34/A19/TIN30/DD20P37/A22/TIN33/DD23 VCCE Port 2 P106/TO14/TXD4/DD1 P106/TO14/TXD4/DD1 VCC-BUS Port 1 Port 10 P105/TO13/SCLKI4/SCLKO4/DD2 P105/TO13/SCLKI4/SCLKO4/DD2 M32192F8xFP, M32195F4xFP, M32196F8xFP DRI Port 0 AVSS0 VCC