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REJ09B0024-0600 H8/3802 H8/38004 H8/38002S H8/38104 H8/300L H8/3801 H8/3800 - Datasheet Archive
The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and
REJ09B0024-0600 REJ09B0024-0600 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. 8 H8/3802 H8/3802, H8/38004 H8/38004, H8/38002S H8/38002S, H8/38104 H8/38104 Group Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L H8/300L Super Low Power Series H8/3802 H8/3802 Group H8/38004 H8/38004 Group H8/3802 H8/3802 H8/3801 H8/3801 H8/3800 H8/3800 H8/38004 H8/38004 H8/38003 H8/38003 H8/38002 H8/38002 H8/38001 H8/38001 H8/38000 H8/38000 H8/38002S H8/38002S Group H8/38104 H8/38104 Group Rev. 6.00 Revision Date: Mar 15, 2005 H8/38002S H8/38002S H8/38001S H8/38001S H8/38000S H8/38000S H8/38104 H8/38104 H8/38103 H8/38103 H8/38102 H8/38102 H8/38101 H8/38101 H8/38100 H8/38100 Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. Rev. 6.00 Mar 15, 2005 page ii of l General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product's state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system's operation is not guaranteed if they are accessed. Rev. 6.00 Mar 15, 2005 page iii of l Configuration of This Manual This manual comprises the following items: 1. 2. 3. 4. 5. 6. General Precautions on Handling of Product Configuration of This Manual Preface Contents Overview Description of Functional Modules · CPU and System-Control Modules · On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. List of Registers 8. Electrical Characteristics 9. Appendix 10. Main Revisions and Additions in this Edition (only for revised versions) The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual. 11. Index Rev. 6.00 Mar 15, 2005 page iv of l Preface The H8/3802 H8/3802 Group, H8/38004 H8/38004 Group, and H8/38104 H8/38104 Group are single-chip microcomputers made up of the high-speed H8/300L H8/300L CPU employing Renesas technology's original architecture as their cores, and the peripheral functions required to configure a system. The H8/300L H8/300L CPU has an instruction set that is compatible with the H8/300 H8/300 CPU. Below is a table listing the product specifications for each group. H8/3802 H8/3802 Group H8/38004 H8/38004 Group Item ZTAT Memory H8/38002S H8/38002S Group H8/38104 H8/38104 Group Mask ROM Flash ROM Mask ROM Mask ROM Flash ROM Mask ROM ROM 16 k 8 k to 16 k 16 k/32 k 32 k 8 k to 16 k 16 k/32 k 8 k to 32 k RAM 1k 512 or 1 k 1k 1k 512 k 1k 512 or 1 k 16 MHz 16 MHz - 16 MHz - 20 MHz 20 MHz 10 MHz 10 MHz - 16 MHz - 20 MHz 20 MHz 4 MHz 4 MHz - - - - - - - 10 MHz - 10 MHz - - 1.8 to 3.6 V - - 4 MHz (2.2 V or more) - 4 MHz - - 9 Operating 4.5 to 5.5 V voltage 2.7 to 5.5 V and operating 1.8 to 5.5 V frequency 2.7 to 3.6 V I/O ports 9 9 9 9 9 9 6 6 6 5 6 5 5 I/O Timers Input Output 39 39 39 39 39 39 39 Clock (timer A) 1 1 1 1 1 1 1 Compare (timer F) 1 1 1 1 1 1 1 AEC 1 1 1 1 1 1 1 WDT 1 WDT (discrete) SCI UART/Clock frequency A-D (resolution × input channels) LCD 1 1 1 ch 1 ch 1 ch 1 1 ch 1 ch 1 1 ch 1 ch 10 bit × 4 ch 10 bit × 4 ch 10 bit × 4 ch 10 bit × 4 ch 10 bit × 4 ch 10 bit × 4 ch 10 bit × 4 ch seg 25 com 25 25 25 25 25 25 4 4 4 4 4 4 4 11(8) External interrupt (internal wakeup) 11(8) 11(8) 11(8) 11(8) 11(8) 11(8) POR (power-on reset) - - - - - 1 1 LVD - - - - - 1 1 FP-64A FP-64A FP-64A FP-64A FP-64A FP-64A FP-64A FP-64A FP-64A FP-64A FP-64A FP-64A FP-64A FP-64A FP-64E FP-64E FP-64E FP-64E FP-64E FP-64E FP-64E FP-64E FP-64K FP-64K* FP-64E FP-64E FP-64E FP-64E DP-64S DP-64S DP-64S DP-64S Package die Operating temperature die Standard specifications: 20 to 75°C, WTR: 40 to 85°C Note: * Under development. Rev. 6.00 Mar 15, 2005 page v of l Target Users: This manual was written for users who will be using the H8/3802 H8/3802 Group, H8/38004 H8/38004 Group, H8/38002S H8/38002S Group, and H8/38104 H8/38104 Group in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of the H8/3802 H8/3802 Group, H8/38004 H8/38004 Group, H8/38002S H8/38002S Group, and H8/38104 H8/38104 Group to the target users. Refer to the H8/300L H8/300L Series Programming Manual for a detailed description of the instruction set. Notes on reading this manual: · In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics. · In order to understand the details of the CPU's functions Read the H8/300L H8/300L Series Programming Manual. · In order to understand the details of a register when its name is known Read the index that is the final part of the manual to find the page number of the entry on the register. The addresses, bits, and initial values of the registers are summarized in section 14, List of Registers. Example: Bit order: The MSB is on the left and the LSB is on the right. Notes: The following limitations apply to H8/38004 H8/38004, H8/38002 H8/38002, H8/38104 H8/38104, and H8/38102 H8/38102 programming and debugging when the on-chip emulator is used. 1. Pin P95 is not available because it is used exclusively by the on-chip emulator. 2. Pins P33, P34, and P35 are unavailable for use. In order to use these pins additional hardware must be mounted on the user board. 3. The address range H'7000 to H'7FFF is used by the on-chip emulator and is unavailable to the user. 4. The address range H'F780 to H'FB7F must not be accessed under any circumstances. 5. When the on-chip emulator is being used, pin P95 is I/O, pins P33 and P34 are input, and pin P35 is output. 6. When using the on-chip emulator, pins OSC1 and OSC2 should be connected to an oscillator, or an external clock should be supplied to pin OSC1, even if the on-chip oscillator of the H8/38104 H8/38104 Group is selected. Related Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/eng/ Rev. 6.00 Mar 15, 2005 page vi of l H8/3802 H8/3802 Group, H8/38004 H8/38004 Group, H8/38002S H8/38002S Group, H8/38104 H8/38104 Group manuals: Document Title Document No. H8/3802 H8/3802 Group, H8/38004 H8/38004 Group, H8/38002S H8/38002S Group, H8/38104 H8/38104 Group Hardware Manual This manual H8/300L H8/300L Series Programming Manual ADE-602-040 ADE-602-040 User's manuals for development tools: Document Title Document No. H8S, H8/300 H8/300 Series C/C+ Compiler, Assembler, Optimizing Linkage Editor User's Manual REJ10B0058-0100H REJ10B0058-0100H (ADE-702-247 ADE-702-247) H8S, H8/300 H8/300 Series Simulator/Debugger User's Manual ADE-702-282 ADE-702-282 H8S, H8/300 H8/300 Series High-performance Embedded Workshop, Highperformance Debugging Interface Tutorial ADE-702-231 ADE-702-231 High-performance Embedded Workshop User's Manual ADE-702-201 ADE-702-201 Application notes: Document Title Single Power Supply F-ZTAT Document No. TM On-Board Programming ADE-502-055 ADE-502-055 Rev. 6.00 Mar 15, 2005 page vii of l Rev. 6.00 Mar 15, 2005 page viii of l Main Revisions and Additions in this Edition Item Page All Preface Revisions (See Manual for Details) H8/38002S H8/38002S added v Table amended H8/3802 H8/3802 Group H8/38004 H8/38004 Group Item ZTAT Memory H8/38002S H8/38002S Group H8/38104 H8/38104 Group Mask ROM Flash ROM Mask ROM Mask ROM Flash ROM Mask ROM ROM 16 k 8 k to 16 k 16 k/32 k 32 k 8 k to 16 k 16 k/32 k 8 k to 32 k RAM 1k 512 or 1 k 1k 1k 512 k 1k 512 or 1 k 16 MHz 16 MHz - 16 MHz - 20 MHz 20 MHz 10 MHz 10 MHz - 16 MHz - 20 MHz 20 MHz 4 MHz 4 MHz - - - - - - - 10 MHz - 10 MHz - - 1.8 to 3.6 V - - 4 MHz (2.2 V or more) - 4 MHz - - Input 9 9 9 9 9 9 9 Output 6 6 6 5 6 5 5 I/O 39 39 39 39 39 39 39 Operating 4.5 to 5.5 V voltage 2.7 to 5.5 V and operating 1.8 to 5.5 V frequency 2.7 to 3.6 V I/O ports Timers Clock (timer A) 1 1 1 1 1 1 1 Compare (timer F) 1 1 1 1 1 1 1 AEC 1 1 1 1 1 1 1 WDT 1 WDT (discrete) SCI UART/Clock frequency A-D (resolution × input input channels) LCD 1 1 1 ch 1 ch 1 ch 1 ch 1 1 ch 1 1 ch 1 ch 10 bit × 4 ch 10 bit × 4 ch 10 bit × 4 ch 10 bit × 4 ch 10 bit × 4 ch 10 bit × 4 ch 10 bit × 4 ch seg 25 25 25 25 25 25 com 4 4 4 4 4 4 4 11(8) 11(8) 11(8) 11(8) 11(8) 11(8) 11(8) 1 External interrupt (internal wakeup) 25 POR power-on ( reset) - - - - - 1 LVD - - - - - 1 1 FP-64A FP-64A FP-64A FP-64A FP-64A FP-64A FP-64A FP-64A FP-64A FP-64A FP-64A FP-64A FP-64A FP-64A FP-64E FP-64E FP-64E FP-64E FP-64E FP-64E FP-64E FP-64E FP-64K FP-64K* FP-64E FP-64E FP-64E FP-64E DP-64S DP-64S DP-64S DP-64S Package die Operating temperature die Standard specifications: 20 to 75 C, WTR: 40 to 85 C Note: * Under development. Rev. 6.00 Mar 15, 2005 page ix of l Item Page Revisions (See Manual for Details) 1.1 Features 1 to 3 Description amended · Various peripheral functions Watchdog timer (WDT) (H8/38004 H8/38004, H8/38002S H8/38002S Group and H8/38104 H8/38104 Group only) · On-chip memory Product Classification Model ROM RAM H8/38002S H8/38002S HD64338002S HD64338002S 16 kbytes 512 bytes H8/38001S H8/38001S HD64338001S HD64338001S 12 kbytes 512 bytes H8/38000S H8/38000S HD64338000S HD64338000S 8 kbytes 512 bytes H8/38104 H8/38104 HD64338104 HD64338104 32 kbytes 1 kbyte H8/38103 H8/38103 HD64338103 HD64338103 24 kbytes 1 kbyte H8/38102 H8/38102 HD64338102 HD64338102 16 kbytes 1 kbyte H8/38101 H8/38101 HD64338101 HD64338101 12 kbytes 512 bytes H8/38100 H8/38100 Mask ROM version HD64338100 HD64338100 8 kbytes 512 bytes · Compact package Package Code Body Size Pin Pitch QFP-64 QFP-64 FP-64A FP-64A 14.0 × 14.0 mm 0.8 mm LQFP-64 LQFP-64 FP-64E FP-64E LQFP-64 LQFP-64 FP-64K FP-64K* DP-64S DP-64S DP-64S DP-64S 17.0 × 57.6 mm Die 10.0 × 10.0 mm 10.0 × 10.0 mm 0.5 mm 0.5 mm 1.0 mm Note added Note: * Under development. The package dimensions of the FP-64K FP-64K and FP-64E FP-64E differ. For details, see appendix E, Package Dimensions. Rev. 6.00 Mar 15, 2005 page x of l Item Page Revisions (See Manual for Details) 1.2 Internal Block Diagram 4 Figure amended OSC1 OSC2 P31/TMOFL P31/TMOFL P32/TMOFH P32/TMOFH P33 P34 P35 P36/AEVH P36/AEVH P37/AEVL P37/AEVL Port 3 P40/SCK32 P40/SCK32 P41/RXD32 P41/RXD32 P42/TXD32 P42/TXD32 P43/IRQ0 P43/IRQ0 Port 4 System clock oscillator Vss Vss = AVss Vcc RES TEST H8/300L H8/300L CPU Subclock oscillator RAM Port A x1 x2 PA3/COM4 PA2/COM3 PA1/COM2 PA0/COM1 ROM Asynchronous event counter (AEC) Port 8 P80/SEG25 P80/SEG25 P77/SEG24 P77/SEG24 P76/SEG23 P76/SEG23 P75/SEG22 P75/SEG22 P74/SEG21 P74/SEG21 P73/SEG20 P73/SEG20 P72/SEG19 P72/SEG19 P71/SEG18 P71/SEG18 P70/SEG17 P70/SEG17 10-bit PWM1 Timer F AVcc RAM LCD controller/driver Port B LCD power supply 10-bit PWM2 P60/SEG9 P60/SEG9 P61/SEG10 P61/SEG10 P62/SEG11 P62/SEG11 P63/SEG12 P63/SEG12 P64/SEG13 P64/SEG13 P65/SEG14 P65/SEG14 P66/SEG15 P66/SEG15 P67/SEG16 P67/SEG16 P95 P94 P93 P92 P91/PWM2 P91/PWM2 P90/PWM1 P90/PWM1 Port 7 Port 5 P50/WKP0/SEG1 P50/WKP0/SEG1 P51/WKP1/SEG2 P51/WKP1/SEG2 P52/WKP2/SEG3 P52/WKP2/SEG3 P53/WKP3/SEG4 P53/WKP3/SEG4 P54/WKP4/SEG5 P54/WKP4/SEG5 P55/WKP5/SEG6 P55/WKP5/SEG6 P56/WKP6/SEG7 P56/WKP6/SEG7 P57/WKP7/SEG8 P57/WKP7/SEG8 Timer A Port 9 IRQAEC Port 6 Figure 1.1 Internal Block Diagram of H8/3802 H8/3802 Group V1 V2 V3 PB3/AN3/IRQ1 PB2/AN2 PB1/AN1 PB0/AN0 10-bit A/D converter Rev. 6.00 Mar 15, 2005 page xi of l Item Page Revisions (See Manual for Details) 1.2 Internal Block Diagram 5 Figure amended OSC1 OSC2 Port 3 P40/SCK32 P40/SCK32 P41/RXD32 P41/RXD32 P42/TXD32 P42/TXD32 P43/IRQ0 P43/IRQ0 Port 4 System clock oscillator P31/TMOFL P31/TMOFL P32/TMOFH P32/TMOFH P33 P34 P35 P36/AEVH P36/AEVH P37/AEVL P37/AEVL RAM PA3/COM4 PA2/COM3 PA1/COM2 PA0/COM1 IRQAEC Asynchronous event counter (AEC) P80/SEG25 P80/SEG25 P77/SEG24 P77/SEG24 P76/SEG23 P76/SEG23 P75/SEG22 P75/SEG22 P74/SEG21 P74/SEG21 P73/SEG20 P73/SEG20 P72/SEG19 P72/SEG19 P71/SEG18 P71/SEG18 P70/SEG17 P70/SEG17 10-bit PWM1 Timer F SCI3 LCD controller/driver AVcc 10-bit A/D converter Port B Port 6 WDT LCD power supply 10-bit PWM2 P60/SEG9 P60/SEG9 P61/SEG10 P61/SEG10 P62/SEG11 P62/SEG11 P63/SEG12 P63/SEG12 P64/SEG13 P64/SEG13 P65/SEG14 P65/SEG14 P66/SEG15 P66/SEG15 P67/SEG16 P67/SEG16 P95 P94 P93 P92 P91/PWM2 P91/PWM2 P90/PWM1 P90/PWM1 Port 8 Timer A Port 9 ROM Port 7 Port 5 P50/WKP0/SEG1 P50/WKP0/SEG1 P51/WKP1/SEG2 P51/WKP1/SEG2 P52/WKP2/SEG3 P52/WKP2/SEG3 P53/WKP3/SEG4 P53/WKP3/SEG4 P54/WKP4/SEG5 P54/WKP4/SEG5 P55/WKP5/SEG6 P55/WKP5/SEG6 P56/WKP6/SEG7 P56/WKP6/SEG7 P57/WKP7/SEG8 P57/WKP7/SEG8 Rev. 6.00 Mar 15, 2005 page xii of l Vss Vss = AVss Vcc RES TEST H8/300L H8/300L CPU Subclock oscillator Port A x1 x2 Figure 1.2 Internal Block Diagram of H8/38004 H8/38004 Group V1 V2 V3 PB3/AN3/IRQ1 PB2/AN2 PB1/AN1 PB0/AN0 Item Page Revisions (See Manual for Details) 1.2 Internal Block Diagram 6 Figure amended OSC1 OSC2 Port 3 P40/SCK32 P40/SCK32 P41/RXD32 P41/RXD32 P42/TXD32 P42/TXD32 P43/IRQ0 P43/IRQ0 Port 4 System clock oscillator P31/TMOFL P31/TMOFL P32/TMOFH P32/TMOFH P33 P34 P35 P36/AEVH P36/AEVH P37/AEVL P37/AEVL 1.4 Pin Functions PA3/COM4 PA2/COM3 PA1/COM2 PA0/COM1 Port 9 P95 P93/Vref P92 P91/PWM2 P91/PWM2 P90/PWM1 P90/PWM1 Port 8 P80/SEG25 P80/SEG25 Port 7 Power-on reset and low-voltage detection circuit Timer A P77/SEG24 P77/SEG24 P76/SEG23 P76/SEG23 P75/SEG22 P75/SEG22 P74/SEG21 P74/SEG21 P73/SEG20 P73/SEG20 P72/SEG19 P72/SEG19 P71/SEG18 P71/SEG18 P70/SEG17 P70/SEG17 Port 5 10-bit PWM1 Timer F LCD power supply Port 6 WDT LCD controller/driver Port B SCI3 AVcc Figure 1.4 Pin Arrangement of H8/3802 H8/3802, H8/38004 H8/38004 and H8/38002S H8/38002S Group (FP64A FP64A, FP-64E FP-64E, FP-64K FP-64K) Asynchronous event counter (AEC) ROM 10-bit PWM2 P60/SEG9 P60/SEG9 P61/SEG10 P61/SEG10 P62/SEG11 P62/SEG11 P63/SEG12 P63/SEG12 P64/SEG13 P64/SEG13 P65/SEG14 P65/SEG14 P66/SEG15 P66/SEG15 P67/SEG16 P67/SEG16 7 RAM IRQAEC P50/WKP0/SEG1 P50/WKP0/SEG1 P51/WKP1/SEG2 P51/WKP1/SEG2 P52/WKP2/SEG3 P52/WKP2/SEG3 P53/WKP3/SEG4 P53/WKP3/SEG4 P54/WKP4/SEG5 P54/WKP4/SEG5 P55/WKP5/SEG6 P55/WKP5/SEG6 P56/WKP6/SEG7 P56/WKP6/SEG7 P57/WKP7/SEG8 P57/WKP7/SEG8 1.3 Pin Arrangement CVcc Vss Vss = AVss Vcc RES TEST H8/300L H8/300L CPU Subclock oscillator Port A x1 x2 Figure 1.3 Internal Block Diagram of H8/38104 H8/38104 Group V1 V2 V3 PB3/AN3/IRQ1 PB2/AN2 PB1/AN1/extU PB0/AN0/extD 10-bit A/D converter Title and figure amended FP-64A FP-64A, FP-64E FP-64E, FP-64K FP-64K (Top view) 19 to 22 Table amended Pin No. Table 1.4 Pin Functions Type Symbol FP-64A FP-64A, FP-64E FP-64E, FP-64K FP-64K I/O Functions Clock pins X1 2 10 2 2 Input X2 3 11 3 3 Output These pins connect to a 32.768or 38.4-kHz*5 crystal resonator for subclocks. DP-64S DP-64S Pad Pad No.*1*3 No.*2 See section 4, Clock Pulse Generators, for a typical connection. Note added Note: 5. Does not apply to H8/38104 H8/38104 Group Rev. 6.00 Mar 15, 2005 page xiii of l Item Page Revisions (See Manual for Details) 2.2 Address Space and Memory Map 29 Notes amended Note 1. This area is unavailable to the user. Figure 2.1(6) H8/38002 H8/38002, H8/38102 H8/38102 Memory Map Figure 2.1(7) H8/38002S H8/38002S Memory Map 30 Newly added Figure 2.1(8) 31 H8/38001 H8/38001, H8/38001S H8/38001S, H8/38101 H8/38101 Memory Map Title amended 32 Figure 2.1(9) H8/38000 H8/38000, H8/38000S H8/38000S, H8/38100 H8/38100 Memory Map Title amended 3.2.4 Interrupt Request Register 1 (IRR1) Table amended 80 Bit Bit Name Initial Value R/W Description 7 IRRTA 0 R/W * Timer A Interrupt Request Flag [Setting condition] When the timer A counter value overflows [Clearing condition] When IRRTA = 1, it is cleared by writing 0 3.5.3 Interrupt Request Flag Clearing Method 89, 90 Replaced 3.5.4 Notes on Rewriting Port Mode Registers 90 to 92 Replaced 4.1 Features 93 Description amended Figure 4.1 shows a block diagram of the clock pulse generators of the H8/3802 H8/3802, H8/38004 H8/38004 and H8/38002S H8/38002S Group. Figure 4.1 Block Diagram of Clock Pulse Generators (H8/3802 H8/3802, H8/38004 H8/38004, H8/38002S H8/38002S Group) Title amended Rev. 6.00 Mar 15, 2005 page xiv of l Item Page Revisions (See Manual for Details) 4.3 System Clock Generator 96 Figure amended OSC2 Figure 4.3 Block Diagram of System Clock Generator LPM OSC1 4.3.1 Connecting Crystal Resonator Figure 4.4(2) Typical Connection to Crystal Resonator (H8/38004 H8/38004, H8/38002S H8/38002S, H8/38104 H8/38104 Group) Table 4.1 Crystal Resonator Parameters Description amended Figure 4.4(1) shows a typical method of connecting a crystal oscillator to the H8/3802 H8/3802 Group, and figure 4.4(2) shows a typical method of connecting a crystal oscillator to the H8/38004 H8/38004, H8/38104 H8/38104 and H8/38002S H8/38002S Group. 97 Title amended Table amended Frequency (MHz) RS (max) C0 (max) 4.10 4.193 100 7 pF Rev. 6.00 Mar 15, 2005 page xv of l Item Page Revisions (See Manual for Details) 4.3.2 Connecting Ceramic Resonator 98 Description amended Figure 4.6(1) shows a typical method of connecting a ceramic oscillator to the H8/3802 H8/3802 Group, and figure 4.6(2) shows a typical method of connecting a crystal oscillator to the H8/38004 H8/38004, H8/38002S H8/38002S and H8/38104 H8/38104 Group. Title amended Figure 4.6(2) Typical Connection to Ceramic Resonator (H8/38004 H8/38004, H8/38002S H8/38002S, H8/38104 H8/38104 Group) Figure amended Frequency Manufacturer Prodoct Name C1, C2 Recommendation Value 2.0 MHz Murata Manufacturing Co., CSTCC2M00G53-B0 CSTCC2M00G53-B0 Ltd. CSTCC2M00G56-B0 CSTCC2M00G56-B0 15 pF ±20% 10.0 MHz CSTLS10M0G53-B0 CSTLS10M0G53-B0 15 pF ±20% CSTLS10M0G56-B0 CSTLS10M0G56-B0 47 pF ±20% 16.0 MHz*1 CSTLS16M0X53-B0 CSTLS16M0X53-B0 15 pF ±20% 20.0 MHz*2 CSTLS20M0X53-B0 CSTLS20M0X53-B0 15 pF ±20% 47 pF ±20% Rf = 1 M ±20% Notes: Consult with the crystal resonator manufacturer to determine the circuit constants. 1. This does not apply to the H8/38004 H8/38004 and H8/38002S H8/38002S Group. 2. H8/38104 H8/38104 Group only. 4.4.1 Connecting 32.768-kHz/38.4-kHz Crystal Resonator 100 Figure amended C1 = C2 = 6 to 12.5 pF (typ.) Figure 4.9 Typical Connection to 32.768kHz/38.4-kHz Crystal Resonator Figure 4.10 Equivalent 101 Circuit of 32.768kHz/38.4-kHz Crystal Resonator Figure amended CO = 0.8 pF (typ.) RS = 14 k (typ.) fW = 32.768 kHz/38.4 kHz 4.6.3 Definition of 106, 107 Description amended Oscillation Stabilization Meanwhile, once the system clock has halted, a standby time Standby Time is necessary in order for the CPU and peripheral functions to operate normally. Oscillation stabilization standby time = oscillation stabilization time + standby time 1 = trc + (8 to 16,384 states) * . (1) (to 131,072 states) *2 Notes: 1. H8/3802 H8/3802 Group, H8/38004 H8/38004 and H8/38002S H8/38002S Group 2. H8/38104 H8/38104 Group Rev. 6.00 Mar 15, 2005 page xvi of l Item Page 4.6.4 Notes on Use of 107 Resonator Revisions (See Manual for Details) Description amended resonator characteristics, Depending on the individual the oscillation waveform amplitude may not be sufficiently large immediately after the oscillation stabilization standby time, making the oscillation waveform susceptible to influence by fluctuations in the power supply potential. Note: * This figure applies to the H8/3802 H8/3802, H8/38004 H8/38004 and H8/38002S H8/38002S Groups. The number of states on the H8/38104 H8/38104 Group is 8,192 or more. 5.1.1 System Control Register 1 (SYSCR1) 111 Title amended 117 Note amended Table 5.1(1) Operating Frequency and Waiting Time (H8/3802 H8/3802 Group, H8/38004 H8/38004 Group, H8/38002S H8/38002S Group) 5.2 Mode Transitions and States of LSI Figure 5.1 Mode Transition Diagram 120 Table 5.3 Internal State in Each Operating Mode Note: A transition between different modes cannot be made to occur simply because an interrupt request is generated. Make sure that interrupts are enabled. Notes amended Notes: 8. On the H8/38104 H8/38104 Group, operates when w/32 is selected as the internal clock or the on-chip oscillator is selected; otherwise stops and stands by. On the H8/38004 H8/38004, H8/38002S H8/38002S Group, operates when w/32 is selected as the internal clock; otherwise stops and stands by. 9. On the H8/38104 H8/38104 Group, operates when w/32 is selected as the internal clock or the on-chip oscillator is selected; otherwise stops and stands by. On the H8/38004 H8/38004, H8/38002S H8/38002S Group, stops and stands by. 10. On the H8/38104 H8/38104 Group, operates only when the onchip oscillator is selected; other-wise stops and stands by. On the H8/38004 H8/38004, H8/38002S H8/38002S Group, stops and stands by. Rev. 6.00 Mar 15, 2005 page xvii of l Item Page Revisions (See Manual for Details) Section 6 ROM 131 Description amended The H8/3802 H8/3802 has 16 kbytes of the on-chip mask ROM, the H8/3801 H8/3801 has 12 kbytes, and the H8/3800 H8/3800 has 8 kbytes. The H8/38004 H8/38004 and H8/38104 H8/38104 have 32 kbytes of the on-chip mask ROM, the H8/38003 H8/38003 and H8/38103 H8/38103 have 24 kbytes, the H8/38002 H8/38002, H8/38002S H8/38002S and H8/38102 H8/38102 have 16 kbytes, the H8/38001 H8/38001, H8/38001S H8/38001S and H8/38101 H8/38101 have 12 kbytes, and the H8/38000 H8/38000, H8/38000S H8/38000S and H8/38100 H8/38100 have 8 kbytes. The ROM is connected to the CPU by a 16-bit data bus, allowing highspeed two-state access for both byte data and word data. 6.7.1 Boot Mode 151 Product Group 19,200 bps 16 to 20 MHz 9,600 bps 8 to 20 MHz 4,800 bps 4 to 20 MHz 2,400 bps 2 to 20 MHz 1,200 bps 175 Host Bit Rate H8/38104F H8/38104F Group Table 6.7 Oscillation Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible (fOSC) Section 7 RAM Table amended Oscillation Frequency Range of LSI (fOSC) 2 to 20 MHz Table amended Product Classification 178 Table 8.1 Port Functions H8/38002S H8/38002S 512 bytes H'FD80 to H'FF7F 512 bytes H'FD80 to H'FF7F H8/38000S H8/38000S Section 8 I/O Ports RAM Address H8/38001S H8/38001S Mask ROM version RAM Size 512 bytes H'FD80 to H'FF7F Notes amended Notes: 2. Implemented on H8/3802 H8/3802 Group only. Standard highvoltage port on H8/38104 H8/38104 Group, H8/38002S H8/38002S Group and H8/38004 H8/38004 Group. 4. Implemented on H8/3802 H8/3802 Group only. Input port on H8/38004 H8/38004 Group, H8/38002S H8/38002S Group and H8/38104 H8/38104 Group. 8.1.5 Port Mode Register 2 (PMR2) 183 Table amended Bit Bit Name Initial Value R/W Description 2 WDCKS 0 R/W Watchdog Timer Source Clock Select This bit selects the input clock for the watchdog timer. Note that this bit is implemented differently on the H8/38004 H8/38004, H8/38002S H8/38002S Group and on H8/38104 H8/38104 Group. H8/38004 H8/38004, H8/38002S H8/38002S Group: 0: /8,192 1: w/32 H8/38104 H8/38104 Group: 0: Clock specified by timer mode register W (TMW) 1: w/32 Note: This bit is reserved and only 0 can be written in the H8/3802 H8/3802 Group. Rev. 6.00 Mar 15, 2005 page xviii of l Item Page Revisions (See Manual for Details) 8.2.3 Serial Port Control Register (SPCR) 188 Table amended Bit Description 3 TXD32 TXD32 Pin Output Data Inversion Switch This bit selects whether or not the logic level of the TXD32 TXD32 pin output data is inverted. 0: TXD32 TXD32 output data is not inverted 1: TXD32 TXD32 output data is inverted 2 RXD32 RXD32 Pin Input Data Inversion Switch This bit selects whether or not the logic level of the RXD32 RXD32 pin input data is inverted. 0: RXD32 RXD32 input data is not inverted 1: RXD32 RXD32 input data is inverted 8.7 Port 9 202 Description amended Port 9 is a dedicated current port for NMOS output that also functions as a PWM output pin. 8.7.2 Port Mode Register 9 (PMR9) 204 Table amended Bit Bit Name Initial Value R/W Description 3 PIOFF 0 R/W P92 to P90 Step-Up Circuit Control This bit turns on and off the P92 to P90 step-up circuit. 0: Step-up circuit of large-current port is turned on 1: Step-up circuit of large-current port is turned off Note: This bit is valid in the H8/3802 H8/3802 Group only. It functions as a readable/writable reserved bit in versions other than the H8/3802 H8/3802 Group. 8.7.3 Pin Functions 205 · P93/Vref Description amended As shown below, switching is performed based on the setting of VREFSEL in LVDSR. Note that this function is implemented on the H8/38104 H8/38104 Group only. The Vref pin is the input pin for the LVD's external reference voltage. VREFSEL Pin Function 8.9.2 Port Mode Register B (PMRB) 209 0 1 P93 output pin Vref input pin Note deleted Rev. 6.00 Mar 15, 2005 page xix of l Item Page Revisions (See Manual for Details) 9.1 Overview 213 Description amended The H8/3802 H8/3802 Group provides three timers: timer A, timer F, and asynchronous event counter. The H8/38004 H8/38004 Group, H8/38002S H8/38002S Group and H8/38104 H8/38104 Group provide four timers: timer A, timer F, asynchronous event counter, and watchdog timer. Table 9.1 Timer Functions 214 Table and note amended Name Functions Watchdog timer* · Internal Clock /8192, W /32 Generates a reset signal by overflow of 8-bit counter /64 to /8192 w/32 On-chip oscillator Event Input Waveform Pin Output Pin - - Remarks H8/38004 H8/38004, H8/38002S H8/38002S Group H8/38104 H8/38104 Group Note: * The watchdog timer functions differently on the H8/38004 H8/38004, H8/38002S H8/38002S and H8/38104 H8/38104 Group. See section 9.5, Watchdog Timer, for details. 9.2.3 Operation 218 Description amended Clock Time Base Operation: When bit TMA3 in TMA is set to 1, the timer A functions as a clock-timer base by counting clock signals output by prescaler W. The overflow period of timer A is set by bits TMA1 and TMA0 in TMA. A choice of four periods is available. In clock time base operation (TMA3 = 1), setting bit TMA2 to 1 clears both TCA and prescaler W to H'00. 9.3.4 CPU Interface 225 Description amended When performing TCF read/write access or OCRF write access in 16-bit mode, data will not be transferred correctly if only the upper byte or only the lower byte is accessed. Access must be performed for all 16 bits (using two consecutive byte-size MOV instructions), and the upper byte must be accessed before the lower byte. 9.3.5 Operation Timer F Operation · Operation in 16-bit timer mode 228 Description amended When CKSH2 is cleared to 0 in timer control register F (TCRF), timer F operates as a 16-bit timer. The timer F operating clock can be selected from three internal clocks output by prescaler S by means of bits CKSL2 to CKSL0 in TCRF. Rev. 6.00 Mar 15, 2005 page xx of l Item Page Revisions (See Manual for Details) 9.4.6 Usage Notes 248, 249 Description amended 2. The maximum clock frequency that may be input to the AEVH and AEVL pins is 16 MHz*1. Furthermore, the clock high width and low width should be half or more the OSC clock cycle time. The duty ratio does not matter as long as the high width and low width satisfy the minimum requirement. Maximum Clock Frequency Input to AEVH/AEVL Pin Mode Watch, subactive, subsleep, standby (W/2) 1000 kHz W = 32.768 kHz or 38.4 kHz* (W/4) 500 kHz 2 (W/8) 250 kHz Notes: 1. Up to 10 MHz in the H8/38004 H8/38004, H8/38002S H8/38002S Group. 2. Does not apply to H8/38104 H8/38104 Group. 9.5 Watchdog Timer 250 Description amended However, as shown in watchdog timer block diagrams figure 9.12 (1) and figure 9.12 (2), the implementation differs in the H8/38004 H8/38004, H8/38002S H8/38002S Group and the H8/38104 H8/38104 Group. 9.5.1 Features Description amended · Selectable from two counter input clocks (H8/38004 H8/38004, H8/38002S H8/38002S Group). Figure 9.12(1) Block Diagram of Watchdog Timer (H8/38004 H8/38004, H8/38002S H8/38002S Group) 9.5.2 Register Descriptions Title amended 253 Notes: 2.Initial value 0 on H8/38004 H8/38004, H8/38002S H8/38002S Group and 1 on H8/38104 H8/38104 Group. Timer Control/Status Register W (TCSRW) 9.5.3 Operation Notes amended 3.On reset, cleared to 0 on H8/38004 H8/38004, H8/38002S H8/38002S Group and set to 1 on H8/38104 H8/38104 Group. 254 Description amended The input clock is selected by the WDCKS bit in the port mode register 2 (PMR2)*: On the H8/38004 H8/38004, H8/38002S H8/38002S Group, /8192 is selected when the WDCKS bit is cleared to 0, and w/32 when set to 1. Rev. 6.00 Mar 15, 2005 page xxi of l Item Page Revisions (See Manual for Details) 9.5.4 Operating States 256 of Watchdog Timer Description amended Table 9.8(1) Operating States of Watchdog Timer (H8/38004 H8/38004, H8/38002S H8/38002S Group) Title amended 10.3.8 Bit Rate Register (BRR) 269 Tables 9.8(1) and 9.8(2) summarize the operating states of the watchdog timer for the H8/38004 H8/38004, H8/38002S H8/38002S Group and H8/38104 H8/38104 Group, respectively. Description amended The values are shown in table 10.5 N= Table 10.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) 271 B: N: : n: 1 Bit rate (bit/s) BRR setting for baud rate generator (0 N 255) Operating frequency (Hz) Baud rate generator input clock number (n = 0, 2, or 3) (The relation between n and the clock is shown in table 10.3.) Table amended 10 MHz Bit Rate (bit/s) n N Error (%) 110 3 43 0.88 150 3 32 1.36 200 3 23 1.73 250 3 19 2.34 300 3 15 1.73 600 3 7 1.73 1200 3 3 1.73 2400 3 1 1.73 4800 3 0 1.73 9600 2 1 1.73 19200 2 0 1.73 31250 0 9 0 38400 0 7 1.73 Rev. 6.00 Mar 15, 2005 page xxii of l 32 · 2 2n · B . B (bit rate obtained from n, N, ) R (bit rate in left-hand column in table 10.2) R (bit rate in left-hand column in table 10.2) Error (%) = Legend: · 100 Item Page Revisions (See Manual for Details) 10.3.8 Bit Rate Register (BRR) 272 Table amended Setting (MHz) Maximum Bit Rate (bit/s) n N 0.0384* 0.0192 600 0 0 2 1 31250 0 0 2.4576 1.2288 38400 0 0 2 62500 0 0 10 5 156250 0 0 16 8 250000 0 0 20 Table 10.5 BRR 273 Settings for Various Bit Rates (Clocked Synchronous Mode) (2) OSC (MHz) 4 Table 10.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) 10 312500 0 0 Table amended 10 MHz Bit Rate (bit/s) n N Error (%) 200 0 12499 0 250 2 624 0 300 0 8332 0 500 0 4999 0 1k 0 2499 0 2.5k 0 999 0 5k 0 499 0 10k 0 249 0 25k 0 99 0 50k 0 49 0 100k 0 24 0 250k 0 9 0 500k 0 4 0 1M - - - Note added Note: The value set in BRR is given by the following formula: N= B: N: : n: 8 · 22n · B 1 Bit rate (bit/s) BRR setting for baud rate generator (0 N 255) Operating frequency (Hz) Baud rate generator input clock number (n = 0, 2, or 3) (The relation between n and the clock is shown in table 10.6.) Rev. 6.00 Mar 15, 2005 page xxiii of l Item Page Revisions (See Manual for Details) 10.3.9 Serial Port Control Register (SPCR) 274 Table amended Bit Description 3 TXD32 TXD32 Pin Output Data Inversion Switch This bit selects whether or not the logic level of the TXD32 TXD32 pin output data is inverted. 0: TXD32 TXD32 output data is not inverted 1: TXD32 TXD32 output data is inverted 2 RXD32 RXD32 Pin Input Data Inversion Switch This bit selects whether or not the logic level of the RXD32 RXD32 pin input data is inverted. 0: RXD32 RXD32 input data is not inverted 1: RXD32 RXD32 input data is inverted 10.5.4 Serial Data Reception (Clocked Synchronous Mode) 291 Figure amended Serial clock Serial data Figure 10.12 Example of SCI3 Reception Operation in Clocked Synchronous Mode Bit 7 Bit 0 Bit 7 Bit 0 1 frame Bit 1 Bit 6 Bit 7 1 frame RDRF OER LSI operation RXI interrupt request generated User processing 10.7 Interrupts 301 RDRF flag cleared to 0 RXI interrupt request generated RDR data read RDR data has not been read (RDRF = 1) ERI interrupt request generated by overrun error Overrun error processing Table and description amended Interrupt Requests Abbreviation Interrupt Sources Receive Data Full RXI Setting RDRF in SSR RIE Transmit Data Empty Table 10.11 SCI3 Interrupt Requests Enable Bit TXI Setting TDRE in SSR TIE Transmission End TEI Setting TEND in SSR TEIE Receive Error ERI Setting OER, FER, or PER in SSR RIE Each interrupt request can be enabled or disabled by means of bits TIE, RIE and TEIE in SCR3. Table 10.12 Transmit/Receive Interrupts 302 10.8.10 Oscillator Use 307 with Serial Communication Interface 3 in Asynchronous Mode (H8/38104 H8/38104 Group Only) Table amended Flag and Enable Bit Title and description amended When implementing serial communication interface 3 in asynchronous mode on the H8/38104 H8/38104 Group, the system clock oscillator must be used. The on-chip oscillator should not be used in this case. Rev. 6.00 Mar 15, 2005 page xxiv of l Item Page Revisions (See Manual for Details) Section 11 10-Bit PWM 309 Description amended Figure 11.1(1) shows a block diagram of the 10-bit PWM of the H8/3802 H8/3802 Group, H8/38004 H8/38004 Group and H8/38002S H8/38002S Group. 11.1 Features Description amended · On the H8/38104 H8/38104 Group it is possible to select between two types of PWM output: pulse-division 10-bit PWM and event counter PWM (PWM incorporating AEC). (The H8/3802 H8/3802 Group, H8/38004 H8/38004 Group and H8/38002S H8/38002S Group can only produce 10-bit PWM output.) Refer to section 9.4, Asynchronous Event Counter, for information on event counter PWM. 310 Figure 11.1(1) Block Diagram of 10-Bit PWM Title amended (H8/3802 H8/3802 Group, H8/38004 H8/38004 Group, H8/38002S H8/38002S Group) 11.2 Input/Output Pins 311 Note amended Table 11.1 Pin Configuration Note: * The event counter PWM output pin is valid on the H8/38104 H8/38104 Group only. 11.3.1 PWM Control Register (PWCR) 312 11.4.1 Operation 315 Description amended On the H8/3802 H8/3802 Group, H8/38004 H8/38004 Group and H8/38002S H8/38002S Group, PWCR selects the conversion period. Description amended 1. Set the PWM2 and/or PWM1 bits in port mode register 9 (PMR9) to 1 to set the P91/PWM2 P91/PWM2 pin or P90/PWM1 P90/PWM1 pin, or both, to function as PWM output pins. 12.1 Features 317 Description amended · Conversion time: at least 12.4 µs per channel ( = 5 MHz operation)/6.2 µs ( = 10 MHz operation)* 12.7.1 Permissible Signal Source Impedance 327 12.7.3 Additional Usage Notes 328 Description amended As a countermeasure, a large capacitance can be provided externally to the analog input pin. This will cause the actual input resistance to comprise only the internal input resistance of 10 k , allowing the signal source impedance to be ignored. This countermeasure has the disadvantage of creating a low-pass filter from the signal source impedance and capacitance, with the result that it may not be possible to follow analog signals having a large differential coefficient (e.g., 5 mV/µs or greater) (see figure 12.7). . Title amended Rev. 6.00 Mar 15, 2005 page xxv of l Item Page Revisions (See Manual for Details) 13.1 Features 329 Description amended · On-chip power supply split-resistance Removal of split-resistance can be controlled in software. Note that this capability is implemented in the H8/38104 H8/38104 Group only. Figure 13.1(1) Block Diagram of LCD Controller/Driver (H8/3802 H8/3802 Group, H8/38004 H8/38004 Group, H8/38002S H8/38002S Group) 330 Title amended 13.3.3 LCD Control Register 2 (LCR2) 338 Note amended 17.1 Absolute Maximum Ratings of H8/3802 H8/3802 Group (ZTAT Version, Mask ROM Version) 377 Title amended 17.2 Electrical Characteristics of H8/3802 H8/3802 Group (ZTAT Version, Mask ROM Version) 378 Title amended 394 17.3 Absolute Maximum Ratings of H8/38004 H8/38004 Group (F-ZTAT Version, Mask ROM Version), H8/38002S H8/38002S Group (Mask ROM Version) Title amended 395 17.4 Electrical Characteristics of H8/38004 H8/38004 Group (F-ZTAT Version, Mask ROM Version), H8/38002S H8/38002S Group (Mask ROM Version) Title amended Note: * Applies to H8/38104 H8/38104 Group only. On the H8/3802 H8/3802 Group, H8/38004 H8/38004 Group or H8/38002S H8/38002S Group, these bits are reserved like bit 4. Rev. 6.00 Mar 15, 2005 page xxvi of l Item Page Revisions (See Manual for Details) 17.4.1 Power Supply Voltage and Operating Ranges 395 Figure amended 10.0 fosc(MHz) Power Supply Voltage and Oscillation Frequency Range (FZTAT Version) 4.0 2.0 2.2 2.7 3.6 Vcc (V) · Active (high-speed) mode · Sleep (high-speed) mode 4 MHz specification 10 MHz specification 17.5 Absolute 416 Maximum Ratings of H8/38104 H8/38104 Group (F-ZTAT Version, Mask ROM Version) Title amended 17.6 Electrical 417 Characteristics of H8/38104 H8/38104 Group (F-ZTAT Version, Mask ROM Version) Title amended 17.6.1 Power Supply Voltage and Operating Ranges Figure amended 20.0 fosc (MHz) Power Supply Voltage and Oscillation Frequency Range (System Clock Oscillator Selected) 2.0 2.7 5.5 VCC (V) · Active (high-speed) mode · Sleep (high-speed) mode Rev. 6.00 Mar 15, 2005 page xxvii of l Item Page Revisions (See Manual for Details) 17.6.1 Power Supply Voltage and Operating Ranges 418 Figure amended 10.0 (MHz) Power Supply Voltage and Operating Frequency Range (System Clock Oscillator Selected) 1.0 2.7 5.5 VCC (V) · Active (high-speed) mode · Sleep (high-speed) mode (except CPU) (kHz) 1250 15.625 2.7 5.5 VCC (V) · Active (medium-speed) mode · Sleep (medium-speed) mode (except A/D converter) 420 Figure amended 10.0 (MHz) Analog Power Supply Voltage and A/D Converter Operating Range (System Clock Oscillator Selected) 1.0 2.7 5.5 AVCC (V) · Active (high-speed) mode · Sleep (high-speed) mode Rev. 6.00 Mar 15, 2005 page xxviii of l Item Page Revisions (See Manual for Details) 17.6.2 DC Characteristics 424 Table amended Values Item Table 17.15 DC Characteristics (4) Symbol Applicable Pins Min Typ Max Unit Notes VCC Active IOPE1 mode current consumption Test Condition Active (high-speed) mode VCC = 5 V, fOSC = 2 MHz - 0.8 - mA *1 *3 *4 Approx. max. value = 1.1 · Typ. - 1.5 *2 *3 *4 - Approx. max. value = 1.1 · Typ. Table 17.15 DC Characteristics (5) 428 Table amended Values Item Symbol Applicable Pins 17.6.3 AC Characteristics 430 Typ Max Unit Port 9 VCC = 4.0 V to 5.5 V - - 15.0 mA Other than above Allowable IOL output low current (per pin) Test Condition - 5.0 - Notes Table amended Values Item Symbol Applicable Pins System clock oscillation frequency fOSC OSC1, OSC2 OSC clock ( cycle time Table 17.16 Control Signal Timing Min tOSC OSC) Test Condition Min Typ Max MHz 2.0 OSC1, OSC2 On-chip oscillator selected - 20.0 0.7 - 2.0 50.0 On-chip oscillator selected Reference Figure Unit - 500 500 - 1429 *2 ns Figure 17.1 External clock high tCPH width 20 - - ns Figure 17.1 External clock low width tCPL OSC1 20 - - ns Figure 17.1 External clock rise time tCPr OSC1 - - 5 ns Figure 17.1 External clock fall time 431 Table 17.17 Serial Interface (SCI3) Timing OSC1 tCPf OSC1 - - 5 ns Figure 17.1 Table amended Reference Figure tRXS 150.0 - - ns Figure 17.5 tRXH 150.0 - - ns Figure 17.5 Receive data hold time (clocked synchronous) 432 17.6.9 Watchdog Timer Characteristics Table 17.27 Watchdog Timer Characteristics Table amended Item Table 17.18 A/D Converter Characteristics Symbol Applicable Test Pins Condition Values Min Typ Max - 124 Reference Figure Unit 6.2 Conversion time 440 Values Typ Max Unit Symbol Receive data setup time (clocked synchronous) 17.6.4 A/D Converter Characteristics Test Condition Min Item µs Table amended Item Symbol On-chip oscillator overflow time tOVF Applicable Pins Rated Values Test Condition Min Typ Max Unit Note VCC = 5 V 0.2 0.4 - s * Rev. 6.00 Mar 15, 2005 page xxix of l Item Page Revisions (See Manual for Details) A.1 Instruction List 455 Notes amended Table A.1 Instruction Set B.7 Port 9 Block Diagrams (4) The number of states required for execution is 4n + 9 (n = value of R4L). In the H8/38004 H8/38004 Group, H8/38002S H8/38002S Group and H8/38104 H8/38104 Group, the number of states required for execution is 4n + 8. 478 Newly added 481 Newly added Figure B.9(c) Port B Block Diagram (Pin PB1, H8/38104 H8/38104 Group Only) 482 Newly added Appendix D Product Code Lineup 487 Newly added Appendix E Package Dimensions 490 Description amended Figure E.3 Package Dimensions (FP-64K FP-64K) 492 Figure B.7(c) Port 9 Block Diagram (Pin P93, H8/38104 H8/38104 Group Only) B.9 Port B Block Diagrams Figure B.9(b) Port B Block Diagram (Pin PB0, H8/38104 H8/38104 Group Only) Table D.3 Product Code Lineup of H8/38002S H8/38002S Group The package dimensions are shown in figure E.1 (FP-64A FP-64A), figure E.2 (FP-64E FP-64E), figure E.3 (FP-64K FP-64K), and figure E.4 (DP64S DP64S). Newly added Rev. 6.00 Mar 15, 2005 page xxx of l Contents Section 1 Overview . 1.1 1.2 1.3 1.4 1 Features. 1 Internal Block Diagram. 4 Pin Arrangement . 7 Pin Functions . 19 Section 2 CPU . 23 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 Features. Address Space and Memory Map . Register Configuration. 2.3.1 General Registers. 2.3.2 Program Counter (PC) . 2.3.3 Condition Code Register (CCR) . 2.3.4 Initial Register Values . Data Formats. 2.4.1 General Register Data Formats. 2.4.2 Memory Data Formats . Instruction Set. 2.5.1 Data Transfer Instructions . 2.5.2 Arithmetic Operations Instructions. 2.5.3 Logic Operations Instructions. 2.5.4 Shift Instructions. 2.5.5 Bit Manipulation Instructions . 2.5.6 Branch Instructions. 2.5.7 System Control Instructions. 2.5.8 Block Data Transfer Instructions . Addressing Modes and Effective Address . 2.6.1 Addressing Modes . 2.6.2 Effective Address Calculation . Basic Bus Cycle . 2.7.1 Access to On-Chip Memory (RAM, ROM). 2.7.2 On-Chip Peripheral Modules . CPU States . Usage Notes . 2.9.1 Notes on Data Access to Empty Areas . 2.9.2 Access to Internal I/O Registers . 2.9.3 EEPMOV Instruction. 2.9.4 Bit Manipulation Instructions . 23 24 33 34 34 35 36 36 36 38 39 41 43 44 44 46 49 51 52 53 53 56 60 60 61 63 64 64 64 65 65 Rev. 6.00 Mar 15, 2005 page xxxi of l Section 3 Exception Handling . 73 3.1 3.2 3.3 3.4 3.5 Exception Sources and Vector Address . Register Descriptions. 3.2.1 Interrupt Edge Select Register (IEGR) . 3.2.2 Interrupt Enable Register 1 (IENR1) . 3.2.3 Interrupt Enable Register 2 (IENR2) . 3.2.4 Interrupt Request Register 1 (IRR1) . 3.2.5 Interrupt Request Register 2 (IRR2) . 3.2.6 Wakeup Interrupt Request Register (IWPR) . 3.2.7 Wakeup Edge Select Register (WEGR) . Reset Exception Handling. Interrupt Exception Handling . 3.4.1 External Interrupts . 3.4.2 Internal Interrupts . 3.4.3 Interrupt Handling Sequence . 3.4.4 Interrupt Response Time. Usage Notes . 3.5.1 Interrupts after Reset. 3.5.2 Notes on Stack Area Use . 3.5.3 Interrupt Request Flag Clearing Method . 3.5.4 Notes on Rewriting Port Mode Registers . 75 77 77 78 79 80 81 82 83 83 84 84 85 86 87 89 89 89 89 90 Section 4 Clock Pulse Generators. 93 4.1 4.2 4.3 4.4 4.5 4.6 Features. Register Description . System Clock Generator . 4.3.1 Connecting Crystal Resonator . 4.3.2 Connecting Ceramic Resonator . 4.3.3 External Clock Input Method . 4.3.4 On-Chip Oscillator Selection Method (H8/38104 H8/38104 Group Only). Subclock Generator . 4.4.1 Connecting 32.768-kHz/38.4-kHz Crystal Resonator . 4.4.2 Pin Connection when Not Using Subclock. 4.4.3 External Clock Input. Prescalers . 4.5.1 Prescaler S . 4.5.2 Prescaler W. Usage Notes . 4.6.1 Note on Resonators. 4.6.2 Notes on Board Design . 4.6.3 Definition of Oscillation Stabilization Standby Time. 4.6.4 Notes on Use of Resonator . Rev. 6.00 Mar 15, 2005 page xxxii of l 93 95 96 96 98 99 99 100 100 101 101 102 102 102 102 102 104 105 107 4.6.5 Notes on H8/38104 H8/38104 Group. 108 Section 5 Power-Down Modes . 109 5.1 5.2 5.3 5.4 5.5 Register Descriptions. 5.1.1 System Control Register 1 (SYSCR1) . 5.1.2 System Control Register 2 (SYSCR2) . 5.1.3 Clock Halt Registers 1 and 2 (CKSTPR1 and CKSTPR2) . Mode Transitions and States of LSI. 5.2.1 Sleep Mode . 5.2.2 Standby Mode. 5.2.3 Watch Mode. 5.2.4 Subsleep Mode. 5.2.5 Subactive Mode . 5.2.6 Active (Medium-Speed) Mode . Direct Transition . 5.3.1 Direct Transition from Active (High-Speed) Mode to Active (Medium-Speed) Mode. 5.3.2 Direct Transition from Active (Medium-Speed) Mode to Active (High-Speed) Mode . 5.3.3 Direct Transition from Subactive Mode to Active (High-Speed) Mode. 5.3.4 Direct Transition from Subactive Mode to Active (Medium-Speed) Mode . 5.3.5 Notes on External Input Signal Changes before/after Direct Transition. Module Standby Function. Usage Notes . 5.5.1 Standby Mode Transition and Pin States . 5.5.2 Notes on External Input Signal Changes before/after Standby Mode. 110 110 113 114 116 120 121 121 122 122 123 124 125 126 126 127 127 128 128 128 128 Section 6 ROM. 131 6.1 6.2 6.3 6.4 6.5 6.6 Block Diagram. H8/3802 H8/3802 PROM Mode. 6.2.1 Setting to PROM Mode . 6.2.2 Socket Adapter Pin Arrangement and Memory Map. H8/3802 H8/3802 Programming. 6.3.1 Writing and Verifying. 6.3.2 Programming Precautions. Reliability of Programmed Data . Overview of Flash Memory . 6.5.1 Features. 6.5.2 Block Diagram. 6.5.3 Block Configuration . Register Descriptions. 6.6.1 Flash Memory Control Register 1 (FLMCR1). 131 132 132 132 135 135 139 140 141 141 142 143 144 145 Rev. 6.00 Mar 15, 2005 page xxxiii of l 6.6.2 Flash Memory Control Register 2 (FLMCR2) . 6.6.3 Erase Block Register (EBR) . 6.6.4 Flash Memory Power Control Register (FLPWCR). 6.6.5 Flash Memory Enable Register (FENR). 6.7 On-Board Programming Modes. 6.7.1 Boot Mode . 6.7.2 Programming/Erasing in User Program Mode. 6.7.3 Notes on On-Board Programming . 6.8 Flash Memory Programming/Erasing. 6.8.1 Program/Program-Verify. 6.8.2 Erase/Erase-Verify. 6.8.3 Interrupt Handling when Programming/Erasing Flash Memory. 6.9 Program/Erase Protection . 6.9.1 Hardware Protection . 6.9.2 Software Protection . 6.9.3 Error Protection . 6.10 Programmer Mode . 6.10.1 Socket Adapter . 6.10.2 Programmer Mode Commands. 6.10.3 Memory Read Mode . 6.10.4 Auto-Program Mode. 6.10.5 Auto-Erase Mode. 6.10.6 Status Read Mode . 6.10.7 Status Polling . 6.10.8 Programmer Mode Transition Time . 6.10.9 Notes on Memory Programming . 6.11 Power-Down States for Flash Memory. 146 146 147 147 148 148 151 152 153 153 157 157 159 159 159 159 160 160 160 164 167 169 170 172 173 173 174 Section 7 RAM. 175 7.1 Block Diagram. 176 Section 8 I/O Ports . 177 8.1 8.2 Port 3. 8.1.1 Port Data Register 3 (PDR3) . 8.1.2 Port Control Register 3 (PCR3) . 8.1.3 Port Pull-Up Control Register 3 (PUCR3). 8.1.4 Port Mode Register 3 (PMR3) . 8.1.5 Port Mode Register 2 (PMR2) . 8.1.6 Pin Functions . 8.1.7 Input Pull-Up MOS. Port 4. 8.2.1 Port Data Register 4 (PDR4) . Rev. 6.00 Mar 15, 2005 page xxxiv of l 179 180 180 181 182 183 184 185 186 186 8.2.2 Port Control Register 4 (PCR4) . 8.2.3 Serial Port Control Register (SPCR). 8.2.4 Pin Functions . 8.3 Port 5. 8.3.1 Port Data Register 5 (PDR5) . 8.3.2 Port Control Register 5 (PCR5) . 8.3.3 Port Pull-Up Control Register 5 (PUCR5). 8.3.4 Port Mode Register 5 (PMR5) . 8.3.5 Pin Functions . 8.3.6 Input Pull-Up MOS. 8.4 Port 6. 8.4.1 Port Data Register 6 (PDR6) . 8.4.2 Port Control Register 6 (PCR6) . 8.4.3 Port Pull-Up Control Register 6 (PUCR6). 8.4.4 Pin Functions . 8.4.5 Input Pull-Up MOS. 8.5 Port 7. 8.5.1 Port Data Register 7 (PDR7) . 8.5.2 Port Control Register 7 (PCR7) . 8.5.3 Pin Functions . 8.6 Port 8. 8.6.1 Port Data Register 8 (PDR8) . 8.6.2 Port Control Register 8 (PCR8) . 8.6.3 Pin Functions . 8.7 Port 9. 8.7.1 Port Data Register 9 (PDR9) . 8.7.2 Port Mode Register 9 (PMR9) . 8.7.3 Pin Functions . 8.8 Port A. 8.8.1 Port Data Register A (PDRA). 8.8.2 Port Control Register A (PCRA) . 8.8.3 Pin Functions . 8.9 Port B . 8.9.1 Port Data Register B (PDRB) . 8.9.2 Port Mode Register B (PMRB). 8.9.3 Pin Functions . 8.10 Usage Notes . 8.10.1 How to Handle Unused Pin . 187 187 189 190 191 191 192 192 193 194 194 195 195 196 196 197 198 198 199 199 200 201 201 202 202 203 204 204 205 206 206 207 208 209 209 210 211 211 Section 9 Timers . 213 9.1 9.2 Overview. 213 Timer A. 215 Rev. 6.00 Mar 15, 2005 page xxxv of l 9.3 9.4 9.5 9.2.1 Features. 9.2.2 Register Descriptions. 9.2.3 Operation . 9.2.4 Timer A Operating States . Timer F . 9.3.1 Features. 9.3.2 Input/Output Pins. 9.3.3 Register Descriptions. 9.3.4 CPU Interface . 9.3.5 Operation . 9.3.6 Timer F Operating States. 9.3.7 Usage Notes. Asynchronous Event Counter (AEC). 9.4.1 Features. 9.4.2 Input/Output Pins. 9.4.3 Register Descriptions. 9.4.4 Operation . 9.4.5 Operating States of Asynchronous Event Counter . 9.4.6 Usage Notes. Watchdog Timer . 9.5.1 Features. 9.5.2 Register Descriptions. 9.5.3 Operation . 9.5.4 Operating States of Watchdog Timer . 215 216 218 218 219 219 221 221 225 227 230 230 234 234 236 236 243 248 248 250 250 251 254 256 Section 10 Serial Communication Interface 3 (SCI3) . 257 10.1 Features. 257 10.2 Input/Output Pins. 259 10.3 Register Descriptions. 259 10.3.1 Receive Shift Register (RSR) . 259 10.3.2 Receive Data Register (RDR). 260 10.3.3 Transmit Shift Register (TSR). 260 10.3.4 Transmit Data Register (TDR) . 260 10.3.5 Serial Mode Register (SMR) . 261 10.3.6 Serial Control Register 3 (SCR3) . 264 10.3.7 Serial Status Register (SSR) . 266 10.3.8 Bit Rate Register (BRR) . 269 10.3.9 Serial Port Control Register (SPCR). 274 10.4 Operation in Asynchronous Mode . 275 10.4.1 Clock. 276 10.4.2 SCI3 Initialization. 280 10.4.3 Data Transmission . 281 Rev. 6.00 Mar 15, 2005 page xxxvi of l 10.4.4 Serial Data Reception . 10.5 Operation in Clocked Synchronous Mode . 10.5.1 Clock. 10.5.2 SCI3 Initialization. 10.5.3 Serial Data Transmission . 10.5.4 Serial Data Reception (Clocked Synchronous Mode) . 10.5.5 Simultaneous Serial Data Transmission and Reception. 10.6 Multiprocessor Communication Function . 10.6.1 Multiprocessor Serial Data Transmission . 10.6.2 Multiprocessor Serial Data Reception . 10.7 Interrupts. 10.8 Usage Notes . 10.8.1 Break Detection and Processing . 10.8.2 Mark State and Break Sending. 10.8.3 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) . 10.8.4 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode . 10.8.5 Note on Switching SCK32 SCK32 Function. 10.8.6 Relation between Writing to TDR and Bit TDRE . 10.8.7 Relation between RDR Reading and bit RDRF. 10.8.8 Transmit and Receive Operations when Making State Transition. 10.8.9 Setting in Subactive or Subsleep Mode . 10.8.10 Oscillator Use with Serial Communications Interface 3 (H8/38104 H8/38104 Group only) . 283 287 287 287 288 291 293 295 297 298 301 303 303 303 304 304 305 306 306 307 307 307 Section 11 10-Bit PWM . 309 11.1 Features. 309 11.2 Input/Output Pins. 311 11.3 Register Descriptions. 312 11.3.1 PWM Control Register (PWCR) . 312 11.3.2 PWM Data Registers U and L (PWDRU, PWDRL). 314 11.4 Operation . 315 11.4.1 Operation . 315 11.4.2 PWM Operating States . 316 Section 12 A/D Converter . 317 12.1 Features. 317 12.2 Input/Output Pins. 319 12.3 Register Descriptions. 319 12.3.1 A/D Result Registers H and L (ADRRH and ADRRL). 319 12.3.2 A/D Mode Register (AMR) . 320 Rev. 6.00 Mar 15, 2005 page xxxvii of l 12.3.3 A/D Start Register (ADSR) . 12.4 Operation . 12.4.1 A/D Conversion . 12.4.2 Operating States of A/D Converter. 12.5 Example of Use. 12.6 A/D Conversion Accuracy Definitions . 12.7 Usage Notes . 12.7.1 Permissible Signal Source Impedance . 12.7.2 Influences on Absolute Accuracy . 12.7.3 Additional Usage Notes. 321 321 321 322 322 325 327 327 327 327 Section 13 LCD Controller/Driver . 329 13.1 Features. 329 13.2 Input/Output Pins. 332 13.3 Register Descriptions. 333 13.3.1 LCD Port Control Register (LPCR). 333 13.3.2 LCD Control Register (LCR) . 336 13.3.3 LCD Control Register 2 (LCR2) . 338 13.4 Operation . 339 13.4.1 Settings up to LCD Display . 339 13.4.2 Relationship between LCD RAM and Display. 341 13.4.3 Operation in Power-Down Modes . 346 13.4.4 Boosting LCD Drive Power Supply. 347 Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38104 H8/38104 Group Only). 349 14.1 Features. 349 14.2 Register Descriptions. 351 14.2.1 Low-Voltage Detection Control Register (LVDCR) . 351 14.2.2 Low-Voltage Detection Status Register (LVDSR) . 353 14.2.3 Low-Voltage Detection Counter (LVDCNT) . 354 14.3 Operation . 354 14.3.1 Power-On Reset Circuit. 354 14.3.2 Low-Voltage Detection Circuit . 355 Section 15 Power Supply Circuit (H8/38104 H8/38104 Group Only) . 363 15.1 When Using Internal Power Supply Step-Down Circuit . 363 15.2 When Not Using Internal Power Supply Step-Down Circuit. 364 Section 16 List of Registers. 365 16.1 Register Addresses (Address Order). 366 16.2 Register Bits . 370 Rev. 6.00 Mar 15, 2005 page xxxviii of l 16.3 Register States in Each Operating Mode . 373 Section 17 Electrical Characteristics . 377 17.1 Absolute Maximum Ratings of H8/3802 H8/3802 Group (ZTAT Version, Mask ROM Version) . 17.2 Electrical Characteristics of H8/3802 H8/3802 Group (ZTAT Version, Mask ROM Version) . 17.2.1 Power Supply Voltage and Operating Ranges . 17.2.2 DC Characteristics . 17.2.3 AC Characteristics . 17.2.4 A/D Converter Characteristics. 17.2.5 LCD Characteristics. 17.3 Absolute Maximum Ratings of H8/38004 H8/38004 Group (F-ZTAT Version, Mask ROM Version), H8/38002S H8/38002S Group (Mask ROM Version). 17.4 Electrical Characteristics of H8/38004 H8/38004 Group (F-ZTAT Version, Mask ROM Version), H8/38002S H8/38002S Group (Mask ROM Version). 17.4.1 Power Supply Voltage and Operating Ranges . 17.4.2 DC Characteristics . 17.4.3 AC Characteristics . 17.4.4 A/D Converter Characteristics. 17.4.5 LCD Characteristics. 17.4.6 Flash Memory Characteristics . 17.5 Absolute Maximum Ratings of H8/38104 H8/38104 Group (F-ZTAT Version, Mask ROM Version) . 17.6 Electrical Characteristics of H8/38104 H8/38104 Group (F-ZTAT Version, Mask ROM Version) . 17.6.1 Power Supply Voltage and Operating Ranges . 17.6.2 DC Characteristics . 17.6.3 AC Characteristics . 17.6.4 A/D Converter Characteristics. 17.6.5 LCD Characteristics. 17.6.6 Flash Memory Characteristics . 17.6.7 Power Supply Voltage Detection Circuit Characteristics . 17.6.8 Power-On Reset Circuit Characteristics . 17.6.9 Watchdog Timer Characteristics. 17.7 Operation Timing. 17.8 Output Load Condition . 17.9 Resonator Equivalent Circuit. 17.10 Usage Note. 377 378 378 381 388 391 393 394 395 395 399 406 411 413 414 416 417 417 421 430 432 433 434 436 439 440 440 442 443 444 Appendix A Instruction Set . 445 A.1 A.2 Instruction List. 445 Operation Code Map. 456 Rev. 6.00 Mar 15, 2005 page xxxix of l A.3 Number of Execution States . 458 Appendix B I/O Port Block Diagrams . 465 B.1 B.2 B.3 B.4 B.5 B.6 B.7 B.8 B.9 Port 3 Block Diagrams. Port 4 Block Diagrams. Port 5 Block Diagram . Port 6 Block Diagram . Port 7 Block Diagram . Port 8 Block Diagram . Port 9 Block Diagrams. Port A Block Diagram . Port B Block Diagrams . 465 469 473 474 475 476 477 479 480 Appendix C Port States in Each Operating State . 483 Appendix D Product Code Lineup . 484 Appendix E Package Dimensions. 490 Appendix F Chip Form Specifications . 494 Appendix G Bonding Pad Form. 496 Appendix H Chip Tray Specifications . 497 Index . 501 Rev. 6.00 Mar 15, 2005 page xl of l Figures Section 1 Overview Figure 1.1 Internal Block Diagram of H8/3802 H8/3802 Group . 4 Figure 1.2 Internal Block Diagram of H8/38004 H8/38004 Group . 5 Figure 1.3 Internal Block Diagram of H8/38104 H8/38104 Group . 6 Figure 1.4 Pin Arrangement of H8/3802 H8/3802 and H8/38004 H8/38004 Group (FP-64A FP-64A, FP-64E FP-64E). 7 Figure 1.5 Pin Arrangement of H8/3802 H8/3802 Group (DP-64S DP-64S) . 8 Figure 1.6 Pin Arrangement of H8/38104 H8/38104 Group (FP-64A FP-64A, FP-64E FP-64E) . 9 Figure 1.7 Pad Arrangement of HCD6433802 HCD6433802, HCD6433801 HCD6433801, and HCD6433800 HCD6433800 (Top View). 10 Figure 1.8 Pad Arrangement of HCD64338004 HCD64338004, HCD64338003 HCD64338003, HCD64338002 HCD64338002, HCD64338001 HCD64338001, and HCD64338000 HCD64338000 (Top View) . 13 Figure 1.9 Pad Arrangement of HCD64F38004 HCD64F38004 and HCD64F38002 HCD64F38002 (Top View). 16 Section 2 CPU Figure 2.1(1) H8/3802 H8/3802 Memory Map . Figure 2.1(2) H8/3801 H8/3801 Memory Map . Figure 2.1(3) H8/3800 H8/3800 Memory Map . Figure 2.1(4) H8/38004 H8/38004, H8/38104 H8/38104 Memory Map . Figure 2.1(5) H8/38003 H8/38003, H8/38103 H8/38103 Memory Map . Figure 2.1(6) H8/38002 H8/38002, H8/38102 H8/38102 Memory Map . Figure 2.1(7) H8/38001 H8/38001, H8/38101 H8/38101 Memory Map . Figure 2.1(8) H8/38000 H8/38000, H8/38100 H8/38100 Memory Map . Figure 2.2 CPU Registers. Figure 2.3 Stack Pointer. Figure 2.4 General Register Data Formats. Figure 2.5 Memory Data Formats . Figure 2.6 Instruction Formats of Data Transfer Instructions . Figure 2.7 Instruction Formats of Arithmetic, Logic, and Shift Instructions . Figure 2.8 Instruction Formats of Bit Manipulation Instructions. Figure 2.9 Instruction Formats of Branch Instructions . Figure 2.10 Instruction Formats of System Control Instructions . Figure 2.11 Instruction Format of Block Data Transfer Instructions . Figure 2.12 On-Chip Memory Access Cycle . Figure 2.13 On-Chip Peripheral Module Access Cycle (2-State Access) . Figure 2.14 On-Chip Peripheral Module Access Cycle (3-State Access) . Figure 2.15 CPU Operation States . Figure 2.16 State Transitions . Figure 2.17 Example of Timer Configuration with Two Registers Allocated to Same Address . 24 25 26 27 28 29 30 31 32 33 36 37 41 44 47 49 50 51 58 59 60 61 62 63 Rev. 6.00 Mar 15, 2005 page xli of l Section 3 Exception Handling Figure 3.1 Reset Sequence . Figure 3.2 Stack Status after Exception Handling. Figure 3.3 Interrupt Sequence . Figure 3.4 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure. 79 81 82 85 Section 4 Clock Pulse Generators Figure 4.1 Block Diagram of Clock Pulse Generators (H8/3802 H8/3802, H8/38004 H8/38004 Group) . Figure 4.2 Block Diagram of Clock Pulse Generators (H8/38104 H8/38104 Group) . Figure 4.3 Block Diagram of System Clock Generator . Figure 4.4(1) Typical Connection to Crystal Resonator (H8/3802 H8/3802 Group) . Figure 4.4(2) Typical Connection to Crystal Resonator (H8/38004 H8/38004, H8/38104 H8/38104 Group). Figure 4.5 Equivalent Circuit of Crystal Resonator . Figure 4.6(1) Typical Connection to Ceramic Resonator (H8/3802 H8/3802 Group) . Figure 4.6(2) Typical Connection to Ceramic Resonator (H8/38004 H8/38004, H8/38104 H8/38104 Group). Figure 4.7 Example of External Clock Input . Figure 4.8 Block Diagram of Subclock Generator. Figure 4.9 Typical Connection to 32.768-kHz/38.4-kHz Crystal Resonator . Figure 4.10 Equivalent Circuit of 32.768-kHz/38.4-kHz Crystal Resonator . Figure 4.11 Pin Connection when Not Using Subclock. Figure 4.12 Pin Connection when Inputting External Clock. Figure 4.13 Example of Crystal and Ceramic Resonator Arrangement . Figure 4.14 Negative Resistor Measurement and Proposed Changes in Circuit. Figure 4.15 Example of Incorrect Boar