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REJ09B0020-0200Z SH7047 SH7047F SH7049 HD64F7047 HD6437049 REJ09B0171 - Datasheet Archive
The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and
REJ09B0020-0200Z REJ09B0020-0200Z The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. 32 SH-2 SH7047 SH7047 Group Hardware Manual Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series TM SH7047F SH7047F SH7049 SH7049 Rev.2.00 Revision Date: Sep. 16, 2004 HD64F7047 HD64F7047 HD6437049 HD6437049 Rev. 2.00, 09/04, page ii of xl Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. Rev. 2.00, 09/04, page iii of xl General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are they are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product's state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system's operation is not guaranteed if they are accessed. Precaution on Handling HCAN2 Restrictions apply to the use of the HCAN2. Carefully read section 15.8, Usage Notes, beforehand. Rev. 2.00, 09/04, page iv of xl Configuration of This Manual This manual comprises the following items: 1. 2. 3. 4. 5. 6. General Precautions on Handling of Product Configuration of This Manual Preface Contents Overview Description of Functional Modules · CPU and System-Control Modules · On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. Electrical Characteristics 8. Appendix · List of registers, product code lineup, and package dimensions · Main Revisions and Additions in this Edition (only for revised versions) The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual. 9. Index Rev. 2.00, 09/04, page v of xl Preface The SH7047 SH7047 group single-chip RISC (Reduced Instruction Set Computer) microprocessor includes a Renesas -original RISC CPU as its core, and the peripheral functions required to configure a system. Target users: This manual was written for users who will be using the SH7047 SH7047 group MicroComputer Unit (MCU) in the design of application systems. Users of this manual are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of the SH7047 SH7047 group MCU to the above users. Refer to the SH-1, SH-2, SH-DSP Software Manual for a detailed description of the instruction set. Notes on reading this manual: · Product names The following products are covered in this manual. Product Classifications and Abbreviations Basic Classification On-Chip ROM Classification Product Code SH7047 SH7047 (100-pin version) SH7047F SH7047F Flash memory version (ROM: 256 kbytes) HD64F7047 HD64F7047 SH7049 SH7049 Mask ROM version (ROM: 128 kbytes) HD6437049 HD6437049 In this manual, the product abbreviations are used to distinguish products. For example, 100pin products are collectively referred to as the SH7047 SH7047, an abbreviation of the basic type's classification code. There are two versions of each: a flash memory version and a mask ROM version. When a description is limited to the flash memory version alone, the character F is added at the end of the abbreviation, such as SH7047F SH7047F. When a description is limited to the mask ROM version alone, an abbreviation that is determined by the ROM size is used; SH7049 SH7049 is used to indicate the mask ROM version. Rev. 2.00, 09/04, page vi of xl · The typical product The HD64F7047 HD64F7047 is taken as the typical product for the descriptions in this manual. Accordingly, when using an HD6437049 HD6437049, simply replace the HD64F7047 HD64F7047 in those references where no differences between products are pointed out with HD6437049 HD6437049. Where differences are indicated, be aware that each specification apply to the products as indicated. · In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics. · In order to understand the details of the CPU's functions Read the SH-1, SH-2, SH-DSP Software Manual. · In order to understand the details of a register when the user knows its name Read the index that is the final part of the manual to find the page number of the entry on the register. The addresses, bit names, and initial values of the registers are summarized in Appendix A, Internal I/O Register. Rules: Register name: Bit order: Related Manuals: The following notation is used for cases when the same or a similar function, e.g. serial communication, is implemented on more than one channel: XXX_N (XXX is the register name and N is the channel number) The MSB (most significant bit) is on the left and the LSB (least significant bit) is on the right. The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com SH7047 SH7047 Group manuals: Document Title Document No. SH7047 SH7047 Group Hardware Manual This manual SH-1, SH-2, SH-DSP Software Manual REJ09B0171 REJ09B0171 Rev. 2.00, 09/04, page vii of xl Users manuals for development tools: Document Title Document No. SuperH RISC engine C/C+ Compiler, Assembler, Optimizing Linkage Editor User's Manual ADE-702-372 ADE-702-372 SuperH RISC engine Simulator/Debugger User's Manual ADE-702-186 ADE-702-186 High-performance Embedded Workshop User's Manual ADE-702-201 ADE-702-201 Rev. 2.00, 09/04, page viii of xl Contents Section 1 Overview.1 1.1 1.2 1.3 1.4 Features. 2 Internal Block Diagram. 4 Pin Arrangement . 5 Pin Functions . 6 Section 2 CPU.13 2.1 2.2 2.3 2.4 2.5 2.6 Features. 13 Register Configuration. 14 2.2.1 General Registers (Rn). 14 2.2.2 Control Registers . 16 2.2.3 System Registers. 17 2.2.4 Initial Values of Registers. 17 Data Formats. 18 2.3.1 Data Format in Registers . 18 2.3.2 Data Formats in Memory . 18 2.3.3 Immediate Data Format . 19 Instruction Features. 20 2.4.1 RISC-Type Instruction Set. 20 2.4.2 Addressing Modes . 23 2.4.3 Instruction Format. 26 Instruction Set . 29 2.5.1 Instruction Set by Classification . 29 Processing States. 42 2.6.1 State Transitions . 42 Section 3 MCU Operating Modes .45 3.1 3.2 3.3 3.4 3.5 Selection of Operating Modes. 45 Input/Output Pins . 46 Explanation of Operating Modes . 47 3.3.1 Mode 0 (MCU extension mode 0) . 47 3.3.2 Mode 1 (MCU extension mode 1) . 47 3.3.3 Mode 2 (MCU extension mode 2) . 47 3.3.4 Mode 3 (Single chip mode). 47 3.3.5 Clock Mode . 47 Address Map . 48 Initial State of This LSI. 50 Rev. 2.00, 09/04, page ix of xl Section 4 Clock Pulse Generator. 51 4.1 4.2 4.3 Oscillator. 52 4.1.1 Connecting a Crystal Resonator. 52 4.1.2 External Clock Input Method . 53 Function for Detecting the Oscillator Halt. 54 Usage Notes . 55 4.3.1 Note on Crystal Resonator. 55 4.3.2 Notes on Board Design . 55 Section 5 Exception Processing. 57 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 Overview. 57 5.1.1 Types of Exception Processing and Priority . 57 5.1.2 Exception Processing Operations . 58 5.1.3 Exception Processing Vector Table . 59 Resets. 61 5.2.1 Types of Reset . 61 5.2.2 Power-On Reset . 61 5.2.3 Manual Reset . 62 Address Errors . 63 5.3.1 The Cause of Address Error Exception. 63 5.3.2 Address Error Exception Processing . 64 Interrupts. 65 5.4.1 Interrupt Sources. 65 5.4.2 Interrupt Priority Level . 66 5.4.3 Interrupt Exception Processing . 66 Exceptions Triggered by Instructions . 67 5.5.1 Types of Exceptions Triggered by Instructions . 67 5.5.2 Trap Instructions. 67 5.5.3 Illegal Slot Instructions. 68 5.5.4 General Illegal Instructions. 68 Cases when Exception Sources Are Not Accepted. 69 5.6.1 Immediately after a Delayed Branch Instruction . 69 5.6.2 Immediately after an Interrupt-Disabled Instruction. 69 Stack Status after Exception Processing Ends . 70 Usage Notes . 71 5.8.1 Value of Stack Pointer (SP) . 71 5.8.2 Value of Vector Base Register (VBR). 71 5.8.3 Address Errors Caused by Stacking of Address Error Exception Processing. 71 Section 6 Interrupt Controller (INTC). 73 6.1 6.2 6.3 Features. 73 Input/Output Pins. 75 Register Descriptions. 75 Rev. 2.00, 09/04, page x of xl 6.4 6.5 6.6 6.7 6.8 6.3.1 Interrupt Control Register 1 (ICR1). 76 6.3.2 Interrupt Control Register 2 (ICR2). 77 6.3.3 IRQ Status Register (ISR). 79 6.3.4 Interrupt Priority Registers A, D to I, K (IPRA, IPRD to IPRI, IPRK) . 80 Interrupt Sources. 82 6.4.1 External Interrupts . 82 6.4.2 On-Chip Peripheral Module Interrupts . 83 6.4.3 User Break Interrupt . 83 6.4.4 H-UDI Interrupt . 83 Interrupt Exception Processing Vectors Table. 84 Interrupt Operation. 88 6.6.1 Interrupt Sequence . 88 6.6.2 Stack after Interrupt Exception Processing . 90 Interrupt Response Time. 91 Data Transfer with Interrupt Request Signals . 93 6.8.1 Handling Interrupt Request Signals as Sources for DTC Activating and CPU Interrupt . 93 6.8.2 Handling Interrupt Request Signals as Source for DTC Activating, but Not CPU Interrupt. 94 6.8.3 Handling Interrupt Request Signals as Source for CPU Interrupt but Not DTC Activating. 94 Section 7 User Break Controller (UBC) .95 7.1 7.2 7.3 7.4 7.5 Overview. 95 Register Descriptions . 97 7.2.1 User Break Address Register (UBAR) . 97 7.2.2 User Break Address Mask Register (UBAMR) . 98 7.2.3 User Break Bus Cycle Register (UBBR) . 98 7.2.4 User Break Control Register (UBCR) . 100 Operation . 101 7.3.1 Flow of the User Break Operation . 101 7.3.2 Break on On-Chip Memory Instruction Fetch Cycle . 103 7.3.3 Program Counter (PC) Values Saved. 103 Examples of Use . 104 Usage Notes . 106 7.5.1 Simultaneous Fetching of Two Instructions . 106 7.5.2 Instruction Fetches at Branches . 106 7.5.3 Contention between User Break and Exception Processing . 107 7.5.4 Break at Non-Delay Branch Instruction Jump Destination. 107 7.5.5 User Break Trigger Output . 107 7.5.6 Module Standby Mode Setting . 108 Rev. 2.00, 09/04, page xi of xl Section 8 Data Transfer Controller (DTC). 109 8.1 8.2 8.3 8.4 8.5 Features. 109 Register Descriptions. 111 8.2.1 DTC Mode Register (DTMR). 112 8.2.2 DTC Source Address Register (DTSAR) . 114 8.2.3 DTC Destination Address Register (DTDAR) . 114 8.2.4 DTC Initial Address Register (DTIAR). 114 8.2.5 DTC Transfer Count Register A (DTCRA). 114 8.2.6 DTC Transfer Count Register B (DTCRB) . 114 8.2.7 DTC Enable Registers (DTER) . 115 8.2.8 DTC Control/Status Register (DTCSR). 116 8.2.9 DTC Information Base Register (DTBR) . 117 Operation . 118 8.3.1 Activation Sources. 118 8.3.2 Location of Register Information and DTC Vector Table . 118 8.3.3 DTC Operation . 121 8.3.4 Interrupt Source . 127 8.3.5 Operation Timing. 127 8.3.6 DTC Execution State Counts . 128 Procedures for Using DTC. 129 8.4.1 Activation by Interrupt. 129 8.4.2 Activation by Software . 129 8.4.3 DTC Use Example. 130 Cautions on Use . 131 8.5.1 Prohibition against DTC Register Access by DTC. 131 8.5.2 Module Standby Mode Setting . 131 8.5.3 On-Chip RAM . 131 Section 9 Bus State Controller (BSC) . 133 9.1 9.2 9.3 9.4 9.5 9.6 9.7 Features. 133 Input/Output Pin . 135 Register Configuration. 135 Address Map . 136 Description of Registers. 138 9.5.1 Bus Control Register 1 (BCR1) . 138 9.5.2 Bus Control Register 2 (BCR2) . 139 9.5.3 Wait Control Register 1 (WCR1) . 140 9.5.4 RAM Emulation Register (RAMER). 140 Accessing External Space . 141 9.6.1 Basic Timing. 141 9.6.2 Wait State Control . 142 9.6.3 CS Assert Period Extension. 144 Waits between Access Cycles. 145 Rev. 2.00, 09/04, page xii of xl 9.7.1 Prevention of Data Bus Conflicts. 145 9.7.2 Simplification of Bus Cycle Start Detection. 145 9.8 Bus Arbitration. 146 9.9 Memory Connection Example . 147 9.10 On-chip Peripheral I/O Register Access . 148 9.11 Cycles in which Bus is not Released. 148 9.12 CPU Operation when Program is In External Memory . 148 Section 10 Multi-Function Timer Pulse Unit (MTU) .149 10.1 Features. 149 10.2 Input/Output Pins . 153 10.3 Register Descriptions . 154 10.3.1 Timer Control Register (TCR). 156 10.3.2 Timer Mode Register (TMDR) . 160 10.3.3 Timer I/O Control Register (TIOR) . 162 10.3.4 Timer Interrupt Enable Register (TIER) . 180 10.3.5 Timer Status Register (TSR). 182 10.3.6 Timer Counter (TCNT). 185 10.3.7 Timer General Register (TGR) . 185 10.3.8 Timer Start Register (TSTR) . 186 10.3.9 Timer Synchro Register (TSYR) . 187 10.3.10 Timer Output Master Enable Register (TOER) . 188 10.3.11 Timer Output Control Register (TOCR). 189 10.3.12 Timer Gate Control Register (TGCR) . 191 10.3.13 Timer Subcounter (TCNTS) . 192 10.3.14 Timer Dead Time Data Register (TDDR). 192 10.3.15 Timer Period Data Register (TCDR) . 193 10.3.16 Timer Period Buffer Register (TCBR). 193 10.3.17 Bus Master Interface. 193 10.4 Operation . 194 10.4.1 Basic Functions. 194 10.4.2 Synchronous Operation. 200 10.4.3 Buffer Operation . 202 10.4.4 Cascaded Operation . 206 10.4.5 PWM Modes . 207 10.4.6 Phase Counting Mode. 212 10.4.7 Reset-Synchronized PWM Mode. 218 10.4.8 Complementary PWM Mode. 222 10.5 Interrupts. 247 10.5.1 Interrupts and Priorities. 247 10.5.2 DTC Activation. 249 10.5.3 A/D Converter Activation. 249 10.6 Operation Timing. 250 Rev. 2.00, 09/04, page xiii of xl 10.6.1 Input/Output Timing. 250 10.6.2 Interrupt Signal Timing . 255 10.7 Usage Notes . 258 10.7.1 Module Standby Mode Setting . 258 10.7.2 Input Clock Restrictions . 258 10.7.3 Caution on Period Setting . 259 10.7.4 Contention between TCNT Write and Clear Operations. 259 10.7.5 Contention between TCNT Write and Increment Operations. 260 10.7.6 Contention between TGR Write and Compare Match. 261 10.7.7 Contention between Buffer Register Write and Compare Match . 262 10.7.8 Contention between TGR Read and Input Capture. 264 10.7.9 Contention between TGR Write and Input Capture. 265 10.7.10 Contention between Buffer Register Write and Input Capture . 266 10.7.11 TCNT2 Write and Overflow/Underflow Contention in Cascade Connection . 266 10.7.12 Counter Value during Complementary PWM Mode Stop . 268 10.7.13 Buffer Operation Setting in Complementary PWM Mode . 268 10.7.14 Reset Sync PWM Mode Buffer Operation and Compare Match Flag . 269 10.7.15 Overflow Flags in Reset Sync PWM Mode. 270 10.7.16 Contention between Overflow/Underflow and Counter Clearing. 271 10.7.17 Contention between TCNT Write and Overflow/Underflow. 272 10.7.18 Cautions on Transition from Normal Operation or PWM Mode 1 to Reset-Synchronous PWM Mode . 273 10.7.19 Output Level in Complementary PWM Mode and Reset-Synchronous PWM Mode . 273 10.7.20 Interrupts in Module Standby Mode . 273 10.7.21 Simultaneous Input Capture of TCNT-1 and TCNT-2 in Cascade Connection. 273 10.8 MTU Output Pin Initialization. 274 10.8.1 Operating Modes . 274 10.8.2 Reset Start Operation . 274 10.8.3 Operation in Case of Re-Setting Due to Error During Operation, etc. . 275 10.8.4 Overview of Initialization Procedures and Mode Transitions in Case of Error during Operation, Etc. . 276 10.9 Port Output Enable (POE) . 306 10.9.1 Features. 306 10.9.2 Pin Configuration. 308 10.9.3 Register Configuration. 308 10.9.4 Operation . 313 10.9.5 Usage Notes . 315 Section 11 Watchdog Timer. 317 11.1 Features. 317 11.2 Input/Output Pin . 318 11.3 Register Descriptions. 319 Rev. 2.00, 09/04, page xiv of xl 11.3.1 Timer Counter (TCNT). 319 11.3.2 Timer Control/Status Register (TCSR). 319 11.3.3 Reset Control/Status Register (RSTCSR). 321 11.4 Operation . 322 11.4.1 Watchdog Timer Mode . 322 11.4.2 Interval Timer Mode. 323 11.4.3 Clearing Software Standby Mode . 324 11.4.4 Timing of Setting the Overflow Flag (OVF) . 324 11.4.5 Timing of Setting the Watchdog Timer Overflow Flag (WOVF). 325 11.5 Interrupts. 325 11.6 Usage Notes . 325 11.6.1 Notes on Register Access. 325 11.6.2 TCNT Write and Increment Contention . 327 11.6.3 Changing CKS2 to CKS0 Bit Values . 327 11.6.4 Changing between Watchdog Timer/Interval Timer Modes. 327 11.6.5 System Reset by WDTOVF Signal. 328 11.6.6 Internal Reset in Watchdog Timer Mode. 328 11.6.7 Manual Reset in Watchdog Timer Mode . 328 11.6.8 Handling of WDTOVF pin . 328 Section 12 Serial Communication Interface (SCI) .329 12.1 Features. 329 12.2 Input/Output Pins . 331 12.3 Register Descriptions . 332 12.3.1 Receive Shift Register (RSR) . 333 12.3.2 Receive Data Register (RDR) . 333 12.3.3 Transmit Shift Register (TSR) . 333 12.3.4 Transmit Data Register (TDR). 333 12.3.5 Serial Mode Register (SMR) . 334 12.3.6 Serial Control Register (SCR) . 335 12.3.7 Serial Status Register (SSR) . 337 12.3.8 Serial Direction Control Register (SDCR). 340 12.3.9 Bit Rate Register (BRR) . 340 12.4 Operation in Asynchronous Mode . 351 12.4.1 Data Transfer Format. 351 12.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode . 353 12.4.3 Clock. 354 12.4.4 SCI initialization (Asynchronous mode). 355 12.4.5 Data transmission (Asynchronous mode) . 356 12.4.6 Serial data reception (Asynchronous mode) . 358 12.5 Multiprocessor Communication Function. 362 12.5.1 Multiprocessor Serial Data Transmission . 364 Rev. 2.00, 09/04, page xv of xl 12.5.2 Multiprocessor Serial Data Reception . 365 12.6 Operation in Clocked Synchronous Mode . 368 12.6.1 Clock. 368 12.6.2 SCI initialization (Clocked Synchronous mode) . 368 12.6.3 Serial data transmission (Clocked Synchronous mode). 369 12.6.4 Serial data reception (Clocked Synchronous mode) . 372 12.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous mode). 374 12.7 SCI Interrupts. 376 12.7.1 Interrupts in Normal Serial Communication Interface Mode . 376 12.8 Usage Notes . 377 12.8.1 TDR Write and TDRE Flag . 377 12.8.2 Module Standby Mode Setting . 377 12.8.3 Break Detection and Processing (Asynchronous Mode Only). 377 12.8.4 Sending a Break Signal (Asynchronous Mode Only) . 377 12.8.5 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) . 378 12.8.6 Constraints on DTC Use . 378 12.8.7 Cautions on Clocked Synchronous External Clock Mode . 378 12.8.8 Caution on Clocked Synchronous Internal Clock Mode. 378 Section 13 A/D Converter . 379 13.1 Features. 379 13.2 Input/Output Pins. 381 13.3 Register Description . 382 13.3.1 A/D Data Registers 0 to 15 (ADDR0 to ADDR15 ADDR15). 382 13.3.2 A/D Control/Status Registers 0, 1 (ADCSR_0, ADCSR_1). 383 13.3.3 A/D Control Registers 0, 1 (ADCR_0, ADCR_1). 384 13.3.4 A/D Trigger Select Register (ADTSR). 386 13.4 Operation . 387 13.4.1 Single Mode. 387 13.4.2 Continuous Scan Mode. 387 13.4.3 Single-Cycle Scan Mode . 388 13.4.4 Input Sampling and A/D Conversion Time . 388 13.4.5 A/D Converter Activation by MTU or MMT . 390 13.4.6 External Trigger Input Timing. 390 13.5 Interrupt Sources and DTC Transfer Requests . 391 13.6 Definitions of A/D Conversion Accuracy. 392 13.7 Usage Notes . 394 13.7.1 Module Standby Mode Setting . 394 13.7.2 Permissible Signal Source Impedance . 394 13.7.3 Influences on Absolute Accuracy . 394 13.7.4 Range of Analog Power Supply and Other Pin Settings. 395 Rev. 2.00, 09/04, page xvi of xl 13.7.5 Notes on Board Design . 395 13.7.6 Notes on Noise Countermeasures . 395 Section 14 Compare Match Timer (CMT) .397 14.1 Features. 397 14.2 Register Descriptions . 398 14.2.1 Compare Match Timer Start Register (CMSTR) . 398 14.2.2 Compare Match Timer Control/Status Register_0 and 1 (CMCSR_0, CMCSR_1) . 399 14.2.3 Compare Match Timer Counter_0 and 1 (CMCNT_0, CMCNT_1). 400 14.2.4 Compare Match Timer Constant Register_0 and 1 (CMCOR_0, CMCOR_1). 400 14.3 Operation . 400 14.3.1 Cyclic Count Operation . 400 14.3.2 CMCNT Count Timing. 401 14.4 Interrupts. 401 14.4.1 Interrupt Sources. 401 14.4.2 Compare Match Flag Set Timing. 401 14.4.3 Compare Match Flag Clear Timing . 402 14.5 Usage Notes . 403 14.5.1 Contention between CMCNT Write and Compare Match. 403 14.5.2 Contention between CMCNT Word Write and Incrementation . 404 14.5.3 Contention between CMCNT Byte Write and Incrementation . 405 Section 15 Controller Area Network 2 (HCAN2) .407 15.1 Features. 407 15.2 Input/Output Pins . 410 15.3 Register Descriptions . 410 15.3.1 Master Control Register (MCR) . 413 15.3.2 General Status Register (GSR) . 418 15.3.3 Bit Timing Configuration Register 1 (HCAN2_BCR1) . 420 15.3.4 Bit Timing Configuration Register 0 (HCAN2_BCR0) . 422 15.3.5 Interrupt Request Register (IRR) . 422 15.3.6 Interrupt Mask Register (IMR) . 427 15.3.7 Error Counter Register (TEC/REC). 429 15.3.8 Transmit Wait Registers (TXPR1, TXPR0). 430 15.3.9 Transmit Wait Cancel Registers (TXCR1, TXCR0). 432 15.3.10 Transmit Acknowledge Registers (TXACK1, TXACK0) . 434 15.3.11 Abort Acknowledge Registers (ABACK1, ABACK0). 436 15.3.12 Receive Complete Registers (RXPR1, RXPR0). 438 15.3.13 Remote Request Registers (RFPR1, RFPR0) . 440 15.3.14 Mailbox Interrupt Mask Registers (MBIMR1, MBIMR0) . 442 15.3.15 Unread Message Status Registers (UMSR1, UMSR0) . 444 15.3.16 Mailboxes (MB0 to MB31) . 445 Rev. 2.00, 09/04, page xvii of xl 15.4 15.5 15.6 15.7 15.8 15.3.17 Timer Counter Register (TCNTR). 454 15.3.18 Timer Control Register (TCR). 455 15.3.19 Timer Status Register (TSR). 457 15.3.20 Local Offset Register (LOSR) . 458 15.3.21 Input Capture Registers 0 and 1 (ICR0, ICR1). 459 15.3.22 Timer Compare Match Registers 0 and 1 (TCMR0 and TCMR1) . 459 Operation . 460 15.4.1 Hardware and Software Resets . 460 15.4.2 Initialization after Hardware Reset . 460 15.4.3 Message Transmission by Event Trigger. 466 15.4.4 Message Reception . 469 15.4.5 Mailbox Reconfiguration. 472 15.4.6 HCAN2 Sleep Mode. 473 15.4.7 HCAN2 Halt Mode. 476 Interrupt Sources. 477 DTC Interface . 478 CAN Bus Interface. 479 Usage Notes . 479 15.8.1 Time Trigger Transmit Setting/Timer Operation Disabled. 479 15.8.2 Reset . 479 15.8.3 HCAN2 Sleep Mode. 480 15.8.4 Interrupts. 480 15.8.5 Error Counters . 480 15.8.6 Register Access. 480 15.8.7 Register in Standby Modes . 480 15.8.8 Transmission Cancellation during SOF or Intermission. 480 15.8.9 Cases when the Transmit Wait Register (TXPR) is Set during Transfer of EOF . 481 15.8.10 Limitation on Access to the Local Acceptance Filter Mask (LAFM). 481 15.8.11 Notes on Using Auto Acknowledge Mode . 481 15.8.12 Notes on Usage of the Transmit Wait Cancel Register (TXCR) . 481 15.8.13 Setting and Cancellation of Transmission during Bus-Idle State . 482 15.8.14 Releasing HCAN2 Reset . 482 15.8.15 Accessing Mailboxes When HCAN2 Is in Sleep Mode . 482 15.8.16 Module Standby Mode Setting . 482 Section 16 Motor Management Timer (MMT) . 483 16.1 Features. 483 16.2 Input/Output Pins. 485 16.3 Register Descriptions. 486 16.3.1 Timer Mode Register (MMT_TMDR) . 487 16.3.2 Timer Control Register (TCNR). 488 16.3.3 Timer Status Register (MMT_TSR) . 489 Rev. 2.00, 09/04, page xviii of xl 16.4 16.5 16.6 16.7 16.8 16.3.4 Timer Counter (MMT_TCNT) . 490 16.3.5 Timer Buffer Registers (TBR) . 490 16.3.6 Timer General Registers (TGR). 490 16.3.7 Timer Dead Time Counters (TDCNT). 490 16.3.8 Timer Dead Time Data Register (MMT_TDDR) . 490 16.3.9 Timer Period Buffer Register (TPBR) . 490 16.3.10 Timer Period Data Register (TPDR). 491 Operation . 491 16.4.1 Sample Setting Procedure . 492 16.4.2 Output Protection Functions . 500 Interrupts. 500 Operation Timing. 501 16.6.1 Input/Output Timing . 501 16.6.2 Interrupt Signal Timing. 504 Usage Notes . 505 16.7.1 Module Standby Mode Setting . 505 16.7.2 Notes for MMT Operation . 505 Port Output Enable (POE). 508 16.8.1 Features. 508 16.8.2 Input/Output Pins. 509 16.8.3 Register Descriptions. 509 16.8.4 Operation . 512 16.8.5 Usage Note. 513 Section 17 Pin Function Controller (PFC).515 17.1 Register Descriptions . 525 17.1.1 Port A I/O Register L (PAIORL). 525 17.1.2 Port A Control Registers L3 to L1 (PACRL3 to PACRL1). 525 17.1.3 Port B I/O Register (PBIOR) . 529 17.1.4 Port B Control Registers 1 and 2 (PBCR1 and PBCR2). 529 17.1.5 Port D I/O Register L (PDIORL). 530 17.1.6 Port D Control Registers L1 and L2 (PDCRL1 and PDCRL2) . 531 17.1.7 Port E I/O Registers L and H (PEIORL and PEIORH). 532 17.1.8 Port E Control Registers L1, L2, and H (PECRL1, PECRL2, and PECRH) . 533 17.2 Precautions for Use . 536 Section 18 I/O Ports .537 18.1 Port A. 537 18.1.1 Register Descriptions. 538 18.1.2 Port A Data Register L (PADRL) . 538 18.2 Port B . 539 18.2.1 Register Descriptions. 539 18.2.2 Port B Data Register (PBDR) . 539 Rev. 2.00, 09/04, page xix of xl 18.3 Port D. 541 18.3.1 Register Descriptions. 541 18.3.2 Port D Data Register L (PDDRL). 541 18.4 Port E . 543 18.4.1 Register Descriptions. 544 18.4.2 Port E Data Registers H and L (PEDRH and PEDRL) . 544 18.5 Port F . 546 18.5.1 Register Descriptions. 546 18.5.2 Port F Data Register (PFDR) . 546 Section 19 Flash Memory (F-ZTAT Version). 549 19.1 19.2 19.3 19.4 19.5 19.6 19.7 19.8 19.9 19.10 19.11 19.12 19.13 Features. 549 Mode Transitions . 550 Block Configuration . 554 Input/Output Pins. 555 Register Descriptions. 555 19.5.1 Flash Memory Control Register 1 (FLMCR1) . 555 19.5.2 Flash Memory Control Register 2 (FLMCR2) . 557 19.5.3 Erase Block Register 1 (EBR1) . 557 19.5.4 Erase Block Register 2 (EBR2) . 558 19.5.5 RAM Emulation Register (RAMER). 558 On-Board Programming Modes. 559 19.6.1 Boot Mode . 560 19.6.2 Programming/Erasing in User Program Mode. 562 Flash Memory Emulation in RAM . 563 Flash Memory Programming/Erasing. 565 19.8.1 Program/Program-Verify Mode. 565 19.8.2 Erase/Erase-Verify Mode . 567 19.8.3 Interrupt Handling when Programming/Erasing Flash Memory. 567 Program/Erase Protection . 569 19.9.1 Hardware Protection . 569 19.9.2 Software Protection . 570 19.9.3 Error Protection . 570 PROM Programmer Mode. 571 Notes on Use. 571 Notes when Converting the F-ZTAT Versions to the Mask-ROM Versions. 571 Notes on Flash Memory Programming and Erasing . 571 Section 20 Mask ROM . 577 20.1 Notes on Use. 577 Section 21 RAM . 579 21.1 Usage Note. 579 Rev. 2.00, 09/04, page xx of xl Section 22 High-Performance User Debugging Interface (H-UDI) .581 22.1 Overview. 581 22.1.1 Features. 581 22.1.2 Block Diagram. 582 22.2 Input/Output Pins . 583 22.3 Register Description. 583 22.3.1 Instruction Register (SDIR) . 584 22.3.2 Status Register (SDSR). 585 22.3.3 Data Register (SDDR) . 586 22.3.4 Bypass Register (SDBPR) . 586 22.4 Operation . 587 22.4.1 H-UDI Interrupt . 587 22.4.2 Bypass Mode . 590 22.4.3 H-UDI Reset . 590 22.5 Usage Notes . 590 Section 23 Advanced User Debugger (AUD).593 23.1 Overview. 593 23.1.1 Features. 593 23.1.2 Block Diagram. 594 23.2 Pin Configuration. 594 23.2.1 Pin Descriptions. 595 23.3 Branch Trace Mode. 597 23.3.1 Overview. 597 23.3.2 Operation . 597 23.4 RAM Monitor Mode . 598 23.4.1 Overview. 598 23.4.2 Communication Protocol . 599 23.4.3 Operation . 599 23.5 Usage Notes . 601 23.5.1 Initialization . 601 23.5.2 Operation in Software Standby Mode. 601 23.5.3 Setting the PA15/CK/POE6/TRST/BACK PA15/CK/POE6/TRST/BACK pin. 601 23.5.4 Pin States . 601 23.5.5 AUD Activation Procedures . 602 Section 24 Power-Down Modes .603 24.1 Input/Output Pins . 606 24.2 Register Descriptions . 606 24.2.1 Standby Control Register (SBYCR) . 607 24.2.2 System Control Register (SYSCR) . 608 24.2.3 Module Standby Control Register 1 and 2 (MSTCR1 and MSTCR2). 609 24.3 Operation . 611 Rev. 2.00, 09/04, page xxi of xl 24.3.1 Sleep Mode . 611 24.3.2 Software Standby Mode. 611 24.3.3 Hardware Standby Mode . 614 24.3.4 Module Standby Mode. 615 24.4 Usage Notes . 615 24.4.1 I/O Port Status. 615 24.4.2 Current Consumption during Oscillation Stabilization Wait Period. 616 24.4.3 On-Chip Peripheral Module Interrupt. 616 24.4.4 Writing to MSTCR1 and MSTCR2 . 616 24.4.5 Handling of HSTBY Pin. 616 24.4.6 Electromagnetic Interference on HSTBY Pin. 616 24.4.7 DTC or AUD operation in Sleep Mode . 617 Section 25 Electrical Characteristics . 619 25.1 Absolute Maximum Ratings . 619 25.2 DC Characteristics . 620 25.3 AC Characteristics . 623 25.3.1 Test Conditions for the AC Characteristics . 623 25.3.2 Clock Timing . 624 25.3.3 Control Signal Timing . 626 25.3.4 Bus Timing . 629 25.3.5 Multi-Function Timer Pulse Unit (MTU)Timing . 633 25.3.6 I/O Port Timing. 634 25.3.7 Watchdog Timer (WDT)Timing. 635 25.3.8 Serial Communication Interface (SCI)Timing. 636 25.3.9 Motor Management Timer (MMT) Timing . 638 25.3.10 Port Output Enable (POE) Timing. 639 25.3.11 HCAN2 Timing . 640 25.3.12 A/D Converter Timing. 641 25.3.13 H-UDI Timing . 642 25.3.14 AUD Timing. 644 25.3.15 UBC Trigger Timing . 646 25.4 A/D Converter Characteristics . 647 25.5 Flash Memory Characteristics . 648 Appendix A Internal I/O Register . 651 A.1 A.2 A.3 Register Addresses (Order of Address) . 651 Register Bits. 678 Register States in Each Operating Mode . 690 Appendix B Pin States. 698 Appendix C Product Code Lineup . 702 Rev. 2.00, 09/04, page xxii of xl Appendix D Package Dimensions .703 Main Revisions and Additions in this Edition .705 Index .717 Rev. 2.00, 09/04, page xxiii of xl Rev. 2.00, 09/04, page xxiv of xl Figures Section 1 Overview Figure 1.1 Block Diagram of SH7047 SH7047 . 4 Figure 1.2 SH7047 SH7047 Pin Arrangement. 5 Section 2 Figure 2.1 Figure 2.2 Figure 2.3 Figure 2.4 CPU CPU Internal Registers . 15 Data Format in Registers . 18 Data Formats in Memory. 18 Transitions between Processing States . 42 Section 3 MCU Operating Modes Figure 3.1 The Address Map for the Operating Modes of SH7047 SH7047 Flash Memory Version . 48 Figure 3.2 The Address Map for the Operating Modes of SH7049 SH7049 Mask ROM Version . 49 Section 4 Figure 4.1 Figure 4.2 Figure 4.3 Figure 4.4 Figure 4.5 Figure 4.6 Clock Pulse Generator Block Diagram of the Clock Pulse Generator . 51 Connection of the Crystal Resonator (Example) . 52 Crystal Resonator Equivalent Circuit . 52 Example of External Clock Connection . 53 Cautions for Oscillator Circuit System Board Design. 55 Recommended External Circuitry Around the PLL . 56 Section 6 Figure 6.1 Figure 6.2 Figure 6.3 Figure 6.4 Figure 6.5 Figure 6.6 Interrupt Controller (INTC) INTC Block Diagram . 74 Block Diagram of IRQ3 to IRQ0 Interrupts Control. 83 Interrupt Sequence Flowchart. 89 Stack after Interrupt Exception Processing. 90 Example of the Pipeline Operation when an IRQ Interrupt is Accepted . 92 Interrupt Control Block Diagram . 93 Section 7 User Break Controller (UBC) Figure 7.1 User Break Controller Block Diagram . 96 Figure 7.2 Break Condition Determination Method . 102 Section 8 Figure 8.1 Figure 8.2 Figure 8.3 Figure 8.4 Figure 8.5 Figure 8.6 Figure 8.7 Figure 8.8 Data Transfer Controller (DTC) Block Diagram of DTC . 110 Activating Source Control Block Diagram . 118 DTC Register Information Allocation in Memory Space. 119 Correspondence between DTC Vector Address and Transfer Information. 119 DTC Operation Flowchart. 122 Memory Mapping in Normal Mode . 123 Memory Mapping in Repeat Mode . 124 Memory Mapping in Block Transfer Mode. 125 Rev. 2.00, 09/04, page xxv of xl Figure 8.9 Chain Transfer. 126 Figure 8.10 DTC Operation Timing Example (Normal Mode) . 127 Section 9 Figure 9.1 Figure 9.2 Figure 9.3 Figure 9.4 Figure 9.5 Bus State Controller (BSC) BSC Block Diagram. 134 Address Format . 136 Basic Timing of External Space Access. 141 Wait State Timing of External Space Access (Software Wait Only) . 142 Wait State Timing of External Space Access (Two Software Wait States + WAIT Signal Wait State). 143 Figure 9.6 CS Assert Period Extension Function . 144 Figure 9.7 Example of Idle Cycle Insertion at Same Space Consecutive Access. 145 Figure 9.8 Bus Mastership Release Procedure . 147 Figure 9.9 Example of 8-bit Data Bus Width ROM Connection. 147 Figure 9.10 One Bus Cycle. 148 Section 10 Multi-Function Timer Pulse Unit (MTU) Figure 10.1 Block Diagram of MTU . 152 Figure 10.2 Complementary PWM Mode Output Level Example . 190 Figure 10.3 Example of Counter Operation Setting Procedure . 194 Figure 10.4 Free-Running Counter Operation . 195 Figure 10.5 Periodic Counter Operation. 196 Figure 10.6 Example of Setting Procedure for Waveform Output by Compare Match. 196 Figure 10.7 Example of 0 Output/1 Output Operation . 197 Figure 10.8 Example of Toggle Output Operation . 197 Figure 10.9 Example of Input Capture Operation Setting Procedure . 198 Figure 10.10 Example of Input Capture Operation . 199 Figure 10.11 Example of Synchronous Operation Setting Procedure . 200 Figure 10.12 Example of Synchronous Operation. 201 Figure 10.13 Compare Match Buffer Operation. 202 Figure 10.14 Input Capture Buffer Operation. 203 Figure 10.15 Example of Buffer Operation Setting Procedure. 203 Figure 10.16 Example of Buffer Operation (1) . 204 Figure 10.17 Example of Buffer Operation (2) . 205 Figure 10.18 Cascaded Operation Setting Procedure . 206 Figure 10.19 Example of Cascaded Operation . 207 Figure 10.20 Example of PWM Mode Setting Procedure . 209 Figure 10.21 Example of PWM Mode Operation (1) . 209 Figure 10.22 Example of PWM Mode Operation (2) . 210 Figure 10.23 Example of PWM Mode Operation (3) . 211 Figure 10.24 Example of Phase Counting Mode Setting Procedure. 212 Figure 10.25 Example of Phase Counting Mode 1 Operation . 213 Figure 10.26 Example of Phase Counting Mode 2 Operation . 214 Figure 10.27 Example of Phase Counting Mode 3 Operation . 215 Rev. 2.00, 09/04, page xxvi of xl Figure 10.28 Figure 10.29 Figure 10.30 Figure 10.31 Figure 10.32 Figure 10.33 Figure 10.34 Figure 10.35 Figure 10.36 Figure 10.37 Figure 10.38 Figure 10.39 Figure 10.40 Figure 10.41 Figure 10.42 Figure 10.43 Figure 10.44 Figure 10.45 Figure 10.46 Figure 10.47 Figure 10.48 Figure 10.49 Figure 10.50 Figure 10.51 Figure 10.52 Figure 10.53 Figure 10.54 Figure 10.55 Figure 10.56 Figure 10.57 Figure 10.58 Figure 10.59 Figure 10.60 Figure 10.61 Figure 10.62 Figure 10.63 Figure 10.64 Figure 10.65 Figure 10.66 Figure 10.67 Figure 10.68 Example of Phase Counting Mode 4 Operation . 216 Phase Counting Mode Application Example. 217 Procedure for Selecting the Reset-Synchronized PWM Mode. 220 Reset-Synchronized PWM Mode Operation Example (When the TOCR's OLSN = 1 and OLSP = 1). 221 Block Diagram of Channels 3 and 4 in Complementary PWM Mode . 224 Example of Complementary PWM Mode Setting Procedure. 226 Complementary PWM Mode Counter Operation. 227 Example of Complementary PWM Mode Operation . 229 Example of PWM Cycle Updating. 231 Example of Data Update in Complementary PWM Mode . 233 Example of Initial Output in Complementary PWM Mode (1). 234 Example of Initial Output in Complementary PWM Mode (2). 235 Example of Complementary PWM Mode Waveform Output (1) . 237 Example of Complementary PWM Mode Waveform Output (2) . 237 Example of Complementary PWM Mode Waveform Output (3) . 238 Example of Complementary PWM Mode 0% and 100% Waveform Output (1) . 238 Example of Complementary PWM Mode 0% and 100% Waveform Output (2) . 239 Example of Complementary PWM Mode 0% and 100% Waveform Output (3) . 239 Example of Complementary PWM Mode 0% and 100% Waveform Output (4) . 240 Example of Complementary PWM Mode 0% and 100% Waveform Output (5) . 240 Example of Toggle Output Waveform Synchronized with PWM Output. 241 Counter Clearing Synchronized with Another Channel . 242 Example of Output Phase Switching by External Input (1). 243 Example of Output Phase Switching by External Input (2). 244 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (1). 244 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (2). 245 Count Timing in Internal Clock Operation. 250 Count Timing in External Clock Operation. 250 Count Timing in External Clock Operation (Phase Counting Mode). 251 Output Compare Output Timing (Normal Mode/PWM Mode). 251 Output Compare Output Timing (Complementary PWM Mode/Reset Synchronous PWM Mode) . 252 Input Capture Input Signal Timing. 252 Counter Clear Timing (Compare Match) . 253 Counter Clear Timing (Input Capture) . 253 Buffer Operation Timing (Compare Match). 254 Buffer Operation Timing (Input Capture) . 254 TGI Interrupt Timing (Compare Match) . 255 TGI Interrupt Timing (Input Capture) . 255 TCIV Interrupt Setting Timing. 256 TCIU Interrupt Setting Timing. 256 Timing for Status Flag Clearing by the CPU. 257 Rev. 2.00, 09/04, page xxvii of xl Figure 10.69 Figure 10.70 Figure 10.71 Figure 10.72 Figure 10.73 Figure 10.74 Figure 10.75 Timing for Status Flag Clearing by DTC Activation . 257 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode . 258 Contention between TCNT Write and Clear Operations. 259 Contention between TCNT Write and Increment Operations . 260 Contention between TGR Write and Compare Match . 261 Contention between Buffer Register Write and Compare Match (Channel 0) . 262 Contention between Buffer Register Write and Compare Match (Channels 3 and 4). 263 Figure 10.76 Contention between TGR Read and Input Capture . 264 Figure 10.77 Contention between TGR Write and Input Capture . 265 Figure 10.78 Contention between Buffer Register Write and Input Capture. 266 Figure 10.79 TCNT_2 Write and Overflow/Underflow Contention with Cascade Connection . 267 Figure 10.80 Counter Value during Complementary PWM Mode Stop . 268 Figure 10.81 Buffer Operation and Compare-Match Flags in Reset Sync PWM Mode. 269 Figure 10.82 Reset Sync PWM Mode Overflow Flag . 270 Figure 10.83 Contention between Overflow and Counter Clearing . 271 Figure 10.84 Contention between TCNT Write and Overflow. 272 Figure 10.85 Error Occurrence in Normal Mode, Recovery in Normal Mode. 277 Figure 10.86 Error Occurrence in Normal Mode, Recovery in PWM Mode 1. 278 Figure 10.87 Error Occurrence in Normal Mode, Recovery in PWM Mode 2. 279 Figure 10.88 Error Occurrence in Normal Mode, Recovery in Phase Counting Mode . 280 Figure 10.89 Error Occurrence in Normal Mode, Recovery in Complementary PWM Mode . 281 Figure 10.90 Error Occurrence in Normal Mode, Recovery in Reset-Synchronous PWM Mode . 282 Figure 10.91 Error Occurrence in PWM Mode 1, Recovery in Normal Mode. 283 Figure 10.92 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 1 . 284 Figure 10.93 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 2 . 285 Figure 10.94 Error Occurrence in PWM Mode 1, Recovery in Phase Counting Mode. 286 Figure 10.95 Error Occurrence in PWM Mode 1, Recovery in Complementary PWM Mode. 287 Figure 10.96 Error Occurrence in PWM Mode 1, Recovery in Reset-Synchronous PWM Mode . 288 Figure 10.97 Error Occurrence in PWM Mode 2, Recovery in Normal Mode. 289 Figure 10.98 Error Occurrence in PWM Mode 2, Recovery in PWM Mode 1 . 290 Figure 10.99 Error Occurrence in PWM Mode 2, Recovery in PWM Mode 2 . 291 Figure 10.100 Error Occurrence in PWM Mode 2, Recovery in Phase Counting Mode. 292 Figure 10.101 Error Occurrence in Phase Counting Mode, Recovery in Normal Mode . 293 Figure 10.102 Error Occurrence in Phase Counting Mode, Recovery in PWM Mode 1. 294 Figure 10.103 Error Occurrence in Phase Counting Mode, Recovery in PWM Mode 2. 295 Figure 10.104 Error Occurrence in Phase Counting Mode, Recovery in Phase Counting Mode. 296 Figure 10.105 Error Occurrence in Complementary PWM Mode, Recovery in Normal Mode . 297 Rev. 2.00, 09/04, page xxviii of xl Figure 10.106 Error Occurrence in Complementary PWM Mode, Recovery in PWM Mode 1 . 298 Figure 10.107 Error Occurrence in Complementary PWM Mode, Recovery in Complementary PWM Mode . 299 Figure 10.108 Error Occurrence in Complementary PWM Mode, Recovery in Complementary PWM Mode . 300 Figure 10.109 Error Occurrence in Complementary PWM Mode, Recovery in Reset-Synchronous PWM Mode . 301 Figure 10.110 Error Occurrence in Reset-Synchronous PWM Mode, Recovery in Normal Mode . 302 Figure 10.111 Error Occurrence in Reset-Synchronous PWM Mode, Recovery in PWM Mode 1 . 303 Figure 10.112 Error Occurrence in Reset-Synchronous PWM Mode, Recovery in Complementary PWM Mode . 304 Figure 10.113 Error Occurrence in Reset-Synchronous PWM Mode, Recovery in Reset-Synchronous PWM Mode. 305 Figure 10.114 POE Block Diagram. 307 Figure 10.115 Low-Level Detection Operation. 313 Figure 10.116 Output-Level Detection Operation . 314 Figure 10.117 Falling Edge Detection Operation . 315 Section 11 Figure 11.1 Figure 11.2 Figure 11.3 Figure 11.4 Figure 11.5 Figure 11.6 Figure 11.7 Figure 11.8 Figure 11.9 Watchdog Timer Block Diagram of WDT . 318 Operation in Watchdog Timer Mode. 323 Operation in Interval Time