R8A66597FP/DFP/BG REJ03F0229-0101 R8A66597 R8A66597FP/DFP PLQP0080LA-A - Datasheet Archive

 

ASSP (USB2.0 2 Port Host/1 Port Peripheral Controller) REJ03F0229-0101 Rev1.01 Oct 17, 2008 1 Overview 1.1 Overview The R8A66597

 

R8A66597FP/DFP/BG R8A66597FP/DFP/BG ASSP (USB2.0 2 Port Host/1 Port Peripheral Controller) REJ03F0229-0101 REJ03F0229-0101 Rev1.01 Oct 17, 2008 1 Overview 1.1 Overview The R8A66597 R8A66597 is a Universal Serial Bus (USB) Controller equipped with USB Host functions and Peripheral functions applicable for On-The-Go. When selecting the Host Controller function, it has two USB ports available for Hi-Speed, Full-Speed, and Low-Speed transfer compliant with USB Specification Revision 2.0. When selecting the Peripheral Controller function, it has one USB port available for Hi-Speed and Full-Speed transfer compliant with USB Specification Revision 2.0. This controller has a built-in USB transceiver and is compatible with all the transfer types defined in USB Specification Revision 2.0. The internal buffer memory is 8.5K, and a maximum ten pipes can be used for transferring data. For Pipe1 to Pipe9, any endpoint address can be assigned matching the peripheral functions for communication or user system. Separate bus or multiplex bus can be selected for the CPU connection. A split bus interface (exclusively for the DMA interface) that is different from the CPU bus interface is provided and is suitable for systems demanding high-performance data transfer. 1.2 Features 1.2.1 Built-in Host Controller and Peripheral Controller compatible with Hi-Speed USB · · · 1.2.2 Built-in USB Host Controller and Peripheral Controller Toggle between USB Host functions and Peripheral functions is possible according to what is written to the register Built-in USB transceiver Low power consumption · · · · 1.2.3 1.5V core power consumes less power when operating With the installed Low Power Sleep Mode functions, less power is consumed when the USB is not in use, which is also applicable for portable devices Standby power consumption can be greatly reduced by keeping only the VIF power source ON when not using the USB function. Operational with a 3.3V single power supply using the internal 1.5V core power regulator Space-saving package · Rev1.01 Few external devices and space-saving package VBUS signal can be connected directly to the controller input pin Built-in D+ pull-up resistor (for Peripheral function) Built-in D+ and D- pull-down resistors (for Host function) Built-in D+ and D- terminating resistors (for Hi-Speed operations) Built-in D+ and D- output resistors (for Full-Speed and Low-Speed operations) Oct 17, 2008 page 1 of 183 R8A66597FP/DFP/BG R8A66597FP/DFP/BG 1.2.4 Compatible with all USB transfer types · 1.2.5 Compatible with all USB transfer types, including isochronous transfer Control transfer Bulk transfer Interrupt transfer (not compatible with high-bandwidth) Isochronous transfer (not compatible with high-bandwidth) Bus interface · · · · 1.2.6 16-bit CPU bus interface Compatible with 16-bit separate bus/16-bit multiplex bus Compatible with DMA transfer in 8-bit/16-bit access (slave function) 8-bit split bus (exclusive for external direct memory access controller (DMAC) interface Built-in two DMA interface channels DMA transfer provides 40MB/second high-performance data transfer Pipe configuration · · · · · 1.2.7 Built-in 8.5KB buffer memory for USB communication Maximum of ten pipes can be selected (including default control pipe) Programmable pipe configuration Any endpoint address can be assigned to Pipe1 to Pipe9 Transfer conditions that can be written for each pipe Pipe0: Control transfer, single buffer fixed at 256 bytes Pipe1~Pipe2: Bulk transfer/Isochronous transfer, continuous transfer modes. programmable buffer size (specifiable up to 2K bytes per side, double buffer also specifiable) Pipe3~Pipe5: Bulk transfer, continuous transfer modes, programmable buffer size (specifiable up to 2K bytes per side, double buffer also specifiable) Pipe6~Pipe9: Interrupt transfer, single buffer fixed at 64 bytes Features when selecting Host functions · · · · · 1.2.8 Compatible with Hi-Speed (480Mbps), Full-Speed (12Mbps) and Low-Speed transfer (1.5Mbps) Several Peripheral devices can be connected through one tier hub Reset handshake auto response SOF and packet transmission schedule automation Transfer interval setup function for Isochronous and Interrupt transfer Features when selecting Peripheral functions · · · · · · · 1.2.9 Compatible with Hi-Speed (480Mbps) and Full-Speed transfer (12Mbps) Auto identification of Hi-Speed or Full-Speed operations according to reset handshake auto response Control transfer stage management function Device state management function Auto response function related to SET_ADDRESS request NAK response interrupt function (NRDY) SOF interpolation function Functions that Provide On-The-Go Support · · Built-in ID pin and ID pin monitor bit enables determination of A-Device/B-Device at start-up Built-in control bit facilitates Host Negotiation Protocol 1.2.10 Other functions · · · · · · · · · Rev1.01 Compatible with the CPU of big-endian or little-endian according to the byte-endian swap function Transfer end function according to transaction count End function of DMA transfer by external trigger (DEND pin) SOF plus output function Three types of input clock can be selected by built-in PLL Select from 48MHz/24MHz/12MHz Function to modify the BRDY interrupt event notification timing (BFRE) Function to clear the auto buffer memory after the pipe data specified in the DxFIFO port is read (DCLRM) Function to provide the auto clock from clock stop status NAK setting function (SHTNAK) for PID response corresponding to transfer end Oct 17, 2008 Page 2 of 183 Confidential R8A66597FP/DFP/BG R8A66597FP/DFP/BG 1.2.11 Usage Navigation systems, DVD recorders, set-top boxes, audio devices, printers, external storage devices and other devices equipped with USB Rev1.01 Oct 17, 2008 Page 3 of 183 Confidential R8A66597FP/DFP/BG R8A66597FP/DFP/BG 1.3 Package 1.3.1 Pin Layout GND VBUS RST_N VCC MPBUS G ND A2 A1 VDD GND A3 A5 A4 A7/ALE A6 WR0_N RD_N CS_N WR1_N VIF Figure 1.1 shows the pin layout (top view) for this controller. 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 61 40 62 39 63 38 64 37 65 36 66 35 R8A66597FP/DFP R8A66597FP/DFP 67 68 34 33 69 32 70 31 TOP VIEW 71 72 30 29 73 28 74 27 75 26 76 25 77 24 78 23 79 22 80 21 The "_N" in the signal name indicates that the signal is in the "L" active state. DP0 DM0 GND DP1 DM1 VCC OVCUR0B OVCUR0A ID0 EXTLP0 VBOUT0 OVCUR1 VBOUT1 REFRIN AGND AVCC XOUT XIN VCC GND 9 10 11 12 13 14 15 16 17 18 19 20 SD7 VIF 8 SD5 SD6 7 SD3 SD4 6 SD1 SD2 5 VDD GND SD0 4 DACK1_N DEND1_N 3 DEND0_N DREQ1_N 2 DREQ0_N DACK0_N VIF 1 INT_N SO F_N GND D0 D1/AD1 D2/AD2 D3/AD3 D4/AD4 D5/AD5 D6/AD6 D7/AD7 VIF GND D8 D9 D10 D11 D12 D13 D14 D15 GND Package R8A66597 R8A66597 : PLQP0080LA-A PLQP0080LA-A : 80pinLQFP (0.4mm pitch) Figure 1.1 R8A66597FP/DFP R8A66597FP/DFP Pin Layout Rev1.01 Oct 17, 2008 Page 4 of 183 Confidential R8A66597FP/DFP/BG R8A66597FP/DFP/BG R8A66597BG R8A66597BG ( TOP VIEW ) 1 2 3 4 5 6 7 8 9 A GND D15 D14 D10 GND D5/AD5 D2/AD2 D0 GND A B VIF INT_N D13 D11 VIF D4/AD4 D1/AD1 CS_N VIF B C DREQ0_N DACK0_N SOF_N D9 D7/AD7 D3/AD3 WR1_N W R0_N RD_N C D DREQ1_N DACK1_N DEND0_N D12 D8 D6/AD6 A6 A4 A5 D E GND VDD DEND1_N SD0 GND A7/ALE A3 VDD GND E F SD2 SD3 SD4 SD1 VBOUT0 A2 GND MPBUS A1 F G SD5 SD6 AVCC VBOUT1 OVCUR1 EXTLP0 ID0 RST_N VCC G H VIF SD7 XIN AGND VCC OVCUR0B OVCUR0A GND VBUS H J GND VCC XOUT REFRIN DM1 DP1 GND DM0 DP0 J 1 2 3 4 5 6 7 8 9 The "_N" in the signal name indicates that the signal is in the "L" active Package R8A66597BG R8A66597BG : PLBG0081KA-A PLBG0081KA-A : 81pinLFBGA (0.5mm pitch) Figure 1.2 R8A66597BG R8A66597BG Pin Layout Rev1.01 Oct 17, 2008 Page 5 of 183 Confidential R8A66597FP/DFP/BG R8A66597FP/DFP/BG 1.4 Pin Description Pin descriptions are given in Table 1.1, and the processing method of unused pins is given in Table 1.2. Table 1.1 Pin Description Pin Name Name Number of Pins Being Function Reset D15-0 D15-0 Data bus AD7-1 Multiplex address bus A7-1 ALE CPU bus interface CS_N RD_N WR0_N WR1_N MPBUS SPLIT bus interface SD7-0 DREQ0_N DREQ1_N DMA bus interface DACK0_N DACK1_N DEND0_N DEND1_N Interrupt/ SOF output INT_N SOF_N XIN Clock XOUT System control Rev1.01 I/O USB bus interface Oct 17, 2008 Address bus Address latch enabled Chip select I/O This is a 16-bit data bus. When selecting to the multiplex bus, these pins I/O are used in the time division as a part of the data bus (D7-D1) or address bus (A7-A1). This is the address bus. IN A0 does not exist for the 16-bit data bus. While selecting to the multiplex bus, the A7 pin IN is used as an ALE signal. IN The controller is selected in "L" level. Reads the data from the register of this controller in "L" level. D7-0 Byte write Writes D7-D0 in the register of this controller at IN strobe the rising edge. D15-8 D15-8 byte write Writes D15-D8 D15-D8 in the register of this controller IN strobe at the rising edge. This is a separate bus in "L" level. This is a Bus mode IN multiplex bus in "H" Level. Fix either "H" or "L" selection level. When the split bus is selected, it functions as Split data bus I/O the split data bus. Notifies the DMA transfer request of D0FIFO DMA request OUT port and D1FIFO port. DMA Enter the DMA acknowledgement signal of acknowledgeme IN D0FIFO port and D1FIFO port. nt For FIFO port access write direction: Receives transmission completion signal as an input DMA transfer I/O signal from other chips or CPU. end For FIFO port access read direction: Shows the last transmitted data as an output signal. Notifies various types of interrupts related to USB communication by "L" active. Active is by Interrupt OUT default "L" active, however it can be changed to "H" active by modifying the setup value of INTA bit in the software. For Host function: When the controller issues an SOF, outputs an SOF pluse SOF pulse by "L" active. OUT output For Peripheral function: When an SOF is detected, outputs an SOF pulse by "L" active. Input for Connect crystal oscillator between XIN and IN oscillation XOUT. Connect external clock signal to XIN in order to input external clock, and leave open Output for OUT XOUT. oscillation Read strobe Reset signal Page 6 of 183 IN IN Resets this controller at "L" level. 16 Immediately After Reset Classification Pin Status *5) *2) *2) Input *3) Input *3) Input Input 1 Input *4) 1 Input Input *4) Input 7 Input *4) Input *4) Input *4) Input *4) Input *1) Input *1) Input (Hi-Z) H Input (Hi-Z) H 2 Input Input 2 Input (Hi-Z) Input (Hi-Z) H H H H Input (L) Input (H) 1 1 1 8 2 1 1 1 1 1 Confidential R8A66597FP/DFP/BG R8A66597FP/DFP/BG Pin Name USB bus interface DP0 DP1 DM0 DM1 Name I/O Reset VBUS monitoring input Input (Hi-Z) 1 Input Input 2 L L 2 Input Input 1 Input Input 1 L L USB D-data I/O Connect to D- pin of USB bus. 2 REFRIN Reference input ID0 ID input External power on Overcurrent input for Port0 Overcurrent input for Port1 When Host Controller function is selected: leave open or connect directly to Vbus of USB bus. This pin cannot supply Vbus to the connected IN device. When Peripheral Controller function is selected: Connect directly to Vbus of USB bus. Can detect Vbus connection/disconnection. Connect to 5V when not connecting to Vbus. Connect to analog GND pin through 5.6k±1% IN resistor. When using USB Mini-AB receptacle, connect IN to ID pin. Used for ON/OFF output to external power circuit. Connect to external power circuit for OUT Vbus supply. VBOUT1 pin cannot be used when using DP0/DM0 as OTG. Used for input of over-current detection from external power circuit. Connect to PORT0 external power circuit. IN When input for over-current detection from external power circuit is one pin, connect to OVCUR0A and fix OVCUR0B to High or Low. Used for input of over-current detection from external power circuit. Connect to PORT1 IN external power circuit. OVCUR1 pin cannot be used when using DP0/DM0 as OTG. Used for low-power consumption mode ON/OFF switch when external power circuit OUT has low-consumption mode. Connect to PORT0 external power circuit. - Connect to 3.3V. - Connect to 3.3V. AVCC AGND VCC Control of external power for low power consumption Analog power Analog GND Power GND GND - VIF IO power - VDD Core power EXTLP0 Input (Hi-Z) 2 VBUS input OVCUR1 Input (Hi-Z) Input (Hi-Z) I/O Connect to D+ pin of USB bus. VBUS OVCUR0A Power OVCUR0B manageme nt related if USB Host Input (Hi-Z) Input (Hi-Z) USB D+ data VBOUT0 VBOUT1 Reference resistance On-The-Go related Power /GND Number of Pins Being Function Connect to 3.3V or 1.8V. Output 1.5V with internal regulator ­generated. For stability core power, Connect the 4.7uF OUT and 0.1uF capacitor between GND. No connection of external power is necessary. Immediately After Reset Classification Pin Status *5) 1 1 1 1 3 9 (FP) 10(BG) 4 2 *1) *2) *3) *4) The input level of MPBUS pin must be fixed. Do not switch the level during controller operations. Pin is for OUTPUT when CS N = "L" and RD N="L", otherwise INPUT. Hi-Z input (open) is enabled when MPBUS = "H". Maintain status (a) or (b) as described below during reset and immediately after reset release for CS_N, WR0_N and WR1_N signals. (a) CS_N = "H" (b) WR0 N = "H" and WR1_N = "H" *5) Explanations for "Pin Status" column (a) input: input port, Hi-Z status (open) disabled (b) Input (Hi-Z): input port, Hi-Z status (open) enabled (c) H, L, H/L: indicates output port status Rev1.01 Oct 17, 2008 Page 7 of 183 Confidential R8A66597FP/DFP/BG R8A66597FP/DFP/BG Table 1.2 Example of Unused R8A66597 R8A66597 Pin Classification Split Bus Interface SOF Ouptput Pin Name SD7-0 DREQ0_N, DREQ1_N DACK0_N, DACK1_N DEND0_N, DEND1_N SOF_N VBUS Monitor Input VBUS USB Host: Power Supply Management related ID0 VBOUT0, VBOUT1 OVCUR0A, OVCUR0B, OVCUR1 EXTLP0 DMA Bus Interface *1) *2) Rev1.01 Process Contents Open Open Fixed to VIF "H" level *1) Open *2) Open When using Host Function: open When using Peripheral function: Connect to VBUS signal on USB connector Fixed to "L" Open Fixed to "L" Open When not using DACKn_N pin, set DMAnCFG register DFROM bit to "000" and DACKA bit to "0" (n=0, 1) When not using DENDn_N pin, set DMAnCFG register DENDE bit to "0" (n=0, 1) Oct 17, 2008 Page 8 of 183 Confidential R8A66597FP/DFP/BG R8A66597FP/DFP/BG 1.5 Structure of Pin Functions Block diagram of the controller pin functions is shown in Figure 1.3. CPU bus interface D15-8 D15-8, D7-1(/AD7-1), D0 A7/ALE, A6-1 CS_N RD_N WR0_N WR1_N MPBUS 16 7 Clock XIN XOUT Interrupt/SOFoutput INT_N SOF_N VBUS monitoring input VBUS R8A66597 R8A66597 USB interface 0 DP0, DM0 VBOUT0 EXTLP0 OVCUR0A, OVCUR0B 2 2 DMA interface DREQ0_N DACK0_N DEND0_N DREQ1_N DACK1_N DEND1_N USB interface 1 DP1, DM1 VBOUT1 OVCUR1 2 Split bus SD7-0 On-The-Go related pin ID0 8 System control Reference resistance REFRIN RST_N Figure 1.3 Block Diagram of Pin Functions Rev1.01 Oct 17, 2008 Page 9 of 183 Confidential R8A66597FP/DFP/BG R8A66597FP/DFP/BG 1.6 Functional Overview 1.6.1 Selection of controller functions The controller can toggle between Host functions and Peripheral functions according to what is written to the register. The hardware can automatically identify the USB transmission speed, irrespective of whether the Host or Peripheral function is selected. 1.6.2 Bus interface The controller is compatible with the bus interfaces given below. 1.6.2.1 External bus interface The CPU accesses the control register of the controller using the CPU bus interface. There are two types of access below for the bus interface from the CPU. Access using a chip select pin (CS_N) and three strobe pins (RD_N, WR0_N and WR1_N). 16-bit separate bus Seven address buses (A7-1) and sixteen data buses (D15-0 D15-0) are used. 16-bit multiplex bus The ALE pin (ALE) and sixteen data buses (D15-0 D15-0) are used. The data bus uses the address and data in the time division. Separate bus or multiplex bus are selected at the MPBUS pin signal level while canceling the hardware reset. 1.6.2.2 FIFO buffer memory access method This controller is compatible with the following two access types as an access method of the FIFO buffer memory for USB data transmission. Read (write) of the data from the FIFO buffer memory is possible by accessing (read/write) the FIFO port from the CPU (DMAC). (1) CPU access Write the data in, or read the data from, the FIFO buffer memory using the address signal and control signal. (2) DMA access Write the data in the FIFO buffer memory from the CPU's built-in DMAC or dedicated DMAC, or read the data from the FIFO buffer memory. USB communication is executed by a little endian. A byte endian swap function is provided in the FIFO port access. For 16-bit access, the endian can be changed according to what is written to the register. 1.6.2.3 FIFO buffer memory access method from DMAC To access the FIFO buffer memory through the DMA access, select an access method from the following: (1) Method of using common bus with CPU (2) Method in which dedicated bus (split bus) is used 1.6.3 USB event The controller notifies the events regarding USB operations to the user system through the interrupt. It also notifies that the DMA interface can access the buffer memory of the selected pipe by asserting the DREQ signal. Depending on what the software writes, interrupt notification activation can be selected for the type and factor. Rev1.01 Oct 17, 2008 Page 10 of 183 Confidential R8A66597FP/DFP/BG R8A66597FP/DFP/BG 1.6.4 USB data transfer All types of data transfer of USB communication, such as control transfer, bulk transfer, interrupt transfer and isochronous transfer, are possible with this controller. The following are the pipe resources for each transfer type: (1) Control transfer dedicated pipe - 1 (2) Interrupt transfer dedicated pipes - 4 (3) Bulk transfer dedicated pipes - 3 (4) Bulk transfer or isochronous transfer selection pipes - 2 Write the USB transfer requirements for each pipe, such as transfer type, endpoint address, maximum packet size, etc., according to the user system. This controller is equipped with an 8.5KB buffer memory. Allocate the buffer memory according to the user system or execute the settings such as buffer operation mode, for the bulk transfer dedicated pipe, and bulk transfer or isochronous transfer selection pipe. In buffer operations mode, high-performance data transfer with low interrupt frequency is possible by using a double buffer configuration or continuous transfer function of the data packet. A transfer completion function has been added, using the transaction counter function for efficient data transfer rates of bulk and isochronous transfer pipes. The user system control CPU and DMA controller access the buffer memory through three FIFO port registers. 1.6.5 Interface for access from DMAC The DMA interface is the data transfer between the user system and this controller, in which the DxFIFO port is used, and it is a data transfer that does not use the CPU. This controller is equipped with 2-ch DMA interface and includes the following functions: (1) Transfer end notification function corresponding to the transfer end signal (DEND signal) (2) FIFO buffer auto clear function while receiving a zero-length packet This controller is equipped with an interface compatible with the two types of DMA transfers given below: (1) Cycle Steal Transfer Assert and negate of the DREQ pin is repeatedly transmitted for one data transmission (1 byte/1 word). (2) Burst Transmission This is a transmission in which the DREQ pin is asserted (not negated) until the transmission is completed, due to the pipe buffer memory area allocated to the FIFO port or DEND signal. "CS_N, RD_N and WR_N" or DACK_N can be selected as the handshake signal (pin) of the DMA interface. High-performance DMA transmission is possible in the DMA transmission by a split bus by modifying the data setup timing using an OBUS bit operation of the DMAxCFG register. 1.6.6 SOF pulse output function This controller is equipped with an SOF pulse output function that notifies the SOF packet send/receive timing. When the Host Controller function is selected, a pulse is output from the SOF_N pin at sending the SOF packet. When the Peripheral Controller function is selected, a pulse is output from the SOF_N pin at receiving the SOF packet. When the SOF packet is damaged, a pulse is output within the specified period according to the SOF interpolation timer. Rev1.01 Oct 17, 2008 Page 11 of 183 Confidential R8A66597FP/DFP/BG R8A66597FP/DFP/BG 1.6.7 Importing the external devices This controller is equipped with the external devices listed below. Also, as the VBUS pin has 5V-tolerant, the user system can connect the VBUS signal directly to this controller. (1) Resistors necessary in D+ and D-line control The following D+ and D- resistors necessary for USB communication are installed: D+ pull-up resistor (for Peripheral operations) D+ pull-down resistor (for host operations) D+ and D- termination resistors (for Hi-Speed operations) D+ and D- output resistors (for Full-Speed and Low-Speed operations) (2) 48MHz and 480MHz PLL Operations can be executed by selecting one of the three types of external clocks (12MHz/24MHz/48MHz). (3) 3.3V 1.5V regulator 1.5V core power is generated in this controller. In the system where a 3.3V interface power is used, this controller can be operated on a single power supply. Rev1.01 Oct 17, 2008 Page 12 of 183 Confidential R8A66597FP/DFP/BG R8A66597FP/DFP/BG 2 Register Design of Register Table 1 Bit number: Each register is connected to the 16-bit internal bus. Odd address are from b15 to b8, and even address are from b7 to b0. 2 Status after reset: Indicates the register initial status immediately after the reset operation. A hardware reset is the initialization status when the external reset signal is entered from the RST_N pin. A USB reset is the initialization status when a USB bus reset is detected by the controller. Significant points in the reset operation are mentioned in the notes. "-" indicates the status of retained user settings without any controller operations. "?" indicates the status when the value is not determined. 3 Software access conditions: Conditions when the register is accessed by the software. 4 Hardware access conditions: Conditions when the register is accessed by the controller during operations other than reset: R.Read only W.Write only R/W.Read/Write R(0)."0" Read only W(1)."1" Write only 5 Remarks: Remarks and detailed description item number. H.When the Host Controller function is selected P.When the Peripheral Controller function is selected 6 Name: This is the bit symbol and bit name. 7 Function: This is the description of the function. When there is no particular rejection, the value during read is the value written by the software or hardware. Example: The shaded portions are unassigned. Fix to"0". 1 Bit Number Bit Symbol 2 Hardware reset USB reset 15 ? ? 14 13 12 A bit B bit C bit 0 0 0 0 - 11 10 Bit 15 Name Unassigned. Fix to "0". 14 A bit AAA enabled 0: Operations disabled 1: Operations enabled B bit BBB operation C bit CCC control 6 0: Low output 1: High output 0: 1: 13 12 Function Rev1.01 Oct 17, 2008 page 13 of 183 8 7 6 5 4 3 2 1 Software Hardware Remarks R/W R Writing disabled when P R W R(0)/W(1) 7 Remarks 9 R 3 4 5 0 R8A66597FP/DFP/BG R8A66597FP/DFP/BG 2.1 Register List The controller register list is shown in Table 2.1. Table 2.1 Register List Address 00 02 04 06 08 0A 0C 0E 10 12 14 16 18 1A 1C 1E 20 22 24 26 28 2A 2C 2E 30 32 34 36 38 3A 3C 3E 40 42 44 46 48 4A 4C 4E 50 54 56 58 5A 5C 5E 60 62 64 66 68 6A 6C 6E 70 72 74 Rev1.01 Symbol SYSCFG0 SYSCFG1 SYSSTS0 SYSSTS1 DVSTCTR0 DVSTCTR1 TESTMODE PINCFG DMA0CFG DMA1CFG CFIFO Name System configuration control register Port1 System configuration control register Port0 System configuration status register Port1 System configuration status register Port0 Device control register Port1 Device control register Test mode register Data pin configuration register DMA0 Pin configuration register DMA1 Pin configuration register CFIFO Port register D0FIFO D0FIFO Port register D1FIFO D1FIFO Port register CFIFOSEL CFIFOCTR CFIFO Port selection register CFIFO Port control register D0FIFOSEL D0FIFOCTR D1FIFOSEL D1FIFOCTR INTENB0 INTENB1 INTENB2 BRDYENB NRDYENB BEMPENB SOFCFG D0FIFO Port selection register D0FIFO Port control register D1FIFO Port selection register D1FIFO Port control register Interrupt enable register 0 Interrupt enable register 1 Interrupt enable register 2 BRDY Interrupt enable register NRDY Interrupt enable register BEMP Interrupt enable register SOF Output configuration register INTSTS0 INTSTS1 INTSTS2 BRDYSTS NRDYSTS BEMPSTS FRMNUM UFRMNUM USBADDR USBREQ USBVAL USBINDX USBLENG DCPCFG DCPMAXP DCPCTR Interrupt status register0 Interrupt status register1 Interrupt status register2 BRDY Interrupt status register NRDY Interrupt status register BEMP Interrupt status register Frame number register Microframe number register USB address register USB request type register USB request value register USB request index register USB request length register DCP configuration register DCP maximum packet size register DCP control register PIPESEL Pipe window selection register PIPECFG PIPEBUF PIPEMAXP PIPEPERI PIPE1CTR PIPE2CTR PIPE3CTR Pipe configuration register Pipe buffer specification register Pipe maximum packet size register Pipe period control register Pipe1 Control register Pipe2 Control register Pipe3 Control register Oct 17, 2008 page 14 of 183 Index R8A66597FP/DFP/BG R8A66597FP/DFP/BG Address 76 78 7A 7C 7E 80 82-8E 82-8E 90 92 94 96 98 9A 9C 9E A0 A2 A4-CE D0 D2 D4 D6 D8 DA DC DE E0 E2 E4 E6 Symbol PIPE4CTR PIPE5CTR PIPE6CTR PIPE7CTR PIPE8CTR PIPE9CTR Pipe4 Control register Pipe5 Control register Pipe6 Control register Pipe7 Control register Pipe8 Control register Pipe9 Control register Name PIPE1TRE PIPE1TRN PIPE2TRE PIPE2TRN PIPE3TRE PIPE3TRN PIPE4TRE PIPE4TRN PIPE5TRE PIPE5TRN Pipe1 Transaction counter enabled register Pipe1 Transaction counter register Pipe2 Transaction counter enabled register Pipe2 Transaction counter register Pipe3 Transaction counter enabled register Pipe3 Transaction counter register Pipe4 Transaction counter enabled register Pipe4 Transaction counter register Pipe5 Transaction counter enabled register Pipe5 Transaction counter register DEVADD0 DEVADD1 DEVADD2 DEVADD3 DEVADD4 DEVADD7 DEVADD6 DEVADD7 DEVADD8 DEVADD9 DEVADDA Device address 0 configuration register Device address 1 configuration register Device address 2 configuration register Device address 3 configuration register Device address 4 configuration register Device address 5 configuration register Device address 6 configuration register Device address 7 configuration register Device address 8 configuration register Device address 9 configuration register Device address A configuration register Nothing is assigned to the shaded portions. Do not access. Rev1.01 Oct 17, 2008 page 15 of 183 Index R8A66597FP/DFP/BG R8A66597FP/DFP/BG 2.2 Bit Symbol List A list of controller bit symbols is shown in Table 2.2. Table 2.2 Bit Symbol List Addr 00 02 04 06 08 0A 0C 0E 10 12 14 16 18 1A 1C 1E 20 22 24 26 28 2A 2C 2E 30 32 34 36 38 3A 3C 3E 40 42 44 46 48 4A 4C 4E 50 52 54 56 58 5A 5C 5E 60 62 64 66 68 6A 6C 6E Register name 15 14 13 Odd numbers 12 11 SYSCFG0 XTAL XCKE PLLC SYSCFG1 CNTFLG SYSSTS0 OVCMON SYSSTS1 OVCMON DVSTCTR0 HNPBTOA DVSTCTR1 UTEST PINCFG LDRV DMA0CFG DREQA BURST DMA1CFG DREQA BURST CFIFO 10 9 8 6 HSE HSE SCKE 7 5 Even numbers 4 3 DCFM DRPD DPRPU PCSDIS LPSME DRPD HDDM HDDM EXTLP0 VBOUT WKUP RWUPE USBRST RESUME UACT VBOUT RWUPE USBRST RESUME UACT DACKA DACKA DFORM DFORM CFPORT D0FIFO 1 0 USBE IDMON LNST LNST RHST RHST UTST INTA OBUS OBUS DENDE DENDE D0FPORT D1FIFO DENDA PKTM DENDA PKTM 2 D1FIPORT CFIFOSEL CFIFOCTR RCNT BVAL D0FIFOSEL BIGEND RCNT BVAL RCNT BVAL VBSE REW BCLR MBW ISEL DTLN FRDY REW DCLRM DREQE MBW BIGEND BCLR FRDY D1FIFOSEL REW DCLRM DREQE MBW BIGEND D1FIFOCTR BCLR FRDY INTENB0 RSME SOFE DVSE CTRE BEMPE NRDYE BRDYE INTENB1 DTCHE ATTCHE OVRCRE BCHGE INTENB2 DTCHE ATTCHE OVRCRE BCHGE BRDYENB NRDYENB BEMPENB SOFCFG TRNENSEL D0FIFOCTR INTSTS0 INTSTS1 INTSTS2 BRDYSTS NRDYSTS BEMPSTS FRMNUM UFRMNUM USBADDR USBREQ USBVAL USBINDX USBLENG DCPCFG DCPMAXP DCPCTR VBINT RESM OVRCR BCHG OVRCR BCHG OVRN SOFR DVST DTCH DTCH CTRT ATTCH ATTCH BEMP NRDY BRDY CURPIPE CURPIPE DTLN CURPIPE DTLN EOFERRE SIGNE SACKE EOFERRE BRDYM VBSTS CRCE PIPEBRDYE PIPENRDYE PIPEBEMPE INTL EDGESTS DVSQ EOFERR SIGN SACK EOFERR PIPEBRDY PIPENRDY PIPEBEMP FRNM SOFM VALID UFRNM USBADDR bRequest bmRequestType wValue wIndex wLength CNTMD SHTNAK BSTS DEVSEL SUREQ CSCLR CSSTS DIR MXPS SQCLR SQSET SQMON PBUSY PINGE SUREQCLR CCPL PIPESEL PID PIPESEL PIPECFG PIPEBUF PIPEMAXP PIPEPERI Rev1.01 CTSQ TYPE BFRE DBLB CNTMD SHTNAK DIR BUFSIZE DEVSEL Oct 17, 2008 EPNUM BUFNMB MXPS IFIS page 16 of 183 IITV R8A66597FP/DFP/BG R8A66597FP/DFP/BG Addr Register name 15 70 PIPE1CTR 72 PIPE2CTR 74 PIPE3CTR 76 PIPE4CTR 78 PIPE5CTR 7A PIPE6CTR 7C PIPE7CTR 7E PIPE8CTR 80 PIPE9CTR 828E 90 PIPE1TRE 92 PIPE1TRN 94 PIPE2TRE 96 PIPE2TRN 98 PIPE3TRE 9A PIPE3TRN 9C PIPE4TRE 9E PIPE4TRN A0 PIPE5TRE A2 A4CE D0 D2 D4 D6 D8 DA DC DE E0 E2 E4 14 13 BSTS BSTS BSTS BSTS BSTS BSTS BSTS BSTS BSTS INBUFM INBUFM INBUFM INBUFM INBUFM CSCLR CSCLR CSCLR CSCLR CSCLR CSCLR CSCLR CSCLR CSCLR Odd numbers 12 11 CSSTS CSSTS CSSTS CSSTS CSSTS CSSTS CSSTS CSSTS CSSTS HPPHUB HPPHUB HPPHUB HPPHUB HPPHUB HPPHUB HPPHUB HPPHUB HPPHUB HPPHUB HPPHUB E6 Rev1.01 Oct 17, 2008 9 8 7 6 5 ATREPM ATREPM ATREPM ATREPM ATREPM ACLRM ACLRM ACLRM ACLRM ACLRM ACLRM ACLRM ACLRM ACLRM SQCLR SQCLR SQCLR SQCLR SQCLR SQCLR SQCLR SQCLR SQCLR SQSET SQSET SQSET SQSET SQSET SQSET SQSET SQSET SQSET SQMON SQMON SQMON SQMON SQMON SQMON SQMON SQMON SQMON PBUSY PBUSY PBUSY PBUSY PBUSY PBUSY PBUSY PBUSY PBUSY Even numbers 4 3 2 1 0 PID PID PID PID PID PID PID PID PID TRENB TRCLR TRNCNT TRENB TRCLR TRNCNT TRENB TRCLR TRNCNT TRENB TRCLR TRNCNT TRENB TRCLR TRNCNT PIPE5TRN DEVADD0 DEVADD1 DEVADD2 DEVADD3 DEVADD4 DEVADD5 DEVADD6 DEVADD7 DEVADD8 DEVADD9 DEVADDA 10 page 17 of 183 HUBPORT HUBPORT HUBPORT HUBPORT HUBPORT HUBPORT HUBPORT HUBPORT HUBPORT HUBPORT HUBPORT USBSPD USBSPD USBSPD USBSPD USBSPD USBSPD USBSPD USBSPD USBSPD USBSPD USBSPD RTPORT RTPORT RTPORT RTPORT RTPORT RTPORT RTPORT RTPORT RTPORT RTPORT RTPORT R8A66597FP/DFP/BG R8A66597FP/DFP/BG 2.3 System Configuration Control System configuration control register (SYSCFG0) 15 14 13 12 11 10 9 XTAL XCKE PLLC SCKE 0 0 0 ? 0 0 ? ? ? Bit 15-14 Name 8 ? ? 7 HSE 0 - 6 5 4 DCFM DRPD DPRPU 0 0 0 - Function XTAL XIN clock selection 13 XCKE Oscillation buffer enabled 12 Specifies the clock frequency entered from the XIN pin. 00: 12MHz input 01: 24MHz input 10: 48MHz input 11: Reserved Specifies whether the oscillation buffer operations are disabled or enabled. 0: Oscillation buffer operations disabled 1: Oscillation buffer operations enabled 3 ? ? Software 2 1 0 USBE ? ? 0 ? ? Hardware Remarks R/W R R/W R R/W R/W R/W R/W R/W R R/W R Unassigned. Fix to "0". Specifies whether 48MHz PLL operations are PLLC disabled or enabled. 11 48MHz PLL Operations enabled 0: PLL operations disabled 1: PLL operations enabled Specifies whether 48MHz clock can be provided to SCKE USB block. 10 USB block clock enabled 0: Cannot provide clock to USB block 1: Can provide clock to USB block 9-8 Unassigned. Fix to "0". Specifies whether Port0 Hi-Speed operations are disabled or enabled. 0: Hi-Speed operations disabled HSE (When a Peripheral function is selected: 7 Port0 Hi-Speed Operations Full-Speed, enabled When the Host function is selected: Full-Speed/Low-Speed) 1: Hi-Speed operations enabled (Controller detects communication speed) Specifies the controller functions. DCFM 6 0: Peripheral Controller function selection Controller functions selection 1: Host Controller function selection Specifies whether D+/D- line pull-down for the Host DRPD Controller function of Port0 is disabled or enabled. 5 D+/D-line resistance control of 0: Pull-down disabled Port0 1: Pull-down enabled Specifies D+ line pull-up for the Peripheral DPRPU Controller function of Port0 is disabled or enabled. 4 D+line resistance control 0: Pull-up disabled 1: Pull-up enabled 3-1 Unassigned. Fix to "0". Specifies USB block operations are disabled or USBE enabled. 0 USB block operations enabled 0: USB block operations disabled 1: USB block operations enabled Remarks None Rev1.01 Oct 17, 2008 page 18 of 183 R/W R R/W R R/W R H (Write to "0" when P) P (Write to "0" when H) R8A66597FP/DFP/BG R8A66597FP/DFP/BG 2.3.1 XIN clock selection bit (XTAL) In this bit, write the value corresponding to the quartz crystal or oscillator connected to the XIN pin. This controller determines the increasing multiples of 48MHz PLL according to the setup value of this bit. This bit is set immediately after a hardware reset. Do not modify it during controller operations. 2.3.2 Oscillation buffer enable bit (XCKE) Write "1" to this bit to enable the oscillation buffer operations of this controller. Write "0" to disable the oscillation buffer operations. Do not write "XCKE=0" for the time (time when "CNTFLG=1" is displayed) when clock restoration process is carried out by the controller. Write "XCKE=1" to end the clock restoration process. 2.3.3 48MHz PLL operations enabled bit (PLLC) Write "1" to this bit to enable this controller's 48MHz PLL operations. Write "0" to disable them. 2.3.4 USB block clock enabled bit (SCKE) Write "1" to this bit to enable this controller's clock supply to the USB block. Write "0" to disable it. When "0" is written to this bit, the registers that can be written to are shown in Table 2.3. Other registers cannot be written. Each register can be read when "0" is written to this bit. Table 2.3 List of Registers That Can Be Written by the Software When "SCKE=0" Address 00H 02H 0EH 2.3.5 Register name SYSCFG0 SYSCFG1 PINCFG Hi-Speed operations enabled bit (HSE) Write "1" to this bit to enable Hi-Speed operations for Port0. When "HSE=1" is written, this controller operates Port0 with Hi-Speed or Full-Speed depending on the reset handshake result. 2.3.5.1 Host Controller function selection When "HSE=0" is written, the port operates at Low-Speed or Full-Speed. When it is detected that a Low-Speed peripheral device is attached to the port, always write "HSE=0". When "HSE=1" is written, this controller executes the reset handshake protocol and, depending on its result, the port operates at Hi-Speed or Full-Speed automatically. This bit can be modified "after attach detection (ATTCH interrupt detection) and before the USB bus reset (before writing "USBRESET=1")". Rev1.01 Oct 17, 2008 page 19 of 183 R8A66597FP/DFP/BG R8A66597FP/DFP/BG 2.3.5.2 Peripheral Controller function selection When "HSE=0" is written, the controller executes Full-Speed operations. When "HSE=1" is written, the controller executes reset handshake protocol and, depending on the result, Hi-Speed or Full-Speed operations are executed automatically. This bit can be modified when "DPRPU=0". 2.3.6 Controller function selection bit (DCFM) Set this bit to specify the Host Controller function or Peripheral Controller function for the controller. This bit can be modified when "DPRPU=0" and "DRPD=0". 2.3.7 D+, D- line resistance control for Port0 (DRPD and DPRPU) Settings related to USB data bus resistance of Port0 are given in Table 2.4. Select USB data bus resistance in DRPD and DPRPU bits. Table 2.4 Port0 USB Data Bus Resistance Control Write DRPD 0 Contents DPRPU 0 0 1 1 0 1 1 D- Line Open D+ Line Open USB data bus resistance control Remarks Execute these settings when the controller is operated as the Peripheral Controller. Execute these settings when the controller is operated as the Host Pull-down Pull-down Controller. Pull-down Pull-up Write disabled Open Pull-up 2.3.7.1 Port0 pull-down resistance control (DRPD) for the Host Controller function If "1" is written to this bit while selecting the Host Controller function, the controller pulls down the Port0 D+ and Dlines. When selecting the Host Controller function, write "1" to this bit. 2.3.7.2 Port0 D+ pull-up resistance control (DPRPU) for the Peripheral Controller function If "1" is written to this bit while selecting the Peripheral Controller function, the controller pulls up the Port0 D+ line to 3.3V, and can notify the USB host of an "attach". The controller cancels the D+ line pull-up if the bit setting is changed from "1" to "0", and the status for the USB Host can be shown as detached. Set this bit to "1" when selecting the Peripheral Controller function. Rev1.01 Oct 17, 2008 page 20 of 183 R8A66597FP/DFP/BG R8A66597FP/DFP/BG 2.3.8 USB block operations enabled bit (USBE) This controller's USB block operations can be enabled/disabled by writing to this bit. If the bit is modified from "USBE=1" to "USBE=0", the controller initializes the bits shown in Table 2.5 and Table 2.6. Table 2.5 List of Registers Initialized When Writing "USBE=0" (When the Peripheral Controller function ("DCFM=0" setting) is selected) Register Name SYSSTS0 SYSSTS1 DVSTCTR0 DVSTCTR0 INTSTS0 USBADDR USBREQ USBVAL USBINDX USBLENG Bit name Remark LNST Value retained while selecting the Host Controller function RHST DVSQ USBADDR bRequest bmRequestType wValue wIndex wLength Value retained while selecting the Host Controller function Value retained while selecting the Host Controller function Value retained while selecting the Host Controller function Value retained while selecting the Host Controller function Value retained while selecting the Host Controller function Value retained while selecting the Host Controller function Table 2.6 List of Registers Initialized When Writing "USBE=0" (While the Host Controller function ("DCFM=1" setting) is selected) Register Name DVSTCTR0 DVSTCTR0 FRMNUM UFRMNUM Bit Name Remark RHST FRNM UFRNM Value retained while selecting the Peripheral Controller function Value retained while selecting the Peripheral Controller function This bit can be modified when "SCKE=1". When selecting the Host Controller function, write "DPRD=1", reject the LNST bit chattering, confirm that the USB bus is stable, and then write "USBE=1". Rev1.01 Oct 17, 2008 page 21 of 183 R8A66597FP/DFP/BG R8A66597FP/DFP/BG Port1 System configuration control register [SYSCFG1] 15 14 13 12 11 10 9 8 7 CNTFLG PCSDIS LPSME HSE ? ? ? 0 ? ? 0 0 0 ? ? ? ? ? Bit Name 6 ? ? 5 DRPD 0 - 4 3 2 ? ? ? ? 1 0 ? ? Function ? ? ? ? Software Hardware Remarks 15-13 Unassigned. Fix to "0". 12 CNTFLG Auto clock monitor Displays whether auto clock setup process is currently being executed. 0: Auto clock process complete or clock stopped 1: Auto clock processing R W R/W R R/W R 11-10 Unassigned. Fix to "0". Specifies whether restoration from low power sleep PCSDIS mode is possible due to fall in CS_N. 9 Restoration from low power sleep 0: Restoration enabled due to CS_N mode by CS N disabled 1: Restoration disabled due to CS_N Specifies whether the controller can shift to low LPSME power sleep mode when the clock is being stopped. 8 Low power sleep mode enabled 0: Low power sleep mode disabled 1: Low power sleep mode enabled Enables Port1 Hi-Speed operations when the Host HSE Controller function is selected. 7 Port1 Hi-Speed operations enabled 0: Hi-Speed operations disabled (Full-/Low-Speed) 1: Hi-Speed operations enabled (controller detects) 6 Unassigned. Fix to "0". Specifies whether D+/D- line pull-down for the Host DRPD Controller function of Port1 is disabled or enabled 5 D+/D- line resistance control of 0: Pull-down disabled Port1 1: Pull-down enabled 4-0 Unassigned. Fix to "0". R/W R/W R H (Write to "0" when P) R H (Write to "0" when P) Remarks None 2.3.9 Auto clock monitoring bit (CNTFLG) This bit sets "1" when the clock restoration process is being executed by the controller. This bit is modified from "0" to "1" when the clock restoration process by the controller is started, and after the clock is restored and when "SCKE=1", "1" is modified to "0". 2.3.10 CS_N Restoration disabled bit (PCSDIS) This bit enables or disables the falling edge of CS_N as an event to shift the controller from low power sleep mode to normal status. Refer to Table 2.7 for the difference in restoration events according to the setup value of this bit. Rev1.01 Oct 17, 2008 page 22 of 183 R8A66597FP/DFP/BG R8A66597FP/DFP/BG 2.3.11 Low power sleep mode enabled bit (LPSME) This controller enters low power sleep mode when the oscillation buffer is stopped ("XCKE=0" setting) and when "LPSME=1". The standby power can be further reduced compared to when "LPSME=0" and in the oscillation buffer stopped mode. The two types of events that help this controller restore to normal clock operating status from the low power sleep mode, which was caused by "LPSME=1" and "XCKE=0", are given below. Table 2.7 Restoration Event from Low Power Sleep Mode ("LPSME=1" and "XCKE=0") Controller Function Selection (DCFM Bit Setup Value) Conditions Restoration Events If writing "PCSDIS=1" (1) BCHG interrupt detection in the port written as "BCHGE=1" (2) CS_N signal assert by dummy reading from CPU If writing "PCSDIS=1" When selecting the Host Controller function (1) RESM interrupt detection if writing "RSME=1" (2) VBINT interrupt detection if writing "VBSE=1" (3) CS_N signal assert by dummy reading from CPU (1) RESM interrupt detection if writing "RSME=1" (2) VBINT interrupt detection if writing "VBSE=1" If writing "PCSDIS=0" When selecting the Peripheral Controller function (1) BCHG interrupt detection in the port written as "BCHGE=1" If writing "PCSDIS=0" Write "LPSME=1" when "XCKE=1". When writing "LPSME=1", writing "XCKE=0" makes this controller enter low power sleep mode, and access to the controller is disabled for 10µs. Therefore, exit from low power sleep mode with a dummy reading from the CPU after at least 10µs have elapsed after writing "XCKE=0". When the controller is shifted to low power sleep mode, the value in the FIFO buffer is lost. While using the controller with "LPSME=1", read the FIFO contents or clear the FIFO buffer before writing "XCKE=0". 2.3.12 Hi-Speed operations enabled bit (HSE) Hi-Speed operations are enabled for Port1 by writing "1" to this bit". If "HSE=1" written, the controller operates Port1 at Hi-Speed or Full-Speed according to the reset handshake result. 2.3.12.1 Selecting the Host Controller function Refer to 2.3.5.1. 2.3.12.2 Selecting the Peripheral Controller function Write "0" to this bit. Port1 cannot be used when the Peripheral Controller function is in use. 2.3.13 D+, D- line resistor control bit for Port1 (DRPD) The settings for the Port1 USB data bus resistor are shown in Table 2.8. Select the USB data bus resistance using the SYSCFG1 register DRPD bit. Table 2.8 Port1 USB Data Bus Resistance Control DRPD 0 1 D- Line Open D+ Line Open Remarks When Port1 is not used Write to this status during operations as Host Pull-down Pull-down Controller. The controller pulls down the Port1 D+ and D- lines if "1" is written to this bit when selecting the Host Controller function. Rev1.01 Oct 17, 2008 page 23 of 183 R8A66597FP/DFP/BG R8A66597FP/DFP/BG 2.4 System Configuration Status Port0 System Configuration Status Register [SYSSTS0] 15 14 13 12 11 10 9 8 OVCMON ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? Bit 15-14 Name 7 6 5 4 3 ? ? ? ? ? ? ? ? ? ? 2 1 0 IDMON LNST ? 0 0 ? ? ? Function OVCMON OVCUR0A, OVCUR0B pin monitor Software Sets the input status of OVCUR0A and OVCUR0B pins. 00: OVCUR0A=Low, OVCUR0B=Low 01: OVCUR0A=Low, OVCUR0B=High 10: OVCUR0A=High, OVCUR0B=Low 11: OVCUR0A=High, OVCUR0B=High Hardware Remarks R W Displays the status of UACT bit setting in response to Port0 operations 0: (micro) SOF issuance stopped 1: (micro) SOF issuance continued R W R W R W 13-6 Unassigned. Fix to "0". 5 SOFEA Port 0 HOST SOF active monitor 4-3 Unassigned. Fix to "0". 2 1-0 IDMON ID pin monitor LNST Port0 USB data line interface monitor Sets the input status of ID0 pin. 0: ID0=Low 1: ID0=High Sets the USB line status of Port0. Refer to the detailed explanation. Remarks None 2.4.1 OVCUR0A, OVCUR0B pin monitor bit (OVCMON) The controller sets the OVCUR0A pin status to bit 15 of this register, and the input status of OVCUR0B pin to bit 14. 2.4.2 Port0 HOST SOF Active Monitor Bit (SOFEA) When the UACT bit is set to "1" by software while the Host Controller function is valid, the controller displays "1" at this bit, puts PORT0 in the USB bus enabled status, and outputs SOF. When the UACT bit is set to "0" by software, the controller goes to the idle status after SOF is output, and displays "0" at this bit. When a suspend is executed, after the UAC bit is cleared to "0" by software, this bit can be used to confirm that the controller outputs the last SOF to Port0 2.4.3 ID0 pin monitor bit (IDMON) The controller sets the input status of the ID0 pin to this bit. 2.4.4 Line status monitor bit (LNST) USB data bus line status table of the controller is shown in Table 2.9. The controller monitors the Port0 USB data bus line status (D+ and D- line) in the SYSSTS0 register LNST bit. Refer to this LNST bit after the "attach" process (write "DPRPU=1") when the Peripheral Controller function is selected, and after pull-down is enabled (write "DRPD=1") when the Host Controller function is selected. Rev1.01 Oct 17, 2008 page 24 of 183 R8A66597FP/DFP/BG R8A66597FP/DFP/BG Table 2.9 USB Data Bus Line Status Low-Speed operations (Only Full-Speed Hi-Speed LNST [1] LNST [0] when the Host Chirp operations operations operations Controller function is selected) 0 0 SE0 SE0 Squelch Squelch 0 1 K-State J-State Unsquelch Chirp J 1 0 J-State K-State Invalid Chirp K 1 1 SE1 SE1 Invalid Invalid Chirp: Reset handshake protocol being executed in Hi-Speed operations enabled status (HSE="1") Squelch: SE0 or idle status Unsquelch: Hi-Speed J State or Hi-Speed K State Chirp J: Chirp J-State Chirp K: Chirp K-State Rev1.01 Oct 17, 2008 page 25 of 183 R8A66597FP/DFP/BG R8A66597FP/DFP/BG Port1 System Configuration Status Register [SYSSTS1] 15 14 13 12 11 10 9 8 OVCMON ? 0 ? ? ? ? ? ? ? 0 ? ? ? ? ? ? Bit Name 7 6 ? ? ? ? 5 SOFEA 0 ? 4 3 2 ? ? ? ? ? ? 1 0 LNST 0 0 ? ? Function Sets the status of OVCUR1 pin in bit 15. Bit 14 is fixed to "0". 00: OVCUR1=Low 10: OVCUR1=High OVCMON 15-14 OVCUR1 pin monitor Software Hardware Remarks R W Displays the status of UACT bit setting in response to Port1 operations 0: (micro) SOF issuance stopped 1: (micro) SOF issuance continued R W 13-6 Unassigned. Fix to "0". 5 4-2 1-0 SOFEA Port1 HOST SOF active monitor Unassigned. Fix to "0". LNST Port1 USB data line status monitor Sets the Port1 USB line status. Refer to the detailed explanation. R W H (Read value is invalid when P) Remarks None 2.4.5 OVCUR1 pin monitor bit (OVCMON) The controller sets the OVCUR1 pin status to bit 15 of this resister. Bit 14 is fixed to "0". 2.4.6 Port1 HOST SOF Active Monitor Bit (SOFEA) When the UACT bit is set to "1" by software while the Host Controller function is valid, the controller displays "1" at this bit, puts PORT1 in the USB bus enabled status, and outputs SOF. When the UACT bit is set to "0" by software, the controller goes to the idle status after SOF is output, and displays "0" at this bit. When a suspend is executed, after the UAC bit is cleared to "0" by software, this bit can be used to confirm that the controller outputs the last SOF to Port1 2.4.7 Line status monitor bit (LNST) The controller monitors the USB data bus line status (D+ line and D- line) of Port1 in the SYSSTS1 register LNST bit. Each LNST bit consists of two bits. Refer to Table 2.9 for the meaning of each bit. The Port1 LNST bit is valid only when the Host Controller function is selected. Refer to the LNST bit after pull-down is enabled (write "DRPD=1") while selecting the Host Controller function. Rev1.01 Oct 17, 2008 page 26 of 183 R8A66597FP/DFP/BG R8A66597FP/DFP/BG 2.5 USB Signal Control Device state control register [DVSTCTR0] 15 14 13 12 11 10 ? ? ? ? Bit ? ? ? ? 9 8 7 6 5 4 HNPBTOA EXTLP0 VBOUT WKUP RWUPE USBRST RESUME UACT 0 0 0 0 0 0 0 0 0 - Name Function 3 2 ? ? 0 - Software Hardware 15-12 Unassigned. Fix to "0". HNPBTOA Used for HNP switch from Peripheral to Host when HNP (Host Negotiation controller is used as On-The-Go (OTG) B-Device. 11 Protocol) B Device Host 0: Normal operations transition control bit 1: Enabled to from OTG Peripheral to Host EXTLP0 Controls the status to be output to the EXTLP0 pin. 10 EXTLP0 R/W pin output 0: EXTLP0 low output (default) control 1: EXTLP0 high output VBOUT Controls the status to be output to the VBOUT0 pin. 9 VBOUT0 R/W pin output 0: VBOUT0=Low output (Default) control 1: VBOUT0=High output Specifies whether the remote wakeup (resume signal output) is disabled/enabled when the Peripheral Controller WKUP 8 function is in use. R/W(1) Wakeup output 0: Remote wakeup signal not output 1: Remote wakeup signal output Specifies whether detection of remote wakeup (resume RWUPE signal output) from Peripheral Device connected to PORT0 7 Remote wakeup detection is disabled/enabled when Host Controller function is in use. R/W disabled 0: Down port remote wakeup output disabled 1: Down port remote wakeup enabled USBRST Controls the USB reset output control of Port0. 6 Port0 USB bus reset 0: Not output R/W output 1: USB bus reset output signal output Controls the resume output of Port0. RESUME 5 R/W 0: Not output Port0 resume output 1: Resume signal output Enables USB bus operations. 0: Down Port operations disabled (SOF/MicroSOF delivery UACT 4 disabled) R/W Port0 USB bus enabled 1: Down Port operations enabled (SOF/MicroSOF delivery enabled) 3 Unassigned. Fix to "0". 2-0 RHST Port0 reset handshake Displays the Port0 reset handshake status. Refer to the detailed explanation. Remarks None Rev1.01 Oct 17, 2008 page 27 of 183 1 0 RHST 0 0 - R Remarks R R R/W(0) P (Write to "0" when H) R H (Write to "0" when P) R R/W(1) R/W(0) W H (Write to "0" when P) H (Write to "0" when P) H (Write to "0" when P) R8A66597FP/DFP/BG R8A66597FP/DFP/BG 2.5.1 HNP (Host Negotiation Protocol) B-Device Transition Control Bit (HNPBTOA) When using the controller as the On-The-Go (OTG) B-Device, set this bit to "1" during the HNP switch from Peripheral to Host. When this bit is "1", the controller's internal peripheral control circuit holds the suspend status until the HNP process is completed, regardless of "DPRPU=0" or "DCFM=1" software settings. In addition, the Resume (RESM) interrupt will not be generated even if a falling edge is detected on the D+ signal. Only program this bit to "1" while operating the controller as an OTG B-Device and the Peripheral Controller Function is in the suspend status. 2.5.2 EXTLP0 Pin Output Control Bit (EXTLP0) If "1" is written to this bit, the controller outputs High from the EXTLP0 pin. If "0" is writthen to the bit, it outputs Low. 2.5.3 VBOUT Pin Output Control Bit (VBOUT0) If "1" is written to this bit, the controller outputs High from the VBOUT0 pin. If "0" is writthen to the bit, it outputs Low. 2.5.4 Remote wakeup (resume signal output) enabled/disabled bit for the Peripheral Controller function (WKUP) If "1" is written to this bit while selecting the Peripheral Controller function, the controller outputs the remote wakeup signal to the Port0 USB bus. The controller manages the output time of the remote wakeup signal. If the software writes "1" to the WKUP bit, the controller outputs a "K-State" of 10ms and then changes the setting to "WKUP=0". According to the USB Specification Revision 2.0, the USB bus idle status should be maintained for at least 5ms until the remote wakeup signal is sent. Therefore, the controller outputs a K-State after waiting for 2ms, although "WKUP=1" is written immediately after detecting the suspend status. Write "1" to the WKUP bit only when the device state is suspend ("DVSQ=1xx") and when the remote wakeup is enabled from the USB Host. Do not stop the internal clock when "1" is written to the WKUP bit, irrespective of the suspend status (write "WKUP=1" in the "SCKE=1" status). 2.5.5 Port0 remote wakeup detection disabled/enabled bit for the Host Controller function (RWUPE) If "1" is written to this bit while selecting the Host Controller function, the controller detects the remote wakeup signal (K-State during 2.5µs) from the Peripheral device connected to the port and executes the resume process (K-State drive). When "0" is written to this bit, the controller ignores the remote wakeup signal (K-State) from the Peripheral device connected to the port, irrespective of detecting it. When "1" is written to this bit, do not stop the internal clock even if it is in suspend status (keep in "SCKE=1" status). Do not reset the USB bus (write "USBRST=1") in suspend status. This is disabled in the USB Specification Revision 2.0. 2.5.6 Port0 USB bus reset output disabled/enabled bit for Host Controller function (USBRST) If writing "1" to this bit while selecting the Host Controller function, the controller drives the port SE0 drive and executes the USB bus reset process. In this case, if the HSE bit compatible to Port0 is "1", execute the reset handshake protocol. This controller continues with the SE0 output when "USBRST=1" (until the software writes "USBRST=0"). While "USBRST=1" (USB bus reset time), write the time based on the USB Specification Revision 2.0. The USB bus is not reset until this controller changes to "UACT=0" and "RESUME=0" when "1" is written to this bit in ("UACT=1") communicate or ("RESUME=1") resume status. Write "1" to the UACT bit simultaneously with the USB bus reset termination (write "USBRST=0"). Rev1.01 Oct 17, 2008 page 28 of 183 R8A66597FP/DFP/BG R8A66597FP/DFP/BG 2.5.7 Port0 resume signal output bit for the Host Controller function (RESUME) If "1" is written to this bit while selecting the Host Controller function, the controller drives Port0 to the K-State and executes resume output. The controller sets this bit to "1" when "RWUPE=1" and the remote wakeup signal is detected in the USB suspend status. The controller continues with the K-State output when "RESUME=1" (until the software writes "RESUME=0"). While "RESUME=1" (resume time), write the time based on the USB Specification Revision 2.0. Write "1" to this bit during the suspend process. Write "1" to the UACT bit and USB bus reset termination (write "USBRST=0") simultaneously. 2.5.8 Port0 USB bus operations enabled bit for the Host Controller function (UACT) If "1" is written to this bit while selecting the Host Controller function, the controller changes the status of Port0 to USB bus enabled status, outputs SOF, and sends/receives the data. Once the software writes "UACT=1", SOF output starts within one (micro) frame time. When the software writes "1" to this bit", the controller transfers to idle status after the (micro) SOF output. The controller write "1" to this bit in the following cases: (1) When the DTCH interrupt is detected during communication (if writing "UACT=1") (2) When the EOFERR interrupt is detected during communication (if writing "UACT=1") Write "1" to this bit while terminating the USB reset process (write "USBRST=0") or while terminating the suspension process (write "RESUME=0"). 2.5.9 Port0 reset handshake status bit (RHST) The controller sets the result of the Port0 reset handshake in this bit. The results of reset handshake are listed in Table 2.10. Table 2.10 USB Data Bus Line Status Bus Status When powered or during disconnect During reset handshake When connecting to Low-Speed When connecting to Full-Speed When connecting to Hi-Speed 2.5.9.1 RHST While selecting the Peripheral Controller function 000 100 010 011 Bit Value While selecting the Host Controller function 000 1xx 001 010 011 Selecting the Host Controller function While selecting the Host Controller function, the bit sets "100" when the software writes "USBRST=1". When "HSE=1" is selected for the port, the bit setss "111" when the controller detects a Chirp K from the Peripheral device. The controller writes the RHST bit value when the software writes "USBRST=0" to the port, and when the controller terminates the SE0 drive. When the software writes "UTST=1xxx" (when parameters are written for a host test), the bit sets "011". Rev1.01 Oct 17, 2008 page 29 of 183 R8A66597FP/DFP/BG R8A66597FP/DFP/BG 2.5.9.2 Selecting the Peripheral Controller function When "HSE=1" is set for the port, the bit shows "100" when the controller detects a USB bus reset. The controller then outputs Chirp K, and this bit shows "011" when Chirp JK is detected three times from the USB Host. After Chirp K is output, if it is not set to Hi-Speed within 2.5ms, the bit shows "010". When "HSE=0" is set for the port, the bit shows "010" when the controller detects the USB bus reset. A DVST interrupt is generated when the RHST bit is set to "0101" or "011" after the USB bus reset is detected by the controller. Rev1.01 Oct 17, 2008 page 30 of 183 R8A66597FP/DFP/BG R8A66597FP/DFP/BG Device state control register [DVSTCTR1] 15 14 13 12 11 10 ? ? ? ? Bit ? ? ? ? ? ? ? ? Name 9 VBOUT 0 - 8 ? ? 7 6 5 4 RWUPE USBRST RESUME UACT 0 0 0 0 - Function 3 2 ? ? 0 - 1 0 RHST 0 0 - Software Hardware Remarks 15-10 Unassigned. Fix to "0". Controls the status output to the VBOUT1 pin. VBOUT 0: VBOUT1=Low output (default) VBOUT pin output control 1: VBOUT1=High output Controls the remote wakeup detection allow/prohibited RWUPE from the Peripheral device connected to Port1. remote wakeup 7 Port1 0: Down port wakeup prohibited detection allowed 1: Down port wakeup allowed USBRST Controls the USB bus reset output of Port1. 6 Port1 USB bus reset 0: USB bus reset not output output 1: USB bus reset signal output Controls the resume output of Port1. RESUME 5 0: Resume no signal output Port1 resume output 1: Resume signal output Enables USB bus of Port1. UACT 4 0: Down port prohibited (SOF/µSOF delivery prohibited) Port1 USB bus allowed 1: Down port allowed (SOF/µSOF delivery allowed) 3 Unassigned. Fix to "0". Status or result of Port1 reset handshake of is set. 000: When powered or disconnected RHST 1xx: During reset handshake 2-0 Port1 reset handshake 001: When connecting to Low-Speed 010: When connecting to Full-Speed 011: When connecting to Hi-Speed 9 R/W R R/W R R/W R R/W R/W(1) R/W R R W H (Write to "0" when P) H (Write to "0" whenP) H (Write to "0" when P) H (Write to "0" when P) H (Write to "0" when P) Remarks None 2.5.10 Port1 remote wakeup detection allowed/prohibited bit for the Host Controller function (RWUPE) Refer to 2.5.5. 2.5.11 Port1 USB bus reset output disabled/enabled bit for the Host Controller function (USBRST) Refer to 2.5.6. 2.5.12 Port1 resume signal output bit for the Host Controller function (RESUME) Refer to 2.5.7. 2.5.13 USB bus operations enabled bit of Port1 for the Host Controller function (UACT) Refer to 2.5.8. Rev1.01 Oct 17, 2008 page 31 of 183 R8A66597FP/DFP/BG R8A66597FP/DFP/BG 2.5.14 Reset handshake status bit of Port1 (RHST) The controller displays the result of the Port1 reset handshake in this bit. The reset handshake results are shown in Table 2.10. Table 2.11 USB Data Bus Line Status Bus status When powered or disconnected During reset handshake When connecting to Low-Speed When connecting to Full-Speed When connecting to Hi-Speed RHST When the Peripheral Controller function is selected - Bit value When the Host Controller function is selected 000 1xx 001 010 011 2.5.14.1 Selecting the Host Controller function Refer to 2.5.9.1. 2.5.14.2 Selecting the Peripheral Controller function The port cannot be used while selecting the Peripheral Controller function, so do not refer to the value of this bit. Rev1.01 Oct 17, 2008 page 32 of 183 R8A66597FP/DFP/BG R8A66597FP/DFP/BG 2.6 Test Mode Test Mode Register [TESTMODE] 15 14 13 12 11 ? ? ? ? ? ? Bit ? ? ? ? 10 9 8 7 6 5 4 3 ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 - Name Function 1 0 UTST 0 0 0 - 2 Software Hardware Remarks 15-4 Unassigned. Fix it to "0". 3-0 UTST test mode Refer to detailed description. R/W R Remarks None 2.6.1 Test mode bit (UTST) The controller writes the value to this bit to output the USB test signal during Hi-Speed operations. The test mode operations of the controller are given in Table 2.12. Table 2.12 Test Mode Operations Test mode Normal operations Test_J Test_K Test_SE0_NAK Test_Packet Test_Force_Enable Reserved Rev1.01 Oct 17, 2008 UTST bit settings When the Peripheral Controller When the Host Controller function function is selected is selected 0000 0000 0001 1001 0010 1010 0011 1011 0100 1100 1101 0101-0111 1110-1111 page 33 of 183 R8A66597FP/DFP/BG R8A66597FP/DFP/BG 2.6.1.1 Selecting the Host Controller function When the Host Controller function is selected, writing to the bit is possible after writing "DRPD=1" corresponding to the test target port from Port0 and Port1. This bit is the common register for Port0 and Port1. The controller outputs the wave for the port where "DRPD=1" and "UACT=1" are written. When the Host Controller function is selected, the controller stops Hi-Speed operations for Port0 and Port1 by writing to the bit. Procedure to set the UTST bit in HOST mode is below: (1) Hardware reset (2) Clock activation (write to XTAL, wait until "XCKE=1" changes to "SCKE=1") (3) "DCFM=1" and "DPRD=1" (not necessary to write "HSE=1") (4) "USBE=1" (5) Write the value corresponding to the test contents in the UTST bit. (6) Write "1" to the UACT bit of the port to be tested Procedure to modify the UTST bit in HOST mode is below: (1) (In the status of above-mentioned (8) "UACT=0" and "USBE=0" (2) "USBE=1" (3) Write the value corresponding to the test contents in the UTST bit. (4) Write "1" to the UACT bit of the port to be tested When writing "Test_SE0_NAK" ("1011"), the controller does not output the SOF packet related to the port for which "UACT=1" was written. When writing "Test_Force_Enable" ("1101"), the controller outputs the SOF packet related to the port for which "UACT=1" is written. The controller does not control the hardware associated with the detection when the mode is set, irrespective of detecting a Hi-Speed disconnection (detecting DTCH interrupt). When selecting the Host Controller function, set all pipe PID bits to "NAK" if writing to the UTST bit. After setting the test mode, reset the hardware when using normal USB communication. 2.6.1.2 Selecting the Peripheral Controller function When the Peripheral Controller function is selected, write this bit according to the set feature request from the USB Host during Hi-Speed communication. The controller does not move to suspend status if "0001" ~ "0100" is written to the bit when the Peripheral Controller function is selected. To perform normal USB communications after the test mode is set, execute a hardware reset first. Rev1.01 Oct 17, 2008 page 34 of 183 R8A66597FP/DFP/BG R8A66597FP/DFP/BG 2.7 Bus Interface Control Data pin configuration register [PINCFG] 15 14 13 12 11 10 LDRV 0 ? ? ? ? ? ? ? ? ? ? Bit 15 9 8 7 6 5 4 3 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? Name Function LDRV Output pin drive current control 1 0 INTA ? 0 ? - Software Hardware Remarks 0: When VIF=1.6-2.0V 1: When VIF=2.7-3.6V R/W R Sets active of interrupt output from INT_N pin. 0: Low active 1: High active R/W R 14-1 Unassigned. Fix to "0". 0 INTA INT_N active settings Remarks 2.7.1 Output pin drive current control bit (LDRV) For this bit, write the value that matches the VIF power supply. The following are the output pins to be controlled using the drive current according to this bit: SD7-0, D15-0 D15-0, INT_N, DREQx_N, DENDx_N and SOF_N pins. Write to this bit after resetting the hardware and do not modify it during controller operations. 2.7.2 INT_N active setting bit (INTA) Set the active (low/high) for interrupt output from INT_N that matches the interrupt input specifications of the CPU for control. Write to this bit after resetting the hardware, and do not modify it during controller operations. Rev1.01 Oct 17, 2008 page 35 of 183 R8A66597FP/DFP/BG R8A66597FP/DFP/BG The DMA0CFG register is for the DMA0 interface input/output pin and to control the D0FIFO port. The DMA1CFG register is for the DMA1 interface input/output pin and to control the D1FIFO port. DMA0 pin configuration register [DMA0CFG] DMA1 pin configuration register [DMA1CFG] 15 14 13 12 11 10 DREQA BURST DACKA ? 0 0 ? ? 0 ? ? ? Bit Name 15 DREQA DREQx_N signal polarity selection 13 BURST Burst mode 0 - 8 DFORM 0 - 7 6 5 4 3 DENDA PKTM DENDE 0 - 0 - 0 - 0 - Function ? ? 2 OBUS 0 - ? ? Unassigned. Fix to "0". 14 9 1 0 Indicates the active of the DREQx_N pin. 0: Low active 1: High active For DxFIFO, specifies whether to access by cycle steal transfer or by burst transfer. 0: Cycle steal transfer 1: Burst transfer Software Hardware Remarks R/W R R/W R R/W R R/W R R/W R R/W R R/W R R/W R 12-11 Unassigned. Fix to "0". 10 DACKA DACKx_N signal polarity selection 9-7 DFORM DMA transfer signal selection 6 DENDA DENDx_N signal polarity selection 5 PKTM DEND output packet mode 4 DENDE DENDx_N signal enabled 3 Unassigned. Fix to "0". 2 OBUS OBUS operations disabled Specifies active of the DACKx_N pin. 0: Low active 1: High active Specifies the control signal while accessing the FIFO buffer by DMA. 000: Use address signal+RD_N/WRx_N signal (CPU bus) 010: Use DACKx_N+RD_N/WRx_N signal (CPU bus) 011: Use DACKx_N signal only (CPU bus) 100: Use DACKx_N signal (SPLIT bus) 001, 101, 110 and 111: Reserved Specifies active of DENDx_N pin 0: Low active 1: High active Specifies DEND output timing. 0: Assert DENDx_N signal in the transfer unit 1: Assert DENDx_N signal for every data transfer of the given buffer size Enables the input/output of DENDx_N signal. 0: DENDx_N signal disabled (Hi-z output) 1: DENDx_N signal enabled Disables the OBUS operations. 0: OBUS mode enabled 1: OBUS mode disabled 1-0 Unassigned. Fix to "0". Remarks None Rev1.01 Oct 17, 2008 page 36 of 183 ? ? R8A66597FP/DFP/BG R8A66597FP/DFP/BG 2.7.3 DMA signal control If transferring data using the DMA interface, use the DMAxCFG register's BURST bit, PKTM bit, DENDE bit, and OBUS bit to select the DMA interface operation (assert/negate of DREQx_N /DENDx_N signal and DMA transfer mode settings) that is configured to the user system. The DMA signal is valid for access to the FIFO buffer assigned to the pipe selected by the DxFIFOSEL register CURPIPE bit (to be mentioned later). When the status of the pipe FIFO buffer changes to buffer ready (BRDY) status, this controller asserts the DREQx_N signal if "DREQE=1". 2.7.4 DREQx_N signal polarity selection bit (DREQA) Set active of DREQx_N pin in this bit. For the FIFO port, write to this bit when "CURPIPE=000". 2.7.5 Burst mode bit (BURST) When the DMA controller executes a cycle steal transfer for DxFIFO, write "0" to this bit. The controller negates a DREQx_N signal for access to one word or one byte. When the DMA controller executes a burst transfer for DxFIFO, write "1" to this bit. The controller negates the DREQx_N signal for accessing the last one word or one byte of FIFO buffer. Do not modify the bit during pipe communication operations. 2.7.6 DACKx_N signal polarity selection bit (DACKA) In this bit, set active the DACKx_N pin. For the FIFO port, write to this bit when "CURPIPE=000". 2.7.7 DMA transfer signal selection bit (DFORM) In this bit, set the control signal while accessing the FIFO buffer with the DMA controller. For the FIFO port, write to this bit when "CURPIPE=000" 2.7.8 DENDx_N signal polarity selection bit (DENDA) In this bit, set active the DENDx_N pin. For the FIFO port, write to this bit when "CURPIPE=000". 2.7.9 DEND output packet mode bit (PKTM) Write the DEND output timing in this bit. When "0" is written to this bit, the controller asserts the DENDx_N signal when any of the following conditions are fulfilled: (1) During the last read access while reading the short packet data (2) During the last read access while reading the data completed at the transaction counter (TRNCNT) (3) If a zero-length packet is received when the FIFO buffer is empty When "1" is written to this bit, the controller asserts a DENDx_N output for every data transfer of the given FIFO buffer size. For the FIFO port, write to this bit when "CURPIPE=000". Rev1.01 Oct 17, 2008 page 37 of 183 R8A66597FP/DFP/BG R8A66597FP/DFP/BG 2.7.10 Input/Output enabled bit of the DENDx_N signal (DENDE) Set I/O enabled/disabled for the DENDx_N pin in this bit. For the FIFO port, write to this bit when "CURPIPE=000". 2.7.11 OBUS operation disabled bit (OBUS) In this bit, write OBUS operations to be enabled/disabled. When "0" is written to this bit, theSD7-0 of the split bus and DEND is always input/output enabled". When "1" is written to this bit, the SD7-0 of the split bus and DENDx_N are are enabled only when DACKx_N is active. While commonly using D0FIFO and D1FIFO in the split bus, write "1" to all the OBUS bits. Rev1.01 Oct 17, 2008 page 38 of 183 R8A66597FP/DFP/BG R8A66597FP/DFP/BG 2.8 FIFO Port CFIFO Port register [CFIFO] D0FIFO Port register [D0FIFO] D1FIFO Port register [D1FIFO] 15 14 13 12 11 0 - 0 - Bit 15-0 0 - 0 - 0 - 10 9 0 - 0 - Name FIFOPORT FIFO port 8 7 FIFOPORT 0 0 - 6 5 4 3 2 0 - 0 - 0 - 0 - 1 0 0 - Function Reads the received data from the FIFO buffer by accessing this bit, or writes the being transmitted data to the FIFO buffer. 0 - 0 - Software Hardware Remarks R/W R/W Remarks None 2.8.1 FIFO port control The Rx/Tx buffer memory of this controller is made up of a FIFO structure (FIFO buffer). Use the FIFO port register to access the FIFO buffer. The CFIFO port, D0FIFO port and D1FIFO port are the types of FIFO ports. Each FIFO port consists of port registers (CFIFO, D0FIFO and D1FIFO) that read or write the data from or to the FIFO buffer, registers (CFIFOSEL, D0FIFOSEL and D1FIFOSEL) that select the pipes assigned to FIFO port, and control registers (CFIFOCTR, D0FIFOCTR and D1FIFOCTR). The features of each FIFO port are as follows: (1) Access the FIFO buffer for DCP using the CFIFO port. (2) The FIFO buffer access using the DMA transfer can be done through the DxFIFO port. (3) DxFIFO port access by the CPU is also possible. (4) While using functions specific to the FIFO port, the pipe number (selected pipe) to be written to the CURPIPE bit cannot be modified (signal input/output to the pin related to DMA, etc.). (5) Registers containing the FIFO port do not affect the other FIFO ports. (6) Do not assign the same pipe to separate FIFO ports. (7) In the FIFO buffer status, there are two types of access rights: one assigned to the CPU, and the other to SIE. Access from the CPU is not possible when SIE has the rights to access the buffer memory. Rev1.01 Oct 17, 2008 page 39 of 183 R8A66597FP/DFP/BG R8A66597FP/DFP/BG 2.8.2 FIFO port bit (CFIFO, D0FIFO and D1FIFO) The controller accesses the FIFO buffer assigned to the pipe number written to the CURPIPE bit of various selected registers (CFIFOSEL, D0FIFOSEL or D1FIFOSEL). Access to this register is possible only when the FRDY bit of each control register (CFIFOCTR, D0FIFOCTR or D1FIFOCTR) shows "1" (or while this controller asserts DREQx_N). The valid bits of this register differ according to the setup value of the MBW and BIGEND bits. The valid bits are shown in Table 2.13. Table 2.13 FIFO Port Valid Bits MBW SetupValue 0 0 1 1 BIGEND Setup Value 0 1 0 1 b15-b8 Invalid N+0 byte N+1 byte N+0 byte b7-b0 N+0 byte Invalid N+0 byte N+1 byte If writing "MBW =0", the N+0 byte as shown in Table 2.13 can be accessed. During read, access the 16-bit width for addresses 1H, 18 H and 1AH and use them as 8-bit data on N+0 byte as shown in Table 2.13. During write, access the 16-bit width for addresses 14H, 18H and 1AH (access by asserting both WR0_N and WR1_N. In this case, the controller ignores the N+1 byte as shown in Table 2.13), or access the 8-bit width for addresses 14H, 18H and 1AH (assert only WR0_N). If writing "MBW=1", the N+0 byte shown in Table 2.13 can be accessed. During read, access the 16-bit width for addresses 14H, 18H and 1AH. During write, access the 16-bit width for addresses 14H, 18H and 1AH (access by asserting WR0_N and WR1_N). Do not access the address for 15H, 19H and 1BH. Rev1.01 Oct 17, 2008 page 40 of 183 R8A66597FP/DFP/BG R8A66597FP/DFP/BG FIFO port selection register [CFIFOSEL] 15 14 13 12 11 10 RCNT REW MBW 0 0 ? ? ? 0 ? ? ? Bit Name 15 ? ? 8 BIGEND 0 - 7 6 ? ? ? ? 5 ISEL 0 - 4 3 ? ? ? ? Function Specify read mode of CFIFOCTR DTLN. 0: DTLN bit clear by read of all the data received 1: DTLN bit count down for read of all the received data Specify "1" while rewinding the buffer pointer. 0: Do not rewind the buffer pointer 1: Rewind buffer pointer RCNT Read count mode 14 9 REW Buffer pointer rewind 1 0 CURPIPE 0 0 0 - 2 Software Hardware Remarks R/W R R(0)/W R/W(0) Specify the CFIFO port access bit width. 0: 8-bit width 1: 16-bit width R/W R Specify the CFIFO port byte endian. 0: Little endian 1: Big endian R/W R R/W R R/W R 13-11 Unassigned. Fix to "0". 10 MBW CFIFO port access bit width 9 Unassigned. Fix to "0". 8 BIGEND FIFO port endian control 7-6 Unassigned. Fix to "0". Specify access direction of the FIFO port when DCP is ISEL selected in CURPIPE bit. 5 Access direction of the FIFO 0: This selects read from the buffer memory port when DCP is selected 1: This selects write to the buffer memory 4-3 Unassigned. Fix to "0". Specify the pipe number to access the CFIFO port. 0000: DCP CURPIPE 0001: Pipe1 2-0 FIFO port access pipe 0010: Pipe2 specification 1000: Pipe8 1001: Pipe9 Remarks None Rev1.01 Oct 17, 2008 page 41 of 183 R8A66597FP/DFP/BG R8A66597FP/DFP/BG 2.8.3 Read count mode (RCNT) When "0" is written to this bit, if all reception data of the FIFO buffer assigned to the pipe specified in the CURPIPE bit is read (when the data is read on one side of a double buffer), the controller clears the CFIFOCTR register DTLN bit to "0". When "1" is written to this bit, the controller counts the CFIFOCTR register DTLN bit whenever the data received from the FIFO buffer assigned to the specified bit is read. 2.8.4 Buffer pointer rewind (REW) When the the specified pipe is receiving, if "1" is written to this bit during the FIFO buffer read, the initial data of the FIFO buffer can be read (for a double buffer, the initial data on one side can be read again during the read process). When the software writes "1" to this bit, the controller again writes "0" to this bit. Do not modify the "REW=1" and CURPIPE bit settings at the same time. First confirm that "FRDY=1" and then write "REW=1". Use the BLCR bit while rewriting the initial data of the FIFO buffer for the transmission pipe. 2.8.5 CFIFO Port access bit width (MBW) In this bit, set the CFIFO port access bit width. When the pipe specified in the CURPIPE bit is receiving, if read is started after writing "1" to this bit, modify the MBW bit from "1" to "0" only after all the data is read. When the DTLN bit is an odd number, write "MBW=0" and read with the variable having an 8-bit length, or read with a 16-bit maintaining "MBW=1", delete the excess byte, and then read the last byte. When the specified pipe is receiving, set the CURPIPE bit and MBW bit simultaneously. When the the specified pipe is transmitting, to start writing the data having an odd number of bytes by writing "1" to this bit, write "MBW=0" and write with the variable having a 16-bit length (refer to 2.8.2 for the data to be written), or write with the variable having an 8-bit length maintaining "MBW=1", and then write the last byte (write with the WR0_N strobe if "BIGEND=0", and with the WR1_N strobe if "BIGEND=1"). 2.8.6 Control bit of CFIFO port byte endian (BIGEND) In this bit, write the CFIFO port byte endian. Refer to 2.8.2 for details. 2.8.7 FIFO port access direction specification bit when selecting DCP (ISEL) To change this bit when the specified pipe is DCP, first write the data to this bit and then read it. Proceed to the next process after checking if the written values match with the read values. When the settings of this bit are modified during access to the FIFO buffer, access up to then is saved. Access to the buffer can be continued after rewriting the settings. Write to this bit and the CURPIPE bit simultaneously. 2.8.8 FIFO port access byte specification bit (CURPIPE) Write the pipe number for the data to be read or written through the CFIFO port. When modifying this bit, first write the data and then read it. Check that the written values and the read values match, and then proceed to the next process. Do not write to the same pipe to CURPIPE of CFIFOSEL, D0FIFOSEL, and D1FIFOSEL registers. When the settings of this bit are modified during access to the FIFO buffer, access up to then is saved. Access to the buffer can be continued after rewriting the settings. Rev1.01 Oct 17, 2008 page 42 of 183 R8A66597FP/DFP/BG R8A66597FP/DFP/BG D0FIFO port selection register [D0FIFOSEL] D1FIFO port selection register [D1FIFOSEL] 15 14 13 12 11 10 RCNT REW DCLRM DREQE MBW 0 0 0 0 ? 0 ? Bit 9 ? ? 8 BIGEND 0 - 7 6 5 4 3 ? ? ? ? ? ? ? ? ? ? 2 1 0 CURPIPE 0 0 0 - Name Function Software Hardware Remarks Specify the read mode of Dx_FIFOCTR DTLN. 0: The DTLN bit is cleared when all the reception data has RCNT 15 been read R/W R Read count mode 1: The DTLN bit is decremented when the reception data is read Specify "1" to rewind the buffer pointer. REW 0: Invalid R(0)/W R/W(0) 14 Buffer pointer rewind 1: The buffer pointer is rewound DCLRM Specify whether auto buffer memory clear is This is the auto buffer memory disabled/enabled after the data for the specified pipe has 13 clear mode accessed after the been read. R/W R data for the specified pipe has 0: Auto buffer clear mode is disabled been read. 1: Auto buffer clear mode is enabled Specify whether the DREQ signal is disabled/enabled. DREQE 0: Output is disabled 12 R/W R DREQ signal output enabled 1: Output is enabled 11 Unassigned. Fix to "0". Specify the FIFO port access bit width. MBW 0: 8-bit width 10 R/W R FIFO port access bit width 1: 16-bit width 9 Nothing is assigned. Fix to "0". Specify the byte endian of each FIFO port. BIGEND 0: Little endian R/W R 8 FIFO port endian control 1: Big endian 7-4 Unassigned. Fix to "0". CURPIPE 3-0 FIFO port access pipe specification 0000: No specification 0001: Pipe1 0010: Pipe2 R/W R 1000: Pipe8 1001: Pipe9 Remarks None 2.8.9 Read count mode (RCNT) When "1" is written to this bit, if all reception data of the FIFO buffer assigned to the pipe specified in the CURPIPE bit is read (for a double buffer, when the data on one side is read), the controller clears the DxFIFOCTR register DTLN bit to "0". When "1" is written to this bit, the controller counts the DxFIFOCTR register DTLN bits each time during the reception data read of the FIFO buffer assigned to the specified pipe. Write "0" to this bit to access DxFIFO by writing "1" to the BFRE bit. Rev1.01 Oct 17, 2008 page 43 of 183 R8A66597FP/DFP/BG R8A66597FP/DFP/BG 2.8.10 Buffer pointer rewind (REW) When the specified pipe is receiving, if "1" is written to this bit during the FIFO buffer read, the read can be started from the initial data of the FIFO buffer (for a double buffer, during the read process, the initial data on one side can be read again). When the software writes "1" to this bit, the controller again writes "0" to this bit. Do not write "REW=1" and modify the CURPIPE bit. First check "FRDY=1" and then write "REW=1". While accessing DxFIFO by writing "1" to the BFRE bit, do not write "1" to this bit when the short packet data is read. Use the BLCR bit while rewriting the initial data of the FIFO buffer for the transmission pipe. 2.8.11 Auto FIFO buffer clear disabled/enabled bit (DCLRM) After reading the specified pipe data, set disabled/enabled for the auto FIFO buffer clear. When "1" is written to this bit, the controller executes a "BCLR=1" process of the FIFO buffer if a zero-length packet is received when the FIFO buffer assigned to the specified pipe is empty, or when the short packet reception data is read if writing "BFRE=1". If "BRDYM=1" is written when using this controller, make sure to write "0" to this bit. 2.8.12 DREQx_N output disabled/enabled bit (DREQE) Write this bit so that the DxREQ_N signal output can be disabled/enabled. When the DxREQ_N signal output is enabled, write "1" to this bit after writing to the CURPIPE bit. Write "0" to this bit and then modify the CURPIPE bit. 2.8.13 DxFIFO port access bit width (MBW) Write the DxFIFO port access bit width in this bit. Refer to 2.8.5 for details. 2.8.14 Control bit of DxFIFO port byte endian (BIGEND) Write the DxFIFO port byte endian in this bit. Refer to 2.8.2 for details. 2.8.15 FIFO port access pipe specification bit (CURPIPE) Write the pipe number for the data to be read or written through the DxFIFO port. To modify this bit, first write the data to this bit and then read it. Check if the write value matches the read value and then proceed to the next process. Do not write the same pipe to the CFIFOSEL, D0FIFOSEL, and D1FIFOSEL registers' CURPIPE. When this bit is modified during access to the FIFO buffer, access up to then is saved. Access to the buffer can be continued after rewriting. Rev1.01 Oct 17, 2008 page 44 of 183 R8A66597FP/DFP/BG R8A66597FP/DFP/BG CFIFO port control register [CFIFOCTR] D0FIFO port control register [D0FIFOCTR] D1FIFO port control register [D1FIFOCTR] 15 14 13 12 11 10 BVAL BCLR FRDY 0 0 0 ? 0 0 ? Bit Name BVAL 15 Buffer memory valid flag 14 BCLR CPU buffer clear 13 FRDY FIFO port ready 9 8 7 6 5 4 3 2 0 - 0 - 0 - 1 0 0 - DTLN 0 - 0 - 0 - 0 - Function 0 - 0 - Software Hardware Remarks Specify "1" when write of the FIFO buffer ends on the CPU side of pipe specified in CURPIPE. R/W(1) 0: Invalid 1: Writing ended Specify "1" to clear the FIFO buffer on the CPU side of the pipe. R(0)/W(1) 0: Invalid 1: Clears the CPU buffer memory Indicates whether the FIFO port can be accessed. R 0: FIFO port access disabled 1: FIFO port access enabled R/W R/W(0) W 12 Unassigned. Fix to "0". 11-0 DTLN Reception data length Displays reception data corresponding PIPE. length of FIFO buffer for R W Remarks None 2.8.16 Buffer memory valid flag (BVAL) When the pipe specified in the CURPIPE bit is transmitting, write "1" to this bit in the cases below. The controller writes the FIFO buffer from the CPU side to the SIE side to make transmission possible. (1) To transmit the short packet, write "1" to this bit after the data is written. (2) To transmit a zero-Length packet, write "1" to this bit before writing the data to FIFO. (3) For the pipe in continuous transfer mode, write "1" to this bit after writing the maximum packet size in multiples of natural integers and data less than the buffer size. If the data of the maximum packet size is written for the pipe in continuous transfer mode, the controller writes "1" to this bit, sets the CPU FIFO buffer to the SIE side, and changes to transmission possible status. When the controller indicates "FRDY=1", write "1" to this bit. When the specified pipe is receiving, do not write "1" to this bit. Rev1.01 Oct 17, 2008 page 45 of 183 R8A66597FP/DFP/BG R8A66597FP/DFP/BG 2.8.17 CPU buffer clear bit (BCLR) If "1" is written to this bit, the controller clears the FIFO buffer on the CPU side from the FIFO buffers assigned to the specified pipe. When the setting of the FIFO buffer assigned to the specified pipe is a double buffer, the controller clears the FIFO buffer only on one side, though the buffers on both sides can be read. When the specified pipe is DCP, the controller clears the FIFO buffer when "BCLR=1", irrespective of the CPU or SIE side. To clear the buffer on the SIE side, write "BCLR=1" after writing "NAK" to the PID bit. When the specified pipe is transmitting, if "1" is written simultaneously to the BVAL and BCLR bits, the controller clears the data written previously and changes the status of the zero-length packet to transmission possible. If the specified pipe is not DCP, write "1" to this bit when the controller sets "FRDY=1". 2.8.18 FIFO port ready bit (FRDY) In this bit, the controller shows if access is possible to the FIFO port from the CPU (DMAC). In the following cases, the controller sets "FRDY=1", but cannot read the data from the FIFO port since the data is not available. In these cases, write "BCLR=1", clear the FIFO buffer, and then change the status to Data Send/Receive. (1) If a zero-length packet is received when the FIFO buffer assigned to the specified pipe is empty. (2) If "BFRE=1" is written, when the short packet is received and the data is read. 2.8.19 Reception data length bit (DTLN) The controller sets the reception data length in this bit. The value of this bit changes according to the setup value of the RCNT bit during the FIFO buffer read. (1) When "RCNT=0": The controller sets the reception data length in this bit until the CPU (DMAC) reads all the reception data on one side of the FIFO buffer. When "BFRE=1", the controller holds the reception data length until "BCLR=1", although the data is read. (2) When "RCNT=1": The controller counts the DTLN bit display during each data read (counts down by -1 when "MBW=0", and by -2 when "MBW=1"). When the data on one side of the FIFO buffer is read, the controller sets "DTLN=0". However, when the double buffer is set, and when data is received in the FIFO buffer on one side before reading the reception data on other FIFO buffer, the reception data on one side is set in the DTLN bit when read on the first side is being completed. When "RCNT=1", while reading the value of this bit during FIFO buffer read, the controller sets the updated value of this bit up to150ns after the read cycle of the FIFO port. Rev1.01 Oct 17, 2008 page 46 of 183 R8A66597FP/DFP/BG R8A66597FP/DFP/BG 2.9 Interrupts Enabled Interrupt enabled register 0 [INTENB0] 15 14 13 12 11 10 9 8 VBSE RSME SOFE DVSE CTRE BEMPE NRDYE BRDYE 0 0 0 0 0 0 0 0 Bit Name 7 6 5 4 3 2 ? ? ? ? ? ? ? ? ? ? ? ? Function Specify INT_N disabled/enabled detecting VBINT interrupts. 0: Interrupt output disabled 1: Interrupt output enabled Specify INT_N assert disabled/enabled RSME detecting RESM interrupt. Resume interrupts enabled 0: Interrupt output disabled 1: Interrupt output enabled Specify INT_N assert disabled/enabled SOFE detecting SOF interrupt. Frame number update interrupts 0: Interrupt output disabled enabled 1: Interrupt output enabled Specify INT_N assert disabled/enabled DVSE detecting DVST interrupt. Device state transition interrupts 0: Interrupt output disabled enabled 1: Interrupt output enabled Specify INT_N assert disabled/enabled CTRE detecting CTRT interrupt. Control transfer stage transition 0: Interrupt output disabled interrupts enabled 1: Interrupt output enabled Specify INT_N assert disabled/enabled BEMPE detecting BEMP interrupt. Buffer empty interrupts enabled 0: Interrupt output disabled 1: Interrupt output enabled Specify INT_N assert disabled/enabled NRDYE detecting NRDY interrupt. Buffer not ready response interrupts 0: Interrupt output disabled enabled 1: Interrupt output enabled Specify INT_N assert disabled/enabled BRDYE detecting BRDY interrupt. Buffer ready interrupts enabled 0: Interrupt output disabled 1: Interrupt output enabled Unassigned. Fix to "0". Software Hardware 13 12 11 10 9 8 7-0 ? ? ? ? Remarks while VBSE 15 VBUS interrupts enabled 14 1 0 R/W R R/W R R/W R R/W R P (Write to "0" when H) R/W R P (Write to "0" when H) R/W R R/W R R/W R while P (Write to "0" when H) while while while while while while Remarks * RESM, DVSE and CTRE bits can be written to only when the Peripheral Controller function is selected. Do not enable when the Host Controller function is selected. Rev1.01 Oct 17, 2008 page 47 of 183 R8A66597FP/DFP/BG R8A66597FP/DFP/BG Interrupt enabled register 1 [INTENB1] 15 14 13 12 11 OVRCRE BCHGE DTCHE ATTCHE 0 0 ? 0 0 ? Bit 10 9 8 7 ? ? ? ? ? ? ? ? Name 6 5 4 EOFERRE SIGNE SACKE 0 0 0 - Function Specify INT_N assert disabled/enabled while detecting Port0 OVRCR interrupt. 15 0: Interrupt output disabled 1: Interrupt output enabled Specify INT_N assert disabled/enabled while BCHGE detecting Port0 BCHG interrupt. 14 Port0 USB bus change interrupt 0: Interrupt output disabled enabled 1: Interrupt output enabled 13 Unassigned. Fix to "0". Specify INT_N assert disabled/enabled while DTCHE detecting Port0 DTCH interrupt (enabled only if 12 Port0 detach detect interrupt HOST). enabled 0: Interrupt output disabled 1: Interrupt output enabled Specify INT_N assert disabled/enabled while ATTCHE detecting Port0 ATTCH interrupt. 11 Port0 attach detect interrupt 0: Interrupt output disabled enabled 1: Interrupt output enabled 10-7 Unassigned. Fix to "0". Specify INT_N assert disabled/enabled while EOFERRE detecting Port0 EOFERR interrupt. 6 Port0 EOF error detect interrupt 0: Interrupt output disabled enabled 1: Interrupt output enabled Specify INT_N assert disabled/enabled while SIGNE detecting Port0 SIGN interrupt. 5 Port0 Setup transaction error 0: Interrupt output disabled interrupt enabled 1: Interrupt output enabled Specify INT_N assert disabled/enabled while SACKE detecting Port0 SACK interrupt. 4 Port0 Setup transaction complete 0: Interrupt output disabled interrupt enabled 1: Interrupt output enabled 3-0 Unassigned. Fix to "0". OVRCRE Port0 OVRCR interrupt enabled 3 ? ? 1 0 2 ? ? Software ? ? Hardware R/W R R/W R R/W R/W ? ? Remarks H (Write to "0" when P) H (Write to "0" when P) R H (Write to "0" when P) R H (Write to "0" when P) R/W R R/W R R/W R H (Write to "0" when P)" H (Write to "0" when P)" H (Write to "0" when P)" Remarks * The interrupt enabled by the INTENB1 register except the OVRCRE bit can be written to only when the Host Controller function is selected. Do not enable it when the Peripheral Controller function is selected. * The interrupt enabled by the OVRCRE bit can be written to only when the Host Controller function is selected or operate the controller as an OTG A-Device. Rev1.01 Oct 17, 2008 page 48 of 183 R8A66597FP/DFP/BG R8A66597FP/DFP/BG Interrupt enabled register 2 [INTENB2] 15 14 13 12 11 OVRCRE BCHGE DTCHE ATTCHE 0 0 ? 0 0 ? Bit 10 9 8 7 ? ? ? ? ? ? 6 ? ? 5 4 3 2 ? ? ? ? ? ? 1 0 ? ? EOFERRE Name 0 - Function Specify INT_N assert disabled/enabled while OVRCRE detecting Port1 OVRCR interrupt. 15 Port1 OVRCR interrupt enabled 0: Interrupt output disabled 1: Interrupt output enabled Specify INT_N assert disabled/enabled while BCHGE detecting Port1 BCHG interrupt. 14 Port1 USB bus change interrupt 0: Interrupt output disabled enabled 1: Interrupt output enabled 13 Unassigned. Fix to "0". Specify INT_N assert disabled/enabled while detecting Port1 DTCH interrupt (enabled only if DTCHE 12 HOST). Port1 detach detect interrupt enabled 0: Interrupt output disabled 1: Interrupt output enabled Specify INT_N assert disabled/enabled while ATTCHE detecting Port1 ATTCH interrupt. 11 Port1 attach detect interrupt enabled 0: Interrupt output disabled 1: Interrupt output enabled 10-7 Unassigned. Fix to "0". Specify INT_N assert disabled/enabled while EOFERRE detecting Port1 EOFERR interrupt. 6 Port1 EOF error detect interrupt 0: Interrupt output disabled enabled 1: Interrupt output enabled 5-0 Unassigned. Fix to "0". ? ? ? ? Software Hardware Remarks H (Write to "0" when P)" H (Write to "0" when P)" R/W R R/W R R/W R H (Write to "0" when P)" R H (Write to "0" when P)" R H (Write to "0" when P)" R/W R/W Remarks * The interrupt enabled by the INTENB2 register can be written to only when the Host Controller function is selected. Do not enable it when the Peripheral Controller function is selected. 2.9.1 Interrupt enabled registers 0, 1, 2 (INTENB0, INTENB1, INTENB2) When the controller detects the interrupt corresponding to the bit for which the software has written "1" to the register, the controller asserts an interrupt from the INT_N pin. The controller sets "1" to this status bit corresponding to the INTSTS0, INTSTS1 and INTSTS2 registers when the detection conditions of each interrupt factor are satisfied, irrespective of the setup value of the register (interrupt notification disabled/enabled). When the status bit of the INTSTS0, INTSTS1 and INTSTS2 registers corresponding to each interrupt factor are set to "1", if the software modifies the interrupt enabled bit corresponding to the register from "0" to "1", the controller asserts the interrupt from the INT_N pin. Rev1.01 Oct 17, 2008 page 49 of 183 R8A66597FP/DFP/BG R8A66597FP/DFP/BG BRDY interrupt enabled register [BRDYENB] 15 14 13 12 11 10 ? ? ? ? ? ? Bit ? ? ? ? ? ? 9 8 7 6 0 - 0 - 0 - 0 - Name 5 4 PIPEBRDYE 0 0 - Function 3 2 0 - 1 0 0 - 0 - 0 - Software Hardware Remarks 15-10 Unassigned. Fix to "0". PIPEBRDYE 9-0 Interrupts for enabled each pipe Specify