REJ03B0017-0301Z 64P4B 64P6N-A 64P6Q-A 64P6U-A M38034M4H-XXXSP M38034M4H-XXXFP - Datasheet Archive

 

REJ03B0017-0301Z Rev.3.01 Jun 25, 2004 SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 3803 Group (Spec. H) Mask ROM version DESCRIPTION The

 

3803 Group (Spec.H) REJ03B0017-0301Z REJ03B0017-0301Z Rev.3.01 Jun 25, 2004 SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 3803 Group (Spec. H) Mask ROM version DESCRIPTION The 3803 group (Spec. H) is the 8-bit microcomputer based on the 740 family core technology. The 3803 group (Spec. H) is designed for household products, office automation equipment, and controlling systems that require analog signal processing, including the A-D converter and D-A converters. FEATURES qBasic machine-language instructions . 71 qMinimum instruction execution time . 0.24 µs (at 16.8 MHz oscillation frequency) qMemory size ROM . 16 K to 32 K bytes RAM . 640 to 1024 bytes qProgrammable input/output ports . 56 qSoftware pull-up resistors . Built-in qInterrupts 21 sources, 16 vectors . (external 8, internal 12, software 1) qTimers . 16-bit 1 8-bit 4 (with 8-bit prescaler) qWatchdog timer . 16-bit 1 qSerial I/O . 8-bit 2 (UART or Clock-synchronized) 8-bit 1 (Clock-synchronized) qPWM . 8-bit 1 (with 8-bit prescaler) qA-D converter . 10-bit 16 channels (8-bit reading enabled) q D-A converter . 8-bit 2 channels q LED direct drive port . 8 q Clock generating circuit . Built-in 2 circuits (connect to external ceramic resonator or quartz-crystal oscillator) q Power source voltage In high-speed mode At 16.8 MHz oscillation frequency . 4.5 to 5.5 V At 12.5 MHz oscillation frequency . 4.0 to 5.5 V At 8.4 MHz oscillation frequency . 2.7 to 5.5 V At 4.2 MHz oscillation frequency . 2.2 to 5.5 V At 2.1 MHz oscillation frequency . 2.0 to 5.5 V In middle-speed mode At 16.8 MHz oscillation frequency . 4.5 to 5.5 V At 12.5 MHz oscillation frequency . 2.7 to 5.5 V At 8.4 MHz oscillation frequency . 2.2 to 5.5 V At 6.3 MHz oscillation frequency . 1.8 to 5.5 V In low-speed mode At 32 kHz oscillation frequency . 1.8 to 5.5 V q Power dissipation In high-speed mode . 40 mW (typ.) (at 16.8 MHz oscillation frequency, at 5 V power source voltage) In low-speed mode . 45 µW (typ.) (at 32 kHz oscillation frequency, at 3 V power source voltage) q Operating temperature range . ­20 to 85°C q Packages SP . 64P4B 64P4B (64-pin 750 mil SDIP) FP . 64P6N-A 64P6N-A (64-pin 14 14 mm QFP) HP . 64P6Q-A 64P6Q-A (64-pin 10 10 mm LQFP) KP . 64P6U-A 64P6U-A (64-pin 14 14 mm LQFP) Currently support products are listed below. Table 1 Support products (Mask ROM version) Product name ROM size (bytes) ROM size for User in ( ) RAM size (bytes) M38034M4H-XXXSP M38034M4H-XXXSP M38034M4H-XXXFP M38034M4H-XXXFP M38034M4H-XXXHP M38034M4H-XXXHP M38037M6H-XXXHP M38037M6H-XXXHP 640 1024 32768 (32638) 1024 M38039MFH-XXXHP M38039MFH-XXXHP 64P6N-A 64P6N-A 64P6U-A 64P6U-A 64P4B 64P4B 49152 (49022) 2048 64P6N-A 64P6N-A 64P6Q-A 64P6Q-A Under development 64P6U-A 64P6U-A M38039MFH-XXXSP M38039MFH-XXXSP M38039MFH-XXXFP M38039MFH-XXXFP 64P6Q-A 64P6Q-A 64P6Q-A 64P6Q-A M38039MCH-XXXSP M38039MCH-XXXSP M38039MCH-XXXHP M38039MCH-XXXHP M38039MCH-XXXKP M38039MCH-XXXKP 64P6N-A 64P6N-A 64P6U-A 64P6U-A 64P4B 64P4B M38037M8H-XXXKP M38037M8H-XXXKP M38039MCH-XXXFP M38039MCH-XXXFP 64P6Q-A 64P6Q-A 64P4B 64P4B 24576 (24446) M38037M8H-XXXSP M38037M8H-XXXSP M38037M8H-XXXHP M38037M8H-XXXHP 64P6N-A 64P6N-A 64P6U-A 64P6U-A M38037M6H-XXXKP M38037M6H-XXXKP M38037M8H-XXXFP M38037M8H-XXXFP Remarks 64P4B 64P4B 16384 (16254) M38034M4H-XXXKP M38034M4H-XXXKP M38037M6H-XXXSP M38037M6H-XXXSP M38037M6H-XXXFP M38037M6H-XXXFP Package 61440 (61310) M38039MFH-XXXKP M38039MFH-XXXKP 2048 64P4B 64P4B 64P6N-A 64P6N-A 64P6Q-A 64P6Q-A Under development 64P6U-A 64P6U-A Note: Electrical characteristics differ by the 3803 group standard versions and the 3803 group (spec. H). Since the 3803 group standard versions are not indicated to this data sheet, refer to "3803/3804 Group Data Sheet". Rev.3.01 Jun 25, 2004 page 1 of 103 3803 Group (Spec. H) Flash memory version 3803 Group (Spec. H) Flash memory version DESCRIPTION The 3803 group (Spec. H) flash memory version is the 8-bit microcomputer based on the 740 family core technology. The 3803 group (Spec. H) is designed for household products, office automation equipment, and controlling systems that require analog signal processing, including the A-D converter and D-A converters. FEATURES qBasic machine-language instructions . 71 qMinimum instruction execution time . 0.24 µs (at 16.8 MHz oscillation frequency) qMemory size Flash memory . 60 K bytes RAM . 2048 bytes qProgrammable input/output ports . 56 qSoftware pull-up resistors . Built-in qInterrupts 21 sources, 16 vectors . (external 8, internal 12, software 1) qTimers . 16-bit 1 8-bit 4 (with 8-bit prescaler) qWatchdog timer . 16-bit 1 qSerial I/O . 8-bit 2 (UART or Clock-synchronized) 8-bit 1 (Clock-synchronized) qPWM . 8-bit 1 (with 8-bit prescaler) qA-D converter . 10-bit 16 channels (8-bit reading enabled) qD-A converter . 8-bit 2 channels qLED direct drive port . 8 qClock generating circuit . Built-in 2 circuits (connect to external ceramic resonator or quartz-crystal oscillator) qPower source voltage In high-speed mode At 16.8 MHz oscillation frequency . 4.5 to 5.5 V At 12.5 MHz oscillation frequency . 4.0 to 5.5 V At 8.4 MHz oscillation frequency) . 2.7 to 5.5 V In middle-speed mode At 16.8 MHz oscillation frequency . 4.5 to 5.5 V At 12.5 MHz oscillation frequency . 2.7 to 5.5 V In low-speed mode At 32 kHz oscillation frequency . 2.7 to 5.5 V qPower dissipation In high-speed mode . 27.5 mW (typ.) (at 16.8 MHz oscillation frequency, at 5 V power source voltage) In low-speed mode . 1200 µW (typ.) (at 32 kHz oscillation frequency, at 3 V power source voltage) qOperating temperature range . ­20 to 85°C qPackages SP . 64P4B 64P4B (64-pin 750 mil SDIP) FP . 64P6N-A 64P6N-A (64-pin 14 14 mm QFP) HP . 64P6Q-A 64P6Q-A (64-pin 10 10 mm LQFP) KP . 64P6U-A 64P6U-A (64-pin 14 14 mm LQFP) qPower source voltage . Vcc = 2.7 to 5.5 V qProgram/Erase voltage . Vcc = 2.7 to 5.5 V qProgramming method . Programming in unit of byte qErasing method . Block erasing qProgram/Erase control by software command qNumber of times for programming/erasing . 100 sNotes The flash memory version cannot be used for application embedded in the MCU card. Currently support products are listed below. Table 2 Support products (Flash memory version) Product name Flash memory size (bytes) RAM size (bytes) Package M38039FFHSP M38039FFHSP 64P4B 64P4B M38039FFHFP M38039FFHFP 64P6N-A 64P6N-A 64P6Q-A 64P6Q-A Remarks M38039FFHHP M38039FFHHP M38039FFHKP M38039FFHKP 61440 2048 Vcc = 2.7 to 5.5 V 64P6U-A 64P6U-A M38039FFSP M38039FFSP 64P4B 64P4B M38039FFFP M38039FFFP 64P6N-A 64P6N-A M38039FFHP M38039FFHP 64P6Q-A 64P6Q-A Vcc = 4.0 to 5.5 V Note: Since description, features, and electrical charactristics etc. of M38039FFSP M38039FFSP, M38039FFFP M38039FFFP, M38039FFHP M38039FFHP are not indicated, refer to "3803/3804 group Data Sheet". Rev.3.01 Jun 25, 2004 page 2 of 103 3803 Group (Spec. H) P11/INT01 P11/INT01 P12 P13 P14 P15 P16 P17 39 38 37 36 35 34 33 P07/AN15 P07/AN15 P10/INT41 P10/INT41 40 P06/AN14 P06/AN14 42 41 P04/AN12 P04/AN12 P03/AN11 P03/AN11 45 P05/AN13 P05/AN13 P02/AN10 P02/AN10 46 43 P01/AN9 P01/AN9 47 44 P00/AN8 P00/AN8 48 PIN CONFIGURATION (TOP VIEW) P37/SRDY3 P37/SRDY3 49 32 P20(LED0) P36/SCLK3 P36/SCLK3 50 31 P21(LED1) P35/TXD3 P35/TXD3 51 30 P22(LED2) P34/RXD3 P34/RXD3 52 29 P23(LED3) P33 53 28 P24(LED4) P32 54 27 P25(LED5) P31/DA2 P31/DA2 55 26 P26(LED6) P30/DA1 P30/DA1 56 25 P27(LED7) VCC 57 24 VSS VREF 58 23 XOUT AVSS 59 22 XIN P67/AN7 P67/AN7 60 21 P40/INT40/XCOUT P40/INT40/XCOUT P66/AN6 P66/AN6 61 20 P41/INT00/XCIN P41/INT00/XCIN P65/AN5 P65/AN5 62 19 RESET P64/AN4 P64/AN4 63 18 CNVSS P63/AN3 P63/AN3 64 17 P42/INT1 P42/INT1 16 P43/INT2 P43/INT2 15 P44/RXD1 P44/RXD1 14 P45/TXD1 P45/TXD1 12 13 P47/SRDY1/CNTR2 P47/SRDY1/CNTR2 P46/SCLK1 P46/SCLK1 10 11 9 P52/SCLK2 P52/SCLK2 P50/SIN2 P50/SIN2 8 P51/SOUT2 P51/SOUT2 7 5 P56/PWM P56/PWM P53/SRDY2 P53/SRDY2 4 P57/INT3 P57/INT3 P54/CNTR0 P54/CNTR0 3 P60/AN0 P60/AN0 6 2 P61/AN1 P61/AN1 P55/CNTR1 P55/CNTR1 1 P62/AN2 P62/AN2 M38034M4H-XXXFP/HP/KP M38034M4H-XXXFP/HP/KP M38037M6H-XXXFP/HP/KP M38037M6H-XXXFP/HP/KP M38037M8H-XXXFP/HP/KP M38037M8H-XXXFP/HP/KP M38037MCH-XXXFP/HP/KP M38037MCH-XXXFP/HP/KP * M38037MFH-XXXFP/HP/KP M38037MFH-XXXFP/HP/KP * M38039FFHFP/HP/KP M38039FFHFP/HP/KP * Under development Package type : 64P6N-A/64P6Q-A/64P6U-A 64P6N-A/64P6Q-A/64P6U-A Fig. 1 3803 group (Spec. H) pin configuration Table 3 List of package (Spec. H) Package Product name * Under development ROM size (bytes) ROM size for User in ( ) RAM size (bytes) M38034M4H-XXXFP M38034M4H-XXXFP 16384 (16254) 640 M38037M6H-XXXFP M38037M6H-XXXFP 24576 (24446) 1024 M38037M8H-XXXFP M38037M8H-XXXFP 32768 (32638) 1024 M38039MCH-XXXFP M38039MCH-XXXFP* M38039MFH-XXXFP M38039MFH-XXXFP* 49152 (49022) 2048 2048 M38039FFHFP M38039FFHFP M38039FFFP M38039FFFP 61440 61440 M38034M4H-XXXHP M38034M4H-XXXHP 16384 (16254) 640 M38037M6H-XXXHP M38037M6H-XXXHP 64P6N-A 64P6N-A Remarks 24576 (24446) 1024 61440 (61310) Mask ROM version 2048 Flash memory version 2048 Flash memory version (Vcc = 4.0­5.5 V) M38037M8H-XXXHP M38037M8H-XXXHP 32768 (32638) 1024 M38039MCH-XXXHP M38039MCH-XXXHP* 49152 (49022) 2048 M38039MFH-XXXHP M38039MFH-XXXHP* 61440 (61310) 2048 M38039FFHHP M38039FFHHP 61440 2048 Flash memory version M38039FFHP M38039FFHP M38034M4H-XXXKP M38034M4H-XXXKP 64P6Q-A 64P6Q-A 61440 2048 640 Flash memory version (Vcc = 4.0­5.5 V) 16384 (16254) 24576 (24446) 32768 (32638) 1024 M38037M8H-XXXKP M38037M8H-XXXKP M38039MCH-XXXKP M38039MCH-XXXKP* 49152 (49022) 2048 M38039MFH-XXXKP M38039MFH-XXXKP* 61440 (61310) 2048 M38039FFHKP M38039FFHKP 61440 2048 M38037M6H-XXXKP M38037M6H-XXXKP 64P6U-A 64P6U-A Mask ROM version 1024 Mask ROM version Flash memory version Note: Since description, features, and electrical charactristics etc. of M38039FFFP M38039FFFP and M38039FFHP M38039FFHP are not indicated, refer to "3803/ 3804 Group Data Sheet". Rev.3.01 Jun 25, 2004 page 3 of 103 3803 Group (Spec. H) PIN CONFIGURATION (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 M38034M6H-XXXSP M38034M6H-XXXSP M38037M6H-XXXSP M38037M6H-XXXSP M38037M8H-XXXSP M38037M8H-XXXSP M38039MCH-XXXSP M38039MCH-XXXSP* M38039MFH-XXXSP M38039MFH-XXXSP* M38039FFHSP M38039FFHSP VCC VREF AVSS P67/AN7 P67/AN7 P66/AN6 P66/AN6 P65/AN5 P65/AN5 P64/AN4 P64/AN4 P63/AN3 P63/AN3 P62/AN2 P62/AN2 P61/AN1 P61/AN1 P60/AN0 P60/AN0 P57/INT3 P57/INT3 P56/PWM P56/PWM P55/CNTR1 P55/CNTR1 P54/CNTR0 P54/CNTR0 P53/SRDY2 P53/SRDY2 P52/SCLK2 P52/SCLK2 P51/SOUT2 P51/SOUT2 P50/SIN2 P50/SIN2 P47/SRDY1/CNTR2 P47/SRDY1/CNTR2 P46/SCLK1 P46/SCLK1 P45/TXD1 P45/TXD1 P44/RXD1 P44/RXD1 P43/INT2 P43/INT2 P42/INT1 P42/INT1 CNVSS RESET P41/INT00/XCIN P41/INT00/XCIN P40/INT40/XCOUT P40/INT40/XCOUT XIN XOUT VSS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P30/DA1 P30/DA1 P31/DA2 P31/DA2 P32 P33 P34/RXD3 P34/RXD3 P35/TXD3 P35/TXD3 P36/SCLK3 P36/SCLK3 P37/SRDY3 P37/SRDY3 P00/AN8 P00/AN8 P01/AN9 P01/AN9 P02/AN10 P02/AN10 P03/AN11 P03/AN11 P04/AN12 P04/AN12 P05/AN13 P05/AN13 P06/AN14 P06/AN14 P07/AN15 P07/AN15 P10/INT41 P10/INT41 P11/INT01 P11/INT01 P12 P13 P14 P15 P16 P17 P20(LED0) P21(LED1) P22(LED2) P23(LED3) P24(LED4) P25(LED5) P26(LED6) P27(LED7) * Under development Package type : 64P4B 64P4B Fig. 2 3803 group (Spec. H) pin configuration Table 4 List of package (Spec. H) Package Product name * Under development ROM size (bytes) ROM size for User in ( ) RAM size (bytes) M38034M4H-XXXSP M38034M4H-XXXSP 16384 (16254) 640 M38037M6H-XXXSP M38037M6H-XXXSP 24576 (24446) Remarks 1024 M38037M8H-XXXSP M38037M8H-XXXSP 32768 (32638) 1024 M38039MCH-XXXSP M38039MCH-XXXSP* 49152 (49022) 2048 M38039MFH-XXXSP M38039MFH-XXXSP* M38039FFHSP M38039FFHSP 61440 (61310) 61440 2048 2048 Flash memory version M38039FFSP M38039FFSP 64P4B 64P4B 61440 2048 Flash memory version (Vcc = 4.0­5.5 V) Mask ROM version Note: Since description, features, and electrical charactristics etc. of M38039FFSP M38039FFSP are not indicated, refer to "3803/3804 Group Data Sheet". Rev.3.01 Jun 25, 2004 page 4 of 103 Rev.3.01 Jun 25, 2004 31 28 29 Fig. 3 Functional block diagram page 5 of 103 3 VREF AVSS 2 A-D converter (10) I/O port P6 4 5 6 7 8 9 10 11 P6(8) Clock generating circuit 30 ROM INT3 PWM(8) I/O port P5 12 13 14 15 16 17 18 19 P5(8) SI/O2(8) A P4(8) INT00 INT00 INT1 INT2 INT40 INT40 P3(8) I/O port P4 27 I/O port P3 P2(8) I/O port P2 (LED drive) I/O port P1 I/O port P0 49 50 51 52 53 54 55 56 P0(8) Timer Y (8) Timer X (8) Timer 2 (8) Timer 1 (8) INT01 INT01 INT41 INT41 41 42 43 44 45 46 47 48 P1(8) Timer Z (16) Prescaler Y (8) Prescaler X (8) Prescaler 12 (8) CNTR2 CNTR1 26 CNVSS 33 34 35 36 37 38 39 40 CNTR0 SI/O3(8) 57 58 59 60 61 62 63 64 D-A D-A converter converter 2 (8) 1 (8) PS PC L S Y X 20 21 22 23 24 25 28 29 SI/O1(8) PC H C P U Data bus 1 32 RESET RAM Reset input V CC X IN X OUT X CIN X COUT V SS Clock Clock Sub-clock Sub-clock input output input output FUNCTIONAL BLOCK DIAGRAM (Package: 64P4B 64P4B) 3803 Group (Spec. H) FUNCTIONAL BLOCK 3803 Group (Spec. H) PIN DESCRIPTION Table 5 Pin description Pin Functions Name Function except a port function VCC, VSS Power source ·Apply voltage of 1.8 V ­ 5.5 V to Vcc, and 0 V to Vss. In the flash memory version, apply voltage of 2.7 V­5.5 V to Vcc. CNVSS CNVSS input ·This pin controls the operation mode of the chip. VREF Reference voltage ·Reference voltage input pin for A-D and D-A converters. AVSS Analog power source ·Analog power source input pin for A-D and D-A converters. RESET XIN Reset input Clock input ·Input and output pins for the clock generating circuit. XOUT Clock output ·Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency. ·Normally connected to VSS. ·Connect to VSS. ·Reset input pin for active "L". ·When an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. I/O port P0 ·8-bit CMOS I/O port. I/O port P1 P00/AN8 P00/AN8­ P07/AN15 P07/AN15 P10/INT41 P10/INT41 P11/INT01 P11/INT01 ·I/O direction register allows each pin to be individually ·Interrupt input pin programmed as either input or output. ·CMOS compatible input level. ·CMOS 3-state output structure. P12­P17 P20­P27 I/O port P2 ·Pull-up control is enabled in a bit unit. I/O port P3 P30/DA1 P30/DA1 P31/DA2 P31/DA2 ·P20­P27 are enabled to output large current for LED drive. ·D-A converter input pin ·8-bit CMOS I/O port. ·I/O direction register allows each pin to be individually programmed as either input or output. P32, P33 ·CMOS compatible input level. P34/RxD3 P35/TxD3 P36/SCLK3 P36/SCLK3 P37/SRDY3 P37/SRDY3 ·P32, P33 are N-channel open-drain output structure. ·Pull-up control of P30, P31, P34­P37 is enabled in a bit unit. I/O port P4 P42/INT1 P42/INT1 P43/INT2 P43/INT2 ·8-bit CMOS I/O port. ·Interrupt input pin ·I/O direction register allows each pin to be individually ·Sub-clock generating I/O pin programmed as either input or output. (resonator connected) ·CMOS compatible input level. ·Interrupt input pin ·CMOS 3-state output structure. ·Pull-up control is enabled in a bit unit. P44/RxD1 P45/TxD1 P46/SCLK1 P46/SCLK1 P47/SRDY1 P47/SRDY1 /CNTR2 ·Serial I/O1 function pin ·Serial I/O1, timer Z function pin P50/SIN2 P50/SIN2 P51/SOUT2 P51/SOUT2 P52/SCLK2 P52/SCLK2 P53/SRDY2 P53/SRDY2 I/O port P5 ·8-bit CMOS I/O port. ·Serial I/O2 function pin ·I/O direction register allows each pin to be individually programmed as either input or output. ·CMOS compatible input level. P54/CNTR0 P54/CNTR0 ·CMOS 3-state output structure. P55/CNTR1 P55/CNTR1 ·Pull-up control is enabled in a bit unit. P56/PWM P56/PWM P57/INT3 P57/INT3 Rev.3.01 ·Serial I/O3 function pin ·P30, P31, P34­P37 are CMOS 3-state output structure. P40/INT40/ P40/INT40/ XCOUT P41/INT00/ P41/INT00/ XCIN P60/AN0 P60/AN0­ P67/AN7 P67/AN7 ·A-D converter input pin ·Interrupt input pin ·A-D converter input pin I/O port P6 Jun 25, 2004 ·Timer X function pin ·Timer Y function pin ·PWM output pin page 6 of 103 3803 Group (Spec. H) PART NUMBERING Product name M3803 M3803 7 M 8 H ­ XXX SP Package type SP : 64P4B 64P4B FP : 64P6N-A 64P6N-A HP : 64P6Q-A 64P6Q-A KP : 64P6U-A 64P6U-A ROM number Omitted in the flash memory version. ­ : standard Omitted in the flash memory version. H­ : Minner spec. change product ROM/PROM size 9 : 36864 bytes 1 : 4096 bytes A: 40960 bytes 2 : 8192 bytes B: 45056 bytes 3 : 12288 bytes C: 49152 bytes 4 : 16384 bytes D: 53248 bytes 5 : 20480 bytes E: 57344 bytes 6 : 24576 bytes F : 61440 bytes 7 : 28672 bytes 8 : 32768 bytes The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used as a user's ROM area. However, they can be programmed or erased in the flash memory version, so that the users can use them. Memory type M : Mask ROM version F : Flash memory version RAM size 0 : 192 bytes 1 : 256 bytes 2 : 384 bytes 3 : 512 bytes 4 : 640 bytes Fig. 4 Part numbering Rev.3.01 Jun 25, 2004 page 7 of 103 5 : 768 bytes 6 : 896 bytes 7 : 1024 bytes 8 : 1536 bytes 9 : 2048 bytes 3803 Group (Spec. H) GROUP EXPANSION Packages Renesas plans to expand the 3803 group (Spec. H) as follows. Memory Size Flash memory size . 60 K bytes Mask ROM size . 16 K to 60 K bytes RAM size . 640 to 2048 bytes 64P4B 64P4B . 64-pin shrink plastic-molded DIP 64P6N-A 64P6N-A . 0.8 mm-pitch plastic molded QFP 64P6Q-A 64P6Q-A . 0.5 mm-pitch plastic molded LQFP 64P6U-A 64P6U-A . 0.8 mm-pitch plastic molded LQFP Memory Expansion Plan ROM size (bytes) : Under development : Mass production M38039FFH M38039FFH As of Jun. 2004 M38039FF M38039FF M38039MFH M38039MFH M38039MF M38039MF 60K M38039MCH M38039MCH 48K M38039MC M38039MC M38037M8H M38037M8H 32K 28K 24K M38037M6H M38037M6H 20K M38034M4H M38034M4H 16K 12K 8K 384 512 640 768 896 1024 1152 1280 1408 1536 2048 3072 4032 RAM size (bytes) Notes 1: Products under development: the development schedule and specification may be revised without notice. 2: Refer to "3803/3804 Group Data Sheet" about 3803 group products other than 3803 group (spec. H) because there are electrical characteristics differences and so on. Fig. 5 Memory expansion plan Rev.3.01 Jun 25, 2004 page 8 of 103 3803 Group (Spec. H) FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU) [Stack Pointer (S)] The 3803 group (Spec. H) uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction set. Machine-resident 740 Family instructions are as follows: The FST and SLW instructions cannot be used. The STP, WIT, MUL, and DIV instructions can be used. [Accumulator (A)] The accumulator is an 8-bit register. Data operations such as data transfer, etc. are executed mainly through the accumulator. [Index Register X (X)] The index register X is an 8-bit register. In the index addressing modes, the value of the OPERAND is added to the contents of register X and specifies the real address. [Index Register Y (Y)] The stack pointer is an 8-bit register used during subroutine calls and interrupts. This register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. The low-order 8 bits of the stack address are determined by the contents of the stack pointer. The high-order 8 bits of the stack address are determined by the stack page selection bit. If the stack page selection bit is "0" , the high-order 8 bits becomes "0016". If the stack page selection bit is "1", the high-order 8 bits becomes "0116". The operations of pushing register contents onto the stack and popping them from the stack are shown in Figure 7. Store registers other than those described in Figure 7 with program when the user needs them during interrupts or subroutine calls (see Table 6). [Program Counter (PC)] The program counter is a 16-bit counter consisting of two 8-bit registers PCH and PCL. It is used to indicate the address of the next instruction to be executed. The index register Y is an 8-bit register. In partial instruction, the value of the OPERAND is added to the contents of register Y and specifies the real address. b0 b7 A Accumulator b0 b7 X Index register X b0 b7 Y b7 Index register Y b0 S b15 b7 PCH Stack pointer b0 Program counter PCL b7 b0 N V T B D I Z C Processor status register (PS) Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag Index X mode flag Overflow flag Negative flag Fig.6 740 Family CPU register structure Rev.3.01 Jun 25, 2004 page 9 of 103 3803 Group (Spec. H) On-going Routine Interrupt request (Note) M (S) Execute JSR M (S) (PCH) (S) (S) ­ 1 M (S) (PCL) (S) Push return address on stack (S) (S)­ 1 M (S) (S) M (S) (S) Subroutine (PCL) M (S) (S) + 1 (PCH) (PCL) Push return address on stack (S) ­ 1 (PS) Push contents of processor status register on stack (S) ­ 1 I Flag is set from "0" to "1" Fetch the jump vector Execute RTI (S) + 1 (S) POP return address from stack (S) ­ 1 Interrupt Service Routine Execute RTS (S) (PCH) M (S) (S) (PS) M (S) (S) (S) + 1 (PCL) M (S) (S) (S) + 1 (PCH) Note: Condition for acceptance of an interrupt (S) + 1 M (S) POP contents of processor status register from stack POP return address from stack Interrupt enable flag is "1" Interrupt disable flag is "0" Fig. 7 Register push and pop at interrupt generation and subroutine call Table 6 Push and pop instructions of accumulator or processor status register Push instruction to stack Pop instruction from stack Accumulator PHA PLA Processor status register PHP PLP Rev.3.01 Jun 25, 2004 page 10 of 103 3803 Group (Spec. H) [Processor status register (PS)] The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch operations can be performed by testing the Carry (C) flag , Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid. ·Bit 0: Carry flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction. ·Bit 1: Zero flag (Z) The Z flag is set if the result of an immediate arithmetic operation or a data transfer is "0", and cleared if the result is anything other than "0". ·Bit 2: Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruction. Interrupts are disabled when the I flag is "1". ·Bit 3: Decimal mode flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is "0"; decimal arithmetic is executed when it is "1". Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can execute decimal arithmetic. ·Bit 4: Break flag (B) The B flag is used to indicate that the current interrupt was generated by the BRK instruction. The BRK flag in the processor status register is always "0". When the BRK instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to "1". ·Bit 5: Index X mode flag (T) When the T flag is "0", arithmetic operations are performed between accumulator and memory. When the T flag is "1", direct arithmetic operations and direct data transfers are enabled between memory locations. ·Bit 6: Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds +127 to -128. When the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag. ·Bit 7: Negative flag (N) The N flag is set if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag. Table 7 Set and clear instructions of each bit of processor status register C flag Z flag I flag D flag B flag T flag V flag N flag Set instruction SEC ­ SEI SED ­ SET ­ ­ Clear instruction CLC ­ CLI CLD ­ CLT CLV ­ Rev.3.01 Jun 25, 2004 page 11 of 103 3803 Group (Spec. H) [CPU Mode Register (CPUM)] 003B16 003B16 The CPU mode register contains the stack page selection bit, etc. The CPU mode register is allocated at address 003B16 003B16. b7 b0 1 CPU mode register (CPUM : address 003B16 003B16) Processor mode bits b1 b0 0 0 : Single-chip mode 0 1 : 1 0 : Not available 1 1 : Stack page selection bit 0 : 0 page 1 : 1 page Fix this bit to "1". Port XC switch bit 0 : I/O port function (stop oscillating) 1 : XCIN­XCOUT oscillating function Main clock (XIN­XOUT) stop bit 0 : Oscillating 1 : Stopped Main clock division ratio selection bits b7 b6 0 0 : = f(XIN)/2 (high-speed mode) 0 1 : = f(XIN)/8 (middle-speed mode) 1 0 : = f(XCIN)/2 (low-speed mode) 1 1 : Not available Fig. 8 Structure of CPU mode register Rev.3.01 Jun 25, 2004 page 12 of 103 3803 Group (Spec. H) MISRG (1) Bit 0 of address 001016: Oscillation stabilizing time set after STP instruction released bit When the MCU stops the clock oscillation by the STP instruction and the STP instruction has been released by an external interrupt source, usually, the fixed values of Timer 1 and Prescaler 12 (Timer 1 = 0116, Prescaler 12 = FF16) are automatically reloaded in order for the oscillation to stabilize. The user can inhibit the automatic setting by setting "1" to bit 0 of MISRG (address 001016). However, by setting this bit to "1", the previous values, set just before the STP instruction was executed, will remain in Timer 1 and Prescaler 12. Therefore, you will need to set an appropriate value to each register, in accordance with the oscillation stabilizing time, before executing the STP instruction. Figure 9 shows the structure of MISRG. qMiddle-speed mode automatic switch by program The middle-speed mode can also be automatically switched by program while operating in low-speed mode. By setting the middle-speed automatic switch start bit (bit 3) of MISRG (address 001016) to "1" in the condition that the middle-speed mode automatic switch set bit is "1" while operating in low-speed mode, the MCU will automatically switch to middle-speed mode. In this case, the oscillation stabilizing time of the main clock can be selected by the middle-speed automatic switch wait time set bit (bit 2) of MISRG (address 001016). (2) Bits 1, 2, 3 of address 0010 16: Middle-speed Mode Automatic Switch Function In order to switch the clock mode of an MCU which has a subclock, the following procedure is necessary: set CPU mode register (003B16 003B16) -> start main clock oscillation -> wait for oscillation stabilization -> switch to middle-speed mode (or high-speed mode). However, the 3803 group (Spec. H) has the built-in function which automatically switches from low to middle-speed mode by program. b7 b0 MISRG (MISRG : address 001016) Oscillation stabilizing time set after STP instruction released bit 0: Automatically set "0116" to Timer 1, "FF16" to Prescaler 12 1: Automatically set disabled Middle-speed mode automatic switch set bit 0: Not set automatically 1: Automatic switching enabled (Note) Middle-speed mode automatic switch wait time set bit 0: 4.5 to 5.5 machine cycles 1: 6.5 to 7.5 machine cycles Middle-speed mode automatic switch start bit (Depending on program) 0: Invalid 1: Automatic switch start (Note) Not used (return "0" when read) (Do not write "1" to this bit) Note: When automatic switch to middle-speed mode from low-speed mode occurs, the values of CPU mode register (3B16) change. Fig. 9 Structure of MISRG Rev.3.01 Jun 25, 2004 page 13 of 103 3803 Group (Spec. H) MEMORY Special Function Register (SFR) Area Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors. The Special Function Register area in the zero page contains control registers such as I/O ports and timers. Zero Page RAM Access to this area with only 2 bytes is possible in the zero page addressing mode. RAM is used for data storage and for stack area of subroutine calls and interrupts. Special Page ROM Access to this area with only 2 bytes is possible in the special page addressing mode. The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is a user area for storing programs. The reserved ROM area can program/erase in the flash memory version. RAM area RAM size (bytes) Address XXXX16 XXXX16 192 256 384 512 640 768 896 1024 1536 2048 00FF16 00FF16 013F16 013F16 01BF16 01BF16 023F16 023F16 02BF16 02BF16 033F16 033F16 03BF16 03BF16 043F16 043F16 063F16 063F16 083F16 083F16 000016 SFR area Zero page 004016 010016 RAM XXXX16 XXXX16 Not used 0FF016 0FF016 0FFF16 0FFF16 SFR area Not used YYYY16 YYYY16 ROM area Reserved ROM area ROM size (bytes) Address YYYY16 YYYY16 Address ZZZZ16 ZZZZ16 4096 8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440 F00016 F00016 E00016 E00016 D00016 D00016 C00016 C00016 B00016 B00016 A00016 A00016 900016 800016 700016 600016 500016 400016 300016 200016 100016 F08016 F08016 E08016 E08016 D08016 D08016 C08016 C08016 B08016 B08016 A08016 A08016 908016 808016 708016 608016 508016 408016 308016 208016 108016 Fig. 10 Memory map diagram Rev.3.01 Jun 25, 2004 page 14 of 103 (128 bytes) ZZZZ16 ZZZZ16 ROM FF0016 FF0016 FFDC16 FFDC16 Interrupt vector area FFFE16 FFFE16 FFFF16 FFFF16 Reserved ROM area Special page 3803 Group (Spec. H) 000016 Port P0 (P0) 002016 Prescaler 12 (PRE12 PRE12) 000116 Port P0 direction register (P0D) 002116 Timer 1 (T1) 000216 Port P1 (P1) 002216 Timer 2 (T2) 000316 Port P1 direction register (P1D) 002316 Timer XY mode register (TM) 000416 Port P2 (P2) 002416 Prescaler X (PREX) 000516 Port P2 direction register (P2D) 002516 Timer X (TX) 000616 Port P3 (P3) 002616 Prescaler Y (PREY) 000716 Port P3 direction register (P3D) 002716 Timer Y (TY) 000816 Port P4 (P4) 002816 Timer Z low-order (TZL) 000916 Port P4 direction register (P4D) 002916 Timer Z high-order (TZH) 000A16 000A16 Port P5 (P5) 002A16 002A16 Timer Z mode register (TZM) 000B16 000B16 Port P5 direction register (P5D) 002B16 002B16 PWM control register (PWMCON) 000C16 000C16 Port P6 (P6) 002C16 002C16 PWM prescaler (PREPWM) 000D16 000D16 Port P6 direction register (P6D) 002D16 002D16 PWM register (PWM) 000E16 000E16 Timer 12, X count source selection register (T12XCSS T12XCSS) 002E16 002E16 000F16 000F16 Timer Y, Z count source selection register (TYZCSS) 002F16 002F16 Baud rate generator 3 (BRG3) 001016 MISRG 003016 Transmit/Receive buffer register 3 (TB3/RB3) 001116 Reserved 003116 Serial I/O3 status register (SIO3STS) 001216 Reserved 003216 Serial I/O3 control register (SIO3CON) 001316 Reserved 003316 UART3 control register (UART3CON) 001416 Reserved 003416 AD/DA control register (ADCON) 001516 Reserved 003516 A-D conversion register 1 (AD1) 001616 Reserved 003616 D-A1 conversion register (DA1) D-A2 conversion register (DA2) 001716 Reserved 003716 001816 Transmit/Receive buffer register 1 (TB1/RB1) 003816 A-D conversion register 2 (AD2) 001916 Serial I/O1 status register (SIO1STS) 003916 Interrupt source selection register (INTSEL) 001A16 001A16 Serial I/O1 control register (SIO1CON) 003A16 003A16 Interrupt edge selection register (INTEDGE) 001B16 001B16 UART1 control register (UART1CON) 003B16 003B16 CPU mode register (CPUM) 001C16 001C16 Baud rate generator (BRG1) 003C16 003C16 Interrupt request register 1 (IREQ1) 001D16 001D16 Serial I/O2 control register (SIO2CON) 003D16 003D16 Interrupt request register 2 (IREQ2) 001E16 001E16 Watchdog timer control register (WDTCON) 003E16 003E16 Interrupt control register 1 (ICON1) 001F16 001F16 Serial I/O2 register (SIO2) 003F16 003F16 Interrupt control register 2 (ICON2) 0FE016 0FE016 Flash memory control register 0 (FMCR0) 0FF016 0FF016 Port P0 pull-up control register (PULL0) 0FE116 0FE116 Flash memory control register 1 (FMCR1) 0FF116 0FF116 Port P1 pull-up control register (PULL1) 0FE216 0FE216 Flash memory control register 2 (FMCR2) 0FF216 0FF216 Port P2 pull-up control register (PULL2) 0FE316 0FE316 Reserved 0FF316 0FF316 Port P3 pull-up control register (PULL3) 0FE416 0FE416 Reserved 0FF416 0FF416 Port P4 pull-up control register (PULL4) 0FE516 0FE516 Reserved 0FF516 0FF516 Port P5 pull-up control register (PULL5) 0FE616 0FE616 Reserved 0FF616 0FF616 Port P6 pull-up control register (PULL6) 0FE716 0FE716 Reserved 0FE816 0FE816 Reserved 0FE916 0FE916 Reserved 0FEA16 0FEA16 Reserved 0FEB16 0FEB16 Reserved 0FEC16 0FEC16 Reserved 0FED16 0FED16 Reserved 0FEE16 0FEE16 Reserved 0FEF16 0FEF16 Reserved Reserved area: Do not write any data to these addresses, because these areas are reserved. Fig. 11 Memory map of special function register (SFR) Rev.3.01 Jun 25, 2004 page 15 of 103 3803 Group (Spec. H) I/O PORTS The I/O ports have direction registers which determine the input/ output direction of each individual pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input port or output port. When "0" is written to the bit corresponding to a pin, that pin be- comes an input pin. When "1" is written to that bit, that pin becomes an output pin. If data is read from a pin which is set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating. If a pin set to input is written to, only the port output latch is written to and the pin remains floating. Table 8 I/O port function Pin P00/AN8 P00/AN8­P07/AN15 P07/AN15 P10/INT41 P10/INT41 P11/INT01 P11/INT01 Name Port P0 Port P1 CMOS compatible input level I/O Structure Non-Port Function A-D converter input CMOS 3-state output External interrupt input Related SFRs Ref.No. AD/DA control register (1) Interrupt edge selection register (2) P12­P17 (3) P20/LED0 P20/LED0­ P27/LED7 P27/LED7 Port P2 P30/DA1 P30/DA1 Port P3 CMOS compatible input level P31/DA2 P31/DA2 P32 CMOS compatible input level CMOS 3-state output (4) N-channel open-drain output P34/RxD3 AD/DA control register CMOS compatible input level P33 D-A converter output CMOS 3-state output (5) Serial I/O3 function I/O Serial I/O3 control register (6) (7) UART3 control register P35/TxD3 P36/SCLK3 P36/SCLK3 (8) Interrupt edge selection register (10) (9) P37/SRDY3 P37/SRDY3 P40/INT40/XCIN P40/INT40/XCIN P41/INT00/XCOUT P41/INT00/XCOUT CMOS compatible input level External interrupt input CMOS 3-state output Port P4 Sub-clock generating circuit External interrupt input Serial I/O1 function I/O P42/INT1 P42/INT1 CPU mode register Interrupt edge selection register Serial I/O1 control register P43/INT2 P43/INT2 P44/RxD1 P45/TxD1 (11) (2) (6) (7) UART1 control register P46/SCLK1 P46/SCLK1 P47/SRDY1/CNTR2 P47/SRDY1/CNTR2 Serial I/O1 function I/O Timer Z function I/O (8) Serial I/O1 control register (12) Timer Z mode register Port P5 P50/SIN2 P50/SIN2 P51/SOUT2 P51/SOUT2 CMOS compatible input level CMOS 3-state output Serial I/O2 function I/O Serial I/O2 control register (14) (15) P52/SCLK2 P52/SCLK2 (16) P53/SRDY2 P53/SRDY2 Timer X, Y function I/O P55/CNTR1 P55/CNTR1 P56/PWM P56/PWM P57/INT3 P57/INT3 P60/AN0 P60/AN0­P67/AN7 P67/AN7 Port P6 CMOS compatible input level Timer XY mode register (17) PWM output External interrupt input P54/CNTR0 P54/CNTR0 PWM control register Interrupt edge selection register (18) A-D converter input AD/DA control register (1) CMOS 3-state output Notes 1: Refer to the applicable sections how to use double-function ports as function I/O ports. 2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction. When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate. Rev.3.01 (13) Jun 25, 2004 page 16 of 103 (2) 3803 Group (Spec. H) (1) Ports P0, P6 (2) Ports P10, P11, P42, P43, P57 Pull-up control bit Pull-up control bit Direction register Data bus Direction register Port latch Data bus Port latch A-D converter input Analog input pin selection bit (3) Ports P12 to P17, P2 Interrupt input (4) Ports P30, P31 Pull-up control bit Pull-up control bit Direction register Direction register Data bus Port latch Data bus Port latch D-A converter output DA1 output enable (P30) DA2 output enable (P31) (6) Ports P34, P44 (5) Ports P32, P33 Pull-up control bit Serial I/O enable bit Receive enable bit Direction register Data bus Direction register Port latch Data bus Port latch Serial I/O input (7) Ports P35, P45 (8) Ports P36, P46 Pull-up control bit Serial I/O synchronous clock selection bit Pull-up control bit Serial I/O enable bit P-channel output disable bit Serial I/O enable bit Transmit enable bit Serial I/O mode selection bit Serial I/O enable bit Direction register Direction register Data bus Data bus Port latch Serial I/O output Port latch Serial I/O clock output Serial I/O external clock input Fig. 12 Port block diagram (1) Rev.3.01 Jun 25, 2004 page 17 of 103 3803 Group (Spec. H) (10) Port P40 (9) Port P37 Pull-up control bit Pull-up control bit Serial I/O3 mode selection bit Serial I/O3 enable bit SRDY3 output enable bit Port XC switch bit Direction register Direction register Data bus Port latch Data bus Port latch INT40 INT40 interrupt input Serial I/O3 ready output Oscillator Port P41 Port XC switch bit (11) Port P41 (12) Port P47 Pull-up control bit Port XC switch bit Pull-up control bit Serial I/O1 mode selection bit Serial I/O1 enable bit SRDY1 output enable bit Direction register Direction register Data bus Timer Z operating mode bits Bit 2 Bit 1 Bit 0 Port latch Data bus Port latch INT00 INT00 interrupt input Sub-clock generating circuit input Timer output Serial I/O1 ready output CNTR2 interrupt input (14) Port P51 (13) Port P50 Pull-up control bit Pull-up control bit Serial I/O2 transmit completion signal Serial I/O2 port selection bit Direction register Data bus Direction register Port latch Data bus Port latch Serial I/O2 input Serial I/O2 output Fig. 13 Port block diagram (2) Rev.3.01 Jun 25, 2004 page 18 of 103 P-channel output disable bit 3803 Group (Spec. H) (15) Port P52 (16) Port P53 Pull-up control bit Pull-up control bit Serial I/O2 synchronous clock selection bit Serial I/O2 port selection bit SRDY2 enable bit Direction register Direction register Port latch Data bus Data bus Port latch Serial I/O2 ready output Serial I/O2 clock output Serial I/O2 external clock input (17) Ports P54, P55 (18) Port P56 Pull-up control bit Pull-up control bit PWM output enable bit Direction register Data bus Direction register Data bus Port latch Pulse output mode PWM output Timer output CNTR interrupt input Fig. 14 Port block diagram (3) Rev.3.01 Jun 25, 2004 Port latch page 19 of 103 3803 Group (Spec. H) b7 b0 Port P0 pull-up control register (PULL0: address 0FF016 0FF016) P00 pull-up control bit 0: No pull-up 1: Pull-up P01 pull-up control bit 0: No pull-up 1: Pull-up P02 pull-up control bit 0: No pull-up 1: Pull-up P03 pull-up control bit 0: No pull-up 1: Pull-up P04 pull-up control bit 0: No pull-up 1: Pull-up P05 pull-up control bit 0: No pull-up 1: Pull-up P06 pull-up control bit 0: No pull-up 1: Pull-up P07 pull-up control bit 0: No pull-up 1: Pull-up b7 Note: Pull-up control is valid when the corresponding bit of the port direction register is "0" (input). When that bit is "1" (output), pull-up cannot be set to the port of which pull-up is selected. b0 Port P1 pull-up control register (PULL1: address 0FF116 0FF116) P10 pull-up control bit 0: No pull-up 1: Pull-up P11 pull-up control bit 0: No pull-up 1: Pull-up P12 pull-up control bit 0: No pull-up 1: Pull-up P13 pull-up control bit 0: No pull-up 1: Pull-up P14 pull-up control bit 0: No pull-up 1: Pull-up P15 pull-up control bit 0: No pull-up 1: Pull-up P16 pull-up control bit 0: No pull-up 1: Pull-up P17 pull-up control bit 0: No pull-up 1: Pull-up Fig. 15 Structure of port pull-up control register (1) Rev.3.01 Jun 25, 2004 page 20 of 103 Note: Pull-up control is valid when the corresponding bit of the port direction register is "0" (input). When that bit is "1" (output), pull-up cannot be set to the port of which pull-up is selected. 3803 Group (Spec. H) b7 b0 Port P2 pull-up control register (PULL2: address 0FF216 0FF216) P20 pull-up control bit 0: No pull-up 1: Pull-up P21 pull-up control bit 0: No pull-up 1: Pull-up P22 pull-up control bit 0: No pull-up 1: Pull-up P23 pull-up control bit 0: No pull-up 1: Pull-up P24 pull-up control bit 0: No pull-up 1: Pull-up P25 pull-up control bit 0: No pull-up 1: Pull-up P26 pull-up control bit 0: No pull-up 1: Pull-up P27 pull-up control bit 0: No pull-up 1: Pull-up b7 Note: Pull-up control is valid when the corresponding bit of the port direction register is "0" (input). When that bit is "1" (output), pull-up cannot be set to the port of which pull-up is selected. b0 Port P3 pull-up control register (PULL3: address 0FF316 0FF316) P30 pull-up control bit 0: No pull-up 1: Pull-up P31 pull-up control bit 0: No pull-up 1: Pull-up Not used (return "0" when read) P34 pull-up control bit 0: No pull-up 1: Pull-up P35 pull-up control bit 0: No pull-up 1: Pull-up P36 pull-up control bit 0: No pull-up 1: Pull-up P37 pull-up control bit 0: No pull-up 1: Pull-up Fig. 16 Structure of port pull-up control register (2) Rev.3.01 Jun 25, 2004 page 21 of 103 Note: Pull-up control is valid when the corresponding bit of the port direction register is "0" (input). When that bit is "1" (output), pull-up cannot be set to the port of which pull-up is selected. 3803 Group (Spec. H) b7 b0 Port P4 pull-up control register (PULL4: address 0FF416 0FF416) P40 pull-up control bit 0: No pull-up 1: Pull-up P41 pull-up control bit 0: No pull-up 1: Pull-up P42 pull-up control bit 0: No pull-up 1: Pull-up P43 pull-up control bit 0: No pull-up 1: Pull-up P44 pull-up control bit 0: No pull-up 1: Pull-up P45 pull-up control bit 0: No pull-up 1: Pull-up P46 pull-up control bit 0: No pull-up 1: Pull-up P47 pull-up control bit 0: No pull-up 1: Pull-up b7 Note: Pull-up control is valid when the corresponding bit of the port direction register is "0" (input). When that bit is "1" (output), pull-up cannot be set to the port of which pull-up is selected. b0 Port P5 pull-up control register (PULL5: address 0FF516 0FF516) P50 pull-up control bit 0: No pull-up 1: Pull-up P51 pull-up control bit 0: No pull-up 1: Pull-up P52 pull-up control bit 0: No pull-up 1: Pull-up P53 pull-up control bit 0: No pull-up 1: Pull-up P54 pull-up control bit 0: No pull-up 1: Pull-up P55 pull-up control bit 0: No pull-up 1: Pull-up P56 pull-up control bit 0: No pull-up 1: Pull-up P57 pull-up control bit 0: No pull-up 1: Pull-up Fig. 17 Structure of port pull-up control register (3) Rev.3.01 Jun 25, 2004 page 22 of 103 Note: Pull-up control is valid when the corresponding bit of the port direction register is "0" (input). When that bit is "1" (output), pull-up cannot be set to the port of which pull-up is selected. 3803 Group (Spec. H) b7 b0 Port P6 pull-up control register (PULL6: address 0FF616 0FF616) P60 pull-up control bit 0: No pull-up 1: Pull-up P61 pull-up control bit 0: No pull-up 1: Pull-up P62 pull-up control bit 0: No pull-up 1: Pull-up P63 pull-up control bit 0: No pull-up 1: Pull-up P64 pull-up control bit 0: No pull-up 1: Pull-up P65 pull-up control bit 0: No pull-up 1: Pull-up P66 pull-up control bit 0: No pull-up 1: Pull-up P67 pull-up control bit 0: No pull-up 1: Pull-up Fig. 18 Structure of port pull-up control register (4) Rev.3.01 Jun 25, 2004 page 23 of 103 Note: Pull-up control is valid when the corresponding bit of the port direction register is "0" (input). When that bit is "1" (output), pull-up cannot be set to the port of which pull-up is selected. 3803 Group (Spec. H) INTERRUPTS s Notes The 3803 group (Spaec. H)'s interrupts are a type of vector and occur by 16 sources among 21 sources: eight external, twelve internal, and one software. When setting the followings, the interrupt request bit may be set to "1". ·When setting external interrupt active edge Related register: Interrupt edge selection register (address 003A16 003A16) Timer XY mode register (address 002316) Timer Z mode register (address 002A16 002A16) ·When switching interrupt sources of an interrupt vector address where two or more interrupt sources are allocated Related register: Interrupt source selection register (address 003916) When not requiring for the interrupt occurrence synchronized with these setting, take the following sequence. Set the corresponding interrupt enable bit to "0" (disabled). Set the interrupt edge select bit or the interrupt source select bit to "1". Set the corresponding interrupt request bit to "0" after 1 or more instructions have been executed. {Set the corresponding interrupt enable bit to "1" (enabled). Interrupt Control Each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software interrupt set by the BRK instruction. An interrupt occurs if the corresponding interrupt request and enable bits are "1" and the interrupt disable flag is "0". Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software. The reset and the BRK instruction cannot be disabled with any flag or bit. The I (interrupt disable) flag disables all interrupts except the reset and the BRK instruction interrupt. When several interrupt requests occur at the same time, the interrupts are received according to priority. Interrupt Operation By acceptance of an interrupt, the following operations are automatically performed: 1. The contents of the program counter and the processor status register are automatically pushed onto the stack. 2. The interrupt disable flag is set and the corresponding interrupt request bit is cleared. 3. The interrupt jump destination address is read from the vector table into the program counter. Interrupt Source Selection Which of each combination of the following interrupt sources can be selected by the interrupt source selection register (address 003916). 1. INT0 or Timer Z 2. CNTR1 or Serial I/O3 reception 3. Serial I/O2 or Timer Z 7. INT4 or CNTR2 8. A-D converter or serial I/O3 transmission External Interrupt Pin Selection The occurrence sources of the external interrupt INT 0 and INT4 can be selected from either input from INT00 INT00 and INT40 INT40 pin, or input from INT01 INT01 and INT41 INT41 pin by the INT0, INT4 interrupt switch bit of interrupt edge selection register (bit 6 of address 003A16 003A16). Rev.3.01 Jun 25, 2004 page 24 of 103 3803 Group (Spec. H) Table 9 Interrupt vector addresses and priority Interrupt Source Priority Vector Addresses (Note 1) Low High FFFC16 FFFC16 FFFD16 FFFD16 Interrupt Request Generating Conditions Remarks Reset (Note 2) 1 INT0 2 FFFB16 FFFB16 FFFA16 FFFA16 INT1 3 FFF916 FFF916 FFF816 FFF816 At detection of either rising or falling edge of INT1 input External interrupt (active edge selectable) Serial I/O1 reception 4 FFF716 FFF716 FFF616 FFF616 At completion of serial I/O1 data reception Valid when serial I/O1 is selected Serial I/O1 transmission 5 FFF516 FFF516 FFF416 FFF416 At completion of serial I/O1 transmission shift or when transmission buffer is empty Valid when serial I/O1 is selected Timer X 6 FFF316 FFF316 FFF216 FFF216 At timer X underflow Timer Y 7 FFF116 FFF116 FFF016 FFF016 At timer Y underflow Timer 1 8 FFEF16 FFEF16 FFEE16 FFEE16 At timer 1 underflow Timer 2 9 FFED16 FFED16 FFEC16 FFEC16 At timer 2 underflow CNTR0 10 FFEB16 FFEB16 FFEA16 FFEA16 At detection of either rising or falling edge of CNTR0 input External interrupt (active edge selectable) CNTR1 11 FFE916 FFE916 FFE816 FFE816 At detection of either rising or falling edge of CNTR1 input External interrupt (active edge selectable) At completion of serial I/O3 data reception Valid when serial I/O3 is selected At completion of serial I/O2 data transmission or reception Valid when serial I/O2 is selected Timer Z At reset Non-maskable At detection of either rising or falling edge of INT0 input External interrupt (active edge selectable) At timer Z underflow Serial I/O3 reception Serial I/O2 STP release timer underflow 12 FFE716 FFE716 FFE616 FFE616 INT2 13 FFE516 FFE516 FFE416 FFE416 At detection of either rising or falling edge of INT2 input External interrupt (active edge selectable) INT3 14 FFE316 FFE316 FFE216 FFE216 At detection of either rising or falling edge of INT3 input External interrupt (active edge selectable) INT4 15 FFE116 FFE116 FFE016 FFE016 At detection of either rising or falling edge of INT4 input External interrupt (active edge selectable) At detection of either rising or falling edge of CNTR2 input External interrupt (active edge selectable) Timer Z At timer Z underflow CNTR2 A-D converter Serial I/O3 transmission 16 BRK instruction 17 FFDF16 FFDF16 FFDE16 FFDE16 At completion of A-D conversion At completion of serial I/O3 transmission shift or when transmission buffer is empty FFDD16 FFDD16 FFDC16 FFDC16 Valid when serial I/O3 is selected At BRK instruction execution Non-maskable software interrupt Notes 1: Vector addresses contain interrupt jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority. Rev.3.01 Jun 25, 2004 page 25 of 103 3803 Group (Spec. H) Interrupt request bit Interrupt enable bit Interrupt disable flag (I) BRK instruction Reset Fig. 19 Interrupt control Rev.3.01 Jun 25, 2004 page 26 of 103 Interrupt request 3803 Group (Spec. H) b7 b0 Interrupt edge selection register (INTEDGE : address 003A16 003A16) INT0 active edge selection bit INT1 active edge selection bit Not used (returns "0" when read) INT2 active edge selection bit INT3 active edge selection bit INT4 active edge selection bit INT0, INT4 interrupt switch bit 0 : INT00 INT00, INT40 INT40 interrupt 1 : INT01 INT01, INT41 INT41 interrupt Not used (returns "0" when read) b7 b0 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active Interrupt request register 1 (IREQ1 : address 003C16 003C16) b7 b0 INT0/Timer Z interrupt request bit INT1 interrupt request bit Serial I/O1 receive interrupt request bit Serial I/O1 transmit interrupt request bit Timer X interrupt request bit Timer Y interrupt request bit Timer 1 interrupt request bit Timer 2 interrupt request bit Interrupt request register 2 (IREQ2 : address 003D16 003D16) CNTR0 interrupt request bit CNTR1/Serial I/O3 receive interrupt request bit Serial I/O2/Timer Z interrupt request bit INT2 interrupt request bit INT3 interrupt request bit INT4/CNTR2 interrupt request bit AD converter/Serial I/O3 transmit interrupt request bit Not used (returns "0" when read) 0 : No interrupt request issued 1 : Interrupt request issued b7 b0 Interrupt control register 1 (ICON1 : address 003E16 003E16) b7 b0 INT0/Timer Z interrupt enable bit INT1 interrupt enable bit Serial I/O1 receive interrupt enable bit Serial I/O1 transmit interrupt enable bit Timer X interrupt enable bit Timer Y interrupt enable bit Timer 1 interrupt enable bit Timer 2 interrupt enable bit Interrupt control register 2 (ICON2 : address 003F16 003F16) CNTR0 interrupt enable bit CNTR1/Serial I/O3 receive interrupt enable bit Serial I/O2/Timer Z interrupt enable bit INT2 interrupt enable bit INT3 interrupt enable bit INT4/CNTR2 interrupt enable bit AD converter/Serial I/O3 transmit interrupt enable bit Not used (returns "0" when read) 0 : Interrupts disabled 1 : Interrupts enabled b7 b0 Interrupt source selection register (INTSEL: address 003916) INT0/Timer Z interrupt source selection bit 0 : INT0 interrupt 1 : Timer Z interrupt Serial I/O2/Timer Z interrupt source selection bit 0 : Serial I/O2 interrupt 1 : Timer Z interrupt Not used (Do not write "1" to these bits.) (Do not write "1" to these bits simultaneously.) INT4/CNTR2 interrupt source selection bit 0 : INT4 interrupt 1 : CNTR2 interrupt Not used (Do not write "1" to this bit.) CNTR1/Serial I/O3 receive interrupt source selection bit 0 : CNTR1 interrupt 1 : Serial I/O3 receive interrupt AD converter/Serial I/O3 transmit interrupt source selection bit 0 : A-D converter interrupt 1 : Serial I/O3 transmit interrupt Fig. 20 Structure of interrupt-related registers Rev.3.01 Jun 25, 2004 page 27 of 103 3803 Group (Spec. H) TIMERS q8-bit Timers Timer X and Timer Y The 3803 group (Spec. H) has four 8-bit timers: timer 1, timer 2, timer X, and timer Y. The timer 1 and timer 2 use one prescaler in common, and the timer X and timer Y use each prescaler. Those are 8-bit prescalers. Each of the timers and prescalers has a timer latch or a prescaler latch. The division ratio of each timer or prescaler is given by 1/(n + 1), where n is the value in the corresponding timer or prescaler latch. All timers are down-counters. When the timer reaches "0016", an underflow occurs at the next count pulse and the contents of the corresponding timer latch are reloaded into the timer and the count is continued. When the timer underflows, the interrupt request bit corresponding to that timer is set to "1". qTimer divider The divider count source is switched by the main clock division ratio selection bits of CPU mode register (bits 7 and 6 at address 003B 16). When these bits are "00" (high-speed mode) or "01" (middle-speed mode), XIN is selected. When these bits are"10" (low-speed mode), XCIN is selected. qPrescaler 12 The prescaler 12 counts the output of the timer divider. The count source is selected by the timer 12, X count source selection register among 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, 1/1024 of f(XIN) or f(XCIN). Timer 1 and Timer 2 The timer 1 and timer 2 counts the output of prescaler 12 and periodically set the interrupt request bit. qPrescaler X and prescaler Y The prescaler X and prescaler Y count the output of the timer divider or f(XCIN). The count source is selected by the timer 12, X count source selection register (address 000E16 000E16) and the timer Y, Z count source selection register (address 000F 16) among 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, and 1/1024 of f(XIN) or f(XCIN); and f(XCIN). Rev.3.01 Jun 25, 2004 page 28 of 103 The timer X and timer Y can each select one of four operating modes by setting the timer XY mode register (address 002316). (1) Timer mode qMode selection This mode can be selected by setting "00" to the timer X operating mode bits (bits 1 and 0) and the timer Y operating mode bits (bits 5 and 4) of the timer XY mode register (address 002316). qExplanation of operation The timer count operation is started by setting "0" to the timer X count stop bit (bit 3) and the timer Y count stop bit (bit 7) of the timer XY mode register (address 002316). When the timer reaches "00 16", an underflow occurs at the next count pulse and the contents of timer latch are reloaded into the timer and the count is continued. (2) Pulse output mode qMode selection This mode can be selected by setting "01" to the timer X operating mode bits (bits 1 and 0) and the timer Y operating mode bits (bits 5 and 4) of the timer XY mode register (address 002316). qExplanation of operation The operation is the same as the timer mode's. Moreover the pulse which is inverted each time the timer underflows is output from CNTR0/CNTR1 pin. Regardless of the timer counting or not the output of CNTR0/CNTR1 pin is initialized to the level of specified by their active edge switch bits when writing to the timer. When the CNTR0 active edge switch bit (bit 2) and the CNTR1 active edge switch bit (bit 6) of the timer XY mode register (address 002316) is "0", the output starts with "H" level. When it is "1", the output starts with "L" level. Switching the CNTR0 or CNTR1 active edge switch bit will reverse the output level of the corresponding CNTR0 or CNTR1 pin. sPrecautions Set the double-function port of CNTR0/CNTR1 pin and port P54/ P55 to output in this mode. 3803 Group (Spec. H) (3) Event counter mode qMode selection This mode can be selected by setting "10" to the timer X operating mode bits (bits 1 and 0) and the timer Y operating mode bits (bits 5 and 4) of the timer XY mode register (address 002316). qExplanation of operation The operation is the same as the timer mode's except that the timer counts signals input from the CNTR0 or CNTR 1 pin. The valid edge for the count operation depends on the CNTR 0 active edge switch bit (bit 2) or the CNTR1 active edge switch bit (bit 6) of the timer XY mode register (address 002316). When it is "0", the rising edge is valid. When it is "1", the falling edge is valid. sPrecautions Set the double-function port of CNTR0/CNTR1 pin and port P54/ P55 to input in this mode. (4) Pulse width measurement mode qMode selection This mode can be selected by setting "11" to the timer X operating mode bits (bits 1 and 0) and the timer Y operating mode bits (bits 5 and 4) of the timer XY mode register (address 002316). qExplanation of operation When the CNTR0 active edge switch bit (bit 2) or the CNTR1 active edge switch bit (bit 6) of the timer XY mode register (address 002316) is "1", the timer counts during the term of one falling edge of CNTR0/CNTR1 pin input until the next rising edge of input ("L" term). When it is "0", the timer counts during the term of one rising edge input until the next falling edge input ("H" term). sPrecautions Set the double-function port of CNTR0/CNTR1 pin and port P54/ P55 to input in this mode. The count operation can be stopped by setting "1" to the timer X count stop bit (bit 3) and the timer Y count stop bit (bit 7) of the timer XY mode register (address 002316). The interrupt request bit is set to "1" each time the timer underflows. ·Precautions when switching count source When switching the count source by the timer 12, X and Y count source selection bits, the value of timer count is altered in inconsiderable amount owing to generating of thin pulses on the count input signals. Therefore, select the timer count source before setting the value to the prescaler and the timer. Rev.3.01 Jun 25, 2004 page 29 of 103 3803 Group (Spec. H) "00" "01" XIN (1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, 1/1024) Divider Clock for timer 12 Clock for timer Y XCIN Main clock division ratio selection bits Count source selection bit Clock for timer X "10" Data bus Prescaler X latch (8) f(XCIN) Pulse width measurement mode Prescaler X (8) CNTR0 active edge switch bit "0" P54/CNTR0 P54/CNTR0 Event counter mode Timer X latch (8) Timer mode Pulse output mode Timer X (8) Timer X count stop bit To CNTR0 interrupt request bit "1" CNTR0 active edge switch bit "1" Port P54 direction register To timer X interrupt request bit "0" Port P54 latch Q Toggle flip-flop T Q R Timer X latch write pulse Pulse output mode Pulse output mode Data bus Count source selection bit Clock for timer Y Prescaler Y latch (8) Pulse width measurement mode f(XCIN) Prescaler Y (8) CNTR1 active edge switch bit "0" P55/CNTR1 P55/CNTR1 Event counter mode Timer Y latch (8) Timer mode Pulse output mode Timer Y (8) To timer Y interrupt request bit Timer Y count stop bit To CNTR1 interrupt request bit "1" CNTR1 active edge switch bit "1" Q Toggle flip-flop T Q Port P55 direction register Port P55 latch "0" R Timer Y latch write pulse Pulse output mode Pulse output mode Data bus Prescaler 12 latch (8) Clock for timer 12 Prescaler 12 (8) Timer 1 latch (8) Timer 2 latch (8) Timer 1 (8) Timer 2 (8) To timer 2 interrupt request bit To timer 1 interrupt request bit Fig. 21 Block diagram of timer X, timer Y, timer 1, and timer 2 Rev.3.01 Jun 25, 2004 page 30 of 103 3803 Group (Spec. H) b7 b0 Timer XY mode register (TM : address 002316) Timer X operating mode bits b1 b0 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode CNTR0 active edge switch bit 0 : Interrupt at falling edge Count at rising edge in event counter mode 1 : Interrupt at rising edge Count at falling edge in event counter mode Timer X count stop bit 0 : Count start 1 : Count stop Timer Y operating mode bits b5 b4 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode CNTR1 active edge switch bit 0 : Interrupt at falling edge Count at rising edge in event counter mode 1 : Interrupt at rising edge Count at falling edge in event counter mode Timer Y count stop bit 0 : Count start 1 : Count stop Fig. 22 Structure of timer XY mode register Rev.3.01 Jun 25, 2004 page 31 of 103 3803 Group (Spec. H) b7 b0 Timer 12, X count source selection register (T12XCSS T12XCSS : address 000E16 000E16) Timer 12 count source selection bits b3b2b1b0 1010 : 0 0 0 0 : f(XIN)/2 or f(XCIN)/2 1011 : 0 0 0 1 : f(XIN)/4 or f(XCIN)/4 1100 : 0 0 1 0 : f(XIN)/8 or f(XCIN)/8 1101 : 0 0 1 1 : f(XIN)/16 or f(XCIN)/16 1110 : 0 1 0 0 : f(XIN)/32 or f(XCIN)/32 1111 : 0 1 0 1 : f(XIN)/64 or f(XCIN)/64 0 1 1 0 : f(XIN)/128 or f(XCIN)/128 0 1 1 1 : f(XIN)/256 or f(XCIN)/256 1 0 0 0 : f(XIN)/512 or f(XCIN)/512 1 0 0 1 : f(XIN)/1024 or f(XCIN)/1024 Timer X count source selection bits b7b6b5b4 0 0 0 0 : f(XIN)/2 or f(XCIN)/2 0 0 0 1 : f(XIN)/4 or f(XCIN)/4 0 0 1 0 : f(XIN)/8 or f(XCIN)/8 0 0 1 1 : f(XIN)/16 or f(XCIN)/16 0 1 0 0 : f(XIN)/32 or f(XCIN)/32 0 1 0 1 : f(XIN)/64 or f(XCIN)/64 0 1 1 0 : f(XIN)/128 or f(XCIN)/128 0 1 1 1 : f(XIN)/256 or f(XCIN)/256 1 0 0 0 : f(XIN)/512 or f(XCIN)/512 1 0 0 1 : f(XIN)/1024 or f(XCIN)/1024 1 0 1 0 : f(XCIN) b7 1011 : 1100 : 1101 : 1110 : 1111 : Not used Not used b0 Timer Y, Z count source selection register (TYZCSS : address 000F16 000F16) Timer Y count source selection bits b3b2b1b0 0 0 0 0 : f(XIN)/2 or f(XCIN)/2 1011 : 0 0 0 1 : f(XIN)/4 or f(XCIN)/4 1100 : 0 0 1 0 : f(XIN)/8 or f(XCIN)/8 1101 : 0 0 1 1 : f(XIN)/16 or f(XCIN)/16 1110 : 0 1 0 0 : f(XIN)/32 or f(XCIN)/32 1111 : 0 1 0 1 : f(XIN)/64 or f(XCIN)/64 0 1 1 0 : f(XIN)/128 or f(XCIN)/128 0 1 1 1 : f(XIN)/256 or f(XCIN)/256 1 0 0 0 : f(XIN)/512 or f(XCIN)/512 1 0 0 1 : f(XIN)/1024 or f(XCIN)/1024 1 0 1 0 : f(XCIN) Timer Z count source selection bits b7b6b5b4 0 0 0 0 : f(XIN)/2 or f(XCIN)/2 0 0 0 1 : f(XIN)/4 or f(XCIN)/4 0 0 1 0 : f(XIN)/8 or f(XCIN)/8 0 0 1 1 : f(XIN)/16 or f(XCIN)/16 0 1 0 0 : f(XIN)/32 or f(XCIN)/32 0 1 0 1 : f(XIN)/64 or f(XCIN)/64 0 1 1 0 : f(XIN)/128 or f(XCIN)/128 0 1 1 1 : f(XIN)/256 or f(XCIN)/256 1 0 0 0 : f(XIN)/512 or f(XCIN)/512 1 0 0 1 : f(XIN)/1024 or f(XCIN)/1024 1 0 1 0 : f(XCIN) Fig. 23 Structure of timer 12, X and timer Y, Z count source selection registers Rev.3.01 Jun 25, 2004 page 32 of 103 1011 : 1100 : 1101 : 1110 : 1111 : Not used Not used 3803 Group (Spec. H) q16-bit Timer (2) Event counter mode The timer Z is a 16-bit timer. When the timer reaches "000016", an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When the timer underflows, the interrupt request bit corresponding to the timer Z is set to "1". When reading/writing to the timer Z, perform reading/writing to both the high-order byte and the low-order byte. When reading the timer Z, read from the high-order byte first, followed by the low-order byte. Do not perform the writing to the timer Z between read operation of the high-order byte and read operation of the low-order byte. When writing to the timer Z, write to the low-order byte first, followed by the high-order byte. Do not perform the reading to the timer Z between write operation of the low-order byte and write operation of the high-order byte. The timer Z can select the count source by the timer Z count source selection bits of timer Y, Z count source selection register (bits 7 to 4 at address 000F16 000F16). Timer Z can select one of seven operating modes by setting the timer Z mode register (address 002A16 002A16). qMode selection This mode can be selected by setting "000" to the timer Z operating mode bits (bits 2 to 0) and setting "1" to the timer/event counter mode switch bit (bit 7) of the timer Z mode register (address 002A16 002A16). The valid edge for the count operation depends on the CNTR2 active edge switch bit (bit 5) of the timer Z mode register (address 002A16 002A16). When it is "0", the rising edge is valid. When it is "1", the falling edge is valid. qInterrupt The interrupt at an underflow is the same as the timer mode's. qExplanation of operation The operation is the same as the timer mode's. Set the double-function port of CNTR2 pin and port P47 to input in this mode. Figure 26 shows the timing chart of the timer/event counter mode. (1) Timer mode qMode selection This mode can be selected by setting "000" to the timer Z operating mode bits (bits 2 to 0) and setting "0" to the timer/event counter mode switch bit (b7) of the timer Z mode register (address 002A16 002A16). qCount source selection In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/ 128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as the count source. In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/ 512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count source. qInterrupt When an underflow occurs, the INT0/timer Z interrupt request bit (bit 0) of the interrupt request register 1 (address 003C16 003C16) is set to "1". qExplanation of operation During timer stop, usually write data to a latch and a timer at the same time to set the timer value. The timer count operation is started by setting "0" to the timer Z count stop bit (bit 6) of the timer Z mode register (address 002A16 002A16). When the timer reaches "000016", an underflow occurs at the next count pulse and the contents of timer latch are reloaded into the timer and the count is continued. When writing data to the timer during operation, the data is written only into the latch. Then the new latch value is reloaded into the timer at the next underflow. Rev.3.01 Jun 25, 2004 page 33 of 103 (3) Pulse output mode qMode selection This mode can be selected by setting "001" to the timer Z operating mode bits (bits 2 to 0) and setting "0" to the timer/event counter mode switch bit (b7) of the timer Z mode register (address 002A16 002A16). qCount source selection In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/ 128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as the count source. In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/ 512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count source. qInterrupt The interrupt at an underflow is the same as the timer mode's. qExplanation of operation The operation is the same as the timer mode's. Moreover the pulse which is inverted each time the timer underflows is output from CNTR2 pin. When the CNTR2 active edge switch bit (bit 5) of the timer Z mode register (address 002A16 002A16) is "0", the output starts with "H" level. When it is "1", the output starts with "L" level. sPrecautions Set the double-function port of CNTR2 pin and port P47 to output in this mode. The output from CNTR2 pin is initialized to the level depending on CNTR2 active edge switch bit by writing to the timer. When the value of the CNTR2 active edge switch bit is changed, the output level of CNTR2 pin is inverted. Figure 27 shows the timing chart of the pulse output mode. 3803 Group (Spec. H) (4) Pulse period measurement mode (5) Pulse width measurement mode qMode selection This mode can be selected by setting "010" to the timer Z operating mode bits (bits 2 to 0) and setting "0" to the timer/event counter mode switch bit (b7) of the timer Z mode register (address 002A16 002A16). qCount source selection In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as the count source. In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count source. qInterrupt The interrupt at an underflow is the same as the timer mode's. When the pulse period measurement is completed, the INT 4 / CNTR2 interrupt request bit (bit 5) of the interrupt request register 2 (address 003D16 003D16) is set to "1". qExplanation of operation The cycle of the pulse which is input from the CNTR2 pin is measured. When the CNTR2 active edge switch bit (bit 5) of the timer Z mode register (address 002A16 002A16) is "0", the timer counts during the term from one falling edge of CNTR2 pin input to the next falling edge. When it is "1", the timer counts during the term from one rising edge input to the next rising edge input. When the valid edge of measurement completion/start is detected, the 1's complement of the timer value is written to the timer latch and "FFFF16 FFFF16" is set to the timer. Furthermore when the timer underflows, the timer Z interrupt request occurs and "FFFF16 FFFF16" is set to the timer. When reading the timer Z, the value of the timer latch (measured value) is read. The measured value is retained until the next measurement completion. sPrecautions Set the double-function port of CNTR2 pin and port P47 to input in this mode. A read-out of timer value is impossible in this mode. The timer can be written to only during timer stop (no measurement of pulse period). Since the timer latch in this mode is specialized for the read-out of measured values, do not perform any write operation during measurement. "FFFF16 FFFF16" is set to the timer when the timer underflows or when the valid edge of measurement start/completion is detected. Consequently, the timer value at start of pulse period measurement depends on the timer value just before measurement start. Figure 28 shows the timing chart of the pulse period measurement mode. qMode selection This mode can be selected by setting "011" to the timer Z operating mode bits (bits 2 to 0) and setting "0" to the timer/event counter mode switch bit (b7) of the timer Z mode register (address 002A16 002A16). qCount source selection In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as the count source. In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count source. qInterrupt The interrupt at an underflow is the same as the timer mode's. When the pulse widths measurement is completed, the INT 4 / CNTR2 interrupt request bit (bit 5) of the interrupt request register 2 (address 003D16 003D16) is set to "1". qExplanation of operation The pulse width which is input from the CNTR2 pin is measured. When the CNTR2 active edge switch bit (bit 5) of the timer Z mode register (address 002A16 002A16) is "0", the timer counts during the term from one rising edge input to the next falling edge input ("H" term). When it is "1", the timer counts during the term from one falling edge of CNTR2 pin input to the next rising edge of input ("L" term). When the valid edge of measurement completion is detected, the 1's complement of the timer value is written to the timer latch and "FFFF16 FFFF16" is set to the timer. When the timer Z underflows, the timer Z interrupt occurs and "FFFF16 FFFF16" is set to the timer Z. When reading the timer Z, the value of the timer latch (measured value) is read. The measured value is retained until the next measurement completion. sPrecautions Set the double-function port of CNTR2 pin and port P47 to input in this mode. A read-out of timer value is impossible in this mode. The timer can be written to only during timer stop (no measurement of pulse widths). Since the timer latch in this mode is specialized for the read-out of measured values, do not perform any write operation during measurement. "FFFF16 FFFF16" is set to the timer when the timer underflows or when the valid edge of measurement start/completion is detected. Consequently, the timer value at start of pulse width measurement depends on the timer value just before measurement start. Figure 29 shows the timing chart of the pulse width measurement mode. Rev.3.01 Jun 25, 2004 page 34 of 103 3803 Group (Spec. H) (6) Programmable waveform generating mode qMode selection This mode can be selected by setting "100" to the timer Z operating mode bits (bits 2 to 0) and setting "0" to the timer/event counter mode switch bit (b7) of the timer Z mode register (address 002A16 002A16). qCount source selection In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as the count source. In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/ 512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count source. qInterrupt The interrupt at an underflow is the same as the timer mode's. qExplanation of operation The operation is the same as the timer mode's. Moreover the timer outputs the data set in the output level latch (bit 4) of the timer Z mode register (address 002A16 002A16) from the CNTR2 pin each time the timer underflows. Changing the value of the output level latch and the timer latch after an underflow makes it possible to output an optional waveform from the CNTR2 pin. sPrecautions Set the double-function port of CNTR2 pin and port P47 to output in this mode. Figure 30 shows the timing chart of the programmable waveform generating mode. (7) Programmable one-shot generating mode qMode selection This mode can be selected by setting "101" to the timer Z operating mode bits (bits 2 to 0) and setting "0" to the timer/event counter mode switch bit (b7) of the timer Z mode register (address 002A16 002A16). qCount source selection In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/ 128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as the count source. qInterrupt The interrupt at an underflow is the same as the timer mode's. The trigger to generate one-shot pulse can be selected by the INT1 active edge selection bit (bit 1) of the interrupt edge selection register (address 003A16 003A16). When it is "0", the falling edge active is selected; when it is "1", the rising edge active is selected. When the valid edge of the INT1 pin is detected, the INT1 interrupt request bit (bit 1) of the interrupt request register 1 (address 003C16 003C16) is set to "1". qExplanation of operation ·"H" one-shot pulse; Bit 5 of timer Z mode register = "0" The output level of the CNTR2 pin is initialized to "L" at mode selection. When trigger generation (input signal to INT 1 pin) is detected, "H" is output from the CNTR2 pin. When an underflow occurs, "L" is output. The "H" one-shot pulse width is set by the setting value to the timer Z register low-order and high-order. When trigger generating is detected during timer count stop, al- Rev.3.01 Jun 25, 2004 page 35 of 103 though "H" is output from the CNTR2 pin, "H" output state continues because an underflow does not occur. ·"L" one-shot pulse; Bit 5 of timer Z mode register = "1" The output level of the CNTR2 pin is initialized to "H" at mode selection. When trigger generation (input signal to INT 1 pin) is detected, "L" is output from the CNTR 2 pin. When an underflow occurs, "H" is output. The "L" one-shot pulse width is set by the setting value to the timer Z low-order and high-order. When trigger generating is detected during timer count stop, although "L" is output from the CNTR 2 pin, "L" output state continues because an underflow does not occur. sPrecautions Set the double-function port of CNTR2 pin and port P47 to output, and of INT1 pin and port P42 to input in this mode. This mode cannot be used in low-speed mode. If the value of the CNTR2 active edge switch bit is changed during one-shot generating enabled or generating one-shot pulse, then the output level from CNTR2 pin changes. Figure 31 shows the timing chart of the programmable one-shot generating mode. sNotes regarding all modes qTimer Z write control Which write control can be selected by the timer Z write control bit (bit 3) of the timer Z mode register (address 002A16 002A16), writing data to both the latch and the timer at the same time or writing data only to the latch. When the operation "writing data only to the latch" is selected, the value is set to the timer latch by writing data to the address of timer Z and the timer is updated at next underflow. After reset release, the operation "writing data to both the latch and the timer at the same time" is selected, and the value is set to both the latch and the timer at the same time by writing data to the address of timer Z. In the case of writing data only to the latch, if writing data to the latch and an underflow are performed almost at the same time, the timer value may become undefined. qTimer Z read control A read-out of timer value is impossible in pulse period measurement mode and pulse width measurement mode. In the other modes, a read-out of timer value is possible regardless of count operating or stopped. However, a read-out of timer latch value is impossible. qSwitch of interrupt active edge of CNTR2 and INT1 Each interrupt active edge depends on setting of the CNTR2 active edge switch bit and the INT1 active edge selection bit. qSwitch of count source When switching the count source by the timer Z count source selection bits, the value of timer count is altered in inconsiderable amount owing to generating of thin pulses on the count input signals. Therefore, select the timer count source before setting the value to the prescaler and the timer. qUsage of CNTR2 pin as normal I/O port To use the CNTR2 pin as normal I/O port P47, set timer Z operating mode bits (b2, b1, b0) of timer Z mode register (address 002A16 002A16) to "000". 3803 Group (Spec. H) P42/INT1 P42/INT1 CNTR2 active edge Data bus Programmable one-shot switch bit "1" generating mode Programmable one-shot generating circuit Programmable one-shot generating mode "0" To INT1 interrupt request bit Programmable waveform generating mode Output level latch D Q T Pulse output mode CNTR2 active edge switch bit S Q T Q "0" "1" Pulse output mode "001" "100" "101" Timer Z operating mode bits Timer Z low-order latch Timer Z high-order latch Timer Z low-order Timer Z high-order Port P47 latch To timer Z interrupt request bit Port P47 direction register Pulse period measurement mode Pulse width measurement mode Edge detection circuit "1" "0" CNTR2 active edge switch bit XIN XCIN Fig. 24 Block diagram of timer Z Rev.3.01 Jun 25, 2004 page 36 of 103 Clock for timer Z P47/CNTR2 P47/CNTR2 To CNTR2 interrupt request bit "1" f(XCIN) "0" Timer/Event counter mode switch bit Timer Z count stop bit Count source Divider selection bit (1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, 1/1024) 3803 Group (Spec. H) b7 b0 Timer Z mode register (TZM : address 002A16 002A16) Timer Z operating mode bits b2b1b0 0 0 0 : Timer/Event counter mode 0 0 1 : Pulse output mode 0 1 0 : Pulse period measurement mode 0 1 1 : Pulse width measurement mode 1 0 0 : Programmable waveform generating mode 1 0 1 : Programmable one-shot generating mode 1 1 0 : Not available 1 1 1 : Not available Timer Z write control bit 0 : Writing data to both latch and timer simultaneously 1 : Writing data only to latch Output level latch 0 : "L" output 1 : "H" output CNTR2 active edge switch bit 0 : ·Event counter mode: Count at rising edge ·Pulse output mode: Start outputting "H" ·Pulse period measurement mode: Measurement between two falling edges ·Pulse width measurement mode: Measurement of "H" term ·Programmable one-shot generating mode: After start outputting "L", "H" one-shot pulse generated ·Interrupt at falling edge 1 : ·Event counter mode: Count at falling edge ·Pulse output mode: Start outputting "L" ·Pulse period measurement mode: Measurement between two rising edges ·Pulse width measurement mode: Measurement of "L" term ·Programmable one-shot generating mode: After start outputting "H", "L" one-shot pulse generated ·Interrupt at rising edge Timer Z count stop bit 0 : Count start 1 : Count stop Timer/Event counter mode switch bit (Note) 0 : Timer mode 1 : Event counter mode Note: When selecting the modes except the timer/event counter mode, set "0" to this bit. Fig. 25 Structure of timer Z mode register Rev.3.01 Jun 25, 2004 page 37 of 103 3803 Group (Spec. H) FFFF16 FFFF16 TL 000016 TR TR TR TL : Value set to timer latch TR : Timer interrupt request Fig. 26 Timing chart of timer/event counter mode FFFF16 FFFF16 TL 000016 TR TR TR TR Waveform output from CNTR2 pin CNTR2 CNTR2 TL : Value set to timer latch TR : Timer interrupt request CNTR2 : CNTR2 interrupt request (CNTR2 active edge switch bit = "0"; Falling edge active) Fig. 27 Timing chart of pulse output mode Rev.3.01 Jun 25, 2004 page 38 of 103 3803 Group (Spec. H) 000016 T3 T2 T1 FFFF16 FFFF16 TR FFFF16 FFFF16 + T1 TR T2 T3 FFFF16 FFFF16 Signal input from CNTR2 pin CNTR2 CNTR2 CNTR2 CNTR2 CNTR2 of rising edge active TR : Timer interrupt request CNTR2 : CNTR2 interrupt request Fig. 28 Timing chart of pulse period measurement mode (Measuring term between two rising edges) 000016 T3 T2 T1 FFFF16 FFFF16 TR Signal input from CNTR2 pin FFFF16 FFFF16 + T2 T3 T1 CNTR2 CNTR2 CNTR2 CNTR2 interrupt of rising edge active; Measurement of "L" width TR : Timer interrupt request CNTR2 : CNTR2 interrupt request Fig. 29 Timing chart of pulse width measurement mode (Measuring "L" term) Rev.3.01 Jun 25, 2004 page 39 of 103 3803 Group (Spec. H) FFFF16 FFFF16 T3 L T2 T1 000016 Signal output from CNTR2 pin L T3 T1 T2 TR TR TR TR CNTR2 CNTR2 L : Timer initial value TR : Timer interrupt request CNTR2 : CNTR2 interrupt request (CNTR2 active edge switch bit = "0"; Falling edge active) Fig. 30 Timing chart of programmable waveform generating mode FFFF16 FFFF16 L TR Signal input from INT1 pin Signal output from CNTR2 pin L TR L CNTR2 TR L CNTR2 L : One-shot pulse width TR : Timer interrupt request CNTR2 : CNTR2 interrupt request (CNTR2 active edge switch bit = "0"; Falling edge active) Fig. 31 Timing chart of programmable one-shot generating mode ("H" one-shot pulse generating) Rev.3.01 Jun 25, 2004 page 40 of 103 3803 Group (Spec. H) SERIAL I/O Serial I/O1 (1) Clock Synchronous Serial I/O Mode Clock synchronous serial I/O1 mode can be selected by setting the serial I/O1 mode selection bit of the serial I/O1 control register (bit 6 of address 001A16 001A16) to "1". For clock synchronous serial I/O, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the transmit/receive buffer register. Serial I/O1 can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer is also provided for baud rate generation. Data bus Serial I/O1 control register Address 001816 Receive buffer register 1 P44/RXD1 P44/RXD1 Address 001A16 001A16 Receive buffer full flag (RBF) Receive interrupt request (RI) Receive shift register 1 Shift clock Clock control circuit P46/SCLK1 P46/SCLK1 Serial I/O1 synchronous clock selection bit Frequency division ratio 1/(n+1) Baud rate generator 1 1/4 BRG count source selection bit f(XIN) (f(XCIN) in low-speed mode) 1/4 P47/SRDY1 P47/SRDY1 F/F Address 001C16 001C16 Clock control circuit Falling-edge detector Shift clock P45/TXD1 P45/TXD1 Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit shift register 1 Transmit buffer register 1 Address 001816 Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916 Data bus Fig. 32 Block diagram of clock synchronous serial I/O1 Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TxD1 D0 D1 D2 D3 D4 D5 D6 D7 Serial input RxD1 D0 D1 D2 D3 D4 D5 D6 D7 Receive enable signal SRDY1 Write pulse to receive/transmit buffer register (address 001816) TBE = 0 TBE = 1 TSC = 0 RBF = 1 TSC = 1 Overrun error (OE) detection Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TxD pin. 3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes "1" . Fig. 33 Operation of clock synchronous serial I/O1 Rev.3.01 Jun 25, 2004 page 41 of 103 3803 Group (Spec. H) (2) Asynchronous Serial I/O (UART) Mode two buffers have the same address in a memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. The transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O1 mode selection bit of the serial I/O1 control register to "0". Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer, but the Data bus Address 001816 P44/RXD1 P44/RXD1 Serial I/O1 control register Address 001A16 001A16 Receive buffer full flag (RBF) Receive interrupt request (RI) OE Receive buffer register 1 Character length selection bit ST detector 7 bits Receive shift register 1 1/16 8 bits PE FE UART1 control register Address 001B16 001B16 SP detector Clock control circuit Serial I/O1 synchronous clock selection bit P46/SCLK1 P46/SCLK1 BRG count source selection bit Frequency division ratio 1/(n+1) f(XIN) Baud rate generator (f(XCIN) in low-speed mode) Address 001C16 001C16 1/4 ST/SP/PA generator Transmit shift completion flag (TSC) 1/16 P45/TXD1 P45/TXD1 Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit shift register 1 Character length selection bit Transmit buffer register 1 Address 001816 Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916 Data bus Fig. 34 Block diagram of UART serial I/O1 Transmit or receive clock Transmit buffer write signal TBE=0 TSC=0 TBE=1 Serial output TXD1 TBE=0 TSC=1 TBE=1 ST D0 D1 SP ST D0 Receive buffer read signal SP D1 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) Generated at 2nd bit in 2-stop-bit mode RBF=0 RBF=1 Serial input RXD1 ST D0 D1 SP RBF=1 ST D0 D1 SP Notes 1: Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception). 2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes "1," can be selected to occur depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 3: The receive interrupt (RI) is set when the RBF flag becomes "1." 4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle are necessary until changing to TSC=0. Fig. 35 Operation of UART serial I/O1 Rev.3.01 Jun 25, 2004 page 42 of 103 3803 Group (Spec. H) [Serial I/O1 Control Register (SIO1CON)] 001A16 001A16 The serial I/O1 control register consists of eight control bits for the serial I/O1 function. [UART1 Control Register (UART1CON)] 001B16 001B16 The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer, and one bit (bit 4) which is always valid and sets the output structure of the P45/TXD1 P45/TXD1 pin. [Serial I/O1 Status Register (SIO1STS)] 001916 The read-only serial I/O1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O1 function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to "0" when the receive buffer register is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O1 status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing "0" to the serial I/O1 enable bit SIOE (bit 7 of the serial I/O1 control register) also clears all the status flags, including the error flags. Bits 0 to 6 of the serial I/O1 status register are initialized to "0" at reset, but if the transmit enable bit (bit 4) of the serial I/O1 control register has been set to "1", the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become "1". [Transmit Buffer Register 1/Receive Buffer Register 1 (TB1/RB1)] 001816 The transmit buffer register 1 and the receive buffer register 1 are located at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is "0". [Baud Rate Generator 1 (BRG1)] 001C16 001C16 The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. Rev.3.01 Jun 25, 2004 page 43 of 103 3803 Group (Spec. H) b7 b0 Serial I/O1 status register (SIO1STS : address 001916) b7 Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Not used (returns "1" when read) b0 Serial I/O1 control register (SIO1CON : address 001A16 001A16) BRG count source selection bit (CSS) 0: f(XIN) (f(XCIN) in low-speed mode) 1: f(XIN)/4 (f(XCIN)/4 in low-speed mode) Serial I/O1 synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O is selected, BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O is selected, external clock input divided by 16 when UART is selected. SRDY1 output enable bit (SRDY) 0: P47 pin operates as normal I/O pin 1: P47 pin operates as SRDY1 output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O1 mode selection bit (SIOM) 0: Clock asynchronous (UART) serial I/O 1: Clock synchronous serial I/O Serial I/O1 enable bit (SIOE) 0: Serial I/O1 disabled (pins P44 to P47 operate as normal I/O pins) 1: Serial I/O1 enabled (pins P44 to P47 operate as serial I/O pins) b7 b0 UART1 control register (UART1CON : address 001B16 001B16) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P45/TXD1 P45/TXD1 P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) Not used (return "1" when read) Fig. 36 Structure of serial I/O1 control registers Rev.3.01 Jun 25, 2004 page 44 of 103 3803 Group (Spec. H) s Notes concerning serial I/O1 1. Notes when selecting clock synchronous serial I/O 1.1 Stop of transmission operation q Note Clear the serial I/O1 enable bit and the transmit enable bit to "0" (serial I/O and transmit disabled). 2. Notes when selecting clock asynchronous serial I/O 2.1 Stop of transmission operation q Note Clear the transmit enable bit to "0" (transmit disabled). The transmission operation does not stop by clearing the serial I/O1 enable bit to "0". q Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O1 enable bit is cleared to "0" (serial I/O disabled), the internal transmission is running (in this case, since pins TxD1, RxD1, SCLK1, and SRDY1 function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O1 enable bit is set to "1" at this time, the data during internally shifting is output to the TxD1 pin and an operation failure occurs. q Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O1 enable bit is cleared to "0" (serial I/O disabled), the internal transmission is running (in this case, since pins TxD1, RxD1, SCLK1, and S RDY1 function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O1 enable bit is set to "1" at this time, the data during internally shifting is output to the TxD1 pin and an operation failure occurs. 1.2 Stop of receive operation q Note Clear the receive enable bit to "0" (receive disabled), or clear the serial I/O1 enable bit to "0" (serial I/O disabled). 2.2 Stop of receive operation q Note Clear the receive enable bit to "0" (receive disabled). 1.3 Stop of transmit/receive operation q Note Clear both the transmit enable bit and receive enable bit to "0" (transmit and receive disabled). (when data is transmitted and received in the clock synchronous serial I/O mode, any one of data transmission and reception cannot be stopped.) q Reason In the clock synchronous serial I/O mode, the same clock is used for transmission and reception. If any one of transmission and reception