M16C/6N M16C/6N4 16-BIT REJ03B0003-0210 M16C/60 M306N4FCFP M306N4FCGP - Datasheet Archive

 

This document is under development and its contents are subject to change M16C/6N Group (M16C/6N4) SINGLE-CHIP 16-BIT CMOS

 

Under development This document is under development and its contents are subject to change M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) SINGLE-CHIP 16-BIT 16-BIT CMOS MICROCOMPUTER REJ03B0003-0210 REJ03B0003-0210 Rev.2.10 Jun 24, 2005 1. Overview The M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) of single-chip microcomputers are built using the high-performance silicon gate CMOS process using an M16C/60 M16C/60 Series CPU core and are packaged in 100-pin plastic molded QFP and LQFP. These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. With 1 Mbyte of address space, they are capable of executing instructions at high speed. Being equipped with two CAN (Controller Area Network) modules in M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4), the microcomputer is suited to drive automotive and industrial control systems. The CAN modules comply with the 2.0B specification. In addition, this microcomputer contains a multiplier and DMAC which combined with fast instruction processing capability, makes it suitable for control of various OA, communication, and industrial equipment which requires high-speed arithmetic/logic operations. 1.1 Applications Automotive, industrial control systems and other automobile, other Specifications written in this manual are believed to be accurate, but are not guaranteed to be entirely free of error. Specifications in this manual may be changed for functional or performance improvements. Please make sure your manual is the latest edition. Rev.2.10 Jun 24, 2005 REJ03B0003-0210 REJ03B0003-0210 page 1 of 50 Under development This document is under development and its contents are subject to change. M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) 1. Overview 1.2 Performance Outline Table 1.1 lists a performance outline of M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4). Table 1.1 Performance Outline of M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) Performance Normal-ver. T/V-ver. CPU Number of Basic Instructions 91 instructions Minimum Instruction 41.7ns (f(BCLK) = 24MHz, 50.0ns (f(BCLK) = 20MHz, Execution Time 1/1 prescaler, without software wait) 1/1 prescaler, without software wait) Operation Mode Single-chip, memory expansion and microprocessor modes Address Space 1 Mbyte Memory Capacity See Table 1.2 Product List Peripheral Port Input/Output: 87 pins, Input: 1 pin Function Multifunction Timer Timer A: 16 bits 5 channels Timer B: 16 bits 6 channels Three-phase motor control circuit Serial I/O 3 channels Clock synchronous, UART, I2C-bus (1), IEBus (2) 1 channel Clock synchronous A/D Converter 10-bit A/D converter: 1 circuit, 26 channels D/A Converter 8 bits 2 channels DMAC 2 channels CRC Calculation Circuit CRC-CCITT CAN Module 2 channels with 2.0B specification Watchdog Timer 15 bits 1 channel (with prescaler) Interrupt Internal: 31 sources, External: 9 sources Software: 4 sources, Priority level: 7 levels Clock Generating Circuit 4 circuits · Main clock oscillation circuit (*) · Sub clock oscillation circuit (*) · On-chip oscillator · PLL frequency synthesizer (*) Equipped with a built-in feedback resistor Oscillation Stop Detection Main clock oscillation stop and re-oscillation detection function Function Electrical Supply Voltage VCC = 3.0 to 5.5V (f(BCLK) = 24MHz, VCC = 4.2 to 5.5V (f(BCLK) = 20MHz, Characteristics 1/1 prescaler, without software wait) 1/1 prescaler, without software wait) Power Mask ROM 20mA (f(BCLK) = 24MHz, 18mA (f(BCLK) = 20MHz, Consumption PLL operation, no division) PLL operation, no division) Flash Memory 22mA (f(BCLK) = 24MHz, 20mA (f(BCLK) = 20MHz, PLL operation, no division) PLL operation, no division) Mask ROM 3µA (f(BCLK) = 32kHz, Wait mode, Oscillation capacity Low) Flash Memory 0.8µA (Stop mode, Topr = 25°C) Flash Memory Program/Erase Supply Voltage 3.0 ± 0.3V or 5.0 ± 0.5V 5.0 ± 0.5V Version Program and Erase Endurance 100 times I/O I/O Withstand Voltage 5.0V Characteristics Output Current 5mA Operating Ambient Temperature -40 to 85°C T version: -40 to 85°C V version: -40 to 125°C (option) Device Configuration CMOS high performance silicon gate Package 100-pin plastic mold QFP, LQFP NOTES: 1. I2C-bus is a registered trademark of Koninklijke Philips Electronics N.V. 2. IEBus is a registered trademark of NEC Electronics Corporation. option: All options are on request basis. Item Rev.2.10 Jun 24, 2005 REJ03B0003-0210 REJ03B0003-0210 page 2 of 50 Under development This document is under development and its contents are subject to change. M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) 1. Overview 1.3 Block Diagram Figure 1.1 shows a block diagram of M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4). 8 Port P0 8 8 Port P1 Port P3 Three-phase motor control circuit CRC arithmetic circuit (CCITT) (Polynomial: X16+X12+X5+1) Watchdog timer (15 bits) Memory SB ROM (1) R0L R1L page 3 of 50 RAM (2) INTB PC FLG Multiplier 8 Rev.2.10 Jun 24, 2005 REJ03B0003-0210 REJ03B0003-0210 ISP Port P10 A0 A1 FB USP 8 R2 R3 NOTES: 1: ROM size depends on microcomputer type. 2: RAM size depends on microcomputer type. Figure 1.1 Block Diagram CAN module (2 channels) Port P9 D/A converter (8 bits 2 channels) Clock synchronous serial I/O (8 bits 1 channel) M16C/60 M16C/60 series CPU core R0H R1H DMAC (2 channels) XIN-XOUT XCIN-XCOUT PLL frequency synthesizer On-chip oscillator 7 UART or Clock synchronous serial I/O (3 channels) System clock generating circuit Port P6 Port P8_5 Output (timer A): 5 Input (timer B): 6 Port P5 8 8 Timer (16 bits) Port P4 8 Port P8 A/D converter (10 bits 8 channels Expandable up to 26 channels) 8 Port P7 Internal peripheral functions Port P2 8 Under development This document is under development and its contents are subject to change. M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) 1. Overview 1.4 Product List Table 1.2 lists the M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) products and Figure 1.2 shows the type numbers, memory sizes and packages. Table 1.2 Product List Type No. M306N4FCFP M306N4FCFP (D) M306N4FCGP M306N4FCGP (D) M306N4FGFP M306N4FGFP (D) M306N4FGGP M306N4FGGP (D) M306N4FCTFP M306N4FCTFP M306N4FCTGP M306N4FCTGP (D) M306N4FGTFP M306N4FGTFP M306N4FGTGP M306N4FGTGP (D) M306N4FCVFP M306N4FCVFP M306N4FCVGP M306N4FCVGP (D) M306N4FGVFP M306N4FGVFP M306N4FGVGP M306N4FGVGP (D) M306N4MC-XXXGP M306N4MC-XXXGP (D) M306N4MG-XXXGP M306N4MG-XXXGP (D) M306N4MCT-XXXFP M306N4MCT-XXXFP M306N4MCT-XXXGP M306N4MCT-XXXGP (D) M306N4MGT-XXXFP M306N4MGT-XXXFP M306N4MGT-XXXGP M306N4MGT-XXXGP (D) M306N4MCV-XXXFP M306N4MCV-XXXFP M306N4MCV-XXXGP M306N4MCV-XXXGP (D) M306N4MGV-XXXFP M306N4MGV-XXXFP (D) M306N4MGV-XXXGP M306N4MGV-XXXGP (D) (D): Under development ROM Capacity RAM Capacity Package Type 128 K + 4 Kbytes 5 Kbytes PRQP0100JB-A PRQP0100JB-A PLQP0100KB-A PLQP0100KB-A 256 K + 4 Kbytes 10 Kbytes PRQP0100JB-A PRQP0100JB-A PLQP0100KB-A PLQP0100KB-A 128 K + 4 Kbytes 5 Kbytes PRQP0100JB-A PRQP0100JB-A PLQP0100KB-A PLQP0100KB-A 256 K + 4 Kbytes 10 Kbytes PRQP0100JB-A PRQP0100JB-A PLQP0100KB-A PLQP0100KB-A 128 K + 4 Kbytes 5 Kbytes PRQP0100JB-A PRQP0100JB-A PLQP0100KB-A PLQP0100KB-A 256 K + 4 Kbytes 10 Kbytes PRQP0100JB-A PRQP0100JB-A PLQP0100KB-A PLQP0100KB-A 128 Kbytes 5 Kbytes PLQP0100KB-A PLQP0100KB-A 256 Kbytes 10 Kbytes PLQP0100KB-A PLQP0100KB-A 128 Kbytes 5 Kbytes PRQP0100JB-A PRQP0100JB-A PLQP0100KB-A PLQP0100KB-A 256 Kbytes 10 Kbytes PRQP0100JB-A PRQP0100JB-A PLQP0100KB-A PLQP0100KB-A 128 Kbytes 5 Kbytes PRQP0100JB-A PRQP0100JB-A PLQP0100KB-A PLQP0100KB-A 256 Kbytes 10 Kbytes PRQP0100JB-A PRQP0100JB-A PLQP0100KB-A PLQP0100KB-A As of Jun. 2005 Remarks Flash Normal-ver. memory version T-ver. V-ver. Mask ROM version Normal-ver. T-ver. V-ver. Type No. M30 6N 4 M C T - XXX FP Package type: FP : Package PRQP0100JB-A PRQP0100JB-A GP: Package PLQP0100KB-A PLQP0100KB-A ROM No. Omitted on flash memory version Characteristics (no) : Normal-ver. T : T-ver. (Automotive 85°C version) V : V-ver. (Automotive 125°C version) ROM capacity: C : 128 Kbytes G: 256 Kbytes Memory type: M: Mask ROM version F : Flash memory version Shows the number of CAN module, pin count, etc. 6N Group M16C Family Figure 1.2 Type No., Memory Size, and Package Rev.2.10 Jun 24, 2005 REJ03B0003-0210 REJ03B0003-0210 page 4 of 50 Under development This document is under development and its contents are subject to change. M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) 1. Overview 1.5 Pin Configuration Figures 1.3 and 1.4 show the pin configuration (top view). 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P1_0/D8 P1_1/D9 P1_2/D10 2/D10 P1_3/D11 3/D11 P1_4/D12 4/D12 P1_5/D13/INT3 5/D13/INT3 P1_6/D14/INT4 6/D14/INT4 P1_7/D15/INT5 7/D15/INT5 P2_0/AN2_0/A0(/D0/-) P2_1/AN2_1/A1(/D1/D0) P2_2/AN2_2/A2(/D2/D1) P2_3/AN2_3/A3(/D3/D2) P2_4/AN2_4/A4(/D4/D3) P2_5/AN2_5/A5(/D5/D4) P2_6/AN2_6/A6(/D6/D5) P2_7/AN2_7/A7(/D7/D6) VSS P3_0/A8(/-/D7) VCC2 P3_1/A9 P3_2/A10 2/A10 P3_3/A11 3/A11 P3_4/A12 4/A12 P3_5/A13 5/A13 P3_6/A14 6/A14 P3_7/A15 7/A15 P4_0/A16 0/A16 P4_1/A17 1/A17 P4_2/A18 2/A18 P4_3/A19 3/A19 PIN CONFIGURATION (top view) 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 P4_4/CS0 P4_5/CS1 P4_6/CS2 P4_7/CS3 P5_0/WRL/WR P5_1/WRH/BHE P5_2/RD P5_3/BCLK P5_4/HLDA P5_5/HOLD P5_6/ALE P5_7/RDY/CLKOUT P6_0/CTS0/RTS0 P6_1/CLK0 P6_2/RXD0/SCL0 P6_3/TXD0/SDA0 P6_4/CTS1/RTS1/CTS0/CLKS1 P6_5/CLK1 P6_6/RXD1/SCL1 P6_7/TXD1/SDA1 P9_6/ANEX1/CTX0 P9_5/ANEX0/CRX0 P9_4/DA1/TB4IN P9_3/DA0/TB3IN P9_2/TB2IN/SOUT3 (1) P9_1/TB1IN/SIN3 P9_0/TB0IN/CLK3 BYTE CNVSS P8_7/XCIN P8_6/XCOUT RESET XOUT VSS XIN VCC1 P8_5/NMI P8_4/INT2/ZP P8_3/INT1 P8_2/INT0 P8_1/TA4IN/U P8_0/TA4OUT/U P7_7/TA3IN/CRX1 P7_6/TA3OUT/CTX1 P7_5/TA2IN/W P7_4/TA2OUT/W P7_3/CTS2/RTS2/TA1IN/V P7_2/CLK2/TA1OUT/V (1) P7_1/RXD2/SCL2/TA0IN/TB5IN P7_0/TXD2/SDA2/TA0OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 P0_7/AN0_7/D7 P0_6/AN0_6/D6 P0_5/AN0_5/D5 P0_4/AN0_4/D4 P0_3/AN0_3/D3 P0_2/AN0_2/D2 P0_1/AN0_1/D1 P0_0/AN0_0/D0 P10_7/AN7/KI3 P10_6/AN6/KI2 P10_5/AN5/KI1 P10_4/AN4/KI0 P10_3/AN3 P10_2/AN2 P10_1/AN1 AVSS P10_0/AN0 VREF AVCC P9_7/ADTRG NOTE: 1. P7_1 and P9_1 are N channel open-drain pins. Figure 1.3 Pin Configuration (Top View) (1) Rev.2.10 Jun 24, 2005 REJ03B0003-0210 REJ03B0003-0210 page 5 of 50 Package: PRQP0100JB-A PRQP0100JB-A Under development This document is under development and its contents are subject to change. M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) 1. Overview P1_3/D11 3/D11 P1_4/D12 4/D12 P1_5/D13/INT3 5/D13/INT3 P1_6/D14/INT4 6/D14/INT4 P1_7/D15/INT5 7/D15/INT5 P2_0/AN2_0/A0(/D0/-) P2_1/AN2_1/A1(/D1/D0) P2_2/AN2_2/A2(/D2/D1) P2_3/AN2_3/A3(/D3/D2) P2_4/AN2_4/A4(/D4/D3) P2_5/AN2_5/A5(/D5/D4) P2_6/AN2_6/A6(/D6/D5) P2_7/AN2_7/A7(/D7/D6) VSS P3_0/A8(/-/D7) VCC2 P3_1/A9 P3_2/A10 2/A10 P3_3/A11 3/A11 P3_4/A12 4/A12 P3_5/A13 5/A13 P3_6/A14 6/A14 P3_7/A15 7/A15 P4_0/A16 0/A16 P4_1/A17 1/A17 PIN CONFIGURATION (top view) 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P1_2/D10 2/D10 P1_1/D9 P1_0/D8 P0_7/AN0_7/D7 P0_6/AN0_6/D6 P0_5/AN0_5/D5 P0_4/AN0_4/D4 P0_3/AN0_3/D3 P0_2/AN0_2/D2 P0_1/AN0_1/D1 P0_0/AN0_0/D0 P10_7/AN7/KI3 P10_6/AN6/KI2 P10_5/AN5/KI1 P10_4/AN4/KI0 P10_3/AN3 P10_2/AN2 P10_1/AN1 AVSS P10_0/AN0 VREF AVCC P9_7/ADTRG P9_6/ANEX1/CTX0 P9_5/ANEX0/CRX0 76 77 78 79 80 50 49 48 47 46 45 44 43 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 100 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 P9_4/DA1/TB4IN P9_3/DA0/TB3IN P9_2/TB2IN/SOUT3 (1) P9_1/TB1IN/SIN3 P9_0/TB0IN/CLK3 BYTE CNVSS P8_7/XCIN P8_6/XCOUT RESET XOUT VSS XIN VCC1 P8_5/NMI P8_4/INT2/ZP P8_3/INT1 P8_2/INT0 P8_1/TA4IN/U P8_0/TA4OUT/U P7_7/TA3IN/CRX1 P7_6/TA3OUT/CTX1 P7_5/TA2IN/W P7_4/TA2OUT/W P7_3/CTS2/RTS2/TA1IN/V 1 2 P4_2/A18 2/A18 P4_3/A19 3/A19 P4_4/CS0 P4_5/CS1 P4_6/CS2 P4_7/CS3 P5_0/WRL/WR P5_1/WRH/BHE P5_2/RD P5_3/BCLK P5_4/HLDA P5_5/HOLD P5_6/ALE P5_7/RDY/CLKOUT P6_0/CTS0/RTS0 P6_1/CLK0 P6_2/RXD0/SCL0 P6_3/TXD0/SDA0 P6_4/CTS1/RTS1/CTS0/CLKS1 P6_5/CLK1 P6_6/RXD1/SCL1 P6_7/TXD1/SDA1 P7_0/TXD2/SDA2/TA0OUT P7_1/RXD2/SCL2/TA0IN/TB5IN (1) P7_2/CLK2/TA1OUT/V NOTE: 1. P7_1 and P9_1 are N channel open-drain pins. Figure 1.4 Pin Configuration (Top View) (2) Rev.2.10 Jun 24, 2005 REJ03B0003-0210 REJ03B0003-0210 page 6 of 50 Package: PLQP0100KB-A PLQP0100KB-A Under development This document is under development and its contents are subject to change. M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) 1. Overview 1.6 Pin Description Tables 1.3 to 1.5 list the pin descriptions. Table 1.3 Pin Description (1) Signal Name Power supply input Analog power supply input Reset input CNVSS Pin Name VCC1, VCC2, VSS AVCC, AVSS I/O Type Description I Apply 4.2 to 5.5V to the VCC1 and VCC2 pins and 0V to the VSS RESET CNVSS I I External data bus width select input BYTE I Bus control pins D0 to D7 I/O D8 to D15 I/O A0 to A19 A0/D0 to A7/D7 O I/O A1/D0 to A8/D7 I/O I _ _ _ O CS0 to CS3 _ _ WRL/WR _ _ WRH/BHE _ RD O ALE _ HOLD O I _ O I HLDA _ RDY I: Input O: Output pin. The VCC apply condition is that VCC2 = VCC1 (1). Applies the power supply for the A/D converter. Connect the AVCC pin to VCC1. Connect the AVSS pin to VSS. The microcomputer is in a reset state when applying "L" to the this pin. Switches processor mode. Connect this pin to VSS to when after a reset to start up in single-chip mode. Connect this pin to VCC1 to start up in microprocessor mode. Switches the data bus in external memory space. The data bus is 16-bit long when the this pin is held "L" and 8-bit long when the this pin is held "H". Set it to either one. Connect this pin to VSS when an single-chip mode. Inputs and outputs data (D0 to D7) when these pins are set as the separate bus. Inputs and outputs data (D8 to D15) when external 16-bit data bus is set as the separate bus. Output address bits (A0 to A19). Input and output data (D0 to D7) and output address bits (A0 to A7) by time-sharing when external 8-bit data bus are set as the multiplexed bus. Input and output data (D0 to D7) and output address bits (A1 to A8) by time-sharing when external 16-bit data bus are set as the multiplexed bus. _ _ _ _ Output CS0 to CS3 signals. CS0 to CS3 are chip-select signals to specify an external space. _ _ _ _ _ _ _ Output WRL, WRH, (WR, BHE), RD signals. WRL and WRH or _ _ BHE and WR can be switched by program. _ _ _ · WRL, WRH and RD are selected _ The WRL signal becomes "L" by writing data to an even address in an external memory space. _ The WRH signal becomes "L" by writing data to an odd address in an external memory space. _ The RD pin signal becomes "L" by reading data in an external memory space. _ _ _ · WR, BHE and RD are selected _ The WR signal becomes "L" by writing data in an external memory space. _ The RD signal becomes "L" by reading data in an external memory space. _ The BHE signal becomes "L" by accessing an odd address. _ _ _ Select WR, BHE and RD for an external 8-bit data bus. ALE is a signal to latch the address. _ While the HOLD pin is held "L", the microcomputer is placed in a hold state. _ In a hold state, HLDA outputs a "L" signal. _ While applying a "L" signal to the RDY pin, the microcomputer is placed in a wait state. I/O: Input/Output NOTE: 1. In this manual, hereafter, VCC refers to VCC1 unless otherwise noted. Rev.2.10 Jun 24, 2005 REJ03B0003-0210 REJ03B0003-0210 page 7 of 50 Under development This document is under development and its contents are subject to change. M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) 1. Overview Table 1.4 Pin Description (2) Signal Name Main clock input Main clock output Sub clock input Sub clock output BCLK output Clock output INT interrupt input _ NMI interrupt input Key input interrupt input Timer A I/O Type Description XIN Pin Name I XOUT O XCIN I XCOUT O BCLK CLKOUT _ _ INT0 to INT5 _ NMI O O I I I/O pins for the main clock oscillation circuit. Connect a ceramic resonator or crystal oscillator between XIN and XOUT (1). To use the external clock, input the clock from XIN and leave XOUT open. I/O pins for a sub clock oscillation circuit. Connect a crystal oscillator between XCIN and XCOUT (1). To use the external clock, input the clock from XCIN and leave XCOUT open. Outputs the BCLK signal. The clock of the same cycle as fC, f8, or f32 is output. _ Input pins for the_ interrupt. INT Input pin for the NMI interrupt. I Input pins for the key input interrupt. _ _ KI0 to KI3 TA0OUT to TA4OUT TA0IN to TA4IN ZP Timer B TB0IN to_ TB5IN _ _ Three-phase motor U, U, V, V, W, W control output _ _ Serial I/O CTS0 to CTS2 _ _ RTS0 to RTS2 CLK0 to CLK3 RXD0 to RXD2 SIN3 TXD0 to TXD2 SOUT3 CLKS1 I/O I I I O These are timer A0 to timer A4 I/O pins. These are timer A0 to timer A4 input pins. Input pin for the Z-phase. These are timer B0 to timer B5 input pins. These are Three-phase motor control output pins. I O I/O I I O O O I2C mode SDA0 to SDA2 SCL0 to SCL2 I/O I/O Reference VREF These are send control input pins. These are receive control output pins. These are transfer clock I/O pins. These are serial data input pins. These are serial data input pins. These are serial data output pins. These are serial data output pins. This is output pin for transfer clock output from multiple pins function. These are serial data I/O pins. These are transfer clock I/O pins. (except SCL2 for the N-channel open drain output.) Applies the reference voltage for the A/D converter and D/A I converter. voltage input I Analog input pins for the A/D converter. ADTRG I This is an A/D trigger input pin. ANEX0 I/O ANEX1 I This is the extended analog input pin for the A/D converter. D/A converter DA0, DA1 O These are the output pins for the D/A converter. CAN module CRX0, CRX1 I These are the input pins for the CAN module. A/D converter AN0 to AN7 AN0_0 to AN0_7 AN2_0 to AN2_7 _ This is the extended analog input pin for the A/D converter, and is the output in external op-amp connection mode. I: Input These are the output pins for the CAN module. CTX0, CTX1 O O: Output I/O: Input/Output NOTE: 1. Ask the oscillator maker the oscillation characteristic. Rev.2.10 Jun 24, 2005 REJ03B0003-0210 REJ03B0003-0210 page 8 of 50 Under development This document is under development and its contents are subject to change. M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) 1. Overview Table 1.5 Pin Description (3) Signal Name I/O port Pin Name P0_0 to P0_7 I/O Type Description 8-bit I/O ports in CMOS, having a direction register to select I/O P1_0 to P1_7 an input or output. P2_0 to P2_7 Each pin is set as an input port or output port. An input port P3_0 to P3_7 P4_0 to P4_7 can be set for a pull-up or for no pull-up in 4-bit unit by P5_0 to P5_7 (except P7_1 and P9_1 for the N-channel open drain output.) program. P6_0 to P6_7 P7_0 to P7_7 P8_0 to P8_4 P8_6, P8_7 P9_0 to P9_7 P10_0 to P10_7 _ Input port P8_5 I Input pin for the NMI interrupt. Pin states can be read by the P8_5 bit in the P8 register. I: Input O: Output Rev.2.10 Jun 24, 2005 REJ03B0003-0210 REJ03B0003-0210 I/O: Input/Output page 9 of 50 Under development This document is under development and its contents are subject to change. M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) 2. Central Processing Unit (CPU) 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a register bank. There are two register banks. b31 b15 b8 b7 b0 R2 R0H (R0's high bits) R0L (R0's low bits) R3 R1H (R1's high bits) R1L (R1's low bits) Data Registers (1) R2 R3 A0 Address Registers (1) A1 FB b19 Frame Base Registers (1) b15 b0 INTBH Interrupt Table Register INTBL The upper 4 bits of INTB are INTBH and the lower 16 bits of INTB are INTBL. b19 b0 Program Counter PC b15 b0 USP User Stack Pointer ISP Interrupt Stack Pointer SB Static Base Register b15 b0 FLG b15 Flag Register b8 b7 IPL U b0 I O B S Z D C Carry Flag Debug Flag Zero Flag Sign Flag Register Bank Select Flag Overflow Flag Interrupt Enable Flag Stack Pointer Select Flag Reserved Area Processor Interrupt Priority Level Reserved Area NOTE: 1. These registers comprise a register bank. There are two register banks. Figure 2.1 CPU Registers 2.1 Data Registers (R0, R1, R2, and R3) The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to R3 are the same as R0. The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers. R1H and R1L are the same as R0H and R0L. Conversely R2 and R0 can be combined for use as a 32-bit data register (R2R0). R3R1 is the same as R2R0. 2.2 Address Registers (A0 and A1) The A0 register consists of 16 bits, and is used for address register indirect addressing and address register relative addressing. They also are used for transfers and arithmetic/logic operations. A1 is the same as A0. In some instructions, A1 and A0 can be combined for use as a 32-bit address register (A1A0). Rev.2.10 Jun 24, 2005 REJ03B0003-0210 REJ03B0003-0210 page 10 of 50 Under development This document is under development and its contents are subject to change. M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) 2. Central Processing Unit (CPU) 2.3 Frame Base Register (FB) FB is configured with 16 bits, and is used for FB relative addressing. 2.4 Interrupt Table Register (INTB) INTB is configured with 20 bits, indicating the start address of an interrupt vector table. 2.5 Program Counter (PC) PC is configured with 20 bits, indicating the address of an instruction to be executed. 2.6 User Stack Pointer (USP), Interrupt Stack Pointer (ISP) Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits. Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG. 2.7 Static Base Register (SB) SB is configured with 16 bits, and is used for SB relative addressing. 2.8 Flag Register (FLG) FLG consists of 11 bits, indicating the CPU status. 2.8.1 Carry Flag (C Flag) This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. 2.8.2 Debug Flag (D Flag) This flag is used exclusively for debugging purpose. During normal use, it must be set to "0". 2.8.3 Zero Flag (Z Flag) This flag is set to "1" when an arithmetic operation resulted in 0; otherwise, it is "0". 2.8.4 Sign Flag (S Flag) This flag is set to "1" when an arithmetic operation resulted in a negative value; otherwise, it is "0". 2.8.5 Register Bank Select Flag (B Flag) Register bank 0 is selected when this flag is "0" ; register bank 1 is selected when this flag is "1". 2.8.6 Overflow Flag (O Flag) This flag is set to "1" when the operation resulted in an overflow; otherwise, it is "0". 2.8.7 Interrupt Enable Flag (I Flag) This flag enables a maskable interrupt. Maskable interrupts are disabled when the I flag is "0", and are enabled when the I flag is "1". The I flag is set to "0" when the interrupt request is accepted. 2.8.8 Stack Pointer Select Flag (U Flag) ISP is selected when the U flag is "0" ; USP is selected when the U flag is "1". The U flag is set to "0" when a hardware interrupt request is accepted or an INT instruction for software interrupt Nos. 0 to 31 is executed. 2.8.9 Processor Interrupt Priority Level (IPL) IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. If a requested interrupt has priority greater than IPL, the interrupt request is enabled. 2.8.10 Reserved Area When white to this bit, write "0". When read, its content is indeterminate. Rev.2.10 Jun 24, 2005 REJ03B0003-0210 REJ03B0003-0210 page 11 of 50 Under development This document is under development and its contents are subject to change. M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) 3. Memory 3. Memory Figure 3.1 shows a memory map of the M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4). The address space extends the 1 Mbyte from address 00000h to FFFFFh. The internal ROM is allocated in a lower address direction beginning with address FFFFFh. For example, a 128-Kbyte internal ROM is allocated to the addresses from E0000h to FFFFFh. As for the flash memory version, 4-Kbyte space (block A) exists in 0F000h to 0FFFFh. 4-Kbyte space is mainly for storing data. In addition to storing data, 4-Kbyte space also can store programs. The fixed interrupt vector table is allocated to the addresses from FFFDCh to FFFFFh. Therefore, store the start address of each interrupt routine here. The internal RAM is allocated in an upper address direction beginning with address 00400h. For example, a 5-Kbyte internal RAM is allocated to the addresses from 00400h to 017FFh. In addition to storing data, the internal RAM also stores the stack used when calling subroutines and when interrupts are generated. The SFR is allocated to the addresses from 00000h to 003FFh. Peripheral function control registers are located here. Of the SFR, any area which has no functions allocated is reserved for future use and cannot be used by users. The special page vector table is allocated to the addresses from FFE00h to FFFDBh. This vector is used by the JMPS or JSRS instruction. For details, refer to M16C/60 M16C/60 and M16C/20 M16C/20 Series Software Manual. In memory expansion and microprocessor modes, some areas are reserved for future use and cannot be used by users. 00000h SFR 00400h Internal RAM XXXXXh FFE00h Reserved area (1) 0F000h 0FFFFh 10000h Internal ROM (data area) (3) Special page vector table External area 27000h Reserved area FFFDCh BRK instruction Address match Single step External area Internal ROM (3) Internal RAM Capacity Address XXXXXh Capacity Address YYYYYh 5 Kbytes 017FFh 128 Kbytes 02BFFh 256 Kbytes C0000h YYYYYh E0000h 10 Kbytes 80000h FFFFFh Reserved area (2) Oscillation stop and re-oscillation detection / watchdog timer Internal ROM (program area) (4) FFFFFh NOTES: 1. During memory expansion mode or microprocessor mode, cannot be used. 2. In memory expansion mode, cannot be used. 3. As for the flash memory version, 4-Kbyte space (block A) exists. 4. When using the masked ROM version, write nothing to internal ROM area. 5. Shown here is a memory map for the case where the PM10 bit in the PM1 register is "1" (block A enable) and the PM13 bit in the PM1 register is "1" (internal RAM area is expanded over 192 Kbytes). Figure 3.1 Memory Map Rev.2.10 Jun 24, 2005 REJ03B0003-0210 REJ03B0003-0210 page 12 of 50 Undefined instruction Overflow 28000h DBC NMI Reset Under development This document is under development and its contents are subject to change. M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) 4. Special Function Register (SFR) 4. Special Function Register (SFR) SFR (Special Function Register) is the control register of peripheral functions. Tables 4.1 to 4.16 list the SFR information. Table 4.1 SFR Information (1) Address 0000h 0001h 0002h 0003h Register Symbol After Reset 00000000b (CNVSS pin is "L") 00000011b (CNVSS pin is "H") 00001000b 01001000b 00100000b 00000001b XXXXXX00b XX000000b 0004h Processor Mode Register 0 (1) PM0 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh Processor Mode Register 1 System Clock Control Register 0 System Clock Control Register 1 Chip Select Control Register Address Match Interrupt Enable Register Protect Register PM1 CM0 CM1 CSR AIER PRCR Oscillation Stop Detection Register (2) CM2 0X000000b Watchdog Timer Start Register Watchdog Timer Control Register WDTS WDC Address Match Interrupt Register 0 RMAD0 XXh 00XXXXXXb 00h 00h X0h Address Match Interrupt Register 1 RMAD1 Chip Select Expansion Control Register PLL Control Register 0 CSE PLC0 00h 0001X010b Processor Mode Register 2 PM2 XXX00000b DMA0 Source Pointer SAR0 XXh XXh XXh DMA0 Destination Pointer DAR0 XXh XXh XXh DMA0 Transfer Counter TCR0 XXh XXh DMA0 Control Register DM0CON DMA1 Source Pointer SAR1 XXh XXh XXh DMA1 Destination Pointer DAR1 XXh XXh XXh DMA1 Transfer Counter TCR1 XXh XXh DMA1 Control Register DM1CON 00h 00h X0h 00000X00b 00000X00b X: Undefined NOTES: 1. The PM00 and PM01 bits in the PM0 register do not change at software reset, watchdog timer reset and oscillation stop detection reset. 2. The CM20, CM21, and CM27 bits in the CM2 register do not change at oscillation stop detection reset. 3. The blank areas are reserved and cannot be accessed by users. Rev.2.10 Jun 24, 2005 REJ03B0003-0210 REJ03B0003-0210 page 13 of 50 Under development This document is under development and its contents are subject to change. M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) 4. Special Function Register (SFR) Table 4.2 SFR Information (2) Address 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh 006Fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh Register CAN0/1 Wake-up Interrupt Control Register CAN0 Successful Reception Interrupt Control Register CAN0 Successful Transmission Interrupt Control Register INT3 Interrupt Control Register Timer B5 Interrupt Control Register Timer B4 Interrupt Control Register UART1 Bus Collision Detection Interrupt Control Register Timer B3 Interrupt Control Register UART0 Bus Collision Detection Interrupt Control Register CAN1 Successful Reception Interrupt Control Register INT5 Interrupt Control Register CAN1 Successful Transmission Interrupt Control Register SI/O3 Interrupt Control Register INT4 Interrupt Control Register UART2 Bus Collision Detection Interrupt Control Register DMA0 Interrupt Control Register DMA1 Interrupt Control Register CAN0/1 Error Interrupt Control Register A/D Conversion Interrupt Control Register Key Input Interrupt Control Register UART2 Transmit Interrupt Control Register UART2 Receive Interrupt Control Register UART0 Transmit Interrupt Control Register UART0 Receive Interrupt Control Register UART1 Transmit Interrupt Control Register UART1 Receive Interrupt Control Register Timer A0 Interrupt Control Register Timer A1 Interrupt Control Register Timer A2 Interrupt Control Register Timer A3 Interrupt Control Register Timer A4 Interrupt Control Register Timer B0 Interrupt Control Register Timer B1 Interrupt Control Register Timer B2 Interrupt Control Register INT0 Interrupt Control Register INT1 Interrupt Control Register INT2 Interrupt Control Register CAN0 Message Box 0: Identifier / DLC CAN0 Message Box 0: Data Field CAN0 Message Box 0: Time Stamp CAN0 Message Box 1: Identifier / DLC CAN0 Message Box 1: Data Field CAN0 Message Box 1: Time Stamp X: Undefined NOTE: 1. The blank area is reserved and cannot be accessed by users. Rev.2.10 Jun 24, 2005 REJ03B0003-0210 REJ03B0003-0210 page 14 of 50 Symbol C01WKIC C01WKIC C0RECIC C0TRMIC INT3IC TB5IC TB4IC U1BCNIC TB3IC U0BCNIC C1RECIC INT5IC C1TRMIC S3IC INT4IC U2BCNIC DM0IC DM1IC C01ERRIC C01ERRIC ADIC KUPIC S2TIC S2RIC S0TIC S0RIC S1TIC S1RIC TA0IC TA1IC TA2IC TA3IC TA4IC TB0IC TB1IC TB2IC INT0IC INT1IC INT2IC After Reset XXXXX000b XXXXX000b XXXXX000b XX00X000b XXXXX000b XXXXX000b XXXXX000b XX00X000b XX00X000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XX00X000b XX00X000b XX00X000b XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh Under development This document is under development and its contents are subject to change. M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) 4. Special Function Register (SFR) Table 4.3 SFR Information (3) Address 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh 00A0h 00A1h 00A2h 00A3h 00A4h 00A5h 00A6h 00A7h 00A8h 00A9h 00AAh 00ABh 00ACh 00ADh 00AEh 00AFh 00B0h 00B1h 00B2h 00B3h 00B4h 00B5h 00B6h 00B7h 00B8h 00B9h 00BAh 00BBh 00BCh 00BDh 00BEh 00BFh Register CAN0 Message Box 2: Identifier / DLC CAN0 Message Box 2: Data Field CAN0 Message Box 2: Time Stamp CAN0 Message Box 3: Identifier / DLC CAN0 Message Box 3: Data Field CAN0 Message Box 3: Time Stamp CAN0 Message Box 4: Identifier / DLC CAN0 Message Box 4: Data Field CAN0 Message Box 4: Time Stamp CAN0 Message Box 5: Identifier / DLC CAN0 Message Box 5: Data Field CAN0 Message Box 5: Time Stamp X: Undefined Rev.2.10 Jun 24, 2005 REJ03B0003-0210 REJ03B0003-0210 page 15 of 50 Symbol After Reset XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh Under development This document is under development and its contents are subject to change. M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) 4. Special Function Register (SFR) Table 4.4 SFR Information (4) Address 00C0h 00C1h 00C2h 00C3h 00C4h 00C5h 00C6h 00C7h 00C8h 00C9h 00CAh 00CBh 00CCh 00CDh 00CEh 00CFh 00D0h 00D1h 00D2h 00D3h 00D4h 00D5h 00D6h 00D7h 00D8h 00D9h 00DAh 00DBh 00DCh 00DDh 00DEh 00DFh 00E0h 00E1h 00E2h 00E3h 00E4h 00E5h 00E6h 00E7h 00E8h 00E9h 00EAh 00EBh 00ECh 00EDh 00EEh 00EFh 00F0h 00F1h 00F2h 00F3h 00F4h 00F5h 00F6h 00F7h 00F8h 00F9h 00FAh 00FBh 00FCh 00FDh 00FEh 00FFh Register CAN0 Message Box 6: Identifier / DLC CAN0 Message Box 6: Data Field CAN0 Message Box 6: Time Stamp CAN0 Message Box 7: Identifier / DLC CAN0 Message Box 7: Data Field CAN0 Message Box 7: Time Stamp CAN0 Message Box 8: Identifier / DLC CAN0 Message Box 8: Data Field CAN0 Message Box 8: Time Stamp CAN0 Message Box 9: Identifier / DLC CAN0 Message Box 9: Data Field CAN0 Message Box 9: Time Stamp X: Undefined Rev.2.10 Jun 24, 2005 REJ03B0003-0210 REJ03B0003-0210 page 16 of 50 Symbol After Reset XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh Under development This document is under development and its contents are subject to change. M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) 4. Special Function Register (SFR) Table 4.5 SFR Information (5) Address 0100h 0101h 0102h 0103h 0104h 0105h 0106h 0107h 0108h 0109h 010Ah 010Bh 010Ch 010Dh 010Eh 010Fh 0110h 0111h 0112h 0113h 0114h 0115h 0116h 0117h 0118h 0119h 011Ah 011Bh 011Ch 011Dh 011Eh 011Fh 0120h 0121h 0122h 0123h 0124h 0125h 0126h 0127h 0128h 0129h 012Ah 012Bh 012Ch 012Dh 012Eh 012Fh 0130h 0131h 0132h 0133h 0134h 0135h 0136h 0137h 0138h 0139h 013Ah 013Bh 013Ch 013Dh 013Eh 013Fh Register CAN0 Message Box 10: Identifier / DLC CAN0 Message Box 10: Data Field CAN0 Message Box 10: Time Stamp CAN0 Message Box 11: Identifier / DLC CAN0 Message Box 11: Data Field CAN0 Message Box 11: Time Stamp CAN0 Message Box 12: Identifier / DLC CAN0 Message Box 12: Data Field CAN0 Message Box 12: Time Stamp CAN0 Message Box 13: Identifier / DLC CAN0 Message Box 13: Data Field CAN0 Message Box 13: Time Stamp X: Undefined Rev.2.10 Jun 24, 2005 REJ03B0003-0210 REJ03B0003-0210 page 17 of 50 Symbol After Reset XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh Under development This document is under development and its contents are subject to change. M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) 4. Special Function Register (SFR) Table 4.6 SFR Information (6) Address 0140h 0141h 0142h 0143h 0144h 0145h 0146h 0147h 0148h 0149h 014Ah 014Bh 014Ch 014Dh 014Eh 014Fh 0150h 0151h 0152h 0153h 0154h 0155h 0156h 0157h 0158h 0159h 015Ah 015Bh 015Ch 015Dh 015Eh 015Fh 0160h 0161h 0162h 0163h 0164h 0165h 0166h 0167h 0168h 0169h 016Ah 016Bh 016Ch 016Dh 016Eh 016Fh 0170h 0171h 0172h 0173h 0174h 0175h 0176h 0177h 0178h 0179h 017Ah 017Bh 017Ch 017Dh 017Eh 017Fh Register Symbol CAN0 Message Box 14: Identifier /DLC CAN0 Message Box 14: Data Field CAN0 Message Box 14: Time Stamp CAN0 Message Box 15: Identifier /DLC CAN0 Message Box 15: Data Field CAN0 Message Box 15: Time Stamp CAN0 Global Mask Register C0GMR CAN0 Local Mask A Register C0LMAR CAN0 Local Mask B Register C0LMBR X: Undefined NOTE: 1. The blank areas are reserved and cannot be accessed by users. Rev.2.10 Jun 24, 2005 REJ03B0003-0210 REJ03B0003-0210 page 18 of 50 After Reset XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh Under development This document is under development and its contents are subject to change. M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) 4. Special Function Register (SFR) Table 4.7 SFR Information (7) Address 0180h 0181h 0182h 0183h 0184h 0185h 0186h 0187h 0188h 0189h 018Ah 018Bh 018Ch 018Dh 018Eh 018Fh 0190h 0191h 0192h 0193h 0194h 0195h 0196h 0197h 0198h 0199h 019Ah 019Bh 019Ch 019Dh 019Eh 019Fh 01A0h 01A1h 01A2h 01A3h 01A4h 01A5h 01A6h 01A7h 01A8h 01A9h 01AAh 01ABh 01ACh 01ADh 01AEh 01AFh 01B0h 01B1h 01B2h 01B3h 01B4h 01B5h 01B6h 01B7h 01B8h 01B9h 01BAh 01BBh 01BCh 01BDh 01BEh 01BFh Register Symbol After Reset Flash Memory Control Register 1 (1) FMR1 0X00XX0Xb Flash Memory Control Register 0 (1) FMR0 Address Match Interrupt Register 2 RMAD2 Address Match Interrupt Enable Register 2 AIER2 Address Match Interrupt Register 3 RMAD3 00000001b 00h 00h X0h XXXXXX00b 00h 00h X0h X: Undefined NOTES: 1. These registers are included in the flash memory version. Cannot be accessed by users in the mask ROM version. 2. The blank areas are reserved and cannot be accessed by users. Rev.2.10 Jun 24, 2005 REJ03B0003-0210 REJ03B0003-0210 page 19 of 50 Under development This document is under development and its contents are subject to change. M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) 4. Special Function Register (SFR) Table 4.8 SFR Information (8) Address 01C0h 01C1h 01C2h 01C3h 01C4h 01C5h 01C6h 01C7h 01C8h 01C9h 01CAh 01CBh 01CCh 01CDh 01CEh 01CFh 01D0h 01D1h 01D2h 01D3h 01D4h 01D5h 01D6h 01D7h 01D8h 01D9h 01DAh 01DBh 01DCh 01DDh 01DEh 01DFh 01E0h 01E1h 01E2h 01E3h 01E4h 01E5h 01E6h 01E7h 01E8h 01E9h 01EAh 01EBh 01ECh 01EDh 01EEh 01EFh 01F0h 01F1h 01F2h 01F3h 01F4h 01F5h 01F6h 01F7h 01F8h 01F9h 01FAh 01FBh 01FCh 01FDh 01FEh 01FFh Timer B3, B4, B5 Count Start Flag Register Symbol TBSR Timer A1-1 Register TA11 Timer A2-1 Register TA21 Timer A4-1 Register TA41 Three-Phase PWM Control Register 0 Three-Phase PWM Control Register 1 Three-Phase Output Buffer Register 0 Three-Phase Output Buffer Register 1 Dead Time Timer Timer B2 Interrupt Occurrence Frequency Set Counter INVC0 INVC1 IDB0 IDB1 DTT ICTB2 Timer B3 Register TB3 Timer B4 Register TB4 Timer B5 Register TB5 Timer B3 Mode Register Timer B4 Mode Register Timer B5 Mode Register Interrupt Cause Select Register 0 Interrupt Cause Select Register 1 SI/O3 Transmit/Receive Register TB3MR TB4MR TB5MR IFSR0 IFSR1 S3TRR 00XX0000b 00XX0000b 00XX0000b 00XXX000b 00h XXh SI/O3 Control Register SI/O3 Bit Rate Generator S3C S3BRG 01000000b XXh UART0 Special Mode Register 4 UART0 Special Mode Register 3 UART0 Special Mode Register 2 UART0 Special Mode Register UART1 Special Mode Register 4 UART1 Special Mode Register 3 UART1 Special Mode Register 2 UART1 Special Mode Register UART2 Special Mode Register 4 UART2 Special Mode Register 3 UART2 Special Mode Register 2 UART2 Special Mode Register UART2 Transmit/Receive Mode Register UART2 Bit Rate Generator U0SMR4 U0SMR3 U0SMR2 U0SMR U1SMR4 U1SMR3 U1SMR2 U1SMR U2SMR4 U2SMR3 U2SMR2 U2SMR U2MR U2BRG UART2 Transmit Buffer Register U2TB UART2 Transmit/Receive Control Register 0 UART2 Transmit/Receive Control Register 1 U2C0 U2C1 UART2 Receive Buffer Register U2RB 00h 000X0X0Xb X0000000b X0000000b 00h 000X0X0Xb X0000000b X0000000b 00h 000X0X0Xb X0000000b X0000000b 00h XXh XXh XXh 00001000b 00000010b XXh XXh X: Undefined NOTE: 1. The blank areas are reserved and cannot be accessed by users. Rev.2.10 Jun 24, 2005 REJ03B0003-0210 REJ03B0003-0210 page 20 of 50 After Reset 000XXXXXb XXh XXh XXh XXh XXh XXh 00h 00h 00h 00h XXh XXh XXh XXh XXh XXh XXh XXh Under development This document is under development and its contents are subject to change. M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) 4. Special Function Register (SFR) Table 4.9 SFR Information (9) Address 0200h 0201h 0202h 0203h 0204h 0205h 0206h 0207h 0208h 0209h 020Ah 020Bh 020Ch 020Dh 020Eh 020Fh 0210h 0211h 0212h 0213h 0214h 0215h 0216h 0217h 0218h 0219h 021Ah 021Bh 021Ch 021Dh 021Eh 021Fh 0220h 0221h 0222h 0223h 0224h 0225h 0226h 0227h 0228h 0229h 022Ah 022Bh 022Ch 022Dh 022Eh 022Fh 0230h 0231h 0232h 0233h 0234h 0235h 0236h 0237h 0238h 0239h 023Ah 023Bh 023Ch 023Dh 023Eh 023Fh CAN0 Message Control Register 0 CAN0 Message Control Register 1 CAN0 Message Control Register 2 CAN0 Message Control Register 3 CAN0 Message Control Register 4 CAN0 Message Control Register 5 CAN0 Message Control Register 6 CAN0 Message Control Register 7 CAN0 Message Control Register 8 CAN0 Message Control Register 9 CAN0 Message Control Register 10 CAN0 Message Control Register 11 CAN0 Message Control Register 12 CAN0 Message Control Register 13 CAN0 Message Control Register 14 CAN0 Message Control Register 15 Register Symbol C0MCTL0 C0MCTL1 C0MCTL2 C0MCTL3 C0MCTL4 C0MCTL5 C0MCTL6 C0MCTL7 C0MCTL8 C0MCTL9 C0MCTL10 C0MCTL10 C0MCTL11 C0MCTL11 C0MCTL12 C0MCTL12 C0MCTL13 C0MCTL13 C0MCTL14 C0MCTL14 C0MCTL15 C0MCTL15 CAN0 Control Register C0CTLR CAN0 Status Register C0STR CAN0 Slot Status Register C0SSTR CAN0 Interrupt Control Register C0ICR CAN0 Extended ID Register C0IDR CAN0 Configuration Register C0CONR CAN0 Receive Error Count Register CAN0 Transmit Error Count Register C0RECR C0TECR CAN0 Time Stamp Register C0TSR CAN1 Message Control Register 0 CAN1 Message Control Register 1 CAN1 Message Control Register 2 CAN1 Message Control Register 3 CAN1 Message Control Register 4 CAN1 Message Control Register 5 CAN1 Message Control Register 6 CAN1 Message Control Register 7 CAN1 Message Control Register 8 CAN1 Message Control Register 9 CAN1 Message Control Register 10 CAN1 Message Control Register 11 CAN1 Message Control Register 12 CAN1 Message Control Register 13 CAN1 Message Control Register 14 CAN1 Message Control Register 15 C1MCTL0 C1MCTL1 C1MCTL2 C1MCTL3 C1MCTL4 C1MCTL5 C1MCTL6 C1MCTL7 C1MCTL8 C1MCTL9 C1MCTL10 C1MCTL10 C1MCTL11 C1MCTL11 C1MCTL12 C1MCTL12 C1MCTL13 C1MCTL13 C1MCTL14 C1MCTL14 C1MCTL15 C1MCTL15 CAN1 Control Register C1CTLR CAN1 Status Register C1STR CAN1 Slot Status Register C1SSTR CAN1 Interrupt Control Register C1ICR CAN1 Extended ID Register C1IDR CAN1 Configuration Register C1CONR CAN1 Receive Error Count Register CAN1 Transmit Error Count Register C1RECR C1TECR CAN1 Time Stamp Register C1TSR X: Undefined Rev.2.10 Jun 24, 2005 REJ03B0003-0210 REJ03B0003-0210 page 21 of 50 After Reset 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h X0000001b XX0X0000b 00h X0000001b 00h 00h 00h 00h 00h 00h XXh XXh 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h X0000001b XX0X0000b 00h X0000001b 00h 00h 00h 00h 00h 00h XXh XXh 00h 00h 00h 00h Under development This document is under development and its contents are subject to change. M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) 4. Special Function Register (SFR) Table 4.10 SFR Information (10) Address 0240h 0241h 0242h 0243h 0244h 0245h 0246h 0247h 0248h 0249h 024Ah 024Bh 024Ch 024Dh 024Eh 024Fh 0250h 0251h 0252h 0253h 0254h 0255h 0256h 0257h 0258h 0259h 025Ah 025Bh 025Ch 025Dh 025Eh 025Fh 0260h 0261h 0262h 0263h 0264h 0265h 0266h 0267h 0268h 0269h 026Ah 026Bh 026Ch 026Dh 026Eh 026Fh 0270h 0271h 0272h 0273h 0274h 0275h 0276h 0277h 0278h 0279h 027Ah 027Bh 027Ch 027Dh 027Eh 027Fh Register Symbol CAN0 Acceptance Filter Support Register C0AFS CAN1 Acceptance Filter Support Register C1AFS Peripheral Clock Select Register CAN0/1 Clock Select Register PCLKR CCLKR CAN1 Message Box 0: Identifier / DLC CAN1 Message Box 0: Data Field CAN1 Message Box 0:Time Stamp CAN1 Message Box 1: Identifier / DLC CAN1 Message Box 1: Data Field CAN1 Message Box 1:Time Stamp X: Undefined NOTE: 1. The blank areas are reserved and cannot be accessed by users. Rev.2.10 Jun 24, 2005 REJ03B0003-0210 REJ03B0003-0210 page 22 of 50 After Reset XXh XXh XXh XXh 00h 00h XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh Under development This document is under development and its contents are subject to change. M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) 4. Special Function Register (SFR) Table 4.11 SFR Information (11) Address 0280h 0281h 0282h 0283h 0284h 0285h 0286h 0287h 0288h 0289h 028Ah 028Bh 028Ch 028Dh 028Eh 028Fh 0290h 0291h 0292h 0293h 0294h 0295h 0296h 0297h 0298h 0299h 029Ah 029Bh 029Ch 029Dh 029Eh 029Fh 02A0h 02A1h 02A2h 02A3h 02A4h 02A5h 02A6h 02A7h 02A8h 02A9h 02AAh 02ABh 02ACh 02ADh 02AEh 02AFh 02B0h 02B1h 02B2h 02B3h 02B4h 02B5h 02B6h 02B7h 02B8h 02B9h 02BAh 02BBh 02BCh 02BDh 02BEh 02BFh Register CAN1 Message Box 2: Identifier / DLC CAN1 Message Box 2: Data Field CAN1 Message Box 2: Time Stamp CAN1 Message Box 3: Identifier / DLC CAN1 Message Box 3: Data Field CAN1 Message Box 3: Time Stamp CAN1 Message Box 4: Identifier / DLC CAN1 Message Box 4: Data Field CAN1 Message Box 4: Time Stamp CAN1 Message Box 5: Identifier / DLC CAN1 Message Box 5: Data Field CAN1 Message Box 5: Time Stamp X: Undefined Rev.2.10 Jun 24, 2005 REJ03B0003-0210 REJ03B0003-0210 page 23 of 50 Symbol After Reset XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh Under development This document is under development and its contents are subject to change. M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) 4. Special Function Register (SFR) Table 4.12 SFR Information (12) Address 02C0h 02C1h 02C2h 02C3h 02C4h 02C5h 02C6h 02C7h 02C8h 02C9h 02CAh 02CBh 02CCh 02CDh 02CEh 02CFh 02D0h 02D1h 02D2h 02D3h 02D4h 02D5h 02D6h 02D7h 02D8h 02D9h 02DAh 02DBh 02DCh 02DDh 02DEh 02DFh 02E0h 02E1h 02E2h 02E3h 02E4h 02E5h 02E6h 02E7h 02E8h 02E9h 02EAh 02EBh 02ECh 02EDh 02EEh 02EFh 02F0h 02F1h 02F2h 02F3h 02F4h 02F5h 02F6h 02F7h 02F8h 02F9h 02FAh 02FBh 02FCh 02FDh 02FEh 02FFh Register CAN1 Message Box 6: Identifier / DLC CAN1 Message Box 6: Data Field CAN1 Message Box 6: Time Stamp CAN1 Message Box 7: Identifier / DLC CAN1 Message Box 7: Data Field CAN1 Message Box 7: Time Stamp CAN1 Message Box 8: Identifier / DLC CAN1 Message Box 8: Data Field CAN1 Message Box 8: Time Stamp CAN1 Message Box 9: Identifier / DLC CAN1 Message Box 9: Data Field CAN1 Message Box 9: Time Stamp X: Undefined Rev.2.10 Jun 24, 2005 REJ03B0003-0210 REJ03B0003-0210 page 24 of 50 Symbol After Reset XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh Under development This document is under development and its contents are subject to change. M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) 4. Special Function Register (SFR) Table 4.13 SFR Information (13) Address 0300h 0301h 0302h 0303h 0304h 0305h 0306h 0307h 0308h 0309h 030Ah 030Bh 030Ch 030Dh 030Eh 030Fh 0310h 0311h 0312h 0313h 0314h 0315h 0316h 0317h 0318h 0319h 031Ah 031Bh 031Ch 031Dh 031Eh 031Fh 0320h 0321h 0322h 0323h 0324h 0325h 0326h 0327h 0328h 0329h 032Ah 032Bh 032Ch 032Dh 032Eh 032Fh 0330h 0331h 0332h 0333h 0334h 0335h 0336h 0337h 0338h 0339h 033Ah 033Bh 033Ch 033Dh 033Eh 033Fh Register CAN1 Message Box 10: Identifier / DLC CAN1 Message Box 10: Data Field CAN1 Message Box 10: Time Stamp CAN1 Message Box 11: Identifier / DLC CAN1 Message Box 11: Data Field CAN1 Message Box 11: Time Stamp CAN1 Message Box 12: Identifier / DLC CAN1 Message Box 12: Data Field CAN1 Message Box 12: Time Stamp CAN1 Message Box 13: Identifier / DLC CAN1 Message Box 13: Data Field CAN1 Message Box 13: Time Stamp X: Undefined Rev.2.10 Jun 24, 2005 REJ03B0003-0210 REJ03B0003-0210 page 25 of 50 Symbol After Reset XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh Under development This document is under development and its contents are subject to change. M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) 4. Special Function Register (SFR) Table 4.14 SFR Information (14) Address 0340h 0341h 0342h 0343h 0344h 0345h 0346h 0347h 0348h 0349h 034Ah 034Bh 034Ch 034Dh 034Eh 034Fh 0350h 0351h 0352h 0353h 0354h 0355h 0356h 0357h 0358h 0359h 035Ah 035Bh 035Ch 035Dh 035Eh 035Fh 0360h 0361h 0362h 0363h 0364h 0365h 0366h 0367h 0368h 0369h 036Ah 036Bh 036Ch 036Dh 036Eh 036Fh 0370h 0371h 0372h 0373h 0374h 0375h 0376h 0377h 0378h 0379h 037Ah 037Bh 037Ch 037Dh 037Eh 037Fh Register Symbol CAN1 Message Box 14: Identifier / DLC CAN1 Message Box 14: Data Field CAN1 Message Box 14: Time Stamp CAN1 Message Box 15: Identifier / DLC CAN1 Message Box 15: Data Field CAN1 Message Box 15: Time Stamp CAN1 Global Mask Register C1GMR CAN1 Local Mask A Register C1LMAR CAN1 Local Mask B Register C1LMBR X: Undefined NOTE: 1. The blank areas are reserved and cannot be accessed by users. Rev.2.10 Jun 24, 2005 REJ03B0003-0210 REJ03B0003-0210 page 26 of 50 After Reset XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh Under development This document is under development and its contents are subject to change. M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) 4. Special Function Register (SFR) Table 4.15 SFR Information (15) Address 0380h 0381h 0382h 0383h 0384h 0385h 0386h 0387h 0388h 0389h 038Ah 038Bh 038Ch 038Dh 038Eh 038Fh 0390h 0391h 0392h 0393h 0394h 0395h 0396h 0397h 0398h 0399h 039Ah 039Bh 039Ch 039Dh 039Eh 039Fh 03A0h 03A1h 03A2h 03A3h 03A4h 03A5h 03A6h 03A7h 03A8h 03A9h 03AAh 03ABh 03ACh 03ADh 03AEh 03AFh 03B0h 03B1h 03B2h 03B3h 03B4h 03B5h 03B6h 03B7h 03B8h 03B9h 03BAh 03BBh 03BCh 03BDh 03BEh 03BFh Count Start Flag Clock Prescaler Reset Flag One-Shot Start Flag Trigger Select Register Up/Down Flag Register Symbol TABSR CPSRF ONSF TRGSR UDF After Reset 00h 0XXXXXXXb 00h 00h 00h (1) Timer A0 Register TA0 Timer A1 Register TA1 Timer A2 Register TA2 Timer A3 Register TA3 Timer A4 Register TA4 Timer B0 Register TB0 Timer B1 Register TB1 Timer B2 Register TB2 Timer A0 Mode Register Timer A1 Mode Register Timer A2 Mode Register Timer A3 Mode Register Timer A4 Mode Register Timer B0 Mode Register Timer B1 Mode Register Timer B2 Mode Register Timer B2 Special Mode Register TA0MR TA1MR TA2MR TA3MR TA4MR TB0MR TB1MR TB2MR TB2SC UART0 Transmit/Receive Mode Register UART0 Bit Rate Generator U0MR U0BRG UART0 Transmit Buffer Register U0TB UART0 Transmit/Receive Control Register 0 UART0 Transmit/Receive Control Register 1 U0C0 U0C1 UART0 Receive Buffer Register U0RB UART1 Transmit/Receive Mode Register UART1 Bit Rate Generator U1MR U1BRG UART1 Transmit Buffer Register U1TB UART1 Transmit/Receive Control Register 0 UART1 Transmit/Receive Control Register 1 U1C0 U1C1 UART1 Receive Buffer Register U1RB UART Transmit/Receive Control Register 2 UCON 00h XXh XXh XXh 00001000b 00XX0010b XXh XXh 00h XXh XXh XXh 00001000b 00XX0010b XXh XXh X0000000b DMA0 Request Cause Select Register DM0SL 00h DMA1 Request Cause Select Register DM1SL 00h CRC Data Register CRCD CRC Input Register CRCIN XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh 00h 00h 00h 00h 00h 00XX0000b 00XX0000b 00XX0000b XXXXXX00b XXh XXh XXh X: Undefined NOTES: 1. The TA2P to TA4P bits in the UDF register are set to "0" after reset. However, the contents in these bits are indeterminate when read. 2. The blank areas are reserved and cannot be accessed by users. Rev.2.10 Jun 24, 2005 REJ03B0003-0210 REJ03B0003-0210 page 27 of 50 Under development This document is under development and its contents are subject to change. M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) 4. Special Function Register (SFR) Table 4.16 SFR Information (16) Address 03C0h 03C1h 03C2h 03C3h 03C4h 03C5h 03C6h 03C7h 03C8h 03C9h 03CAh 03CBh 03CCh 03CDh 03CEh 03CFh 03D0h 03D1h 03D2h 03D3h 03D4h 03D5h 03D6h 03D7h 03D8h 03D9h 03DAh 03DBh 03DCh 03DDh 03DEh 03DFh 03E0h 03E1h 03E2h 03E3h 03E4h 03E5h 03E6h 03E7h 03E8h 03E9h 03EAh 03EBh 03ECh 03EDh 03EEh 03EFh 03F0h 03F1h 03F2h 03F3h 03F4h 03F5h 03F6h 03F7h 03F8h 03F9h 03FAh 03FBh 03FCh Register Symbol After Reset XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh A/D Register 0 AD0 A/D Register 1 AD1 A/D Register 2 AD2 A/D Register 3 AD3 A/D Register 4 AD4 A/D Register 5 AD5 A/D Register 6 AD6 A/D Register 7 AD7 A/D Control Register 2 ADCON2 00h A/D Control Register 0 A/D Control Register 1 D/A Register 0 ADCON0 ADCON1 DA0 00000XXXb 00h 00h D/A Register 1 DA1 00h D/A Control Register DACON 00h Port P0 Register Port P1 Register Port P0 Direction Register Port P1 Direction Register Port P2 Register Port P3 Register Port P2 Direction Register Port P3 Direction Register Port P4 Register Port P5 Register Port P4 Direction Register Port P5 Direction Register Port P6 Register Port P7 Register Port P6 Direction Register Port P7 Direction Register Port P8 Register Port P9 Register Port P8 Direction Register Port P9 Direction Register Port P10 Register P0 P1 PD0 PD1 P2 P3 PD2 PD3 P4 P5 PD4 PD5 P6 P7 PD6 PD7 P8 P9 PD8 PD9 P10 XXh XXh 00h 00h XXh XXh 00h 00h XXh XXh 00h 00h XXh XXh 00h 00h XXh XXh 00X00000b 00h XXh Port P10 Direction Register PD10 00h Pull-up Control Register 0 PUR0 03FDh Pull-up Control Register 1 PUR1 03FEh 03FFh Pull-up Control Register 2 Port Control Register PUR2 PCR 00h 00000000b (1) 00000010b 00h 00h X: Undefined NOTES: 1. At hardware reset, the register is as follows: "00000000b" where "L" is input to the CNVSS pin "00000010b" where "H" is input to the CNVSS pin At software reset, watchdog timer reset and oscillation stop detection reset, the register is as follows: "00000000b" where the PM01 to PM00 bits in the PM0 register are "00b" (single-chip mode) "00000010b" where the PM01 to PM00 bits in the PM0 register are "01b" (memory expansion mode) or "11b" (microprocessor mode) 2. The blank areas are reserved and cannot be accessed by users. Rev.2.10 Jun 24, 2005 REJ03B0003-0210 REJ03B0003-0210 page 28 of 50 Under development This document is under development and its contents are subject to change. M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) 5. Electric Characteristics 5. Electrical Characteristics Table 5.1 Absolute Maximum Ratings Condition Rated Value Unit VCC Supply Voltage (VCC1 = VCC2) VCC = AVCC ­0.3 to 6.5 V AVCC Analog Supply Voltage VCC = AVCC VI Input RESET, CNVSS, BYTE, Voltage P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, Symbol Parameter ­0.3 to 6.5 V ­0.3 to VCC+0.3 V ­0.3 to 6.5 V ­0.3 to VCC+0.3 V _ P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7, VREF, XIN P7_1, P9_1 Output P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, Voltage VO P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7, XOUT ­0.3 to 6.5 V 700 mW Pd P7_1, P9_1 Power Dissipation Topr Operating Ambient When the Microcomputer is T version: ­40 to 85 Temperature V version: ­40 to 125 (option) Operating Flash Program Erase Tstg Storage Temperature option: All options are on request basis. Rev.2.10 Jun 24, 2005 REJ03B0003-0210 REJ03B0003-0210 page 29 of 50 Topr = 25°C °C 0 to 60 ­65 to 150 °C Under development This document is under development and its contents are subject to change. M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) 5. Electric Characteristics Table 5.2 Recommended Operating Conditions (1) Symbol (1) Parameter Min. Standard Max. Typ. Unit VCC Supply Voltage (VCC1 = VCC2) AVCC Analog Supply Voltage VCC V VSS Supply Voltage 0 V AVSS Analog Supply Voltage 0 V VIH HIGH Input P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, Voltage P7_0, P7_2 to P7_7, P8_0 to P8_7, P9_0, P9_2 to P9_7, 4.2 5.0 5.5 V VCC V 0.8V CC 6.5 V 0.8V CC VCC V 0.5V CC VCC V 0 0.2VCC V 0 0.2VCC V 0 0.16VCC 16VCC V ­10.0 mA ­5.0 mA 10.0 mA 5.0 mA 0.8V CC _ P10_0 to P10_7, XIN, RESET, CNVSS, BYTE P7_1, P9_1 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 (During single-chip mode) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 (Data input during memory expansion and microprocessor modes) VIL LOW Input P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, Voltage P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, _ XIN, RESET, CNVSS, BYTE P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 (During single-chip mode) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 (Data input during memory expansion and microprocessor modes) IOH(peak) HIGH Peak P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, Output Current P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7 IOH(avg) HIGH Average P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, Output Current P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0, IOL(peak) LOW Peak IOL(avg) LOW Average P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, Output Current P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 P9_2 to P9_7, P10_0 to P10_7 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, Output Current P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 NOTES: 1. Referenced to VCC = 4.2 to 5.5V at Topr = ­40 to 85°C unless otherwise specified. 2. The mean output current is the mean value within 100 ms. 3. The total IOL(peak) for ports P0, P1, P2, P8_6, P8_7, P9 and P10 must be 80mA max. The total IOL(peak) for ports P3, P4, P5, P6, P7 and P8_0 to P8_4 must be 80mA max. The total IOH(peak) for ports P0, P1, and P2 must be ­40mA max. The total IOH(peak) for ports P3, P4 and P5 must be ­40mA max. The total IOH(peak) for ports P6, P7 and P8_0 to P8_4 must be ­40mA max. The total IOH(peak) for ports P8_6, P8_7, P9 and P10 must be ­40mA max. Rev.2.10 Jun 24, 2005 REJ03B0003-0210 REJ03B0003-0210 page 30 of 50 Under development This document is under development and its contents are subject to change. M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) 5. Electric Characteristics Table 5.3 Recommended Operating Conditions (2) Symbol f(XIN) (1) Parameter Min. Main Clock Input Oscillation No Wait Mask ROM Version VCC = 4.2 to 5.5V Frequency (2) (3) (4) Standard Max. Typ. 0 Unit 16 MHz 50 kHz Flash Memory Version f(XCIN) Sub Clock Oscillation Frequency f(Ring) On-chip Oscillation Frequency f(PLL) PLL Clock Oscillation Frequency f(BCLK) CPU Operation Clock tsu(PLL) PLL Frequency Synthesizer Stabilization Wait Time 20 ms f(ripple) Power Supply Ripple Allowable Frequency (VCC) 10 kHz V P-P(ripple) Power Supply Ripple Allowable Amplitude Voltage VCC = 5V V CC(|V/T|) Power Supply Ripple Rising/Falling Gradient 0.5 0.3 V/ms 32.768 1 VCC = 4.2 to 5.5V otherwise specified. 2. Relationship between main clock oscillation frequency and supply voltage is shown right. 3. Execute program/erase of flash memory by VCC = 5.0 ± 0.5 V. 4. When using over 16MHz, use PLL clock. PLL clock oscillation frequency which can be used is 16MHz or 20MHz. VP-P(ripple) Power Supply Ripple Allowable Amplitude Voltage page 31 of 50 20 MHz 0 20 MHz V Main clock input oscillation frequency 16.0 0.0 4.2 5.5 VCC [V] (main clock: no division) f(ripple) VCC Figure 5.1 Timing of Voltage Fluctuation Rev.2.10 Jun 24, 2005 REJ03B0003-0210 REJ03B0003-0210 f(XIN) operating maximum frequency [MHz] VCC = 5V NOTES: 1. Referenced to VCC = 4.2 to 5.5V at Topr = ­40 to 85°C unless f(ripple) Power Supply Ripple Allowable Frequency (VCC) MHz 16 VP-P(ripple) Under development This document is under development and its contents are subject to change. M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) 5. Electric Characteristics Table 5.4 Electrical Characteristics (1) (1) Parameter Symbol P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, VOH HIGH Output Voltage P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7 XOUT HIGHPOWER VOH HIGH Output Voltage LOWPOWER XCOUT HIGHPOWER HIGH Output Voltage LOWPOWER P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, VOL LOW Output Voltage P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, VOL LOW Output Voltage P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 VOL XOUT HIGHPOWER LOW Output Voltage LOWPOWER XCOUT HIGHPOWER LOW Output Voltage LOWPOWER _ _ VT+-VT- Hysteresis HOLD, RDY, TA0IN to TA4IN, TB0IN to TB5IN, _ _ _ _ _ _ INT0 to INT5, NMI, ADTRG, CTS0 to CTS2, SCL0 to SCL2, SDA0 to SDA2, CLK0 to CLK3, _ _ TA0OUT to TA4OUT, KI0 to KI3, RXD0 to RXD2, SIN3 _ VT+-VT- Hysteresis RESET VT+-VT- Hysteresis XIN HIGH Input IIH P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, Current P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, _ XIN, RESET, CNVSS, BYTE LOW Input P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, IIL Current P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, _ XIN, RESET, CNVSS, BYTE P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, RPULLUP Pull-up Resistance P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7 Feedback Resistance XIN RfXIN Feedback Resistance XCIN RfXCIN RAM Retention Voltage VRAM NOTES: VOH HIGH Output Voltage IOH = ­5mA Standard Min. Typ. Max. VCC VCC-2.0 IOH = ­200µA VCC-0.3 VCC V 3.0 3.0 VCC VCC V Measuring Condition IOH = ­1mA IOH = ­0.5mA With no load applied With no load applied IOL = 5mA 2.5 1.6 Unit V V 2.0 V IOL = 200µA 0.45 V IOL = 1mA IOL = 0.5mA With no load applied With no load applied 2.0 2.0 V 0 0 V 0.2 1.0 V 0.2 0.2 V VI = 5V 2.5 0.8 5.0 V µA VI = 0V ­5.0 µA 170 k VI = 0V 30 50 1.5 15 At stop mode 2.0 M M V 1. Referenced to VCC = 4.2 to 5.5V, VSS = 0V at Topr = ­40 to 85°C, f(BCLK) = 20MHz unless otherwise specified. Rev.2.10 Jun 24, 2005 REJ03B0003-0210 REJ03B0003-0210 page 32 of 50 Under development This document is under development and its contents are subject to change. M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) Table 5.5 Electrical Characteristics (2) Symbol ICC 5. Electric Characteristics (1) Parameter Measuring Condition Min. Power Supply Output pins are open Mask ROM f(BCLK) = 20MHz, Current and other pins are VSS. Standard Typ. Max. 18 32 Unit PLL operation, (VCC = 4.2 to 5.5V) mA No division On-chip oscillation, No division Flash Memory f(BCLK) = 20MHz, 1 20 mA 34 mA PLL operation, No division On-chip oscillation, No division Flash Memory f(BCLK) = 10MHz, Program Mask ROM mA 15 mA 25 mA 25 µA 25 µA 420 µA 50 µA 8.5 µA 3.0 µA VCC = 5V Flash Memory f(BCLK) = 10MHz, Erase 1.8 VCC = 5V f(BCLK) = 32kHz, Low power dissipation mode, ROM (2) Flash Memory f(BCLK) = 32kHz, Low power dissipation mode, RAM (2) f(BCLK) = 32kHz, Low power dissipation mode, Flash memory (2) Mask ROM On-chip oscillation, Flash Memory Wait mode f(BCLK) = 32kHz, Wait mode (3), Oscillation capacity High f(BCLK) = 32kHz, Wait mode (3), Oscillation capacity Low Stop mode, 0.8 3.0 µA Topr = 25°C NOTES: 1. Referenced to VCC = 4.2 to 5.5V, VSS = 0V at Topr = ­40 to 85°C, f(BCLK) = 20MHz unless otherwise specified. 2. This indicates the memory in which the program to be executed exists. 3. With one timer operated using fC32. Rev.2.10 Jun 24, 2005 REJ03B0003-0210 REJ03B0003-0210 page 33 of 50 Under development This document is under development and its contents are subject to change. M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) 5. Electric Characteristics Table 5.6 A/D Conversion Characteristics Symbol Parameter ­ Resolution INL Integral 10 bits Measuring Condition Min. VREF = VCC VREF ANEX0, ANEX1 input, AN0 to AN7 input, Standard Typ. Max. 10 Error 8 bits Unit Bit ±3 LSB ±2 VREF = AVCC = VCC = 5V VREF ANEX0, ANEX1 input, AN0 to AN7 input, LSB ±7 = VCC AN0_0 to AN0_7 input, AN2_0 to AN2_7 input = 5V External operation amp connection mode Nonlinearity ­ (1) LSB 10 bits Accuracy ±3 LSB = VCC AN0_0 to AN0_7 input, AN2_0 to AN2_7 input = 5V External operation amp connection mode Absolute ±7 LSB VREF = AVCC = VCC = 5V ±2 LSB DNL Differential Nonlinearity Error ±1 LSB ­ Offset Error ±3 LSB ­ Gain Error ±3 LSB RLADDER Resistor Ladder VREF = VCC 10 40 k tCONV 10-bit Conversion Time, VREF = VCC = 5V, AD = 10MHz 3.3 µs VREF = VCC = 5V, AD = 10MHz 2.8 µs µs 8 bits Sample & Hold function Available 8-bit Conversion time, Sample & Hold function Available tSAMP Sampling Time 0.3 VREF Reference Voltage 2.0 VCC V 0 VREF V VIA NOTES: Analog Input Voltage 1. Referenced to VCC = AVCC = VREF = 4.2 to 5.5V, VSS = AVSS = 0V, ­40 to 85°C unless otherwise specified. 2. AD frequency must be 10MHz or less. 3. When sample & hold function is disabled, AD frequency must be 250kHz or more in addition to a limit of NOTE 2. When sample & hold function is enabled, AD frequency must be 1MHz or more in addition to a limit of NOTE 2. Table 5.7 D/A conversion Characteristics Symbol (1) Parameter ­ Setup Time RO Output Resistance IVREF Reference Power Supply Input Current Standard Typ. Max. 8 Absolute Accuracy tsu Min. Resolution ­ Measuring condition Unit Bits 1.0 4 (NOTE 2) 10 % 3 µs 20 k 1.5 mA NOTES: 1. Referenced to VCC = AVCC = VREF = 4.2 to 5.5V, VSS = AVSS = 0V, ­40 to 85°C unless otherwise specified. 2. This applies when using one D/A converter, with the DAi register (i = 0, 1) for the unused D/A converter set to "00h". The resistor ladder of the A/D converter is not included. Also, the current IVREF always flows even though VREF may have been set to be unconnected by the ADCON1 register. Rev.2.10 Jun 24, 2005 REJ03B0003-0210 REJ03B0003-0210 page 34 of 50 Under development This document is under development and its contents are subject to change. M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) 5. Electric Characteristics Table 5.8 Power Supply Circuit Timing Characteristics Symbol Measuring Condition Parameter Min. Standard Typ. Max. 2 Unit td(P-R) Time for Internal Power Supply Stabilization During Powering-On VCC = 4.2 to 5.5V td(R-S) STOP Release Time 150 µs td(W-S) Low Power Dissipation Mode Wait Mode Release Time 150 µs td(P-R) Time for Internal Power Supply Stabilization During Powering-On VCC td(P-R) CPU clock td(R-S) STOP Release Time Interrupt for (a) Stop mode release or (b) Wait mode release td(W-S) Low Power Dissipation Mode Wait Mode Release Time CPU clock (a) (b) Figure 5.2 Power Supply Circuit Timing Diagram Rev.2.10 Jun 24, 2005 REJ03B0003-0210 REJ03B0003-0210 page 35 of 50 td(R-S) td(W-S) ms Under development This document is under development and its contents are subject to change. M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) 5. Electric Characteristics Timing Requirements (Referenced to VCC = 5V, VSS = 0V, at Topr = ­40 to 85°C unless otherwise specified) Table 5.9 External Clock Input (XIN Input) Symbol Parameter tC External Clock Input Cycle Time tw(H) External Clock Input HIGH Pulse Width tw(L) External Clock Input LOW Pulse Width tr External Clock Rise Time tf Standard Min. Max. 62.5 25 External Clock Fall Time 25 15 15 Unit ns ns ns ns ns Table 5.10 Memory Expansion Mode and Microprocessor Mode Symbol Parameter tac1(RD-DB) Data input access time (for setting with no wait) tac2(RD-DB) tac3(RD-DB) Data input access time (for setting with wait) tsu(DB-RD) tsu(RDY-BCLK) Data input setup time Standard Unit Min. Max. (NOTE 1) ns (NOTE 2) ns (NOTE 3) Data input access time (when accessing multiplexed bus area) 40 30 _ RDY input setup time _ tsu(HOLD-BCLK) HOLD input setup time th(RD-DB) Data input hold time _ th(BCLK-RDY) RDY input hold time _ th(BCLK-HOLD) HOLD input hold time 40 0 0 0 ns ns ns ns ns ns ns NOTES: 1. Calculated according to the BCLK frequency as follows: 0.5 10 ­ 45 [ns] f(BCLK) 9 2. Calculated according to the BCLK frequency as follows: (n ­0.5) 10 f(BCLK) 9 ­ 45 [ns] n is "2" for 1-wait setting, "3" for 2-wait setting and "4" for 3-wait setting. 3. Calculated according to the BCLK frequency as follows: (n ­0.5) 109 ­ 45 [ns] f(BCLK) Rev.2.10 Jun 24, 2005 REJ03B0003-0210 REJ03B0003-0210 page 36 of 50 n is "2" for 2-wait setting, "3" for 3-wait setting. Under development This document is under development and its contents are subject to change. M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) 5. Electric Characteristics Timing Requirements (Referenced to VCC = 5V, VSS = 0V, at Topr = ­40 to 85°C unless otherwise specified) Table 5.11 Timer A Input (Counter Input in Event Counter Mode) Parameter Symbol tc(TA) TAiIN Input Cycle Time tw(TAH) TAiIN Input HIGH Pulse Width tw(TAL) TAiIN Input LOW Pulse Width Standard Min. Max. 100 40 40 Unit ns ns ns Table 5.12 Timer A Input (Gating Input in Timer Mode) Parameter Symbol tc(TA) TAiIN Input Cycle Time tw(TAH) TAiIN Input HIGH Pulse Width tw(TAL) TAiIN Input LOW Pulse Width Standard Min. Max. 400 200 200 Unit ns ns ns Table 5.13 Timer A Input (External Trigger Input in One-shot Timer Mode) Symbol Parameter tc(TA) TAiIN Input Cycle Time tw(TAH) TAiIN Input HIGH Pulse Width tw(TAL) TAiIN Input LOW Pulse Width Standard Min. Max. 200 100 100 Unit ns ns ns Table 5.14 Timer A Input (External Trigger Input in Pulse Width Modulation Mode) tw(TAH) TAiIN Input HIGH Pulse Width Standard Min. Max. 100 tw(TAL) TAiIN Input LOW Pulse Width 100 Symbol Parameter Unit ns ns Table 5.15 Timer A Input (Counter Increment/decrement Input in Event Counter Mode) Symbol Parameter Standard Min. Max. 2000 1000 tc(UP) TAiOUT Input Cycle Time tw(UPH) TAiOUT Input HIGH Pulse Width tw(UPL) TAiOUT Input LOW Pulse Width tsu(UP-TIN) TAiOUT Input Setup Time 1000 400 th(TIN-UP) TAiOUT Input Hold Time 400 Unit ns ns ns ns ns Table 5.16 Timer A Input (Two-phase Pulse Input in Event Counter Mode) Symbol Parameter tc(TA) TAiIN Input Cycle Time tsu(TAIN-TAOUT) TAiOUT Input Setup Time tsu(TAOUT-TAIN) TAiIN Input Setup Time Rev.2.10 Jun 24, 2005 REJ03B0003-0210 REJ03B0003-0210 page 37 of 50 Standard Max. Min. 800 200 200 Unit ns ns ns Under development This document is under development and its contents are subject to change. M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) 5. Electric Characteristics Timing Requirements (Referenced to VCC = 5V, VSS = 0V, at Topr = ­40 to 85°C unless otherwise specified) Table 5.17 Timer B Input (Counter Input in Event Counter Mode) Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Parameter TBiIN Input Cycle Time (counted on one edge) TBiIN Input HIGH Pulse Width (counted on one edge) TBiIN Input LOW Pulse Width (counted on one edge) Standard Min. Max. 100 40 40 TBiIN Input HIGH Pulse Width (counted on both edges) TBiIN Input LOW Pulse Width (counted on both edges) ns ns ns ns 200 80 80 TBiIN Input Cycle Time (counted on both edges) Unit ns ns Table 5.18 Timer B Input (Pulse Period Measurement Mode) TBiIN Input HIGH Pulse Width Standard Min. Max. 400 200 TBiIN Input LOW Pulse Width 200 Symbol tc(TB) tw(TBH) tw(TBL) Parameter TBiIN Input Cycle Time Unit ns ns ns Table 5.19 Timer B Input (Pulse Width Measurement Mode) Symbol tc(TB) tw(TBH) tw(TBL) Parameter TBiIN Input Cycle Time TBiIN Input HIGH Pulse Width Standard Min. Max. 400 200 200 TBiIN Input LOW Pulse Width Unit ns ns ns Table 5.20 A/D Trigger Input Symbol tC(AD) tw(ADL) Parameter _ ADTRG Input Cycle Time (trigger able minimum) Standard Min. Max. 1000 _ ADTRG Input LOW Pulse Width 125 Unit ns ns Table 5.21 Serial I/O CLKi Input HIGH Pulse Width Standard Min. Max. 200 100 CLKi Input LOW Pulse Width 100 Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) Parameter CLKi Input Cycle Time 80 TXDi Output Delay Time RXDi Input Setup Time 0 70 RXDi Input Hold Time 90 TXDi Hold Time Unit ns ns ns ns ns ns ns _ Table 5.22 External Interrupt INTi Input Symbol tw(INH) tw(INL) Parameter _ INTi Input HIGH Pulse Width _ INTi Input LOW Pulse Width Rev.2.10 Jun 24, 2005 REJ03B0003-0210 REJ03B0003-0210 page 38 of 50 Standard Min. Max. 250 250 Unit ns ns Under development This document is under development and its contents are subject to change. M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) 5. Electric Characteristics Switching Characteristics (Referenced to VCC = 5 V, VSS = 0 V, at Topr = ­40 to 85 °C unless otherwise specified) Table 5.23 Memory Expansion Mode and Microprocessor Mode (for setting with no wait) Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) Standard Min. Max. 25 Measuring condition Parameter Address output delay time Figure 5.3 Address output hold time (refers to BCLK) ns ns ns 4 Address output hold time (refers to RD) 0 Address output hold time (refers to WR) (NOTE 1) 25 ns ns 25 Chip select output hold time (refers to BCLK) ns ns 15 Chip select output delay time ns ns 4 ALE signal output delay time ALE signal output hold time ­4 RD signal output delay time RD signal output hold time ns 0 WR signal output delay time 25 WR signal output hold time Data output hold time (refers to BCLK) 40 (3) ns ns 0 Data output delay time (refers to BCLK) ns 4 ns (NOTE 1) (3) ns (NOTE 2) Data output delay time (refers to WR) Data output hold time (refers to WR) Unit ns _ td(BCLK-HLDA) HLDA output delay time 40 ns NOTES: 1. Calculated according to the BCLK frequency as follows: 0.5 10 ­ 10 [ns] f(BCLK) 9 2. Calculated according to the BCLK frequency as follows: 0.5 10 ­ 40 [ns] f(BCLK) 9 f(BCLK) is 12.5 MHz or less. 3. This standard value shows the timing when the output is off, and does not show hold time of data bus. Hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = ­ CR ln (1 ­ VOL / VCC) by a circuit of the right figure. For example, when VOL = 0.2 VCC, C = 30 pF, R =1 k, hold time of output "L" level is t = ­ 30 pF 1 k ln (1 ­ 0.2 VCC / VCC) = 6.7 ns. R DBi C P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 30pF Figure 5.3 Port P0 to P10 Measurement Circuit Rev.2.10 Jun 24, 2005 REJ03B0003-0210 REJ03B0003-0210 page 39 of 50 Under development This document is under development and its contents are subject to change. M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) 5. Electric Characteristics Switching Characteristics (Referenced to VCC = 5 V, VSS = 0 V, at Topr = ­40 to 85 °C unless otherwise specified) Table 5.24 Memory Expansion Mode and Microprocessor Mode (for 1- to 3-wait setting and external area access) Symbol Measuring condition Parameter td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) Address output delay time Figure 5.3 Address output hold time (refers to BCLK) Standard Min. Max. 25 Unit ns ns ns 4 Address output hold time (refers to RD) 0 Address output hold time (refers to WR) (NOTE 1) 25 15 ns ns 25 ns ns 40 Chip select output hold time (refers to BCLK) ns ns 25 Chip select output delay time ns ns ns ns 4 ALE signal output delay time ALE signal output hold time ­4 RD signal output delay time RD signal output hold time 0 WR signal output delay time WR signal output hold time 0 Data output delay time (refers to BCLK) Data output hold time (refers to BCLK) (3) Data output delay time (refers to WR) Data output hold time (refers to WR) ns ns 4 (NOTE 2) (3) ns (NOTE 1) _ td(BCLK-HLDA) HLDA output delay time 40 ns NOTES: 1. Calculated according to the BCLK frequency as follows: 0.5 10 ­ 10 [ns] f(BCLK) 9 2. Calculated according to the BCLK frequency as follows: (n ­ 0.5) 10 ­ 40 [ns] f(BCLK) 9 n is "1" for 1-wait setting, "2" for 2-wait setting and "3" for 3-wait setting. When n = 1, f(BCLK) is 12.5 MHz or less. 3. This standard value shows the timing when the output is off, and does not show hold time of data bus. Hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = ­ CR ln (1 ­ VOL / VCC) by a circuit of the right figure. For example, when VOL = 0.2 VCC, C = 30 pF, R =1 k, hold time of output "L" level is t = ­ 30 pF 1 k ln (1 ­ 0.2 VCC / VCC) = 6.7 ns. Rev.2.10 Jun 24, 2005 REJ03B0003-0210 REJ03B0003-0210 page 40 of 50 R DBi C Under development This document is under development and its contents are subject to change. M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) 5. Electric Characteristics Switching Characteristics (Referenced to VCC = 5 V, VSS = 0 V, at Topr = ­40 to 85 °C unless otherwise specified) Table 5.25 Memory Expansion Mode and Microprocessor Mode (for 2- to 3-wait setting, external area access and multiplexed bus selection) Symbol Parameter td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) th(RD-CS) th(WR-CS) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) Address output delay time Measuring condition Figure 5.3 Standard Min. Max. 25 Address output hold time (refers to BCLK) (NOTE 1) Address output hold time (refers to WR) (NOTE 1) Chip select output delay time 25 Chip select output hold time (refers to BCLK) (NOTE 1) Chip select output hold time (refers to WR) (NOTE 1) RD signal output delay time ns 25 RD signal output hold time 25 WR signal output hold time ns ns 0 Data output delay time (refers to BCLK) ns ns 0 WR signal output delay time ns ns ns ns 4 Chip select output hold time (refers to RD) ns ns ns 4 Address output hold time (refers to RD) Unit 40 ns Data output hold time (refers to BCLK) 4 ns Data output delay time (refers to WR) (NOTE 2) ns Data output hold time (refers to WR) (NOTE 1) ns _ 40 td(BCLK-HLDA) td(BCLK-ALE) th(BCLK-ALE) td(AD-ALE) th(ALE-AD) td(AD-RD) td(AD-WR) tdZ(RD-AD) ALE signal output delay time (refers to BCLK) ns 15 HLDA output delay time ns ­4 ns ALE signal output delay time (refers to Address) (NOTE 3) ns ALE signal output hold time (refers to Address) (NOTE 4) ns RD signal output delay from the end of Address 0 ns WR signal output delay from the end of Address 0 ALE signal output hold time (refers to BCLK) Address output floating start time NOTES: 1. Calculated according to the BCLK frequency as follows: 0.5 109 ­ 10 [ns] f(BCLK) 2. Calculated according to the BCLK frequency as follows: (n ­0.5) 10 f(BCLK) 9 ­ 40 [ns] n is "2" for 2-wait setting, "3" for 3-wait setting. 3. Calculated according to the BCLK frequency as follows: 0.5 10 ­ 25 [ns] f(BCLK) 9 4. Calculated according to the BCLK frequency as follows: 0.5 109 ­ 15 [ns] f(BCLK) Rev.2.10 Jun 24, 2005 REJ03B0003-0210 REJ03B0003-0210 page 41 of 50 ns 8 ns Under development This document is under development and its contents are subject to change. M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) 5. Electric Characteristics XIN input tr tr tw(H) tw(L) tc tc(TA) tw(TAH) TAiIN input tw(TAL) tc(UP) tw(UPH) TAiOUT input tw(UPL) TAiOUT input (Up/down input) During event counter mode TAiIN input (When count on falling edge is selected) th(TIN-UP) tsu(UP-TIN) TAiIN input (When count on rising edge is selected) Two-phase pulse input in event counter mode tC(TA) TAiIN input tsu(TAIN-TAOUT) tsu(TAIN-TAOUT) tsu(TAOUT-TAIN) TAiOUT input tsu(TAOUT-TAIN) tc(TB) tw(TBH) TBiIN input tw(TBL) tc(AD) tw(ADL) ADTRG input tc(CK) tw(CKH) CLKi tw(CKL) th(C-Q) TXDi td(C-Q) tsu(D-C) RXDi tw(INL) INTi input tw(INH) Figure 5.4 Timing Diagram (1) Rev.2.10 Jun 24, 2005 REJ03B0003-0210 REJ03B0003-0210 page 42 of 50 th(C-D) Under development This document is under development and its contents are subject to change. M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) 5. Electric Characteristics Memory Expansion Mode and Microprocessor Mode (Effective for setting with wait) BCLK RD (Separate bus) WR, WRL, WRH (Separate bus) RD (Multiplexed bus) WR, WRL, WRH (Multiplexed bus) RDY input tsu(RDY-BCLK) th(BCLK-RDY) (Common to setting with wait and setting without wait) BCLK tsu(HOLD-BCLK) th(BCLK-HOLD) HOLD input HLDA output td(BCLK-HLDA) td(BCLK-HLDA) Hi-Z P0, P1, P2, P3, P4, P5_0 to P5_2 (1) NOTE: 1. The above pins are set to high-impedance regardless of the input level of the BYTE pin, the PM06 bit in the PM0 register and the PM11 bit in the PM1 register. Measuring conditions : VCC = 5 V Input timing voltage : Determined with VIL = 1.0 V, VIH = 4.0 V Output timing voltage: Determined with VOL = 2.5 V, VOH = 2.5 V Figure 5.5 Timing Diagram (2) Rev.2.10 Jun 24, 2005 REJ03B0003-0210 REJ03B0003-0210 page 43 of 50 Under development This document is under development and its contents are subject to change. M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) 5. Electric Characteristics Memory Expansion Mode and Microprocessor Mode (For setting with no wait) Read timing BCLK td(BCLK-CS) th(BCLK-CS) 25ns.max 4ns.min CSi tcyc td(BCLK-AD) th(BCLK-AD) 25ns.max 4ns.min ADi BHE td(BCLK-ALE) th(BCLK-ALE) -4ns.min 25ns.max th(RD-AD) 0ns.min ALE td(BCLK-RD) 25ns.max th(BCLK-RD) 0ns.min RD tac1(RD-DB) (0.5 tcyc-45)ns.max Hi-Z DBi tSU(DB-RD) 40ns.min th(RD-DB) 0ns.min Write timing BCLK td(BCLK-CS) th(BCLK-CS) 25ns.max 4ns.min CSi tcyc td(BCLK-AD) th(BCLK-AD) 25ns.max 4ns.min ADi BHE td(BCLK-ALE) th(BCLK-ALE) 25ns.max th(WR-AD) (0.5 tcyc-10)ns.min -4ns.min ALE td(BCLK-WR) 25ns.max th(BCLK-WR) 0ns.min WR,WRL, WRH td(BCLK-DB) th(BCLK-DB) 4ns.min 40ns.max Hi-Z DBi td(DB-WR) Measuring conditions : VCC = 5 V Input timing voltage : VIL = 0.8 V, VIH = 2.0 V Output timing voltage : VOL = 0.4 V, VOH = 2.4 V Figure 5.6 Timing Diagram (3) Rev.2.10 Jun 24, 2005 REJ03B0003-0210 REJ03B0003-0210 th(WR-DB) (0.5 tcyc-40)ns.min (0.5 tcyc-10)ns.min 1 tcyc = f(BCLK) page 44 of 50 Under development This document is under development and its contents are subject to change. M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) 5. Electric Characteristics Memory Expansion Mode and Microprocessor Mode (For 1-wait setting and external area access) Read timing BCLK td(BCLK-CS) th(BCLK-CS) 25ns.max 4ns.min CSi tcyc td(BCLK-AD) th(BCLK-AD) 25ns.max 4ns.min ADi BHE td(BCLK-ALE) th(RD-AD) th(BCLK-ALE) 0ns.min -4ns.min 25ns.max ALE td(BCLK-RD) th(BCLK-RD) 0ns.min 25ns.max RD tac2(RD-DB) (1.5 tcyc-45)ns.max DBi Hi-Z th(RD-DB) tSU(DB-RD) 0ns.min 40ns.min Write timing BCLK td(BCLK-CS) th(BCLK-CS) 25ns.max 4ns.min CSi tcyc td(BCLK-AD) th(BCLK-AD) 25ns.max 4ns.min ADi BHE td(BCLK-ALE) th(BCLK-ALE) th(WR-AD) (0.5 tcyc-10)ns.min -4ns.min 25ns.max ALE td(BCLK-WR) 25ns.max th(BCLK-WR) 0ns.min WR,WRL, WRH td(BCLK-DB) th(BCLK-DB) 4ns.min 40ns.max Hi-Z DBi td(DB-WR) (0.5 tcyc-40)ns.min 1 tcyc = f(BCLK) Measuring conditions : VCC = 5 V Input timing voltage : VIL = 0.8 V, VIH = 2.0 V Output timing voltage : VOL = 0.4 V, VOH = 2.4 V Figure 5.7 Timing Diagram (4) Rev.2.10 Jun 24, 2005 REJ03B0003-0210 REJ03B0003-0210 page 45 of 50 th(WR-DB) (0.5 tcyc-10)ns.min Under development This document is under development and its contents are subject to change. M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) 5. Electric Characteristics Memory Expansion Mode and Microprocessor Mode (For 2-wait setting and external area access) Read timing tcyc BCLK th(BCLK-CS) 4ns.min td(BCLK-CS) 25ns.max CSi th(BCLK-AD) 4ns.min td(BCLK-AD) 25ns.max ADi BHE td(BCLK-ALE) 25ns.max th(RD-AD) th(BCLK-ALE) -4ns.min 0ns.min ALE th(BCLK-RD) 0ns.min td(BCLK-RD) 25ns.max RD tac2(RD-DB) (2.5 tcyc-45)ns.max DBi Hi-Z tSU(DB-RD) 40ns.min th(RD-DB) 0ns.min Write timing tcyc BCLK td(BCLK-CS) 25ns.max th(BCLK-CS) td(BCLK-AD) 25ns.max th(BCLK-AD) 4ns.min CSi 4ns.min ADi BHE td(BCLK-ALE) 25ns.max th(WR-AD) (0.5 tcyc-10)ns.min th(BCLK-ALE) -4ns.min ALE td(BCLK-WR) 25ns.max th(BCLK-WR) 0ns.min WR, WRL WRH td(BCLK-DB) 40ns.max DBi Hi-Z td(DB-WR) (1.5 tcyc-40)ns.min tcyc = th(BCLK-DB) 4ns.min 1 f(BCLK) Measuring conditions : VCC = 5 V Input timing voltage : VIL = 0.8 V, VIH = 2.0 V Output timing voltage : VOL = 0.4 V, VOH = 2.4 V Figure 5.8 Timing Diagram (5) Rev.2.10 Jun 24, 2005 REJ03B0003-0210 REJ03B0003-0210 page 46 of 50 th(WR-DB) (0.5 tcyc-10)ns.min Under development This document is under development and its contents are subject to change. M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) 5. Electric Characteristics Memory Expansion Mode and Microprocessor Mode (For 3-wait setting and external area access) Read timing tcyc BCLK th(BCLK-CS) 4ns.min td(BCLK-CS) 25ns.max CSi th(BCLK-AD) td(BCLK-AD) 25ns.max 4ns.min ADi BHE td(BCLK-ALE) th(RD-AD) 0ns.min th(BCLK-ALE) 25ns.max -4ns.min ALE th(BCLK-RD) td(BCLK-RD) 25ns.max 0ns.min RD tac2(RD-DB) (3.5 tcyc-45)ns.max DBi Hi-Z tSU(DB-RD) th(RD-DB) 40ns.min 0ns.min Write timing tcyc BCLK td(BCLK-CS) 25ns.max th(BCLK-CS) 4ns.min td(BCLK-AD) th(BCLK-AD) 4ns.min CSi 25ns.max ADi BHE td(BCLK-ALE) 25ns.max th(WR-AD) (0.5 tcyc-10)ns.min th(BCLK-ALE) -4ns.min ALE td(BCLK-WR) 25ns.max th(BCLK-WR) 0ns.min WR, WRL WRH td(BCLK-DB) DBi th(BCLK-DB) 40ns.max 4ns.min Hi-Z td(DB-WR) (2.5 tcyc-40)ns.min 1 tcyc = f(BCLK) Measuring conditions : VCC = 5 V Input timing voltage : VIL = 0.8 V, VIH = 2.0 V Output timing voltage : VOL = 0.4 V, VOH = 2.4 V Figure 5.9 Timing Diagram (6) Rev.2.10 Jun 24, 2005 REJ03B0003-0210 REJ03B0003-0210 page 47 of 50 th(WR-DB) (0.5 tcyc-10)ns.min Under development This document is under development and its contents are subject to change. M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) 5. Electric Characteristics Memory Expansion Mode and Microprocessor Mode (For 1- or 2-wait setting, external area access and multiplexed bus selection) Read timing BCLK td(BCLK-CS) th(RD-CS) (0.5 tcyc-10)ns.min tcyc 25ns.max th(BCLK-CS) 4ns.min CSi td(AD-ALE) (0.5 tcyc-25)ns.min ADi /DBi th(ALE-AD) (0.5 tcyc-15)ns.min Address 8ns.max Address Data input tdZ(RD-AD) tac3(RD-DB) (1.5 tcyc-45)ns.max tSU(DB-RD) th(RD-DB) 0ns.min 40ns.min td(AD-RD) 0ns.min td(BCLK-AD) th(BCLK-AD) 4ns.min 25ns.max ADi BHE td(BCLK-ALE) th(BCLK-ALE) 25ns.max th(RD-AD) (0.5 tcyc-10)ns.min -4ns.min ALE td(BCLK-RD) th(BCLK-RD) 0ns.min 25ns.max RD Write timing BCLK td(BCLK-CS) th(BCLK-CS) th(WR-CS) (0.5 tcyc-10)ns.min tcyc 25ns.max 4ns.min CSi th(BCLK-DB) td(BCLK-DB) 4ns.min 40ns.max ADi /DBi Address Data output td(DB-WR) td(AD-ALE) (1.5 tcyc-40)ns.min (0.5 tcyc-25)ns.min Address th(WR-DB) (0.5 tcyc-10)ns.min td(BCLK-AD) th(BCLK-AD) 25ns.max 4ns.min ADi BHE td(BCLK-ALE) 25ns.max th(BCLK-ALE) td(AD-WR) -4ns.min 0ns.min th(WR-AD) (0.5 tcyc-10)ns.min ALE td(BCLK-WR) 25ns.max WR,WRL, WRH tcyc = 1 f(BCLK) Measuring conditions : VCC = 5 V Input timing voltage : VIL = 0.8 V, VIH = 2.0 V Output timing voltage : VOL = 0.4 V, VOH = 2.4 V Figure 5.10 Timing Diagram (7) Rev.2.10 Jun 24, 2005 REJ03B0003-0210 REJ03B0003-0210 page 48 of 50 th(BCLK-WR) 0ns.min Under development This document is under development and its contents are subject to change. M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) 5. Electric Characteristics Memory Expansion Mode and Microprocessor Mode (For 3-wait setting, external area access and multiplexed bus selection) Read timing tcyc BCLK th(RD-CS) (0.5 tcyc-10)ns.min td(BCLK-CS) th(BCLK-CS) 4ns.min 25ns.max CSi td(AD-ALE) (0.5 tcyc-25)ns.min ADi /DBi th(ALE-AD) (0.5 tcyc-15)ns.min Address td(BCLK-AD) td(AD-RD) 25ns.max ADi BHE Data input tdZ(RD-AD) 8ns.max th(RD-DB) tac3(RD-DB) (2.5 tcyc-45)ns.max 0ns.min tSU(DB-RD) 0ns.min th(BCLK-AD) 40ns.min 4ns.min (no multiplex) td(BCLK-ALE) 25ns.max th(RD-AD) th(BCLK-ALE) (0.5 tcyc-10)ns.min -4ns.min ALE th(BCLK-RD) td(BCLK-RD) 0ns.min 25ns.max RD Write timing tcyc BCLK th(WR-CS) (0.5 tcyc-10)ns.min td(BCLK-CS) 25ns.max th(BCLK-CS) 4ns.min CSi th(BCLK-DB) td(BCLK-DB) 40ns.max ADi /DBi Address 4ns.min Data output td(AD-ALE) td(DB-WR) (0.5 tcyc-25)ns.min (2.5 tcyc-40)ns.min th(WR-DB) (0.5 tcyc-10)ns.min td(BCLK-AD) th(BCLK-AD) 25ns.max 4ns.min ADi BHE (no multiplex) td(BCLK-ALE) 25ns.max th(BCLK-ALE) th(WR-AD) -4ns.min td(AD-WR) ALE td(BCLK-WR) 25ns.max WR, WRL WRH tcyc = (0.5 tcyc-10)ns.min 0ns.min 1 f(BCLK) Measuring conditions : VCC = 5 V Input timing voltage : VIL = 0.8 V, VIH = 2.0 V Output timing voltage : VOL = 0.4 V, VOH = 2.4 V Figure 5.11 Timing Diagram (8) Rev.2.10 Jun 24, 2005 REJ03B0003-0210 REJ03B0003-0210 page 49 of 50 th(BCLK-WR) 0ns.min Under development This document is under development and its contents are subject to change. M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) Appendix 1. Package Dimensions Appendix 1. Package Dimensions JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-QFP100-14x20-0.65 PRQP0100JB-A PRQP0100JB-A 100P6S-A 100P6S-A 1.6g HD *1 D 80 51 81 50 E *2 HE NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. ZE Reference Symbol Dimension in Millimeters Max 19.8 20.0 20.2 E 31 Nom D 100 Min 13.8 14.0 14.2 2.8 A2 c A2 F 22.5 22.8 23.1 HE 16.5 16.8 17.1 0 0.1 0.2 bp 30 Index mark ZD HD A1 1 0.25 0.3 0.4 c 0.13 0.15 A1 A A L *3 e y 3.05 0° bp Detail F e 0.5 0.65 y 0.575 ZD JEITA Package Code RENESAS Code P-LQFP100-14x14-0.50 PLQP0100KB-A PLQP0100KB-A Previous Code 100P6Q-A 100P6Q-A / FP-100U FP-100U / FP-100UV FP-100UV 0.8 0.10 ZE L 0.2 10° 0.825 0.4 0.6 0.8 MASS[Typ.] 0.6g HD *1 D 51 75 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 50 76 bp c1 Reference Symbol c E *2 HE b1 Dimension in Millimeters Nom Max D 13.9 14.0 14.1 E Terminal cross section Min 13.9 14.0 14.1 A2 1.4 15.8 16.0 16.2 HE 15.8 16.0 16.2 A1 0.05 0.1 0.15 bp 26 ZE HD 100 0.15 0.20 0.25 A 1 25 Index mark ZD F 1.7 0.18 b1 0.09 e *3 bp A1 e y L x L1 Detail F page 50 of 50 8° 0.08 y 0.08 1.0 ZD 1.0 ZE L1 0.20 0.5 x L Rev.2.10 Jun 24, 2005 REJ03B0003-0210 REJ03B0003-0210 0.145 0.125 0° c A2 A c c1 0.35 0.5 1.0 0.65 REVISION HISTORY Rev. Date M16C/6N M16C/6N Group (M16C/6N4 M16C/6N4) Data Sheet Description Page Summary 1.00 Jun. 30, 2003 ­ First edition issued 2.00 Nov. 10, 2004 ­ Revised edition issued * Words standardizes (on-chip oscillator) * 100P6Q-A 100P6Q-A (100-pin vers