W83877ATF W83877F RECS-80 IRQ15 360K/720K/1 44M/2 W83877ATD RIB/A15 DCDB/A14 - Datasheet Archive

 

Preliminary GENERAL DESCRIPTION The W83877ATF is an enhanced version from Winbond`s most popular I/O chip W83877F - which

 

W83877ATF W83877ATF Preliminary GENERAL DESCRIPTION The W83877ATF W83877ATF is an enhanced version from Winbond`s most popular I/O chip W83877F W83877F - which integrates the disk drive adapter, serial port (UART), IrDA 1.0 SIR, parallel port, configurable plugand-play registers for the whole chip - plus additional powerful features: IrDA 1.1 (MIR for 1.152M bps or FIR for 4M bps), TV remote IR, ACPI, full 16-bit address decoding, and serial IRQ. In addition to the function enhancement, W83877ATF W83877ATF is pin-to-pin compatible to W83877F W83877F. The disk drive adapter functions of W83877ATF W83877ATF include a floppy disk drive controller compatible with the industry standard 82077/ 765, data separator, write pre-compensation circuit, decode logic, data rate selection, clock generator, drive interface control logic, and interrupt and DMA logic. The wide range of functions integrated onto the W83877ATF W83877ATF greatly reduces the number of components required for interfacing with floppy disk drives. The W83877ATF W83877ATF supports four 360K, 720K, 1.2M, 1.44M, or 2.88M disk drives and data transfer rates of 250 Kb/s, 300 Kb/s, 500 Kb/s,1 Mb/s, and 2 Mb/s. The W83877ATF W83877ATF provides two high-speed serial communication ports (UARTs), one of which supports serial Infrared communication. Each UART includes a 16-byte send/receive FIFO, a programmable baud rate generator, complete modem control capability, and a processor interrupt system. One of the UARTs supports infrared (IR) includes 32-byte FIFO, serial IR, 1.152M bps MIR, 0.576M bps, 4M bps FIR, and TV remote IR (supporting NEC, RC-5, extended RC-5, and RECS-80 RECS-80 protocols). Both UARTs provide legacy speed with baud rate 115.2k and provide advanced speed with baud rate 230k, 460k, and 921k bps which support higher speed Modems. The W83877ATF W83877ATF supports one PC-compatible printer port (SPP), Bi-directional Printer port (BPP) and also Enhanced Parallel Port (EPP) and Extended Capabilities Port (ECP). Through the printer port interface pins, also available are: Extension FDD Mode and Extension 2FDD Mode allowing one or two external floppy disk drives to be connected. Especially in the application of notebook computer, this feature is very useful. A new feature PNF (Printer-Not-Floppy) is provided for automatically detecting if attached device is printer or floppy drive. Winbond W83877ATF W83877ATF provides functions that complies with ACPI (Advanced Configuration and Power Interface), which includes support of legacy and ACPI power management through SMI or SCI function pins. One 24-bit power management timer is implemented with carry notify interrupt. W83877ATF W83877ATF also has auto power management to reduce power consumption. The Serial IRQ for PCI architecture is supported, ISA IRQs (IRQ1~IRQ15 IRQ15) can be cascaded into one IRQ pin. W83877ATF W83877ATF also features ISA bus IRQ sharing and allows two or more devices to share the same IRQ. W83877ATF W83877ATF is made to fully comply with Microsoft PC97 Hardware Design Guide. IRQs, DMAs, and I/O space resource are flexible to adjust to meet ISA PnP requirement. Full 16-bit address decoding without no extra external circuits is also provided. Moreover W83877ATF W83877ATF is made to meet the specification of PC97`s requirement in the power management: ACPI and DPM (Device Power Management). The configuration registers support mode selection, function enable/disable, and power down function selection. Furthermore, the configurable PnP features are compatible with the plug-and-play feature demand of Windows 95TM, which makes system resource allocation more efficient than ever. -1- Publication Release Date: January 1997 Revision 0.2 W83877ATF W83877ATF Preliminary FEATURES General: · Plug & Play 1.0A Compliant · Support 8 IRQs (ISA), or 15 IRQs (Serial IRQ), 4 DMA channels, and 480 re-locatable addresses · Capable of ISA Bus IRQ Sharing · Compliant with Microsoft PC97 Hardware Design Guide · Support DPM (Device Power Management), ACPI · Report ACPI status interrupt by nSCI signal from serial IRQ pin, or from IRQ A~H pins FDC: · Compatible with IBM PC AT disk drive systems · Variable write pre-compensation with track selectable capability · DMA enable logic · Support floppy disk drives and tape drives · Detects all overrun and underrun conditions · Built-in address mark detection circuit to simplify the read electronics · Single 24 MHz clock input · FDD anti-virus functions with software write protect and FDD write enable signal (write data signal was forced to be inactive) · Support up to four 3.5-inch or 5.25-inch floppy disk drives · Completely compatible with industry standard 82077 · 360K/720K/1 360K/720K/1.2M/1.44M/2 44M/2.88M format; 250K, 300K, 500K, 1M, 2M bps data transfer rate · Support vertical recording format · Support 3-mode FDD, and its Win95 driver · 16-byte data FIFOs UART: · Two high-speed 16550 compatible UARTs with 16-byte send/receive FIFOs · MIDI compatible · Fully programmable serial-interface characteristics: - 5, 6, 7 or 8-bit characters - Even, odd or no parity bit generation/detection - 1, 1.5 or 2 stop bits generation · Internal diagnostic capabilities: -2- Publication Release Date: November 1996 Revision 0.2 W83877ATF W83877ATF Preliminary - Loop-back controls for communications link fault isolation - Break, parity, overrun, framing error simulation · Programmable baud generator allows division of 1.8461 M Hz and 24 MHz by 1 to (216-1) · Maximum baud rate up to 921k bps for 14.768M Hz and 1.5M bps for 24M Hz Infrared: · Support IrDA version 1.0 SIR protocol with maximum baud rate up to 115.2K bps · Support SHARP ASK-IR protocol with maximum baud rate up to 57,600 bps · Support IrDA version 1.1 MIR (1.152M bps) and FIR (4M bps) protocol - Single DMA channel for transmitter or receiver - 32-byte FIFO is supported in both FIR TX/RX transmission - 8-byte status FIFO is supported to store received frame status (such as overrun, CRC error, etc.) · Support auto-config SIR and FIR Parallel Port: · Compatible with IBM parallel port · Support PS/2 compatible bi-directional parallel port · Support Enhanced Parallel Port (EPP)- Compatible with IEEE 1284 specification · Support Extended Capabilities Port (ECP) - Compatible with IEEE 1284 specification · B Extension FDD mode supports disk drive B; and Extension 2FDD mode supports disk drives A and through parallel port · Enhanced printer port back-drive current protection Others: · Programmable configuration settings · Immediate or automatic power-down mode for power management · All hardware power-on settings have internal pull-up or pull-down resistors as default value · Fully 16-bit address decode (UART B pin option) · PNF pin (Printer-Not-Floppy pin) for distinguishing printer port connection - FDD or Printer; unique for notebook application of external floppy through printer port Package: · 100-pin QFP (W83877ATF W83877ATF), and also 100-pin TQFP (W83877ATD W83877ATD) -3- Publication Release Date: November 1996 Revision 0.2 W83877ATF W83877ATF Preliminary PIN CONFIGURATION / D / S T / R K / M M A/ C A O O KWH 1 B A 0 P G 0 X X X X X / R D / / A G I I A V T D D D D D D D D N O O E A A A A A D A A A A A A 7 6 5 4 3 2 1 0 D W R N 9 8 7 6 5 D 4 3 2 1 0 X X X X X X X X X X X X X X X X 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 INDEX STEP DSA DSB WE WD RWC HEAD DIR GND X X X X X X X X X X IRQ_H IRQ_B IRQIN IRRX2 X IRTX2 IRQ_A TC DACK_B IRQ_F DRQ_B X X X X X X X X X 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 X X X X RIB/A15 RIB/A15 DCDB/A14 DCDB/A14 DSRB/A13 DSRB/A13 CTSB/A12 CTSB/A12 X DTRB X RTSB IRQ_C SOUTB SINB X X X X X X X X X X X X DACK_A GND DRQA SOUTA IRQ_D RTSA DTRA CTSA DSRA X DCDA X RIA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 X / I R Q X / C S , / G A 1 1 X X I R R X H D R Q | C X X X X X X X X X X X X X X I M C / P P P P P P V P P / O R L S D D D D D D D D D D K M 0 1 2 3 4 5 D 6 7 A C C H I I K N R | D C Y -4- X X X X X / S T B / A F D / I N I T / S L I N I R Q | E X X X X X X X B G / P S / S U N A E L E I S D C C R N T R A Y K Publication Release Date: November 1996 Revision 0.2 W83877ATF W83877ATF Preliminary 1.0 PIN DESCRIPTION Note: Refer to section 9.2 DC CHARACTERISTICS for details. I/O8tc - TTL level output pin with 8 mA source-sink capability; CMOS level input voltage I/O12t - TTL level bi-directional pin with 12 mA source-sink capability I/O12ts - TTL level bi-directional pin with 12 mA source-sink capability and Schmitt-triggered input I/O24t - TTL level bi-directional pin with 24 mA source-sink capability OUT8t - TTL level output pin with 8 mA source-sink capability OUT12t - TTL level output pin with 12 mA source-sink capability OD12 - Open-drain output pin with 12 mA sink capability OD24 - Open-drain output pin with 24 mA sink capability INt - TTL level input pin INts - TTL level Schmitt-triggered input pin INcs - CMOS level Schmitt-triggered input pin 1.1 Host Interface SYMBOL PIN I/O D0-D7 66-73 I/O24t A0-A10 A0-A10 51-55 INt FUNCTION System data bus bits 0-7 System address bus bits 0-10 57-61 75 IOCHRDY 5 OD24 MR 6 INts Master Reset. Active high. MR is low during normal operations. CS 2 INts Active low chip select signal. A11 In EPP Mode, this pin is the I/O Channel Ready output to extend the host read/write cycle. System address bus bit 11, when 16-bit address decoder is set in CRxx.bitx AEN 62 INt System address bus enable IOR 63 INts CPU I/O read signal IOW 64 INts CPU I/O write signal DACK_ A 41 INts DMA acknowledge signal A. DRQ_A 39 OUT12t DMA request signal A. DRQ_B 100 OUT12t DMA request signal B DACK_B 98 INts DMA acknowledge signal B -5- Publication Release Date: November 1996 Revision 0.2 W83877ATF W83877ATF Preliminary 1.1 Host Interface, continued SYMBOL PIN I/O DRQ_C 4 OUT12t DACK_ C 18 INts DMA acknowledge signal C IRQIN 93 INts Interrupt request input. DRQ_D OUT12t DMA request signal D. IRSL2 OUT12t IR module mode selection 2. IRRXH/IRSL0 I/O12ts When input, act as a function of high speed IR receiving terminal. When output selected, act as a IR module mode selection 0 PNF 3 Detect printer is active, and not external FDC. When PNF=1, the device is connected to parallel printer. When PNF=0, the device is connected to external FDC. The pin is configured in CRxx.bitx. I/O12ts IRSL1 When input pin, high speed IR received terminal. When as output pin, IR module mode select 0. Input or output are definied in high speed IR register. INts OUT12t TC 97 INts IRQ_ A 96 OUT12t GIO1 IRQ_ B DMA request signal C INts IRRXH/IRSL0 DACK_D FUNCTION I/O12t 92 GIO0 OUT12t I/O12t DMA acknowledge signal for channel D. IR module mode select 1. Terminal Count. When active, this pin indicates termination of a DMA transfer. When CR16 Bit 5 (GOIQSEL) = 0: Interrupt request signal A; When CR16 Bit 5 (GOIQSEL) = 1: General Purpose I/O port 1. When CR16 Bit 4 (GOIQSEL) = 0: Interrupt request signal B; When CR16 Bit 4 (GOIQSEL) = 1: General Purpose I/O port 0. IRQ_C 44 OUT12t Interrupt request signal C IRQ_D 37 OUT12t Interrupt request signal D IRQ_E 23 OUT12t Interrupt request signal E IRQ_F 99 OUT12t Interrupt request signal F IRQ_G 1 OUT12t Interrupt request signal G. DRQ_D OUT12t DMA request signal channel D. IRSL2 OUT12t IR module mode select 2. PCICLK INt PCI clock input when the serial IRQ function is selected. -6- Publication Release Date: November 1996 Revision 0.2 W83877ATF W83877ATF Preliminary 1.1 Host Interface, continued SYMBOL PIN I/O 91 OUT12t Interrupt request signal H. OUT12t IR module mode selection 2. DACK_D INts DMA acknowledge signal D. SERIRQ OUT12t IRQ_H IRSL2 CLKIN 7 INt SMI 8 OUT12t FUNCTION Serial Interrupt output, when the function of the serial IRQ is set in CRxx.bitx 24M Hz clock input For the power management, the SMI is and active low by the power management events, that generate an nSCI in ACPI mode. 1.2 Serial Port Interface SYMBOL PIN I/O CTSA 34 INt Clear To Send is the modem control input. CTSB 47 INt Clear To Send is the modem control input. A12 FUNCTION System address bus bit 12, when 16-bit address decoder is selected (CRxx.bitx). DSRA 33 INt Data Set Ready. An active low indicates the modem or data set is ready to establish a communication link and transfer data to the UART. DSRB 48 INt Data Set Ready. An active low indicates the modem or data set is ready to establish a communication link and transfer data to the UART. A13 System address bus bit 13, when 16-bit address decoder is selected. DCDA 32 INt Data Carrier Detect. An active low indicates the modem or data set has detected a data carrier. DCDB 49 INt Data Carrier Detect. An active low indicates the modem or data set has detected a data carrier. A14 RIA System address bus bit 14, when 16-bit address decoder is selected. 31 INt Ring Indicator. An active low indicates that a ring signal is being received by the modem or data set. -7- Publication Release Date: November 1996 Revision 0.2 W83877ATF W83877ATF Preliminary 1.2 Serial Port Interface, continued SYMBOL RIB PIN I/O FUNCTION 50 INt Ring Indicator. An active low indicates that a ring signal is being received by the modem or data set. A15 System address bus bit 15, when 16-bit address decoder is selected. SINA 30 INt Serial Input of COM A. Used to receive serial data from the communication link. SINB 42 INt Serial Input of COM B. Used to receive serial data from the communication link. IRRX1 SOUTA When infrared function is selected, act as infrared input. 38 I/O8tc PEN16SA PEN16SA SOUTB During power-on reset, this pin is pulled up internally and is defined as PEN16SA PEN16SA, which provides the power-on value for CRxx.bitx (PEN16SA PEN16SA). A 4.7 k is recommended when intends to pull down at power-on reset. 43 I/O12t IRTX1 DTRA UART A Serial Output. Used to transmit serial data out to the communication link. UART B Serial Output. Used to transmit serial data out to the communication link. Infrared serial data output when COM B acts as infrared port. 35 I/O8tc PHEFRAS UART A Data Terminal Ready. An active low informs the modem or data set that the controller is ready to communicate. During power-on reset, this pin is pulled down internally and is defined as PHEFRAS, which provides the power-on value for CR16 bit 0 (HEFRAS). A 4.7 k is recommended when intends to pull up at power-on reset. DTRB 46 I/O8t UART B Data Terminal Ready. An active low informs the modem or data set that controller is ready to communicate. RTSA 36 I/O8tc UART A Request To Send. An active low informs the modem or data set that the controller is ready to send data. PPNPCVS During power-on reset, this pin is pulled up internally and is defined as PPNPCVS, which provides the power-on value for CR16 bit 2 (PNPCVS). A 4.7 k is recommended when intends to pull down at power-on reset. -8- Publication Release Date: November 1996 Revision 0.2 W83877ATF W83877ATF Preliminary 1.2 Serial Port Interface, continued SYMBOL RTSB PIN I/O FUNCTION 45 I/O8tc UART B Request To Send. An active low informs the modem or data set that the controller is ready to send data. PGOIQSEL IRTX2 IRRX2 During power-on reset, this pin is pulled down internally and is defined as PGOIQSEL, which provides the power-on value for CR16 bit 4 (GOIQSEL). A 4.7 k is recommended when intends to pull up at power-on reset. 95 94 OUT12t INt Function as a InfraRed transmission data line. Function as a InfraRed receiving line. 1.3 Multi-Mode Parallel Port The following pins have eight functions, which are controlled by bits PRTMOD0, PRTMOD1, and PRTMOD2 of CR0 and CR9 (refer to section 8.0, Extended Functions). SYMBOL BUSY PIN I/O 24 INt FUNCTION PRINTER MODE: BUSY An active high input indicates that the printer is not ready to receive data. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. OD12 EXTENSION FDD MODE: MOB2 This pin is for Extension FDD B; the function of this pin is the same as that of the MOB pin. OD12 EXTENSION 2FDD MODE: MOB2 This pin is for Extension FDD A and B; the function of this pin is the same as that of the MOB pin. ACK 26 INt PRINTER MODE: ACK An active low input on this pin indicates that the printer has received data and is ready to accept more data. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. OD12 EXTENSION FDD MODE: DSB2 This pin is for the Extension FDD B; its functions are the same as those of the DSB pin. -9- Publication Release Date: November 1996 Revision 0.2 W83877ATF W83877ATF Preliminary 1.3 Multi-Mode Parallel Port, continued SYMBOL PIN I/O OD12 FUNCTION EXTENSION 2FDD MODE: DSB2 This pin is for Extension FDD A and B; this function of this pin is the same as that of the DSB pin. PE 27 INt PRINTER MODE: PE An active high input on this pin indicates that the printer has detected the end of the paper. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. OD12 EXTENSION FDD MODE: WD2 This pin is for Extension FDD B; its function is the same as that of the WD pin. OD12 EXTENSION 2FDD MODE: WD2 This pin is for Extension FDD A and B; this function of this pin is the same as that of the WD pin. SLCT 28 INt JOYSTICK MODE: NC pin. PRINTER MODE: SLCT An active high input on this pin indicates that the printer is selected. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. OD12 EXTENSION FDD MODE: WE2 This pin is for Extension FDD B; its functions are the same as those of the WE pin. OD12 EXTENSION 2FDD MODE: WE2 This pin is for Extension FDD A and B; this function of this pin is the same as that of the WE pin. ERR 29 INt PRINTER MODE: ERR An active low input on this pin indicates that the printer has encountered an error condition. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. OD12 EXTENSION FDD MODE: HEAD2 This pin is for Extension FDD B; its function is the same as that of the HEADpin. - 10 - Publication Release Date: November 1996 Revision 0.2 W83877ATF W83877ATF Preliminary 1.3 Multi-Mode Parallel Port, continued SYMBOL PIN I/O OD12 FUNCTION EXTENSION 2FDD MODE: HEAD2 This pin is for Extension FDD A and B; its function is the same as that of the HEAD pin. SLIN 22 OD12 PRINTER MODE: SLIN Output line for detection of printer selection. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. OD12 EXTENSION FDD MODE: STEP2 This pin is for Extension FDD B; its function is the same as that of the STEP pin. OD12 EXTENSION 2FDD MODE: STEP2 This pin is for Extension FDD A and B; its function is the same as that of the STEP pin . INIT 21 OD12 PRINTER MODE: INIT Output line for the printer initialization. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. OD12 EXTENSION FDD MODE: DIR2 This pin is for Extension FDD B; its function is the same as that of the DIR pin. OD12 EXTENSION 2FDD MODE: DIR2 This pin is for Extension FDD A and B; its function is the same as that of the DIR pin. AFD 20 OD12 PRINTER MODE: AFD An active low output from this pin causes the printer to auto feed a line after a line is printed. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. OD12 EXTENSION FDD MODE: RWC2 This pin is for Extension FDD B; its function is the same as that of the RWC pin. - 11 - Publication Release Date: November 1996 Revision 0.2 W83877ATF W83877ATF Preliminary 1.3 Multi-Mode Parallel Port, continued SYMBOL PIN I/O FUNCTION EXTENSION 2FDD MODE: RWC2 This pin is for Extension FDD A and B; its function is the same as that of the RWC pin. STB 19 OD12 PRINTER MODE: STB An active low output is used to latch the parallel data into the printer. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. - EXTENSION FDD MODE: This pin is a tri-state output. PD0 9 I/O24t EXTENSION 2FDD MODE: This pin is a tri-state output. PRINTER MODE: PD0 Parallel port data bus bit 0. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. INt EXTENSION FDD MODE: INDEX2 This pin is for Extension FDD B; the function of this pin is the same as that of the INDEX pin. This pin is pulled high internally. INt EXTENSION 2FDD MODE: INDEX2 This pin is for Extension FDD A and B; this function of this pin is the same as INDEX pin. This pin is pulled high internally. PD1 10 I/O24t PRINTER MODE: PD1 Parallel port data bus bit 1. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. INt EXTENSION FDD MODE: TRAK02 TRAK02 This pin is for Extension FDD B; the function of this pin is the same as that of the TRAK0 pin. This pin is pulled high internally. INt EXTENSION. 2FDD MODE: TRAK02 TRAK02 This pin is for Extension FDD A and B; this function of this pin is the same as TRAK0 pin. This pin is pulled high internally. - 12 - Publication Release Date: November 1996 Revision 0.2 W83877ATF W83877ATF Preliminary 1.3 Multi-Mode Parallel Port, continued SYMBOL PD2 PIN I/O 11 I/O24t FUNCTION PRINTER MODE: PD2 Parallel port data bus bit 2. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. INt EXTENSION FDD MODE: WP2 This pin is for Extension FDD B; the function of this pin is the same as that of the WP pin. This pin is pulled high internally. INt EXTENSION. 2FDD MODE: WP2 This pin is for Extension FDD A and B; this function of this pin is the same as that of the WP pin. This pin is pulled high internally. PD3 12 I/O24t PRINTER MODE: PD3 Parallel port data bus bit 3. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. INt INt PD4 13 EXTENSION FDD MODE: RDATA2 Motor on B for Extension FDD B; the function of this pin is the same as that of the RDATA pin. This pin is pulled high internally. EXTENSION 2FDD MODE: RDATA2 This pin is for Extension FDD A and B; this function of this pin is the same as that of the RDATA pin. This pin is pulled high internally. PRINTER MODE: PD4 Parallel port data bus bit 4. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. I/O24t INt INt PD5 14 EXTENSION FDD MODE: DSKCHG2 Drive select B for Extension FDD B; the function of this pin is the same as that of DSKCHG pin. This pin is pulled high internally. EXTENSION 2FDD MODE: DSKCHG2 This pin is for Extension FDD A and B; this function of this pin is the same as that of the DSKCHG pin. This pin is pulled high internally. PRINTER MODE: PD5 Parallel port data bus bit 5. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: This pin is a tri-state output. EXTENSION 2FDD MODE: This pin is a tri-state output. I/O24t - - 13 - Publication Release Date: November 1996 Revision 0.2 W83877ATF W83877ATF Preliminary 1.3 Multi-Mode Parallel Port, continued SYMBOL PD6 PIN I/O 16 I/O24t FUNCTION PRINTER MODE: PD6 Parallel port data bus bit 6. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. - EXTENSION FDD MODE: This pin is a tri-state output. IOD24 IOD24 EXTENSION. 2FDD MODE: MOA2 This pin is for Extension FDD A; its function is the same as that of the MOA pin. PD7 17 I/O24t PRINTER MODE: PD7 Parallel port data bus bit 7. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. - EXTENSION FDD MODE: This pin is a tri-state output. OD24 EXTENSION 2FDD MODE: DSA2 This pin is for Extension FDD A; its function is the same as that of the DSA pin. 1.4 FDC Interface SYMBOL PIN I/O FUNCTION RDATA 74 INcs The read data input signal from the FDD. This input pin is pulled up internally by an approximately 1K ohm resistor. The resistor can be disabled by bit 4 of CR6 (FIPURDWN). DSKCHG 76 INcs Diskette change. This signal is active low at power on and whenever the diskette is removed. This input pin is pulled up internally by an approximately 1K ohm resistor. The resistor can be disabled by bit 4 of CR6 (FIPURDWN). WP 77 INcs Write protected. This active low schmitt input from the disk drive indicates that the diskette is write-protected. This input pin is pulled up internally by an approximately 1K ohm resistor. The resistor can be disabled by bit 4 of CR6 (FIPURDWN). TRAK0 78 INcs Track 0. This schmitt input from the disk drive is active low when the head is positioned over the outermost track. This input pin is pulled up internally by an approximately 1K ohm resistor. The resistor can be disabled by bit 4 of CR6 (FIPURDWN). - 14 - Publication Release Date: November 1996 Revision 0.2 W83877ATF W83877ATF Preliminary 1.4 FDC interface, continued SYMBOL INDEX PIN 81 I/O INcs FUNCTION This schmitt input from the disk drive is active low when the head is positioned over the beginning of a track marked by an index hole. This input pin is pulled up internally by an approximately 1K ohm resistor. The resistor can be disabled by bit 4 of CR6 (FIPURDWN). MOA 79 OD24 Motor A On. When set to 0, this pin enables disk drive 0. This is an open drain output. MOB 80 OD24 Motor B On. When set to 0, this pin enables disk drive 1. This is an open drain output. STEP 82 OD24 Step output pulses. This active low open drain output produces a pulse to move the head to another track. DSA 83 OD24 Drive Select A. When set to 0, this pin enables disk drive A. This is an open drain output. DSB 84 OD24 Drive Select B. When set to 0, this pin enables disk drive B. This is an open drain output. WE WD 85 86 OD24 OD24 RWC 87 OD24 HEAD 88 OD24 DIR 89 OD24 Write enable. An open drain output. Write data. This logic low open drain writes precompensation serial data to the selected FDD. An open drain output. Reduced write current. This signal can be used on two-speed disk drives to select the transfer rate. An open drain output. Logic 0 = 250 Kb/s Logic 1 = 500 Kb/s When bit 5 of CR9 (EN3MODE) is set to high, the three-mode FDD function is enabled, and the pin will have a different definition. Refer to the EN3MODE bit in CR9. Head select. This open drain output determines which disk drive head is active. Logic 1 = side 0 Logic 0 = side 1 Direction of the head step motor. An open drain output. Logic 1 = outward motion Logic 0 = inward motion VDD 15, 56 GND 25,40 65,90 +5 power supply for the digital circuitry Ground - 15 - Publication Release Date: November 1996 Revision 0.2 W83877ATF W83877ATF Preliminary ORDERING INSTRUCTION PART NO. PACKAGE W83877ATF W83877ATF 100-pin QFP W83877ATD W83877ATD 100-pin TQFP PACKAGE DIMENSIONS W83877ATF W83877ATF (100-pin QFP) HD D 100 81 Symbol 1 A A1 A2 b c D E e HD HE L L1 y 80 E HE 30 51 Dimension in inches Min. Nom. Max. Dimension in mm Min. Nom. Max. 0.130 0.004 3.30 0.10 0.107 0.112 0.117 2.73 2.85 2.97 0.010 0.012 0.016 0.25 0.30 0.40 0.004 0.006 0.010 0.10 0.15 0.25 0.546 0.551 0.556 13.87 14.00 14.13 0.782 0.787 0.792 19.87 20.00 20.13 0.020 0.026 0.032 0.50 0.65 0.80 0.728 0.740 0.752 18.49 18.80 19.10 0.964 0.976 0.988 24.49 24.80 25.10 0.039 0.047 0.055 1.00 1.20 1.40 0.087 0.094 0.103 2.21 2.40 2.62 0.004 0 12 0.10 0 12 Notes: 31 e b 50 1. Dimension D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Millimeters 4. General appearance spec. should be based on final visual inspection spec. c A2 Seating Plane See Detail F A1 y A L L1 - 16 - Detail F Publication Release Date: November 1996 Revision 0.2 W83877ATF W83877ATF Preliminary W83877ATD W83877ATD (100-pin TQFP) HD D Symbol A A1 A2 b c D E e HD HE L L1 y E HE Dimension in mm Min. Nom. Max. Min. Nom. Max. Dimension in inches 0.006 0.05 0.053 0.055 0.057 0.002 0.004 1.35 1.40 0.10 1.45 0.009 0.013 0.015 0.22 0.32 0.38 0.004 0.006 0.008 0.10 0.15 0.20 0.547 0.551 0.555 13.90 14.00 14.10 0.783 0.787 0.791 19.90 20.00 20.10 0.498 0.65 0.15 0.020 0.026 0.032 0.626 0.630 0.634 15.90 16.00 16.10 0.862 0.866 0.870 21.90 22.00 22.10 0.018 0.024 0.030 0.45 0.60 0.75 1.00 0.039 0.003 0 0.802 7 0.08 0 7 Notes: e 1. Dimensions D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Millimeters 4. General appearance spec. should be based on final visual inspection spec. b C A2 Seating Plane See Detail F Headquarters A1 L y L1 Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5792647 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-7197006 Taipei Office Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2730 Orchard Parkway, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 Note: All data and specifications are subject to change without notice. - 17 - Publication Release Date: November 1996 Revision 0.2