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MSP430F2112IRHBT Texas Instruments 16-bit Ultra-Low-Power Microcontroller, 2kB Flash, 256B RAM, 10 bit ADC, 1 USCI 32-VQFN -40 to 105 visit Texas Instruments
MSP430F2112TPW Texas Instruments 16-bit Ultra-Low-Power Microcontroller, 2kB Flash, 256B RAM, 10 bit ADC, 1 USCI 28-TSSOP -40 to 105 visit Texas Instruments
MSP430F2112TPWR Texas Instruments 16-bit Ultra-Low-Power Microcontroller, 2kB Flash, 256B RAM, 10 bit ADC, 1 USCI 28-TSSOP -40 to 105 visit Texas Instruments Buy
MSP430F2112TRHB Texas Instruments 16-bit Ultra-Low-Power Microcontroller, 2kB Flash, 256B RAM, 10 bit ADC, 1 USCI 32-VQFN -40 to 105 visit Texas Instruments
MSP430F2112TRHBR Texas Instruments 16-bit Ultra-Low-Power Microcontroller, 2kB Flash, 256B RAM, 10 bit ADC, 1 USCI 32-VQFN -40 to 105 visit Texas Instruments Buy
MSP430F2112TRHBT Texas Instruments 16-bit Ultra-Low-Power Microcontroller, 2kB Flash, 256B RAM, 10 bit ADC, 1 USCI 32-VQFN -40 to 105 visit Texas Instruments

RAM 2112 256 word

Catalog Datasheet MFG & Type PDF Document Tags

LCMXO2-256 pinout

Abstract: -1200 256 640 640 1280 1280 2112 2112 4320 6864 Distributed RAM (Kbits) EBR SRAM , Programmable Function Units with Distributed RAM (PFUs) PIOs Arranged into sysIO Banks Note: MachXO2-256 , different widths on each of the ports. The RAM bits are mapped LSB word 0 to MSB word 0, LSB word 1 to MSB , devices with 256 to 6864 LUT4s and ï'  19 to 335 I/Os  Ultra Low Power Devices â'¢ â'¢ â'¢ â , RAM â'¢ Up to 54 Kbits Distributed RAM â'¢ Dedicated FIFO control logic  On-Chip User Flash
Lattice Semiconductor
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Abstract: Kbits Distributed RAM â'¢ Dedicated FIFO control logic  On-Chip User Flash Memory â'¢ Up to 256 , Selection Guide XO2-256 XO2-640 XO2-640U1 256 640 640 1280 1280 2112 2112 , RAM (PFUs) PIOs Arranged into sysIO Banks Note: MachXO2-256, and MachXO2-640/U are similar to , multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB word 0 to , frequency range (10 MHz to ï'  400 MHz)  Flexible Logic Architecture â'¢ Six devices with 256 to Lattice Semiconductor
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DS1035 XO2-2000 LCMXO2-2000ZE-1UWG49CTR LCMXO2-2000ZE-1UWG49ITR
Abstract: Kbits Distributed RAM â'¢ Dedicated FIFO control logic  On-Chip User Flash Memory â'¢ Up to 256 , Selection Guide XO2-256 XO2-640 XO2-640U1 256 640 640 1280 1280 2112 2112 , with Distributed RAM (PFUs) PIOs Arranged into sysIO Banks Note: MachXO2-256, and MachXO2-640/U , multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB word 0 to , frequency range (10 MHz to ï'  400 MHz)  Flexible Logic Architecture â'¢ Six devices with 256 to Lattice Semiconductor
Original
Abstract: Kbits Distributed RAM â'¢ Dedicated FIFO control logic  On-Chip User Flash Memory â'¢ Up to 256 , -2000U1 XO2-4000 XO2-7000 256 640 640 1280 1280 2112 2112 4320 6864 , . The RAM bits are mapped LSB word 0 to MSB word 0, LSB word 1 to MSB word 1, and so on. Although the word size and number of words for each port varies, this mapping scheme applies to each port. RAM , range (10 MHz to ï'  400 MHz)  Flexible Logic Architecture â'¢ Six devices with 256 to 6864 Lattice Semiconductor
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TN1200 XO2-4000HE
Abstract:  Embedded and Distributed Memory â'¢ Up to 240 Kbits sysMEMâ"¢ Embedded Block RAM â'¢ Up to 54 Kbits Distributed RAM â'¢ Dedicated FIFO control logic  On-Chip User Flash Memory â'¢ Up to 256 , -2000U1 XO2-4000 XO2-7000 256 640 640 1280 1280 2112 2112 4320 6864 , memory modes support different widths on each of the ports. The RAM bits are mapped LSB word 0 to MSB , range (10 MHz to ï'  400 MHz)  Flexible Logic Architecture â'¢ Six devices with 256 to 6864 Lattice Semiconductor
Original
Abstract:  Embedded and Distributed Memory â'¢ Up to 240 Kbits sysMEMâ"¢ Embedded Block RAM â'¢ Up to 54 Kbits Distributed RAM â'¢ Dedicated FIFO control logic  On-Chip User Flash Memory â'¢ Up to 256 , RAM (PFUs) PIOs Arranged into sysIO Banks Note: MachXO2-256, and MachXO2-640/U are similar to , multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB word 0 to , frequency range (10 MHz to ï'  400 MHz)  Flexible Logic Architecture â'¢ Six devices with 256 to Lattice Semiconductor
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UWG49
Abstract:  Embedded and Distributed Memory â'¢ Up to 240 Kbits sysMEMâ"¢ Embedded Block RAM â'¢ Up to 54 Kbits Distributed RAM â'¢ Dedicated FIFO control logic  On-Chip User Flash Memory â'¢ Up to 256 , -2000U1 XO2-4000 XO2-7000 256 640 640 1280 1280 2112 2112 4320 6864 , multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB word 0 to , range (10 MHz to ï'  400 MHz)  Flexible Logic Architecture â'¢ Six devices with 256 to 6864 Lattice Semiconductor
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LCMXO2-1200ZE1UWG25ITR50 LCMXO2-1200ZE-1UWG25ITR

LCMXO2-4000

Abstract: LCMX02 multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB word 0 to , differential I/Os Stand-by mode and other power saving options · Six devices with 256 to 6864 LUT4s and 19 to , SPI memory · · · · Embedded and Distributed Memory · Up to 240 Kbits sysMEMTM Embedded Block RAM · Up to 54 Kbits Distributed RAM · Dedicated FIFO control logic On-Chip User Flash Memory · Up to 256 Kbits of User Flash Memory · 100,000 write cycles · Accessible through WISHBONE, SPI, I2C and
Lattice Semiconductor
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LCMXO2-4000 LCMX02 LCMX02 1200 LCMXO2 640HC LCMXO2-4000HC MACHXO2 7000 pinout file XO2-256

LCMXO2-256 pinout

Abstract: LCMXO2-2000 pinout  Embedded and Distributed Memory â'¢ Up to 240 Kbits sysMEMâ"¢ Embedded Block RAM â'¢ Up to 54 Kbits Distributed RAM â'¢ Dedicated FIFO control logic  On-Chip User Flash Memory â'¢ Up to 256 , -2000U1 XO2-4000 XO2-7000 256 640 640 1280 1280 2112 2112 4320 6864 , multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB word 0 to , range (10 MHz to ï'  400 MHz)  Flexible Logic Architecture â'¢ Six devices with 256 to 6864
Lattice Semiconductor
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LCMXO2-256 pinout LCMXO2-2000 pinout

LCMX02

Abstract: LCMX02 1200 -7000 256 640 640 1280 1280 2112 2112 4320 6864 Distributed RAM (Kbits) EBR SRAM , RAM (PFUs) PIOs Arranged into sysIO Banks Note: MachXO2-256, and MachXO2-640/U are similar to , different widths on each of the ports. The RAM bits are mapped LSB word 0 to MSB word 0, LSB word 1 to MSB , frequency range (10 MHz to 400 MHz) Flexible Logic Architecture · Six devices with 256 to 6864 , Distributed Memory · Up to 240 Kbits sysMEMTM Embedded Block RAM · Up to 54 Kbits Distributed RAM ·
Lattice Semiconductor
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LCMXO2-1200HC-4TG144C LCMXO2-1200HC-4MG132C lcmxo2-1200 LCMXO2-640HC-4TG100C TQFP-144 footprint LCMXO2-7000HC XO2-1200-R1 LCMX02-2000UHE4FG484I LCMX02-2000UHE-5FG484I LCMX02-2000UHE-6FG484I AN8086
Abstract: -1200U1 XO2-2000 XO2-2000U1 XO2-4000 XO2-7000 256 640 640 1280 1280 2112 2112 , with Distributed RAM (PFUs) PIOs Arranged into sysIO Banks Note: MachXO2-256, and MachXO2-640/U , multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB word 0 to , devices with 256 to 6864 LUT4s and ï'  19 to 335 I/Os  Ultra Low Power Devices â'¢ â'¢ â'¢ â , RAM â'¢ Up to 54 Kbits Distributed RAM â'¢ Dedicated FIFO control logic  On-Chip User Flash Lattice Semiconductor
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MACHXO2 7000 pinout

Abstract: MachXO2-4000  Embedded and Distributed Memory â'¢ Up to 240 Kbits sysMEMâ"¢ Embedded Block RAM â'¢ Up to 54 Kbits Distributed RAM â'¢ Dedicated FIFO control logic  On-Chip User Flash Memory â'¢ Up to 256 , -2000U1 XO2-4000 XO2-7000 256 640 640 1280 1280 2112 2112 4320 6864 , memory modes support different widths on each of the ports. The RAM bits are mapped LSB word 0 to MSB , range (10 MHz to ï'  400 MHz)  Flexible Logic Architecture â'¢ Six devices with 256 to 6864
Lattice Semiconductor
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MACHXO2 7000 pinout MachXO2-4000
Abstract:  Embedded and Distributed Memory â'¢ Up to 240 Kbits sysMEMâ"¢ Embedded Block RAM â'¢ Up to 54 Kbits Distributed RAM â'¢ Dedicated FIFO control logic  On-Chip User Flash Memory â'¢ Up to 256 , -2000U1 XO2-4000 XO2-7000 256 640 640 1280 1280 2112 2112 4320 6864 , multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB word 0 to , range (10 MHz to ï'  400 MHz)  Flexible Logic Architecture â'¢ Six devices with 256 to 6864 Lattice Semiconductor
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RAM 2112 256 word

Abstract: intel 2112 Static RAM Memory Section of Memory Flash RAM UDC Address Register UDC RAM Control Word Register Character RAM CLOCK , UDC RAM, a UDC Address Register, a Control Word Register, and refresh circuitry necessary to , ) User-Defined Character Address Register (UDC Address Register) Control Word Register This RAM stores either , Load ""F'' into the UDC RAM. When the attribute is enabled through bit 3 of the Control Word and a , Word is a "0," the content of the Flash RAM is ignored. To use this function with multiple display
Agilent Technologies
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HDSP-21XX RAM 2112 256 word intel 2112 Static RAM HDSP-2XXX HDSP-2111 HDSP-2110 HDSP-210 HDSP-211 HDSP-250 HDSP-21 HDSP-211X I-060

LCMX02 1200

Abstract: LCMX02 RAM (PFUs) Note: MachXO2-256, and MachXO2-640/U are similar to MachXO2-1200. MachXO2-256 has a , multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB word 0 to , differential I/Os Stand-by mode and other power saving options · Six devices with 256 to 6864 LUT4s and 19 to , SPI memory · · · · Embedded and Distributed Memory · Up to 240 Kbits sysMEMTM Embedded Block RAM · Up to 54 Kbits Distributed RAM · Dedicated FIFO control logic On-Chip User Flash Memory · Up
Lattice Semiconductor
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LCMX02 256 LCMX02 640 MACHXO2 1200 pinout file MACHXO2-1200ZE LCMXO2-2000 LCMXO2-256HC-4SG32I

LCMXO2-4000HC

Abstract: LCMX02 RAM (PFUs) Note: MachXO2-256, and MachXO2-640/U are similar to MachXO2-1200. MachXO2-256 has a , multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB word 0 to , differential I/Os Stand-by mode and other power saving options · Six devices with 256 to 6864 LUT4s and 19 to , SPI memory · · · · Embedded and Distributed Memory · Up to 240 Kbits sysMEMTM Embedded Block RAM · Up to 54 Kbits Distributed RAM · Dedicated FIFO control logic On-Chip User Flash Memory · Up
Lattice Semiconductor
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Lattice XO2 LCMX02-2000 LCMXO2 wishbone MachXO2-1200 LCMXO2-2000HC-6FTG256C

lcmxo2-1200

Abstract: LCMXO2-2000 1280 2112 4320 6864 Distributed RAM (Kbits) 2 5 10 16 34 54 EBR SRAM , different widths on each of the ports. The RAM bits are mapped LSB word 0 to MSB word 0, LSB word 1 to MSB , MHz to 400 MHz) Flexible Logic Architecture · Six devices with 256 to 6864 LUT4s and 18 to , Kbits sysMEMTM Embedded Block RAM · Up to 54 Kbits Distributed RAM · Dedicated FIFO control logic On-Chip User Flash Memory · Up to 256 Kbits of User Flash Memory · 100,000 write cycles · Accessible
Lattice Semiconductor
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LCMXO2-256 LCMXO2-640 LCMXO2-256HC-4TG100I LCMXO2-7000 LCMXO2-2000HC-4BG256C lcmxo2 640 TN1087 AN8066

RAM 2112 256 word

Abstract: 2650 cpu requirements should become evident from these examples. PARTS DESCRIPTIONS 2112: The 2112 is a static 1024-bit Random Access Memory organized as 256 words by 4 Bits/Word. It is fabricated with N-Channel, Silicon Gate , 7 [T 2112 Til vcc Til a4 TT] r/W TT] ce TT] I/O 4 TT| 1/0 3 Tol "0 2 Vss(GND) [T ~9~| I/O 1 PARTS LIST PART NO. QTY DESCRIPTION REFERENCE DATA SHEET 2650 1 CPU â'" 2112 4 256X4 RAM MOS , use of RAM for program debugging. The second figure represents a possible final system configuration
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KT9000 8T26B 2650 cpu 8T31 8T26 ADR11 ba7t 82S115I ADR14-D/C B2S11S ADR13-E/N 512X8

HDSP2122

Abstract: HDSP-2121 Care UDC RAM 1 0 1 Row Address Control Word Register 1 1 0 Don't Care Character RAM 1 1 1 Character , character ASCII (Katakana) decoder, a 16 character UDC RAM, a UDC Address Register, a Control Word Register , the UDC RAM when the user is writing or reading a custom character. Control Word Register This , of the Control Word and a "1" is stored in the Flash RAM, the corresponding character will flash at , FLASH RAM ADDRESS control word address Dj Dc Dg D4 D3 O7 D6 Db D4 D3 D2 D, REMOVE FLASH AT SPECIFIED
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HDSP-250X HDSP2122 HDSP-2121 hdsp-2500 HDSP-2112 HDSP-2113 HDSP-212X HDSP-211X/ HDSP-211X/-212X/-250X HDSP-211X/-250X

9112C

Abstract: 91L12A 2112 256 x 4 Static RAM B. PACKAGE TYPE P - 16-Pin Plastic DIP (PD 016) C = 16-Pin Ceramic DIP , . SPEED OPTION A " 500 ns B - 400 ns C - 300 ns A. DEVICE NUMBER/DESCRIPTION Am9112 256 X 4 Static RAM , Am9112 2 5 6 x 4 Static RAM ZL16UIV DISTINCTIVE CHARACTERISTICS Low operating power , es guaranteed for sim pler timing Direct plug-in replacem ent for 2112 type devices GENERAL , as fa st as 200 ns and as low as 100 mW typical. Each mem ory is implemented as 256 w ords by 4 bits
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9112C 91L12A AM9112 maxim 2112 AM91L12A P2112A 9112/A 91L12 MIL-STD-883
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