QS3ST257 QS3S257 MDSL-00088-03 - Datasheet Archive

 

Q QUALITY SEMICONDUCTOR, INC. QuickSwitch® Products High-Speed CMOS SynchroSwitchTM Quad 2:1 Mux/Demux With Optional Active

 

QS3ST257 QS3ST257, QS3S257 QS3S257 ADVANCE INFORMATION Q QUALITY SEMICONDUCTOR, INC. QuickSwitch® Products High-Speed CMOS SynchroSwitchTM Quad 2:1 Mux/Demux With Optional Active Terminators (QS3ST257 QS3ST257) QS3ST257 QS3ST257 QS3S257 QS3S257 ADVANCE INFORMATION FEATURES/BENEFITS DESCRIPTION · Enhanced N channel FET with no inherent diode to VCC · Bidirectional signal flow · Flow-through pinout · Zero propagation delay, Zero ground bounce · 4 banks of 2:1 Mux/Demux · Port select synchronous to the clock · Clock enable and Asynchronous switch enable · "Bus hold" terminators on the demux side · Asynchronous SEL option · Break-before-make feature · Available in 20-pin QSOP (Q) · Undershoot clamp diodes on all switch and control pins · Bus-hold eliminates floating bus lines and reduces static power consumption The QS3ST257 QS3ST257 is a high speed CMOS Quad 2:1 multiplexer/demultiplexer with active terminators (bus-hold circuits) on the demux side. Port selection and connection, controlled by SEL signals, can be either asynchronous or synchronous. In the synchronous mode, the A or B port to Y port connection is updated on the rising edge of the input clock CLK. Once the port-to-port connection is made, data flow can be bi-directional with a typical 250ps propagation delay through the switch. Clock Enable, over-riding Asynchronous Enable, and Asynchronous Select controls provide additional design flexibility. APPLICATIONS · Video, audio, graphics switching, muxing · Bus funneling · Voltage translation (QS3S257 QS3S257) an w ny pa The Bus-hold circuits in QS3ST257 QS3ST257 latch the last data driven on the demux side, providing infinite hold time and glitch-free signal transitions. Synchronous controls and bus-hold ease timing constraints in many high speed data mux/demux applications such as memory bank interleaving. om C The QS3S257 QS3S257 performs the same function as QS3ST257 QS3ST257, but does not have terminators on the demux side. This facilitates 5V to 3.3V translation. QuickSwitch Mux/Demux devices provide an order of magnitude faster speed than equivalent logic devices. No Figure 1. Functional Block Diagram R SEL CLK CLKEN OE SYNC T = Control Logic A0 Y0 T T Y1 T T Y2 T T Y3 T B0 A1 B1 A2 B2 A3 B3 T AI = Advance Information MDSL-00088-03 MDSL-00088-03 JULY 31, 1997 QUALITY SEMICONDUCTOR, INC. 1 QS3ST257 QS3ST257, QS3S257 QS3S257 ADVANCE INFORMATION Figure 2. Pin Configuration (All Pins Top View) QSOP Table 1. Pin Description Name I/O Description A0.A3 I/O Demux Port A B0.B3 I/O Demux Port B Y0.Y3 I/O Mux Port Y SEL I Select Input CLK I Clock CLKEN I Clock Enable OE I Output Enable SYNC I Synchronous Enable NC A0 A1 A2 A3 B0 B1 B2 B3 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC OE SEL Y0 Y1 Y2 Y3 CLKEN CLK SYNC ny pa om C Figure 3. Control Logic 1 an w 2:1 MUX No SEL 0 D Q 0 2:1 MUX 1 CLKEN CLK SYNC To Port A Switches OE 2 To Port B Switches QUALITY SEMICONDUCTOR, INC. MDSL-00088-03 MDSL-00088-03 JULY 31, 1997 QS3ST257 QS3ST257, QS3S257 QS3S257 ADVANCE INFORMATION Table 2. Function Table Control Inputs SYNC OE Port Status CLK CLKEN SEL Function Y0 Y1 Y2 Y3 L L L L A0 A1 A2 A3 Select Port A L L L H B0 B1 B2 B3 Select Port B L H L X No change in Mux connection Hold previous data(1) (Switch OFF) L L H X No change in Mux connection Hold previous mux connection(2) (Switch ON) L H H X No change in Mux connection Hold previous data(3) (Switch OFF) H L X X L A0 A1 A2 A3 Select Port A H L X X H B0 B1 B2 B3 Select Port B H H X X X No change in Mux connection ny pa Hold previous data (Switch OFF)(1) om C Notes: 1. Mux switches are turned off and the terminators (last value latches) hold the previous data state. The port connection can be changed by the SEL input. 2. The contents of the "mux select register" are unchanged and the previous mux connection is unchanged. The output (Mux port) data state will depend on the present data state of the input (Demux port). 3. The contents of the "mux select register" are unchanged and the last value latches hold the previous data state. an w Table 3. Absolute Maximum Ratings No Supply Voltage to Ground . ­0.5V to +7.0V DC Switch Voltage VS . ­0.5V to +7.0V DC Input Voltage VIN . ­0.5V to +7.0V AC Input Voltage (for a pulse width 20ns) . ­3.0V DC Output Current Max. Sink Current/Pin . 120mA Maximum Power Dissipation At TA = 85°C . 0.82 watts TSTG Storage Temperature . ­65° to +150°C Note: ABSOLUTE MAXIMUM CONTINUOUS RATINGS are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum conditions is not implied. Table 4. Capacitance TA = 25°C, f = 1MHz, VIN = 0V, VOUT = 0V QSOP Typ Max Pins Control Inputs Unit 4 5 pF QuickSwitch Channels Demux 5 7 pF (Switch OFF) Mux 7 9 pF MDSL-00088-03 MDSL-00088-03 JULY 31, 1997 Note: Capacitance is guaranteed, but not production tested and are typical values. For total capacitance while the switch is ON, please see Section 1 under "Input and Switch Capacitance." QUALITY SEMICONDUCTOR, INC. 3 QS3ST257 QS3ST257, QS3S257 QS3S257 ADVANCE INFORMATION Table 5. DC Electrical Characteristics Over Operating Range TA = ­40°C to 85°C, VCC = 5.0V ± 10% Symbol Parameter Test Conditions Min Typ(1) Max Unit VIH Input HIGH Voltage Guaranteed Logic HIGH for Control Pins 2.0 - - V VIL Input LOW Voltage Guaranteed Logic LOW for Control Pins - - 0.8 V IIN Input Leakage Current (Control Inputs) 0V VIN VCC - 0.01 1 µA RON Switch On Resistance(2) VCC = Min., VIN = 0.0V, ION = 30mA - 4 6 VCC = Min., VIN = 2.4V, ION = 15mA - 7 10 IBHL IBHH Input Hold Current (A or B port) VCC = Min. Switch OFF VIN = 0.8V, VIN = 2.0V 60 ­60 - - - - IBH Input Current(5) (A or B port) VCC = Max. VIN = 0, or VCC 0.8V < VIN < 2.0V VP Pass Voltage(6) VIN = VCC = 5V, IOUT = ­5µA (3,4) µA µA 20 µA 500(5) QS3S257 QS3S257 Only ny pa 3.7 4.0 4.2 V om C Notes: 1. Typical values indicate VCC = 5.0V and TA = 25°C. 2. For a diagram explaining the procedure for RON measurement, please see Section 1 under "DC Electrical Characteristics." RON is guaranteed, but not production tested. 3. IBHL - Minimum sustaining "sink" current at the input for VIN = 0.8V. This parameter signifies the latching capability of the Bus-hold circuit in logic LOW state. 4. IBHH ­ Minimum sustaining "source" current at the input for VIN = 2.0V. This parameter signifies the latching capability of the Bus-hold circuit in logic HIGH state. 5. IBH ­ Magnitude of the input current specified under two conditions: (a) Input voltage at GND or VCC . This indicates the input current under steady-state condition. (b) Input voltage between 0.8V and 2.0V (TTL input threshold range). This indicates the maximum input current during transient condition. The driver connected to the input must overcome this current requirement in order to switch the logic state of the Bus-hold circuit. 6. Pass voltage is guaranteed, but not production tested. an w No Figure 4. Typical ON Resistance vs VIN at VCC = 5.0V RON (ohms) 16 14 12 10 8 6 4 2 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VIN (Volts) 4 QUALITY SEMICONDUCTOR, INC. MDSL-00088-03 MDSL-00088-03 JULY 31, 1997 QS3ST257 QS3ST257, QS3S257 QS3S257 ADVANCE INFORMATION Table 6. Power Supply Characteristics Over Operating Range TA = ­40°C to 85°C, VCC = 5.0V ± 10% Symbol Parameter Test Conditions(1) Max Unit ICCQ Quiescent Power Supply Current VCC = Max., VIN = GND or VCC, f = 0 3 µA ICC Power Supply Current Per Control Input HIGH(2) VCC = Max., VIN = 3.4V, f = 0 1.5 mA QCCD Dynamic Power Supply Current per MHz(3) VCC = Max., A/B and Y Pins Open, Control Input Toggling @ 50% Duty Cycle 0.25 mA/ MHz Notes: 1. For conditions shown as Min. or Max., use the appropriate values specified under DC specifications. 2. Per TTL driven input (VIN = 3.4V, control inputs only). A/B and Y pins do not contribute to ICC. 3. This current applies to the control inputs only and represents the current required to switch internal capacitance at the specified frequency. The A/B and Y inputs generate no significant AC or DC currents as they transition. This parameter is guaranteed, but not production tested. ny pa Table 7. Switching Characteristics Over Operating Range TA = ­40°C to 85°C, VCC = 5.0V ± 10% CLOAD = 50pF, RLOAD = 500 unless otherwise noted. Symbol om C Description(1) Min Typ Max Unit - 0.25 - ns tPLH tPHL Data Propagation Delay(2,3) A/B to Y, Y to A/B tSEC Clock Enable to Clock Setup Time 3.0 - - ns tHEC Clock Enable to Clock Hold Time 0 - - ns tCSO Clock to A, B Switch Turn-on Delay(4) 0.5 - 7.0 ns tASO Asynchronous Select to A, B Switch Turn-on Delay 0.5 - 7.0 ns ow N an (4) tW Clock Pulse Width (High) 3.0 - - ns tSCS SEL to Clock Setup Time 3.0 - - ns tHCS SEL to Clock Hold Time 0 - - ns tPZL, tPZH Asynchronous Enable to Switch Turn-on Delay(4) 1.5 - 5.2 ns tPLZ, tPHZ Asynchronous Enable to Switch Turn-off Delay(2,4) 1.5 - 4.8 ns Notes: 1. See Test Circuit and Waveforms. 2. This parameter is guaranteed, but not production tested. 3. The bus switch contributes no propagation delay other than the RC delay of the ON resistance of the switch and the load capacitance. The time constant for the switch alone is of the order of 0.25ns for CL = 50pF. Since this time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay of the bus switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side. 4. Minimums guaranteed but not production tested. MDSL-00088-03 MDSL-00088-03 JULY 31, 1997 QUALITY SEMICONDUCTOR, INC. 5 QS3ST257 QS3ST257, QS3S257 QS3S257 ADVANCE INFORMATION Figure 5. Timing Waveforms - Synchronous Mode, Demux Function SYNC tSEC tHEC CLKEN CLK tSCS tHCS tSCS tHCS SEL ny pa OE Port Y DATA0 DATA1 DATA2 om C tPLH, tPHL tCSO an w Port A INVALID DATA Port B 6 No DATA0 INVALID DATA DATA1 HOLD PREVIOUS DATA, DATA1 t PLH, tPHL tCSO DATA1 DATA2 HOLD PREVIOUS DATA, DATA2 QUALITY SEMICONDUCTOR, INC. MDSL-00088-03 MDSL-00088-03 JULY 31, 1997 QS3ST257 QS3ST257, QS3S257 QS3S257 ADVANCE INFORMATION Figure 6. Timing Waveforms - Synchronous Mode, Mux Function SYNC tSEC tHEC CLKEN CLK tSCS tHCS tSCS tHCS SEL0, SEL1 Port A DATA1 Port B DATA3 tCSO Port Y ny pa DATA2 an INVALID DATA ow N MDSL-00088-03 MDSL-00088-03 JULY 31, 1997 tPLH, tPHL DATA1 om C tCSO DATA2 DATA4 tPLH, tPHL DATA3 QUALITY SEMICONDUCTOR, INC. DATA4 7 QS3ST257 QS3ST257, QS3S257 QS3S257 ADVANCE INFORMATION Figure 7. Timing Waveforms - Asynchronous Mode, Mux Function SYNC SEL OE Port A INVALID DATA DATA1 tPLH, tPHL Port B ny pa DATA2 tPLH, t PHL om C DATA3 INVALID DATA tPLZ, tPHZ tPZL, tPZH tASO Port Y INVALID DATA DATA1 an w DATA2 DATA3 DATA3 No 8 QUALITY SEMICONDUCTOR, INC. MDSL-00088-03 MDSL-00088-03 JULY 31, 1997 QS3ST257 QS3ST257, QS3S257 QS3S257 ADVANCE INFORMATION ACTIVE TERMINATOR OR 'BUS-HOLD' CIRCUIT The Active Terminator circuit, also known as the Bus-hold circuit, is configured as a `weak latch' with positive feedback. When connected to a TTL or CMOS input port, the Bus-hold circuit holds the last logic state at the input when the input is `disconnected' from the driver. When the output of a device connected to such an input attempts a logic level transition, it will overdrive the Bus-hold circuit. The primary benefit of a Bus-hold circuit is that it prevents CMOS inputs from floating, a situation which should be avoided to prevent spurious switching of inputs and unnecessary power dissipation. Bus-hold is a better solution than the traditional approach of using resistive termination to VCC or GND to prevent bus floating, because the Bus-hold circuit does not consume any static power. Figure 8. V-I Characteristics of Bus-hold Circuit IBH 500 ny pa Sinking Current (+) IBHL +60 +20 ­20 ­60 IBH IBHH * * * +60 IBHL an w om C VT * ­60 IBHH VIL Sourcing Current (­) Voltage +20 IBH * * ­20 IBH V CC VIH No IBH ­500 .8V 2V VT Threshold Voltage 1.5V VIL .80 VIH 2V Figure 8. Shows the input V-I characteristics of a typical Bus-hold implementation. The input characteristics resemble a resistor. As the input voltage is increased from 0 volts, the input `sink' current increases linearly. When the TTL threshold of the circuit is reached (typically 1.5 Volts), the latch changes the logic state due to positive feedback and the direction of current is reversed. As the input voltage is further increased towards VCC, the input `source' current begins to decrease, reaching the lowest level at VIN = VCC. MDSL-00088-03 MDSL-00088-03 JULY 31, 1997 QUALITY SEMICONDUCTOR, INC. 9