NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: QD17, QD18 SL66G SL66G RG82845GL RG82845GL 82845GL 82845GL Desktop A1 QD69 SL6NR RG82845GV RG82845GV 82845GV 82845GV ... | Original |
15 pages, |
QD18 82845GV 845GL 845gv DDR333 RG82845 FSB400 SL66F 82845G 82845GL SL66G rg82845gl RG82845GV SL6PU RG82845G RG82845GV 845G/845GL/845GV 82845G/82845GL/82845GV 845G/845GL/845GV abstract |
|
|||
| Abstract: ® MIC5318-1 MIC5318-1.5YD5 QD15 1.5V 40°C to +125°C 5-Pin Thin SOT23 MIC5318-1 MIC5318-1.8YD5 QD18 1.8V 40°C ... | Original |
11 pages, |
MLF-6 MIC5318 QD18 qd33 MIC5318-3 SC-70 MIC5318 abstract |
|
|||
| Abstract: QD15 1.5V 40°C to +125°C 5-Pin Thin SOT23 MIC5318-1 MIC5318-1.8YD5 QD18 1.8V 40°C to ... | Original |
11 pages, |
QD18 MIC5318 qd33 SC-70 MIC5318 abstract |
|
|||
| Abstract: QD15 1.5V 40°C to +125°C 5-Pin Thin SOT23 MIC5318-1 MIC5318-1.8YD5 QD18 1.8V 40°C to ... | Original |
11 pages, |
QD18 MIC5318 SC-70 MIC5318 abstract |
|
|||
| Abstract: Data Sheet C-3e NETWORK PROCESSOR SILICON REVISION B0 C3ENPB0-DS Rev 03 PRODUCTION Data Sheet C-3e Network Processor Silicon Revision B0 C3ENPB0-DS Rev 03 Copyright © 2003 Motorola, Inc. All rights reserved. No part of this documentation may be reproduced in any form or by any means or used to make any derivative work (such as translation, transformation, or adaptation) without written permission from Motorola. Motorola reserves the right to revise this documentation and ... | Original |
114 pages, |
TD60 RX 3E motorola g18 md75 marking code ta9 CP15 CP-14 datasheet abstract |
|
|||
| Abstract: K2077 QD2 F PCLK CCLK1 QA16 QA10 QA5 QA0 QACLKO QD25 QD18 QD10 QD3 E ... | Original |
110 pages, |
RX 3E motorola g18 MD102 marking code ta9 md108 MD-68 MD-109 datasheet abstract |
|
|||
| Abstract: Data Sheet C-3e NETWORK PROCESSOR SILICON REVISION A1 C3ENPA1-DS/D Rev 03 PRELIMINARY Pr el im ar in C-3e Network Processor Silicon Revision A1 y Data Sheet C3ENPA1-DS/D Rev 03 Copyright © 2002 Motorola, Inc. All rights reserved. No part of this documentation may be reproduced in any form or by any means or used to make any derivative work (such as translation, transformation, or adaptation) without written permission from Motorola. Motorola reserves t ... | Original |
114 pages, |
td58 RX 3E motorola g18 md75 CP-14 QD18 datasheet abstract |
|
|||
| Abstract: LatticeECP2M SERDES/PCS Usage Guide February 2010 Technical Note TN1124 TN1124 Introduction to PCS The LatticeECP2MTM family of FPGAs combines a high-performance FPGA fabric, high-performance I/Os and large embedded RAM in a single industry leading architecture. All LatticeECP2M devices also feature up to 16 channels of embedded SERDES with associated Physical Coding Sublayer (PCS) logic. The PCS logic can be configured to support numerous industry standard high-speed data transfer protocol ... | Original |
93 pages, |
XXX1111100 vhdl code for 16 prbs generator TN1114 mca exam date sheet 1000BASE-X 8bser TN1124 TN1124 abstract |
|
|||
| Abstract: LatticeECP2M SERDES/PCS Usage Guide June 2010 Technical Note TN1124 TN1124 Introduction to PCS The LatticeECP2MTM FPGA family combines a high-performance FPGA fabric, high-performance I/Os and large embedded RAM in a single industry-leading architecture. All LatticeECP2M devices also feature up to 16 channels of embedded SERDES with associated Physical Coding Sublayer (PCS) logic. The PCS logic can be configured to support numerous industry-standard, high-speed data transfer protocols. Eac ... | Original |
96 pages, |
vhdl code for DCO TN1114 1000BASE-X mca exam date sheet TN1124 TN1124 abstract |
|
|||
| Abstract: Data Sheet C-5e NETWORK PROCESSOR SILICON REVISION A1 C5ENPA1-DS/D Rev 03 PRELIMINARY Pr el im ar in C-5e Network Processor Silicon Revision A1 y Data Sheet C5ENPA1-DS/D Rev 03 Copyright © 2002 Motorola, Inc. All rights reserved. No part of this documentation may be reproduced in any form or by any means or used to make any derivative work (such as translation, transformation, or adaptation) without written permission from Motorola. Motorola reserves t ... | Original |
114 pages, |
OC48 motorola g18 CP-14 datasheet abstract |
|
|||
| Abstract: MC54/74F398 MC54/74F398 QUAD 2-PORT REGISTER The MC54/74F398 MC54/74F398 is the logical equivalent of a quad 2-input multiplexer feeding into four edge-triggered flip-flops. A common Select input determines which of the two 4-bit words is accepted. The selected data enters the flipflops on the rising edge of the clock. QUAD 2-PORT REGISTER · Select Inputs from Two Data Sources · Fully Positive Edge-Triggered Operation · Both True and Complement Outputs FASTTM SCHOTTKY TTL CONNECTION DIAGRAM (TOP VIEW) ... | Original |
3 pages, |
MC74FXXXDW MC54/74F398 MC54/74F398 abstract |
|
|||
| Abstract: LS TTL DN74LS DN74LS Series DN74J DN74J.S197 DN74LS197 DN74LS197 LS ... | OCR Scan |
4 pages, |
MA161 DN74LS197 DN74LS DN74J DN74LS abstract |
|
|||
| Abstract: SONY. CXB1139Q CXB1139Q Programmable Delay Line/Duty Cycle Controller Description The CXB1139Q CXB1139Q is an ultra high speed monolithic ECL Delay Line/Duty Cycle Controller IC. Five binary inputs. So to S4, program the delay time from input Din to output Qd in 23 steps. Binary input code 00001 through 00110 provides a delay of 125ps for each increment of the code, while 00111 through 10111 provides a delay of 190ps for each step. A pulse with plus (long) duty cycle is provided at output Qp, and a pulse wi ... | OCR Scan |
5 pages, |
CXB1139Q CXB1139Q abstract |
|
|||
| Abstract: SN54/74LS398 SN54/74LS398 SN54/74LS399 SN54/74LS399 QUAD 2-PORT REGISTER The SN54 / 74LS398 74LS398 and SN54 / 74LS399 74LS399 are Quad 2-Port Registers. They are the logical equivalent of a quad 2-input multiplexer followed by a quad 4-bit edge-triggered register. A Common Select input selects between two 4-bit input ports (data sources). The selected data is transferred to the output register on the LOW-to-HIGH transition of the Clock input. The SN54/ SN54/ 74LS398 74LS398 features both Q and Q inputs, while the SN54 / 74LS399 74LS399 has only Q ou ... | Original |
4 pages, |
SN74LSXXXN SN54LSXXXJ 74LS399 74LS398 SN54/ SN54/74LS398 SN54/74LS399 74LS398 abstract |
|
|||
| Abstract: HV7620 HV7620 40MHz, 32-Channel Serial to Parallel Converter with Push-Pull Outputs Features General Description The HV7620 HV7620 is a low-voltage serial to high-voltage parallel converter with push-pull outputs. This device has been designed for use as a driver for color AC plasma displays. HVCMOS® technology 5.0V logic and 12V supply rail Output voltage up to +200V Low power level shifting Source/sink current minimum 50mA 40MHz equivalent data rate Latched data out ... | Original |
7 pages, |
HV7620PG-G HV7620 A0304 T-con HV7620 abstract |
|
|||
| Abstract: Issued March 1997 232-2661 Data Pack F Data Sheet LED display with integral counter RS stock number 586-992 A red 0.27 in high 7-segment LED display containing a BCD counter, four-bit latch and decoder driver. The BCD counter has dual count inputs providing full lookahead, enabling high speed fully synchronous multidigit counter systems to be realised without the need for external logic. Other features include ripple blanking input/outputs for leading or trailing zero suppressi ... | Original |
4 pages, |
seven segment display ten pin IN4148 COUNTER LED bcd standard 74 series ttl datasheet abstract |
|
|||
| Abstract: Issued July 1984 005-370 Data Pack F Data Sheet LED display with integral counter RS stock number 586-992 A red 0.27 in high 7-segment LED display containing a BCD counter, four-bit latch and decoder driver. The BCD counter has dual count inputs providing full lookahead, enabling high speed fully synchronous multidigit counter systems to be realised without the need for external logic. Other features include ripple blanking input/outputs for leading or trailing zero suppression ... | Original |
4 pages, |
IN4148 datasheet abstract |
|
|||
| Abstract: HV7620 HV7620 40MHz, 32-Channel Serial to Parallel Converter with Push-Pull Outputs Features General Description The HV7620 HV7620 is a low-voltage serial to high-voltage parallel converter with push-pull outputs. This device has been designed for use as a driver for color AC plasma displays. HVCMOS® technology 5.0V logic and 12V supply rail Output voltage up to +200V Low power level shifting Source/sink current minimum 50mA 40MHz equivalent data rate Latched data out ... | Original |
7 pages, |
HV7620PG-G HV7620 HV7620 abstract |
|
|||
| Abstract: Supertex inc. HV7620 HV7620 40MHz, 32-Channel Serial to Parallel Converter with Push-Pull Outputs Features General Description The HV7620 HV7620 is a low-voltage serial to high-voltage parallel converter with push-pull outputs. This device has been designed for use as a driver for color AC plasma displays. HVCMOS® technology 5.0V logic and 12V supply rail Output voltage up to +200V Low power level shifting Source/sink current minimum 50mA 40MHz equivalent data rat ... | Original |
7 pages, |
HV7620PG-G HV7620 datasheet abstract |
|
|||
| Abstract: Octal D-Type Flip-Flop with 3-State Outputs MC74LVX574 MC74LVX574 The MC74LVX574 MC74LVX574 is an advanced high speed CMOS octal flip╜flop with 3╜state outputs. The inputs tolerate voltages up to 7V, allowing the interface of 5V systems to 3V systems. This 8╜bit D╜type flip╜flop is controlled by a clock pulse input and an output enable input. When the output enable input is high, the eight outputs are in a high impedance state. ╥ ╥ ╥ ╥ ╥ ╥ ╥ ╥ LVX High Speed: tPD = 8.5ns (Typ) at VCC = 3.3 ... | Original |
8 pages, |
MC74LVX574 MC74LVX574 abstract |
|
|||
| Abstract | Saved from | Date Saved | File Size | Type | Download |
| Over 1.1 million files (1986-2013): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer. |
|||||
| MODULE adder24 TITLE '24-bit adder' " " Notes "This design is a 24-bit adder with output registers. It implements the "Lattice macro F3ADD in Abel macro's. Propagate/generate are implemented "with simple Boolean equations. Three levels are required. The challenge "in going beyond 24 bits is the 16-input limit imposed by the Lattice "architecture on the number of inputs to the equation for the highest order "carry in. Nodes are preserved to www.datasheetarchive.com/files/lattice/encyclo/pdf/an8007.txt |
Lattice | 11/08/1997 | 17.18 Kb | TXT | an8007.txt |
| _temp_qd[8]; new_temp_qd[17] = old_temp_qd[9]; new_temp_qd[18] = old_temp_qd[10]; new_temp_qd[19] = old _temp_qd[16]; new_temp_qd[2] = old_temp_qd[12] ^ old_temp_qd[17]; new_temp_qd[3] = old_temp_qd[13] ^ old_temp_qd[18]; new_temp_qd[4] = old_temp_qd[14] ^ old_temp_qd[19]; new_temp_qd[5] = old_temp_qd[15] ^ old www.datasheetarchive.com/download/55643034-996015ZC/xapp652.zip (pn23_2shift.v) |
Xilinx | 18/06/2004 | 45.89 Kb | ZIP | xapp652.zip |
| begin 755 xchecker M A !" 420 !)2P ( # 60 $ M/ M % @ 8@ 4 $Y 3D !Z !*@ # &S M ;, !LP &S $ www.datasheetarchive.com/download/61553818-996606ZC/xchkr_hp.tar |
Xilinx | 20/01/1997 | 496 Kb | TAR | xchkr_hp.tar |
| EESchema-LIBRARY Version 2.2 Date: 10/10/2004-17:10:44 # # 74469 # DEF 74469 U 0 40 Y Y 1 0 N F0 "U" 0 0 70 H V C C F1 "74469" 0 -200 70 H V C C DRAW S -350 650 350 -650 0 1 0 N X CBO 14 650 -400 300 L 60 60 1 1 O X OE 13 650 -300 300 L 60 60 1 1 I X Q7 15 650 -100 300 L 60 60 1 1 T X VCC 24 0 650 0 D 60 60 1 1 W N X GND 12 0 -650 0 U 60 60 1 1 W N X Q6 16 650 0 300 L 60 60 1 1 T X Q5 17 650 100 300 L 60 60 1 1 T X Q4 18 650 200 300 L 60 60 1 1 T X Q3 19 650 300 300 L 60 60 1 1 www.datasheetarchive.com/files/kaleidoscope/cad/kicad - kicad/library/74xx.lib |
Kaleidoscope | 10/10/2004 | 110.31 Kb | LIB | 74xx.lib |
| [ver] 4 [sty] [files] [charset] 82 ANSI (Windows, IBM CP 1252) [revisions] 0 [prn] LaserJet SuperDriver [port] LPT2: [lang] 2 [fldnames] Field1 Field2 Field3 Field4 Field5 Field6 Field7 Field8 [desc] 830992725 44 754777256 1357 1 0 0 0 0 1 [fopts] 0 1 0 0 [lnopts] 2 Body Text 1 [docopts] 5 2 [GramStyle] [ParaNum] 1 [tag] Body Text 2 [fnt] Times New Roman 2 www.datasheetarchive.com/files/duracell/amipro/docs/designer/mn9100s.sam |
Duracell | 01/05/1996 | 948.51 Kb | SAM | mn9100s.sam |
| [ver] 4 [sty] [files] [charset] 82 ANSI (Windows, IBM CP 1252) [revisions] 0 [prn] LaserJet SuperDriver [port] LPT2: [lang] 2 [fldnames] Field1 Field2 Field3 Field4 Field5 Field6 Field7 Field8 [desc] 846274613 46 754777256 1739 2 0 0 0 0 1 [fopts] 0 1 0 0 [lnopts] 2 Body Text 1 [docopts] 5 2 [GramStyle] [ParaNum] 1 [tag] Body Text 2 [fnt] Times New Roman 2 www.datasheetarchive.com/files/duracell/amipro/docs/designer/pc918s.sam |
Duracell | 25/10/1996 | 706.95 Kb | SAM | pc918s.sam |
| [ver] 4 [sty] [files] [charset] 82 ANSI (Windows, IBM CP 1252) [revisions] 0 [prn] HP LaserJet 4/4M [port] LPT1: [lang] 2 [desc] 779655864 48 754777256 1715 1 0 0 0 0 1 [fopts] 0 1 0 0 [lnopts] 2 Body Text 1 [docopts] 5 2 [GramStyle] [ParaNum] 1 [tag] Body Text 2 [fnt] Times New Roman 240 0 49152 [algn] 1 1 0 0 0 [spc] 33 273 1 0 0 1 www.datasheetarchive.com/files/duracell/amipro/docs/designer/4r25s.sam |
Duracell | 15/09/1994 | 331.91 Kb | SAM | 4r25s.sam |
| [ver] 4 [sty] [files] [charset] 82 ANSI (Windows, IBM CP 1252) [revisions] 0 [prn] LaserJet SuperDriver [port] LPT2: [lang] 2 [fldnames] Field1 Field2 Field3 Field4 Field5 Field6 Field7 Field8 [desc] 801511924 43 754777256 1464 1 0 0 0 0 1 [fopts] 0 1 0 0 [lnopts] 2 Body Text 1 [docopts] 5 2 [GramStyle] [ParaNum] 1 [tag] Body Text 2 [fnt] Times New Roman 2 www.datasheetarchive.com/files/duracell/amipro/docs/designer/mn21s.sam |
Duracell | 26/05/1995 | 480.72 Kb | SAM | mn21s.sam |
| [ver] 4 [sty] [files] [charset] 82 ANSI (Windows, IBM CP 1252) [revisions] 0 [prn] LaserJet SuperDriver [port] LPT2: [lang] 2 [fldnames] Field1 Field2 Field3 Field4 Field5 Field6 Field7 Field8 [desc] 846274730 47 754777256 1723 1 0 0 0 0 1 [fopts] 0 1 0 0 [lnopts] 2 Body Text 1 [docopts] 5 2 [GramStyle] [ParaNum] 1 [tag] Body Text 2 [fnt] Times New Roman 2 www.datasheetarchive.com/files/duracell/amipro/docs/designer/pc908s.sam |
Duracell | 25/10/1996 | 782.76 Kb | SAM | pc908s.sam |
| [ver] 4 [sty] [files] [charset] 82 ANSI (Windows, IBM CP 1252) [revisions] 0 [prn] LaserJet SuperDriver [port] LPT2: [lang] 2 [fldnames] Field1 Field2 Field3 Field4 Field5 Field6 Field7 Field8 [desc] 801513085 46 754777256 1661 1 0 0 0 0 1 [fopts] 0 1 0 0 [lnopts] 2 Body Text 1 [docopts] 5 2 [GramStyle] [ParaNum] 1 [tag] Body Text 2 [fnt] Times New Roman 2 www.datasheetarchive.com/files/duracell/amipro/docs/designer/mn918s.sam |
Duracell | 26/05/1995 | 403.58 Kb | SAM | mn918s.sam |