MODULE-64 MC68F375 QADC64 10-BIT 16-BIT MC14051 ANX10 ANX12 ANX14 ANX11 ANX13 - Datasheet Archive

 

QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 The MC68F375 includes one independent queued analog-to-digital converter (QADC64)

 

SECTION 5 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MODULE-64 The MC68F375 MC68F375 includes one independent queued analog-to-digital converter (QADC64 QADC64) module. For details of QADC64 QADC64 operation not included in this section, refer to the QADC Reference Manual (QADCRM/AD). 5.1 Overview The QADC64 QADC64 modules consist of an analog front-end and a digital control subsystem, which includes an intermodule bus (IMB3) interface block. Refer to Figure 5-1. The analog section includes input pins, channel selection logic, an analog multiplexer, and one sample and hold analog circuit. The analog conversion is performed by the digital-to-analog converter (DAC) resistor-capacitor array, a high-gain comparator, and a successive approximation register (SAR). The digital control section contains the conversion sequencing logic. Also included are the periodic/interval timer, control and status registers, the conversion command word (CCW) table RAM, and the result word table RAM. EXTERNAL TRIGGERS EXTERNAL MUX ADDRESS UP TO 16 ANALOG INPUT PINS REFERENCE INPUTS ANALOG POWER INPUTS ANALOG INPUT MULTIPLEXER AND DIGITAL PIN FUNCTIONS DIGITAL CONTROL 10-BIT 10-BIT ANALOG TO DIGITAL CONVERTER QUEUE OF 10-BIT 10-BIT CONVERSION COMMAND WORDS (CCW), 64 ENTRIES 10-BIT 10-BIT RESULT TABLE, 64 ENTRIES 10-BIT 10-BIT TO 16-BIT 16-BIT RESULT ALIGNMENT INTERMODULE BUS INTERFACE IMB3 Figure 5-1 QADC64 QADC64 Block Diagram MC68F375 MC68F375 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MODULE-64 REFERENCE MANUAL Rev. 15 Oct 00 MOTOROLA 5-1 5.2 Features The QADC64 QADC64 module offers the following features: · Internal sample and hold · Up to 16 analog input channels using internal multiplexing · Directly supports up to four external multiplexers (for example, the MC14051 MC14051) · Up to 41 total input channels with internal and external multiplexing · Programmable input sample time for various source impedances · Two conversion command queues with a total of 64 entries · Sub-queues possible using pause mechanism · Queue complete and pause software interrupts available on both queues · Queue pointers indicate current location for each queue · Automated queue modes initiated by: - External edge trigger [queues 1 and 2] and gated mode [queue 1 only] - Periodic/interval timer, within QADC64 QADC64 module [queues 1 and 2] - Software command [queues 1 and 2] · Single-scan or continuous-scan of queues · 64 result registers · Output data readable in three formats: - Right-justified unsigned - Left-justified signed - Left-justified unsigned · Unused analog channels can be used as digital ports 5.3 QADC64 QADC64 Pin Functions The QADC64 QADC64 module uses the following 36 pins: · 2 analog reference pins, to which all analog input voltages are scaled · 16 analog input pins with 3 analog inputs multiplexed with multiplex address signals and 2 multiplexed with the on-chip analog multiplexer inputs · 16 analog input pins through the on-chip AMUX circuit · 2 analog power pins (VDDA, VSSA) · 2 trigger pins shared with AN[55:56]/PQA[3:4] The 16 channel/port pins can support up to 41 channels when external multiplexing is used (including internal channels). All of the channel pins can also be used as generalpurpose digital port pins. The following paragraphs describe QADC64 QADC64 pin functions. Figure 5-2 shows the QADC64 QADC64 module pins. MC68F375 MC68F375 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MODULE-64 REFERENCE MANUAL Rev. 15 Oct 00 MOTOROLA 5-2 ANX0 ANX2 ANX4 ANX6 ANX8 ANX10 ANX10 ANX12 ANX12 ANX14 ANX14 ANX1 ANX3 ANX5 ANX7 ANX9 ANX11 ANX11 ANX13 ANX13 ANX15 ANX15 CHARGE PUMP AMUX AMBSTOP AMCLK MUX0 AMADB[0] MUX1 DECODER AMADB[1] AMPMUX AMCHAN[1:0] PADS AMPDAT[10:8]] MUX2 AMADB[2] NC AMADB[3] NC ANALOG POWER ANALOG REFERENCES AQPDAT[10:8] AQBSTOP AQADCCLK AQADB[3:0] QADC64 QADC64 PORT B AN0/ANW/PQB0 AN1/ANX/PQB1 AN2/ANY/PQB2 AN3/ANZ/PQB3 AN48/PQB4 AN48/PQB4 AN49/PQB5 AN49/PQB5 AN50/PQB6 AN50/PQB6 AN51/PQB7 AN51/PQB7 AN52/MA0/PQA0 AN52/MA0/PQA0 AN53/MA1/PQA1 AN53/MA1/PQA1 AN54/MA2/PQA2 AN54/MA2/PQA2 AN55/ETRIG1/PQA3 AN55/ETRIG1/PQA3 AN56/ETRIG2/PQA4 AN56/ETRIG2/PQA4 AN57/PQA5 AN57/PQA5 AN58/PQA6 AN58/PQA6 AN59/PQA7 AN59/PQA7 AQPMUX VSSA VDDA VRH VRL VSSE AQCHAN[1:0] MUX3 ANALOG CONVERTER DIGITAL RESULTS AND CONTROL PORT A ANALOG MULTIPLEXER PADS EXTERNAL TRIGGERS * Not bonded out on this chip. Figure 5-2 QADC64 QADC64 Input and Output Signals MC68F375 MC68F375 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MODULE-64 REFERENCE MANUAL Rev. 15 Oct 00 MOTOROLA 5-3 5.3.1 Port A Pin Functions The eight port A pins can be used as analog inputs, or as a bidirectional 8-bit digital input/output port. 5.3.1.1 Port A Analog Input Pins When used as analog inputs, the eight port A pins are referred to as AN[59:52]. Due to the digital output drivers associated with port A, the analog characteristics of port A are different from those of port B. All of the analog signal input pins may be used for at least one other purpose. 5.3.1.2 Port A Digital Input/Output Pins Port A pins are referred to as PQA when used as a bidirectional 8-bit digital input/output port. These eight pins may be used for general-purpose digital input signals or digital output signals. Port A pins are connected to a digital input synchronizer during reads and may be used as general purpose digital inputs. Since port A read captures the data on all pins, including those used for digital outputs or analog inputs, the user should employ a "masking" operation to filter the inappropriate bits from the input byte. Each port A pin is configured as input or output by programming the port data direction register (DDRQA). Digital input signal states are read into the PORTQA data register when DDRQA specifies that the pins are inputs. Digital data in PORTQA is driven onto the port A pins when the corresponding bits in DDRQA specify outputs. 5.3.2 Port B Pin Functions The eight port B pins can be used as analog inputs, or as an 8-bit digital input only port. Refer to the following paragraphs for more information. 5.3.2.1 Port B Analog Input Pins When used as analog inputs, the eight port B pins are referred to as AN[51:48]/ AN[3:0]. Since port B functions as analog and digital input only, the analog characteristics are different from those of port A. All of the analog signal input pins may be used for at least one other purpose. 5.3.2.2 Port B Digital Input Pins Port B pins are referred to as PQB[7:0] when used as an 8-bit digital input only port. In addition to functioning as analog input pins, the port B pins are also connected to the input of a synchronizer during reads and may be used as general-purpose digital inputs. Since port B pins are input only, there is no associated data direction register. Digital input signal states are read from the PORTQB data register. Since a port B read captures the data on all pins, including those used for analog inputs, the user should employ a "masking" operation to filter the inappropriate bits from the input byte. MC68F375 MC68F375 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MODULE-64 REFERENCE MANUAL Rev. 15 Oct 00 MOTOROLA 5-4 5.3.3 External Trigger Input Pins The QADC64 QADC64 has two external trigger pins (ETRIG[2:1]). Each of the two external trigger pins is associated with one of the scan queues. When a queue is in external trigger mode, the corresponding external trigger pin is configured as a digital input. 5.3.4 Multiplexed Address Output Pins In non-multiplexed mode, the 16 channel pins are connected to an internal multiplexer which routes the analog signals into the A/D converter. In externally multiplexed mode, the QADC64 QADC64 allows automatic channel selection through up to four external 1-of-8 multiplexer chips. The QADC64 QADC64 provides a 3-bit multiplexed address output to the external multiplexer chips to allow selection of one of eight inputs. The multiplexed address output signals MA[2:0] can be used as multiplex address output bits or as general-purpose I/O. When externally multiplexed mode is enabled, MA[2:0] are used as the address inputs for up to four 1-of-8 multiplexer chips (for example, the MC14051 MC14051 and the MC74HC4051 MC74HC4051). Since MA[2:0] are digital outputs in multiplexed mode, the software programmed input/output direction and data for these pins in DDQA[2:0], DDRQA, and PQA[2:0] is ignored, and the value for MA[2:0] is taken from the currently executing CCW. 5.3.5 Multiplexed Analog Input Pins In externally multiplexed mode, four of the port B pins are redefined to each represent a group of eight input channels. Refer to Table 5-1. The analog output of each external multiplexer chip is connected to one of the AN[w, x, y, z] inputs in order to convert a channel selected by the MA[2:0] multiplexed address outputs. Table 5-1 Multiplexed Analog Input Channels Multiplexed Analog Input Channels ANw1 Even numbered channels from 0 to 14 ANx1 Odd numbered channels from 1 to 15 ANy2 Even numbered channels from 16 to 30 ANz2 Odd numbered channels from 17 to 31 NOTES: 1. If the on-chip multiplexer is enabled, ANw and ANx are used as inputs for the AMUX outputs. 2. If the on-chip AMUX is enabled, then AN2 and AN3 should be read as channels AN16 and AN17. 5.3.6 Voltage Reference Pins VRH and VRL are the dedicated input pins for the high and low reference voltages. Separating the reference inputs from the power supply pins allows for additional external MC68F375 MC68F375 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MODULE-64 REFERENCE MANUAL Rev. 15 Oct 00 MOTOROLA 5-5 filtering, which increases reference voltage precision and stability, and subsequently contributes to a higher degree of conversion accuracy. 5.3.7 Dedicated Analog Supply Pins VDDA and VSSA pins supply power to the analog subsystems of the QADC64 QADC64 module. Dedicated power is required to isolate the sensitive analog circuitry from the normal levels of noise present on the digital power supply. 5.3.8 External Digital Supply Pin Each port A pin includes a digital output driver, an analog input signal path, and a digital input synchronizer. The V SSE pin provides the ground level for the drivers on the port A pins. VDDH provides the supply level for the drivers on port A pins. 5.3.9 Digital Supply Pins VDD and VSS provide the power for the digital portions of the QADC64 QADC64, and for all other digital MCU modules. 5.4 QADC64 QADC64 Bus Interface The QADC64 QADC64 supports 8-bit, 16-bit, and 32-bit data transfers, at even and odd addresses. Coherency of results read, (ensuring that all results read were taken consecutively in one scan) is not guaranteed. For example, if two consecutive 16-bit locations in a result area are read, the QADC64 QADC64 could change one 16-bit location in the result area between bus cycles. There is no holding register for the second 16-bit location. All read and write accesses that require more than one 16-bit access to complete occur as two or more independent bus cycles. Depending on bus master protocol, these accesses could include misaligned and 32-bit accesses. Normal reads from and writes to the QADC64 QADC64 require two clock cycles. However, if the CPU tries to access locations that are also accessible to the QADC64 QADC64 while the QADC64 QADC64 is accessing them, the bus cycle will require additional clock cycles. The QADC64 QADC64 may insert from one-to-four wait states in the process of a CPU read from, or write to, such a location. 5.5 Module Configuration The QADC64 QADC64 module configuration register (QADC64MCR QADC64MCR) defines freeze and stop mode operation, supervisor space access, and interrupt arbitration priority. Unimplemented bits read zero and writes have no effect. QADC64MCR QADC64MCR is typically written once when software initializes the QADC64 QADC64, and not changed thereafter. Refer to 5.12.1 QADC64 QADC64 Module Configuration Register for register and bit descriptions. 5.5.1 Low-Power Stop Mode When the STOP bit in QADC64MCR QADC64MCR is set, the clock signal to the A/D converter is disabled, effectively turning off the analog circuitry. This results in a static, low power consumption, idle condition. Low-power stop mode aborts any conversion sequence in progress. Because the bias currents to the analog circuits are turned off in lowMC68F375 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MODULE-64 REFERENCE MANUAL Rev. 15 Oct 00 MOTOROLA 5-6 power stop mode, the QADC64 QADC64 requires some recovery time (tSR, see Table E-12 in APPENDIX E ELECTRICAL CHARACTERISTICS) to stabilize the analog circuits after the STOP bit is cleared. In low-power stop mode, the BIU state machine and logic do not shut down: the QADC64MCR QADC64MCR and the interrupt register (QADC64INT QADC64INT) are fully accessible and are not reset. The data direction register (DDRQA), port data register (PORTQA/PORTQB), and control register 0 (QACR0) are not reset and are read-only accessible. The RAM is not reset and is not accessible. Control register 1 (QACR1), control register 2 (QACR2), and the status registers (QASR0 and QASR1) are reset and are read-only accessible. In addition, the periodic/interval timer is held in reset during stop mode. If the STOP bit is clear, low-power stop mode is disabled. The STOP bit must be clear to program CCW's into RAM or read results from RAM. 5.5.2 Freeze Mode The QADC64 QADC64 enters freeze mode when background debug mode is enabled and a breakpoint is processed. This is indicated by assertion of the FREEZE line on the IMB3. The FRZ bit in QADC64MCR QADC64MCR determines whether or not the QADC64 QADC64 responds to an IMB FREEZE assertion. Freeze mode is useful when debugging an application. When the IMB FREEZE line is asserted and the FRZ bit is set, the QADC64 QADC64 finishes any conversion in progress and then freezes. Depending on when the FREEZE is asserted, there are three possible queue freeze scenarios: · When a queue is not executing, the QADC64 QADC64 freezes immediately. · When a queue is executing, the QADC64 QADC64 completes the current conversion and then freezes. · If during the execution of the current conversion, the queue operating mode for the active queue is changed, or a queue 2 abort occurs, the QADC64 QADC64 freezes immediately. When the QADC64 QADC64 enters the freeze mode while a queue is active, the current CCW location of the queue pointer is saved. During freeze, the analog clock, QCLK, is held in reset and the periodic/interval timer is held in reset. External trigger events that occur during the freeze mode are not captured. The BIU remains active to allow IMB access to all QADC64 QADC64 registers and RAM. Although the QADC64 QADC64 saves a pointer to the next CCW in the current queue, the software can force the QADC64 QADC64 to execute a different CCW by writing new queue operating modes for normal operation. The QADC64 QADC64 looks at the queue operating modes, the current queue pointer, and any pending trigger events to decide which CCW to execute. If the FRZ bit is clear, assertion of the IMB FREEZE line is ignored. 5.5.3 Supervisor/Unrestricted Address Space The QADC64 QADC64 memory map is divided into two segments: supervisor-only data space and assignable data space. Access to supervisor-only data space is permitted only MC68F375 MC68F375 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MODULE-64 REFERENCE MANUAL Rev. 15 Oct 00 MOTOROLA 5-7 when the CPU is operating in supervisor mode. Assignable data space can have either restricted to supervisor-only data space access or unrestricted supervisor and user data space accesses. The SUPV bit in QADC64MCR QADC64MCR designates the assignable space as supervisor or unrestricted. Attempts to read or write supervisor-only data space when the CPU is not in supervisor mode cause the bus master to assert the internal transfer error acknowledge (TEA) signal. The supervisor-only data space segment contains the QADC64 QADC64 global registers, which include QADC64MCR QADC64MCR and QADC64INT QADC64INT. The supervisor/unrestricted space designation for the CCW table, the result word table, and the remaining QADC64 QADC64 registers is programmable. 5.6 General-Purpose I/O Port Operation QADC64 QADC64 port pins, when used as general-purpose input, are conditioned by a synchronizer with an enable feature. The synchronizer is not enabled until the QADC64 QADC64 decodes an IMB bus cycle which addresses the port data register to minimize the highcurrent effect of mid-level signals on the inputs used for analog signals. Digital input signals must meet the input low voltage (VIL) or input high voltage (VIH) requirements, see Table E-3 in APPENDIX E ELECTRICAL CHARACTERISTICS. If an analog input pin does not meet the digital input pin specifications when a digital port read operation occurs, an indeterminate state is read. To avoid reading inappropriate values on analog inputs, the user software should employ a "masking" operation. During a port data register read, the actual value of the pin is reported when its corresponding bit in the data direction register defines the pin to be an input (port A only). When the data direction bit specifies the pin to be an output, the content of the port data register is read. By reading the latch which drives the output pin, software instructions (like bit manipulation instructions) that read data, modify it, and write the result work correctly. There is one special case to consider for digital I/O port operation. When the MUX (externally multiplexed) bit is set in QACR0, the data direction register settings are ignored for the bits corresponding to PQA[2:0] and the three multiplexed address MA[2:0] output pins. The MA[2:0] pins are forced to be digital outputs, regardless of the data direction setting, and the multiplexed address outputs are driven. The data returned during a port data register read is the value of the multiplexed address latches which drive MA[2:0], regardless of the data direction setting. 5.6.1 Port Data Register QADC64 QADC64 ports A and B are accessed through two 8-bit port data registers (PORTQA and PORTQB). Port A pins are referred to as PQA when used as an 8-bit input/output port. Port A can also be used for analog inputs AN[59:52] and external multiplexer address outputs MA[2:0]. MC68F375 MC68F375 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MODULE-64 REFERENCE MANUAL Rev. 15 Oct 00 MOTOROLA 5-8 Port B pins are referred to as PQB when used as an 8-bit input-only digital port. Port B can also be used for non-multiplexed AN[51:48]/AN[3:0] and multiplexed ANz, ANy, ANx, ANw analog inputs. PORTQA and PORTQB are unaffected by reset. Refer to 5.12.3 Port A/B Data Register for register and bit descriptions. 5.6.2 Port Data Direction Register The port data direction register (DDRQA) is associated with the port A digital I/O pins. These bidirectional pins may have somewhat higher leakage and capacitance specifications. Refer to APPENDIX E ELECTRICAL CHARACTERISTICS for more information. Any bit in this register set to one configures the corresponding pin as an output. Any bit in this register cleared to zero configures the corresponding pin as an input. Software is responsible for ensuring that DDRQA bits are not set to one on pins used for analog inputs. When a DDRQA bit is set to one and the pin is selected for analog conversion, the voltage sampled is that of the output digital driver as influenced by the load. NOTE Caution should be exercised when mixing digital and analog inputs. This should be minimized as much as possible. Input pin rise and fall times should be as large as possible to minimize AC coupling effects. Since port B is input-only, a data direction register is not needed. Read operations on the reserved bits in DDRQA return zeros, and writes have no effect. Refer to 5.12.4 Port Data Direction Register for register and bit descriptions. 5.7 External Multiplexing Operation External multiplexers concentrate a number of analog signals onto a few inputs to the analog converter. This is helpful in applications that need to convert more analog signals than the A/D converter can normally provide. External multiplexing also puts the multiplexer closer to the signal source. This minimizes the number of analog signals that need to be shielded due to the close proximity of noisy, high speed digital signals near the MCU. NOTE The main QADC64 QADC64 treats the AMX as an external multiplexer. It is recommended that full external multiplexing not be used on the MC68F375 MC68F375. Mixed internal and external multiplexing should be used. See 5.13.2 Mixed AMUX/External Multiplexing and Figure 5-13. The QADC64 QADC64 can use from one-to-four external multiplexers to expand the number of analog signals that may be converted. Up to 32 analog channels can be converted through external multiplexer selection. The externally multiplexed channels are auto- MC68F375 MC68F375 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MODULE-64 REFERENCE MANUAL Rev. 15 Oct 00 MOTOROLA 5-9 matically selected from the channel field of the conversion command word (CCW) table, the same as internally multiplexed channels. All of the automatic queue features are available for externally and internally multiplexed channels. The software selects externally multiplexed mode by setting the MUX bit in QACR0. Figure 5-3 shows the maximum configuration of four external multiplexers connected to the QADC64 QADC64. The external multiplexers select one of eight analog inputs and connect it to one analog output, which becomes an input to the QADC64 QADC64. The QADC64 QADC64 provides three multiplexed address signals (MA[2:0]), to select one of eight inputs. These outputs are connected to all four multiplexers. The analog output of each multiplexer is each connected to one of four separate QADC64 QADC64 inputs - ANw, ANx, ANy, and ANz. AN0 AN2 AN4 AN6 AN8 AN10 AN12 AN14 MUX AN1 AN3 AN5 AN7 AN9 AN11 AN13 AN15 MUX VSSA VDDA ANALOG POWER V RH VRL ANALOG REFERENCES VSSE V DDH AN17 AN19 AN21 AN23 AN25 AN27 AN29 AN31 PORT B MUX QADC64 QADC64 MUX ANALOG MULTIPLEXER ANALOG CONVERTER DIGITAL RESULTS AND CONTROL PORT A AN16 AN18 AN20 AN22 AN24 AN26 AN28 AN30 AN0/ANW/PQB0 AN1/ANX/PQB1 AN2/ANY/PQB2 AN3/ANZ/PQB3 AN48/PQB4 AN48/PQB4 AN49/PQB5 AN49/PQB5 AN50/PQB6 AN50/PQB6 AN51/PQB7 AN51/PQB7 AN52/MA0/PQA0 AN52/MA0/PQA0 AN53/MA1/PQA1 AN53/MA1/PQA1 AN54/MA2/PQA2 AN54/MA2/PQA2 AN55/ETRIG1/PQA3 AN55/ETRIG1/PQA3 AN55/ETRIG2/PQA4 AN55/ETRIG2/PQA4 AN57/PQA5 AN57/PQA5 AN58/PQA6 AN58/PQA6 AN59/PQA7 AN59/PQA7 ETRIG1 ETRIG2 EXTERNAL TRIGGERS Figure 5-3 Example of Full External Multiplexing When the external multiplexed mode is selected, the QADC64 QADC64 automatically creates the MA[2:0] output signals from the channel number in each CCW. The QADC64 QADC64 also converts the proper input channel (ANw, ANx, ANy, and ANz) by interpreting the CCW channel number. As a result, up to 32 externally multiplexed channels appear to the MC68F375 MC68F375 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MODULE-64 REFERENCE MANUAL Rev. 15 Oct 00 MOTOROLA 5-10 conversion queues as directly connected signals. Software simply puts the channel number of an externally multiplexed channel into a CCW. Figure 5-3 shows that MA[2:0] may also be analog or digital input pins. When external multiplexing is selected, none of the MA[2:0] pins can be used for analog or digital inputs. They become multiplexed address outputs. 5.8 Analog Input Channels The number of available analog channels varies, depending on whether or not external multiplexing is used. A maximum of 16 analog channels are supported by the internal multiplexing circuitry of the converter. Table 5-2 shows the total number of analog input channels supported with zero-to-four external multiplexers. Table 5-2 Analog Input Channels Number of Analog Input Channels Available Directly Connected + External Multiplexed = Total Channels1 No External Mux Chips One External Mux Chip Two External Mux Chips Three External Mux Chips Four External Mux Chips 16 12 + 8 = 20 11 + 16 = 27 10 + 24 = 34 9 + 32 = 41 NOTES: 1. When external multiplexing is used, three input channels become multiplexed address outputs, and for each external multiplexer chip, one input channel becomes a multiplexed analog input. 5.9 Analog Subsystem The QADC64 QADC64 analog subsystem includes a front-end analog multiplexer, a digital-toanalog converter (DAC) array, a comparator, and a successive approximation register (SAR). The analog subsystem path runs from the input pins through the input multiplexing circuitry, into the DAC array, and through the analog comparator. The output of the comparator feeds into the SAR. Figure 5-4 shows a block diagram of the QADC64 QADC64 analog submodule. MC68F375 MC68F375 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MODULE-64 REFERENCE MANUAL Rev. 15 Oct 00 MOTOROLA 5-11 PQA7 CCW CCW 10 BUF INPUT PQA0 PQB7 2 BIAS CIRCUIT SAMPLE BUFFER POWER DOWN STOP RST PQB0 QCLK CSAMP STATE MACHINE & LOGIC WCCW END OF CONV. END OF SMP SAR Timing VRH 10 BIT RC D-C SAR 10 VRL SIGNALS FROM/TO QUEUE CONTROL LOGIC CHAN.[5:0] IST 10-BIT 10-BIT A/D CONVERTER 6 BYP CHAN. DECODE & MUX 16: 1 10 SAR BUF 10 RSAR VDDA ANALOG POWER COMPARATOR VSSA SUCCESSIVE APPROXIMATION REGISTER QADC64 QADC64 DETAIL BLOCK Figure 5-4 QADC64 QADC64 Module Block Diagram 5.9.1 Conversion Cycle Times Total conversion time is made up of initial sample time, final sample time, and resolution time. Initial sample time refers to the time during which the selected input channel is driven by the buffer amplifier onto the sample capacitor. The buffer amplifier can be disabled by means of the BYP bit in the CCW. During the final sampling period, amplifier is bypassed, and the multiplexer input charges the RC DAC array directly. During the resolution period, the voltage in the RC DAC array is converted to a digital value and stored in the SAR. Initial sample time is fixed at two QCLK cycles. Final sample time can be 2, 4, 8, or 16 QCLK cycles, depending on the value of the IST field in the CCW. Resolution time is ten QCLK cycles. Sample and resolution require a minimum of 14 QCLK clocks (7 µs with a 2 MHz QCLK). If the maximum final sample time period of 16 QCLKs is selected, the total conversion time is 13.0 µs with a 2 MHz QCLK. Figure 5-5 illustrates the timing for conversions. This diagram assumes a final sampling period of two QCLK cycles. MC68F375 MC68F375 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MODULE-64 REFERENCE MANUAL Rev. 15 Oct 00 MOTOROLA 5-12 BUFFER FINAL SAMPLE TIME SAMPLE N CYCLES: TIME 2 CYCLES (2, 4, 8, 16) RESOLUTION TIME 10 CYCLES QCLK SAMPLE TIME SUCCESSIVE APPROXIMATION RESOLUTION SEQUENCE Figure 5-5 Conversion Timing 5.9.1.1 Amplifier Bypass Mode Conversion Timing If the amplifier bypass mode is enabled for a conversion by setting the amplifier bypass (BYP) bit in the CCW, the timing changes to that shown in Figure 5-6. The buffered sample time is eliminated, reducing the potential conversion time by two QCLKs. However, due to internal RC effects, a minimum final sample time of four QCLKs must be allowed. This results in no savings of QCLKs. When using the bypass mode, the external circuit should be of low source impedance, typically less than 10 k. Also, the loading effects of the external circuitry by the QADC64 QADC64 need to be considered, since the benefits of the sample amplifier are not present. NOTE Because of internal RC time constants, a sample time of 2 QCKLs in bypass mode for high frequency operation is not recommended. SAMPLE TIME N CYCLES: (2, 4, 8, 16) RESOLUTION TIME 10 CYCLES SAMPLE TIME SUCCESSIVE APPROXIMATION RESOLUTION SEQUENCE QCLK Figure 5-6 Bypass Mode Conversion Timing MC68F375 MC68F375 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MODULE-64 REFERENCE MANUAL Rev. 15 Oct 00 MOTOROLA 5-13 5.9.2 Front-End Analog Multiplexer The internal multiplexer selects one of the 16 analog input pins or one of three special internal reference channels for conversion. The following are the three special channels: · VRH - Reference voltage high · VRL - Reference voltage low · (VRH ­ VRL)/2 - Mid-reference voltage The selected input is connected to one side of the DAC capacitor array. The other side of the DAC array is connected to the comparator input. The multiplexer also includes positive and negative stress protection circuitry, which prevents other channels from affecting the present conversion when excessive voltage levels are applied to the other channels. Refer to APPENDIX E ELECTRICAL CHARACTERISTICS for specific voltage level limits. 5.9.3 Digital-to-Analog Converter Array The digital-to-analog converter (DAC) array consists of binary-weighted capacitors and a resistor-divider chain. The array serves two purposes: · The array holds the sampled input voltage during conversion. · The resistor-capacitor array provides the mechanism for the successive approximation A/D conversion. Resolution begins with the MSB and works down to the LSB. The switching sequence is controlled by the SAR logic. 5.9.4 Comparator The comparator is used during the approximation process to sense whether the digitally selected arrangement of the DAC array produces a voltage level higher or lower than the sampled input. The comparator output feeds into the SAR which accumulates the A/D conversion result sequentially, starting with the MSB. 5.9.5 Successive Approximation Register The input of the successive approximation register (SAR) is connected to the comparator output. The SAR sequentially receives the conversion value one bit at a time, starting with the MSB. After accumulating the ten bits of the conversion result, the SAR data is transferred by the queue control logic in the digital section to the appropriate result location, where it may be read by user software. 5.10 Digital Control Subsystem The digital control subsystem includes the clock and periodic/interval timer, control and status registers, the conversion command word table RAM, and the result word table RAM. The central element for control of QADC64 QADC64 conversions is the 64-entry conversion command word (CCW) table. Each CCW specifies the conversion of one input channel. Depending on the application, one or two queues can be established in the CCW MC68F375 MC68F375 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MODULE-64 REFERENCE MANUAL Rev. 15 Oct 00 MOTOROLA 5-14 table. A queue is a scan sequence of one or more input channels. By using a pause mechanism, subqueues can be created within the two queues. Each queue can be operated using several different scan modes. The scan modes for queue 1 and queue 2 are programmed in QACR1 and QACR2. Once a queue has been started by a trigger event (any of the ways to cause the QADC64 QADC64 to begin executing the CCWs in a queue or subqueue), the QADC64 QADC64 performs a sequence of conversions and places the results in the result word table. 5.10.1 Queue Priority Queue 1 has execution priority over queue 2 execution. Table 5-3 shows the conditions under which queue 1 asserts its priority: Table 5-3 Queue 1 Priority Assertion Queue State Result Inactive A trigger event for queue 1 or queue 2 causes the corresponding queue execution to begin. Queue 1 active/trigger event occurs for queue 2 Queue 2 cannot begin execution until queue 1 reaches completion or the paused state. The status register records the trigger event by reporting the queue 2 status as trigger pending. Additional trigger events for queue 2, which occur before execution can begin, are recorded as trigger overruns. Queue 2 active/trigger event occurs for queue 1 The current queue 2 conversion is aborted. The status register reports the queue 2 status as suspended. Any trigger events occurring for queue 2 while queue 2 is suspended are recorded as trigger overruns. Once queue 1 reaches the completion or the paused state, queue 2 begins executing again. The programming of the resume bit in QACR2 determines which CCW is executed in queue 2. Simultaneous trigger events Queue 1 begins execution and the queue 2 status is changed to trigger pending. occur for queue 1 and queue 2 Subqueues paused The pause feature can be used to divide queue 1 and/or queue 2 into multiple subqueues. A subqueue is defined by setting the pause bit in the last CCW of the subqueue. Figure 5-7 shows the CCW format and an example of using pause to create subqueues. Queue 1 is shown with four CCWs in each subqueue and queue 2 has two CCWs in each subqueue. MC68F375 MC68F375 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MODULE-64 REFERENCE MANUAL Rev. 15 Oct 00 MOTOROLA 5-15 CONVERSION COMMAND WORD (CCW) TABLE P 00 0 RESULT WORD TABLE 00 BEGIN QUEUE 1 0 CHANNEL SELECT, SAMPLE, HOLD, AND A/D CONVERSION 0 1 PAUSE 0 0 0 1 PAUSE 0 P 0 0 BQ2 0 END-OF-QUEUE 1 BEGIN QUEUE 2 1 PAUSE 0 1 PAUSE 0 1 PAUSE 0 P 1 63 0 PAUSE 63 END-OF-QUEUE 2 QADC64 QADC64 CQP Figure 5-7 QADC64 QADC64 Queue Operation with Pause The queue operating mode selected for queue 1 determines what type of trigger event causes the execution of each of the subqueues within queue 1. Similarly, the queue operating mode for queue 2 determines the type of trigger event required to execute each of the subqueues within queue 2. The choice of single-scan or continuous-scan applies to the full queue, and is not applied to each subqueue. Once a subqueue is initiated, each CCW is executed sequentially until the last CCW in the subqueue is executed and the pause state is entered. Execution can only continue with the next CCW, which is the beginning of the next subqueue. A subqueue cannot be executed a second time before the overall queue execution has been completed. Trigger events which occur during the execution of a subqueue are ignored, except that the trigger overrun flag is set. When continuous-scan mode is selected, a trigger event occurring after the completion of the last subqueue (after the queue completion flag is set), causes execution to continue with the first subqueue, starting with the first CCW in the queue. MC68F375 MC68F375 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MODULE-64 REFERENCE MANUAL Rev. 15 Oct 00 MOTOROLA 5-16 When the QADC64 QADC64 encounters a CCW with the pause bit set, the queue enters the paused state after completing the conversion specified in the CCW with the pause bit. The pause flag is set and a pause software interrupt may optionally be issued. The status of the queue is shown to be paused, indicating completion of a subqueue. The QADC64 QADC64 then waits for another trigger event to again begin execution of the next subqueue. 5.10.2 Queue Boundary Conditions The following are queue operation boundary conditions: · The first CCW in a queue contains channel 63, the end-of-queue (EOQ) code. The queue becomes active and the first CCW is read. The end-of-queue is recognized, the completion flag is set, and the queue becomes idle. A conversion is not performed. · BQ2 (beginning of queue 2) is set at the end of the CCW table (63) and a trigger event occurs on queue 2. 5.12.5 QADC64 QADC64 Control Register 0 (QACR0) on BQ2. The end-of-queue condition is recognized, a conversion is performed, the completion flag is set, and the queue becomes idle. · BQ2 is set to CCW0 and a trigger event occurs on queue 1. After reading CCW0, the end-of-queue condition is recognized, the completion flag is set, and the queue becomes idle. A conversion is not performed. · BQ2 (beginning of queue 2) is set beyond the end of the CCW table (64­127) and a trigger event occurs on queue 2. Refer to 5.12.7 QADC64 QADC64 Control Register 2 (QACR2) for information on BQ2. The end-of-queue condition is recognized immediately, the completion flag is set, and the queue becomes idle. A conversion is not performed. NOTE Multiple end-of-queue conditions may be recognized simultaneously, although there is no change in the QADC64 QADC64 behavior. For example, if BQ2 is set to CCW0, CCW0 contains the EOQ code, and a trigger event occurs on queue 1, the QADC64 QADC64 reads CCW0 and detects both end-of-queue conditions. The completion flag is set for queue 1 only and it becomes idle. Boundary conditions also exist for combinations of pause and end-of-queue. One case is when a pause bit is in one CCW and an end-of-queue condition is in the next CCW. The conversion specified by the CCW with the pause bit set completes normally. The pause flag is set. However, since the end-of-queue condition is recognized, the completion flag is also set and the queue status becomes idle, not paused. Examples of this situation include: · The pause bit is set in CCW5 and the channel 63 (EOQ) code is in CCW6. · The pause bit is set in CCW63 CCW63. · During queue 1 operation, the pause bit is set in CCW14 CCW14 and BQ2 points to CCW15 CCW15. MC68F375 MC68F375 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MODULE-64 REFERENCE MANUAL Rev. 15 Oct 00 MOTOROLA 5-17 Another pause and end-of-queue boundary condition occurs when the pause and an end-of-queue condition occur in the same CCW. Both the pause and end-of-queue conditions are recognized simultaneously. The end-of-queue condition has precedence so a conversion is not performed for the CCW and the pause flag is not set. The QADC64 QADC64 sets the completion flag and the queue status becomes idle. Examples of this situation are: · The pause bit is set in CCW0 and EOQ is programmed into CCW0. · During queue 1 operation, the pause bit is set in CCW20 CCW20, which is also BQ2. 5.10.3 Scan Modes The QADC64 QADC64 queuing mechanism provides several methods for automatically scanning input channels. In single-scan mode, a single pass through a sequence of conversions defined by a queue is performed. In continuous-scan mode, multiple passes through a sequence of conversions defined by a queue are executed. The possible modes are: · Disabled and reserved mode · Software initiated single-scan mode · External trigger single-scan mode · External gated single-scan mode (queue 1 only) · Interval timer single-scan mode · Software initiated continuous-scan mode · External trigger continuous-scan mode · External gated continuous-scan mode (queue 1 only) · Interval timer continuous-scan mode The following paragraphs describe the disabled/reserved, single-scan, and continuous-scan operations. 5.10.3.1 Disabled Mode When the disabled mode is selected, the queue is not active. Trigger events cannot initiate queue execution. When both queue 1 and queue 2 are disabled, wait states are not encountered for IMB accesses of the RAM. When both queues are disabled, it is safe to change the QCLK prescaler values. 5.10.3.2 Reserved Mode Reserved mode allows for future mode definitions. When the reserved mode is selected, the queue is not active. CAUTION Do not use a reserved mode. Unspecified operations may result. 5.10.3.3 Single-Scan Modes When the application software wants to execute a single pass through a sequence of conversions defined by a queue, a single-scan queue operating mode is selected. By programming the MQ field in QACR1 or QACR2, the following modes can be selected: MC68F375 MC68F375 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MODULE-64 REFERENCE MANUAL Rev. 15 Oct 00 MOTOROLA 5-18 · Software initiated single-scan mode · External trigger single-scan mode · External gated single-scan mode (queue 1 only) · Interval timer single-scan mode NOTE Queue 2 can not be programmed for external gated single-scan mode. In all single-scan queue operating modes, the software must also enable the queue to begin execution by writing the single-scan enable bit to a one in the queue's control register. The single-scan enable bits, SSE1 and SSE2, are provided for queue 1 and queue 2 respectively. Until the single-scan enable bit is set, any trigger events for that queue are ignored. The single-scan enable bit may be set to a one during the write cycle, which selects the single-scan queue operating mode. The single-scan enable bit can be written as a one or a zero, but is always read as a zero. The completion flag, completion interrupt, or queue status are used to determine when the queue has completed. After the single-scan enable bit is set, a trigger event causes the QADC64 QADC64 to begin execution with the first CCW in the queue. The single-scan enable bit remains set until the queue is completed. After the queue reaches completion, the QADC64 QADC64 resets the single-scan enable bit to zero. If the single-scan enable bit is written to a one or a zero by the software before the queue scan is complete, the queue is not affected. However, if the software changes the queue operating mode, the new queue operating mode and the value of the single-scan enable bit are recognized immediately. The conversion in progress is aborted and the new queue operating mode takes effect. In the software initiated single-scan mode, the writing of a 1 to the single-scan enable bit causes the QADC64 QADC64 to internally generate a trigger event and the queue execution begins immediately. In the other single-scan queue operating modes, once the singlescan enable bit is written, the selected trigger event must occur before the queue can start. The single-scan enable bit allows the entire queue to be scanned once. A trigger overrun is captured if a trigger event occurs during queue execution in the external trigger single-scan mode and the interval timer single-scan mode. In the interval timer single-scan mode, the next expiration of the timer is the trigger event for the queue. After the queue execution is complete, the queue status is shown as idle. The software can restart the queue by setting the single-scan enable bit to a 1. Queue execution begins with the first CCW in the queue. Software Initiated Single-Scan Mode. Software can initiate the execution of a scan sequence for queue 1 or 2 by selecting the software initiated single-scan mode, and writing the single-scan enable bit in QACR1 or QACR2. A trigger event is generated internally and the QADC64 QADC64 immediately begins execution of the first CCW in the queue. If a pause occurs, another trigger event is generated internally, and then execution continues without pausing. MC68F375 MC68F375 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MODULE-64 REFERENCE MANUAL Rev. 15 Oct 00 MOTOROLA 5-19 The QADC64 QADC64 automatically performs the conversions in the queue until an end-ofqueue condition is encountered. The queue remains idle until the software again sets the single-scan enable bit. While the time to internally generate and act on a trigger event is very short, software can momentarily read the status conditions, indicating that the queue is paused. The trigger overrun flag is never set while in the software initiated single-scan mode. The software initiated single-scan mode is useful in the following applications: · Allows software complete control of the queue execution. · Allows the software to easily alternate between several queue sequences. External Trigger Single-Scan Mode. The external trigger single-scan mode is a variation of the external trigger continuous-scan mode, and is also available with both queue 1 and queue 2. The software programs the polarity of the external trigger edge that is to be detected, either a rising or a falling edge. The software must enable the scan to occur by setting the single-scan enable bit for the queue. The first external trigger edge causes the queue to be executed one time. Each CCW is read and the indicated conversions are performed until an end-of-queue condition is encountered. After the queue is completed, the QADC64 QADC64 clears the single-scan enable bit. Software may set the single-scan enable bit again to allow another scan of the queue to be initiated by the next external trigger edge. The external trigger single-scan mode is useful when the input trigger rate can exceed the queue execution rate. Analog samples can be taken in sync with an external event, even though the software is not interested in data taken from every edge. The software can start the external trigger single-scan mode and get one set of data, and at a later time, start the queue again for the next set of samples. When a pause bit is encountered during external trigger single-scan mode, another trigger event is required for queue execution to continue. Software involvement is not needed to enable queue execution to continue from the paused state. The external trigger single-scan mode is also useful when the software needs to change the polarity of the external trigger so that both the rising and falling edges cause queue execution. External Gated Single-Scan Mode. The QADC64 QADC64 provides external gating for queue 1 only. When external gated single-scan mode is selected, a transition on the associated external trigger pin initiates queue execution. The polarity of the external gated signal is fixed so only a high level opens the gate and a low level closes the gate. Once the gate is open, each CCW is read and the indicated conversions are performed until the gate is closed. Software must enable the scan to occur by setting the single-scan enable bit for queue 1. If a pause in a CCW is encountered, the pause flag will not set, and execution continues without pausing. While the gate is open, queue 1 executes one time. Each CCW is read and the indicated conversions are performed until an end-of-queue condition is encountered. When queue 1 completes, the QADC64 QADC64 sets the completion flag (CF1) and clears the MC68F375 MC68F375 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MODULE-64 REFERENCE MANUAL Rev. 15 Oct 00 MOTOROLA 5-20 single-scan enable bit. Software may set the single-scan enable bit again to allow another scan of queue 1 to be initiated during the next open gate. If the gate closes before queue 1 completes execution, the current CCW completes, execution of queue 1 stops, the single-scan enable bit is cleared, and the PF1 bit is set. Software can read the CWPQ1 to determine the last valid conversion in the queue. Software must set the single-scan enable bit again and should clear the PF1 bit before another scan of queue 1 is initiated during the next open gate. The start of queue 1 is always the first CCW in the CCW table. Interval Timer Single-Scan Mode. Both queues can use the periodic/interval timer in a single-scan queue operating mode. The timer interval can range from 128 to 128K QCLK cycles in binary multiples. When the interval timer single-scan mode is selected and the software sets the single-scan enable bit in QACR1(2), the timer begins counting. When the time interval elapses, an internal trigger event is created to start the queue and the QADC64 QADC64 begins execution with the first CCW. The QADC64 QADC64 automatically performs the conversions in the queue until a pause or an end-of-queue condition is encountered. When a pause occurs, queue execution stops until the timer interval elapses again, and queue execution continues. When the queue execution reaches an end-of-queue situation the single-scan enable bit is cleared. Software may set the single-scan enable bit again, allowing another scan of the queue to be initiated by the interval timer. The interval timer generates a trigger event whenever the time interval elapses. The trigger event may cause the queue execution to continue following a pause, or may be considered a trigger overrun. Once the queue execution is completed, the single-scan enable bit must be set again to enable the timer to count again. Normally, only one queue will be enabled for interval timer single-scan mode and the timer will reset at the end-of-queue. However, if both queues are enabled for either single-scan or continuous interval timer mode, the end-of-queue condition will not reset the timer while the other queue is active. In this case, the timer will reset when both queues have reached end-of-queue. The interval timer single-scan mode can be used in applications which need coherent results, for example: · When it is necessary that all samples are guaranteed to be taken during the same scan of the analog pins. · When the interrupt rate in the periodic timer continuous-scan mode would be too high. · In sensitive battery applications, where the single-scan mode uses less power than the software initiated continuous-scan mode. 5.10.3.4 Continuous-Scan Modes When the application software wants to execute multiple passes through a sequence of conversions defined by a queue, a continuous-scan queue operating mode is MC68F375 MC68F375 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MODULE-64 REFERENCE MANUAL Rev. 15 Oct 00 MOTOROLA 5-21 selected. By programming the MQ1(2) field in QACR1(2), the following software initiated modes can be selected: · Software initiated continuous-scan mode · External trigger continuous-scan mode · External gated continuous-scan mode (queue 1 only) · Interval timer continuous-scan mode When a queue is programmed for a continuous-scan mode, the single-scan enable bit in the queue control register does not have any meaning or effect. As soon as the queue operating mode is programmed, the selected trigger event can initiate queue execution. In the case of the software initiated continuous-scan mode, the trigger event is generated internally and queue execution begins immediately. In the other continuous-scan queue operating modes, the selected trigger event must occur before the queue can start. A trigger overrun is captured if a trigger event occurs during queue execution in the external trigger continuous-scan mode and the periodic timer continuous-scan mode. After the queue execution is complete, the queue status is shown as idle. Since the continuous-scan queue operating modes allow the entire queue to be scanned multiple times, software involvement is not needed to enable queue execution to continue from the idle state. The next trigger event causes queue execution to begin again, starting with the first CCW in the queue. NOTE In this version of QADC64 QADC64, coherent samples can be guaranteed. The time between consecutive conversions has been designed to be consistent, provided the sample time bits in both the CCW and IST are identical. However, there is one exception. For queues that end with a CCW containing EOQ code (channel 63), the last queue conversion to the first queue conversion requires 1 additional CCW fetch cycle. Therefore continuous samples are not coherent at this boundary. In addition, the time from trigger to first conversion can not be guaranteed since it is a function of clock synchronization, programmable trigger events, queue priorities, and other factors. Software Initiated Continuous-Scan Mode. When the software initiated continuousscan mode is programmed, the trigger event is generated automatically by the QADC64 QADC64. Queue execution begins immediately. If a pause is encountered, another trigger event is generated internally, and then execution continues without pausing. When the end-of-queue is reached, another internal trigger event is generated, and queue execution begins again from the beginning of the queue. While the time to internally generate and act on a trigger event is very short, software can momentarily read the status conditions, indicating that the queue is idle. The trigger overrun flag is never set while in the software initiated continuous-scan mode. MC68F375 MC68F375 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MODULE-64 REFERENCE MANUAL Rev. 15 Oct 00 MOTOROLA 5-22 The software initiated continuous-scan mode keeps the result registers updated more frequently than any of the other queue operating modes. The software can always read the result table to get the latest converted value for each channel. The channels scanned are kept up to date by the QADC64 QADC64 without software involvement. Software can read a result value at any time. The software initiated continuous-scan mode may be chosen for either queue, but is normally used only with queue 2. When the software initiated continuous-scan mode is chosen for queue 1, that queue operates continuously and queue 2, being lower in priority, never gets executed. The short interval of time between a queue 1 completion and the subsequent trigger event is not sufficient to allow queue 2 execution to begin. The software initiated continuous-scan mode is a useful choice with queue 2 for converting channels that do not need to be synchronized to anything, or for the slow-tochange analog channels. Interrupts are normally not used with the software initiated continuous-scan mode. Rather, the software reads the latest conversion result from the result table at any time. Once initiated, software action is not needed to sustain conversions of channel. Data read at different locations, however, may or may not be coherent (that is, from the same queue scan sequence). External Trigger Continuous-Scan Mode. The QADC64 QADC64 provides external trigger pins for both queues. When the external trigger software initiated continuous-scan mode is selected, a transition on the associated external trigger pin initiates queue execution. The polarity of the external trigger signal is programmable, so that the software can choose to begin queue execution on the rising or falling edge. Each CCW is read and the indicated conversions are performed until an end-of-queue condition is encountered. When the next external trigger edge is detected, the queue execution begins again automatically. Software initialization is not needed between trigger events. When a pause bit is encountered in external trigger continuous-scan mode, another trigger event is required for queue execution to continue. Software involvement is not needed to enable queue execution to continue from the paused state. Some applications need to synchronize the sampling of analog channels to external events. There are cases when it is not possible to use software initiation of the queue scan sequence, since interrupt response times vary. External Gated Continuous-Scan Mode . The QADC64 QADC64 provides external gating for queue 1 only. When external gated continuous-scan mode is selected, a transition on the associated external trigger pin initiates queue execution. The polarity of the external gated signal is fixed so a high level opens the gate and a low level closes the gate. Once the gate is open, each CCW is read and the indicated conversions are performed until the gate is closed. When the gate opens again, the queue execution automatically begins again from the beginning of the queue. Software initialization is not needed between trigger events. If a pause in a CCW is encountered, the pause flag will not set, and execution continues without pausing. MC68F375 MC68F375 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MODULE-64 REFERENCE MANUAL Rev. 15 Oct 00 MOTOROLA 5-23 The purpose of external gated continuous-scan mode is to continuously collect digitized samples while the gate is open and to have the most recent samples available. To ensure consistent sample times in waveform digitizing, for example, the programmer must ensure that all CCW's have identical sample time settings in IST. It is up to the programmer to ensure that the queue is large enough so that a maximum gate open time will not reach an end-of-queue. However it is useful to take advantage of a smaller queue in the manner described below. In the event that the queue completes before the gate closes, a completion flag will be set and the queue will roll over to the beginning and continue conversions until the gate closes. If the gate remains open and the queue completes a second time, the trigger overrun flag will be set and the queue will roll over again. The queue will continue to execute until the gate closes or the mode is disabled. If the gate closes before queue 1 completes execution, the current CCW completes and execution of queue 1 stops and QADC64 QADC64 sets the PF1 bit to indicate an incomplete queue. Software can read the CWPQ1 to determine the last valid conversion in the queue. In this mode, if the gate opens again, execution of queue 1 begins again. The start of queue 1 is always the first CCW in the CCW table. Interval Timer Continuous-Scan Mode. The QADC64 QADC64 includes a dedicated periodic/ interval timer for initiating a scan sequence on queue 1 and/or queue 2. Software selects a programmable timer interval ranging from 128 to 128K times the QCLK period in binary multiples. The QCLK period is prescaled down from the intermodule bus (IMB) MCU clock. When a periodic timer continuous-scan mode is selected for queue 1 and/or queue 2, the timer begins counting. After the programmed interval elapses, the timer generated trigger event starts the appropriate queue. Meanwhile, the QADC64 QADC64 automatically performs the conversions in the queue until an end-of-queue condition or a pause is encountered. When a pause occurs, the QADC64 QADC64 waits for the periodic interval to expire again, then continues with the queue. Once end-of-queue has been detected, the next trigger event causes queue execution to begin again with the first CCW in the queue. The periodic timer generates a trigger event whenever the time interval elapses. The trigger event may cause the queue execution to continue following a pause or queue completion, or may be considered a trigger overrun. As with all continuous-scan queue operating modes, software action is not needed between trigger events. Software enables the completion interrupt when using the periodic timer continuousscan mode. When the interrupt occurs, the software knows that the periodically collected analog results have just been taken. The software can use the periodic interrupt to obtain non-analog inputs as well, such as contact closures, as part of a periodic look at all inputs. MC68F375 MC68F375 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MODULE-64 REFERENCE MANUAL Rev. 15 Oct 00 MOTOROLA 5-24 5.10.4 QADC64 QADC64 Clock (QCLK) Generation Figure 5-8 is a block diagram of the clock subsystem. The QCLK provides the timing for the A/D converter state machine, which controls the timing of the conversion. The QCLK is also the input to a 17-stage binary divider which implements the periodic/ interval timer. To retain the specified analog conversion accuracy, the QCLK frequency (FQCLK) must be within the tolerance specified in APPENDIX E ELECTRICAL CHARACTERISTICS. Before using the QADC64 QADC64, the software must initialize the prescaler with values that put the QCLK within the specified range. Though most software applications initialize the prescaler once and do not change it, write operations to the prescaler fields are permitted. NOTE For software compatibility with earlier versions of QADC64 QADC64, the definition of PSL, PSH, and PSA have been maintained. However, the requirements on minimum time and minimum low time no longer exist. CAUTION A change in the prescaler value while a conversion is in progress is likely to corrupt the result from any conversion in progress. Therefore, any prescaler write operation should be done only when both queues are in the disabled modes. MC68F375 MC68F375 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MODULE-64 REFERENCE MANUAL Rev. 15 Oct 00 MOTOROLA 5-25 RESET QCLK ZERO DETECT 5 SYSTEM CLOCK (FSYS) 5-BIT DOWN COUNTER LOAD PSH CLOCK GENERATE 5 PRESCALER RATE SELECTION (FROM CONTROL REGISTER 0): HIGH TIME CYCLES (PSH) QCLK 3 SET QCLK ONE'S COMPLEMENT COMPARE LOW TIME CYCLES (PSL) 3 ADD HALF CYCLE TO HIGH (PSA) QADC64 QADC64 CLOCK ( Fsys / ÷2 TO Fsys/÷40 ) INPUT SAMPLE TIME (FROM CCW) 2 A/D CONVERTER STATE MACHINE SAR CONTROL SAR 10 BINARY COUNTER 2 7 28 2 9 210 211 212 213 214 215 216 217 Queue 1 & 2 TIMER MODE RATE SELECTION 8 PERIODIC/INTERVAL TIMER SELECT 2 PERIODIC/INTERVAL TRIGGER EVENT FOR Q1 AND Q2 Figure 5-8 QADC64 QADC64 Clock Subsystem Functions To accommodate wide variations of the main MCU clock frequency (IMB system clock ­ FSYS), QCLK is generated by a programmable prescaler which divides the MCU system clock to a frequency within the specified QCLK tolerance range. To allow the A/D conversion time to be maximized across the spectrum of system clock frequencies, the QADC64 QADC64 prescaler permits the frequency of QCLK to be software selectable. It also allows the duty cycle of the QCLK waveform to be programmable. The software establishes the basic high phase of the QCLK waveform with the PSH (prescaler clock high time) field in QACR0, and selects the basic low phase of QCLK with the PSL (prescaler clock low time) field. The combination of the PSH and PSL parameters establishes the frequency of the QCLK. MC68F375 MC68F375 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MODULE-64 REFERENCE MANUAL Rev. 15 Oct 00 MOTOROLA 5-26 NOTE The guideline for selecting PSH and PSL is select is to maintain approximately 50% duty cycle. So for prescaler values less then 16, or PSH PSL. For prescaler values greater than 16 keep PSL as large as possible. Figure 5-8 shows that the prescaler is essentially a variable pulse width signal generator. A 5-bit down counter, clocked at the system clock rate, is used to create both the high phase and the low phase of the QCLK signal. At the beginning of the high phase, the 5-bit counter is loaded with the 5-bit PSH value. When the zero detector finds that the high phase is finished, the QCLK is reset. A 3-bit comparator looks for a one's complement match with the 3-bit PSL value, which is the end of the low phase of the QCLK. The PSA bit was maintained for software compatibility, but has no effect on QADC64 QADC64. The following equations define Qclk frequency: High QCLK Time = (PSH + 1) ÷ FSYS Low QCLK Time = (PSL + 1) ÷ F SYS FQCLK = 1 ÷ (High QCLK Time + Low QCLK Time) Where: · PSH = 0 to 31, the prescaler QCLK high cycles in QACR0 · PSL = 0 to 7, the prescaler QCLK low cycles in QACR0 · FSYS = System clock frequency · FQCLK = QCLK frequency The following are equations for calculating the QCLK high and low phases in example 1 shown in Figure 5-9: High QCLK Time = (11 + 1) ÷ 40 x10 6 = 300 ns Low QCLK Time = (7 + 1) ÷ 40 x106 = 200 ns FQCLK = 1/(300 + 200) = 2 Mhz The following are equations for calculating the QCLK high and low phases in example 2 shown in Figure 5-9: High QCLK Time = (7 + 1) ÷ 32 x 106 = 250 ns Low QCLK Time = (7 + 1) ÷ 32 x 106 = 250 ns FQCLK = 1/(250 + 250) = 2 Mhz MC68F375 MC68F375 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MODULE-64 REFERENCE MANUAL Rev. 15 Oct 00 MOTOROLA 5-27 Figure 5-9 and Table 5-4 show examples of QCLK programmability. The examples include conversion times based on the following assumption: · Input sample time is as fast as possible (IST = 0, 2 QCLK cycles). Figure 5-9 and Table 5-4 also show the conversion time calculated for a single conversion in a queue. For other MCU system clock frequencies and other input sample times, the same calculations can be made. SYSTEM CLOCK FSYS QCLK EXAMPLES 1. 40 MHz 2. 32 MHz 20 CYCLES QADC64 QADC64 QCLK EX Figure 5-9 QADC64 QADC64 Clock Programmability Examples Table 5-4 QADC64 QADC64 Clock Programmability Control Register 0 Information Input Sample Time (IST) = 0b00 Example Number Frequency PSH PSA PSL QCLK (MHz) Conversion Time (µs) 1 40 Mhz 11 0 7 2.0 7.0 2 32 Mhz 7 0 7 2.0 7.0 NOTE PSA is maintained for software compatibility but has no functional benefit to this version of the module. The MCU system clock frequency is the basis of the QADC64 QADC64 timing. The QADC64 QADC64 requires that the system clock frequency be at least twice the QCLK frequency. The QCLK frequency is established by the combination of the PSH and PSL parameters in QACR0. The 5-bit PSH field selects the number of system clock cycles in the high phase of the QCLK wave. The 3-bit PSL field selects the number of system clock cycles in the low phase of the QCLK wave. Example 1 in Figure 5-9 shows that when PSH = 11, the QCLK remains high for twelve cycles of the system clock. It also shows that when PSL = 7, the QCLK remains low for eight system clock cycles. In example 2, PSH = 7, the QCLK remains high for eight cycles of the system clock. It also shows that when PSL = 7, the QCLK remains low for eight system clock cycles. MC68F375 MC68F375 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MODULE-64 REFERENCE MANUAL Rev. 15 Oct 00 MOTOROLA 5-28 5.10.5 Periodic/Interval Timer The on-chip periodic/interval timer is enabled to generate trigger events at a programmable interval, initiating execution of queue 1 and/or 2. The periodic/interval timer stays reset under the following conditions: · Queue 1 and queue 2 are programmed to any queue operating mode which does not use the periodic/interval timer · Interval timer single-scan mode is selected, but the single-scan enable bit is set to zero · IMB system reset or the master reset is asserted · Stop mode is selected · Freeze mode is selected Two other conditions which cause a pulsed reset of the timer are: · Roll over of the timer counter · A queue operating mode change from one periodic/interval timer mode to another periodic/interval timer mode, depending on which queues are active in timer mode. NOTE The periodic/interval timer will not reset for a queue 2 operating mode change from one periodic/interval timer mode to another periodic/ interval timer mode while queue 1 is in an active periodic/interval timer mode. During the low power stop mode, the periodic/interval timer is held in reset. Since low power stop mode causes QACR1 and QACR2 to be reset to zero, a valid periodic or interval timer mode must be written after stop mode is exited to release the timer from reset. When the IMB internal FREEZE line is asserted and a periodic or interval timer mode is selected, the timer counter is reset after the conversion in progress completes. When the periodic or interval timer mode has been enabled (the timer is counting), but a trigger event has not been issued, the freeze mode takes effect immediately, and the timer is held in reset. When the internal FREEZE line is negated, the timer counter starts counting from the beginning. 5.11 Interrupts Interrupt recognition and servicing involve interaction between the integration module, the CPU, and the module requesting interrupt service. This section provides an overview of the QADC interrupt process. Polled operation, an alternative to using interrupts, is discussed along with the different aspects of interrupt operation. An interrupt is a special form of exception processing. Interrupt requests can be generated on-chip, or can come from external sources. However, the CPU services all interrupt requests as though originated by an on-chip module; to the CPU, an external interrupt request appears to come from the integration module. There are schemes to prioritize all interrupt requests and to arbitrate between simultaneous requests of the MC68F375 MC68F375 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MODULE-64 REFERENCE MANUAL Rev. 15 Oct 00 MOTOROLA 5-29 same priority. The QADC is configured to support interrupt acknowledge (IACK) cycles and vector generation. 5.11.1 Interrupt Operation Figure 5-10 displays the QADC64 QADC64 interrupt flow. INTERRUPT CONTROL PIE1 CONVERSION PAUSE ENABLE PF1 CONVERSION PAUSE FLAG CIE1 CONVERSION COMPLETE INTERRUPT ENABLE CF1 CONVERSION COMPLETE FLAG QUEUE 1 (IRL1) INTERRUPT GENERATOR PIE2 PF2 CONVERSION PAUSE FLAG CIE2 CONVERSION COMPLETE INTERRUPT ENABLE CF2 IRQ[7:0] CONVERSION PAUSE ENABLE CONVERSION COMPLETE FLAG QUEUE 2 (IRL2) Figure 5-10 QADC64 QADC64 Interrupt Flow Diagram 5.11.1.1 Polled and Interrupt-Driven Operation QADC inputs can be monitored by polling or by using interrupts. When interrupts are not needed, software can disable the pause and completion interrupts and monitor the completion flag and the pause flag for each queue in the status register (QASR). In other words, flag bits can be polled to determine when new results are available. Table 5-5 displays the status flag and interrupt enable bits which correspond to queue 1 and queue 2 activity. If interrupts are enabled for an event, the QADC requests interrupt service when the event occurs. Using interrupts does not require continuously polling the status flags to see if an event has taken place. However, status flags must be cleared after an interrupt is serviced, in order to disable the interrupt request. In both polled and interrupt-driven operating modes, status flags must be re-enabled after an event occurs. Flags are re-enabled by clearing appropriate QASR bits in a particular sequence. The register must first be read, then zeros must be written to the flags that are to be cleared. If a new event occurs betwe en the time that the register is read and the time that it is written, the associate d flag is not cleared. 5.11.2 Interrupt Sources The QADC includes four sources of interrupt service requests, each of which is separately enabled. Each time the result is written for the last conversion command word (CCW) in a queue, the completion flag for the corresponding queue is set, and when MC68F375 MC68F375 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MODULE-64 REFERENCE MANUAL Rev. 15 Oct 00 MOTOROLA 5-30 enabled, an interrupt request is generated. In the same way, each time the result is written for a CCW with the pause bit set, the queue pause flag is set, and when enabled, an interrupt request is generated. Table 5-5 displays the status flag and interrupt enable bits which correspond to queue 1 and queue 2 activity. The pause and complete interrupts for queue 1 and queue 2 have separate interrupt vector levels, so that each source can be separately serviced. Table 5-5 QADC64 QADC64 Status Flags and Interrupt Sources Queue Interrupt Enable Bit CF1 CIE1 Result written for a CCW with pause bit set in queue 1 PF1 PIE1 Result written for the last CCW in queue 2 Queue 2 Status Flag Result written for the last CCW in queue 1 Queue 1 Queue Activity CF2 CIE2 Result written for a CCW with pause bit set in queue 2 PF2 PIE2 5.11.3 Interrupt Priority Interrupt priority is determined with a three-bit interrupt priority mask that is located in the bus master condition code register or status register. The interrupt priority mask can have eight possible values, from 0b000 to 0b111. There are seven levels of interrupt priority, one to seven, each corresponding to a particular interrupt request signal. The bus master compares the priority of each interrupt service request to the mask value. Interrupt request levels greater than the mask value are accepted; interrupt request levels less than or equal to the mask value are ignored, except for the nonmaskable level seven interrupt request, which is serviced even if the bus master interrupt mask value is seven. The values contained in the IRL1 and IRL2 fields in the interrupt register (QADC64INT QADC64INT) determine the priority of QADC interrupt service requests. A value of 0b000 in either field disables the interrupts associated with that field. IRL1 determines the priority of both queue 1 interrupt sources. IRL2 determines the priority of both queue 2 interrupt sources. As a result, queue 1 and queue 2 can have different priorities in the overall interrupt hierarchy of the MCU. The QADC also has an internal interrupt request prioritization. Queue1 interrupt requests are higher in priority than queue 2 requests, and completion flag requests ar e higher in priority than pause requests. 5.11.4 Interrupt Arbitration After queue 1 or queue 2 issues an interrupt service request, the bus master performs an interrupt acknowledge cycle. During the interrupt acknowledge cycle, the bus master identifies the interrupt request level being acknowledged by placing it on the address bus. The QADC compares the acknowledged interrupt level with IRL1 and IRL2 values, and responds if the values match. MC68F375 MC68F375 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MODULE-64 REFERENCE MANUAL Rev. 15 Oct 00 MOTOROLA 5-31 The same interrupt priority level can be assigned to more than one module. For example, the QADC and the queued serial module (QSM) can both be assigned priority five. If the QADC and the QSM request interrupt service simultaneously, then the interrupt arbitration (IARB) fields in the respective module configuration registers are used to determine which module is serviced first. The IARB field is essentially a second-level priority in case of a tie. Each module that can request interrupt service has an IARB field. Arbitration is per formed by means of serial contention of IARB field bit values. Arbitration always takes place, even when a single source requests service. IARB fields contain four bits. An IARB value of 0b1111 has the highest arbitration priority, and 0b0001 has the lowest. If a module with an IARB field value of 0b0000 requests interrupt service, the bus master processes a spurious interrupt exception because the module requesting the interrupt service cannot confirm that it made the request. Initialization software must assign each IARB field a unique non-zero value in order to implement the arbitration scheme. If two or more modules are assigned the same non-zero IARB field value, operation is undefined when interrupts of the same priority level are recognized. 5.11.5 Interrupt Vectors When the QADC is the only module with an interrupt request pending at the level being acknowledged, or when the QADC IARB value is higher than that of other modules with requests pending at the acknowledged level, the QADC responds to the interrupt acknowledge cycle with an 8-bit interrupt vector number. The CPU uses the vector number to calculate a displacement into the exception vector table, then uses the vector at that location to jump to an interrupt service routine. The interrupt vector base (IVB) field establishes the six high-order bits of the 8-bit interrupt vector number, and the QADC provides two low-order bits which correspond to one of the four internal QADC interrupt sources. Figure 5-11 shows the format of the interrupt vector, and lists the binary coding of the two low-order bits for the four QADC interrupt sources. MC68F375 MC68F375 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MODULE-64 REFERENCE MANUAL Rev. 15 Oct 00 MOTOROLA 5-32 Interrupt Register Provided by Software Vector Bits Provided by QADC64 QADC64 7 6 5 4 3 2 1 0 IVB7 IVB6 IVB5 IVB4 IVB3 IVB2 IVB1 IVB0 1 1 - Queue 1 completion software interrupt 1 0 - Queue 1 pause software interrupt 0 1 - Queue 2 completion software interrupt 0 0 - Queue 2 pause software interrupt 7 6 5 IVB7 IVB6 IVB5 4 IVB4 3 2 1 0 IVB3 IVB2 IVB1 IVB0 Software interrupt vector provided to CPU during software interrupt arbitration (from QADC64 QADC64 module) QADC SWI VECT Figure 5-11 QADC64 QADC64 Interrupt Vector Format 5.12 Programming Model Each QADC64 QADC64 occupies 1 Kbyte (512 16-bit entries) of address space. The address space consists of ten 16-bit control, status, and port registers; 64 16-bit entries in the CCW table; and 64 16-bit entries in the result table. The result table occupies 192 16bit address locations because the result data is readable in three data alignment formats. Table 5-6 shows the QADC64 QADC64 memory map. The lowercase "x" appended to each register name represents "A" or "B" for the QADC64 QADC64_A or QADC64 QADC64_B module, respectively. The address is the base address of the module. Refer to APPENDIX A INTERNAL MEMORY MAP to locate each QADC64 QADC64 module in the MC68F375 MC68F375 memory map. MC68F375 MC68F375 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MODULE-64 REFERENCE MANUAL Rev. 15 Oct 00 MOTOROLA 5-33 Table 5-6 QADC64 QADC64 Address Map Access Address MSB LSB S1 0xYF F400 QADC64 QADC64 Module Configuration Register (QADC64MCR QADC64MCR) See Table 5-7 for bit descriptions. T2 0xYF F402 QADC64 QADC64 Test Register (QADC64TEST QADC64TEST) S 0xYF F404 Interrupt Register (QADC64INT QADC64INT) See Table 5-8 for bit descriptions. S/U3 0xYF F406 Port A Data (PORTQA) See Table 5-10 for bit Port B Data (PORTQB) descriptions. S/U 0xYF F408 Port A Data Direction Register (DDRQA) See Table 5-10 for bit descriptions. S/U 0xYF F40A QADC64 QADC64 Control Register 0 (QACR0) See Table 5-11 for bit descriptions. S/U 0xYF F40C QADC64 QADC64 Control Register 1 (QACR1) See Table 5-12 for bit descriptions. S/U 0xYF F40E QADC64 QADC64 Control Register 2 (QACR2) See Table 5-14 for bit descriptions. S/U 0xYF F410 QADC64 QADC64 Status Register 0 (QASR0) See Table 5-16 for bit descriptions. S/U 0xYF F412 QADC64 QADC64 Status Register 1 (QASR1) See Table 5-16 for bit descriptions. - 0xYF F414 ­ 0xYF F5FE Reserved 0xYF F600 - 0xYF F67F Conversion Command Word (CCW) Table See Table 5-19 for bit descriptions. 0xYF F680 ­ 0xYF F6FE Result Word Table Right-Justified, Unsigned Result Register (RJURR) See 5.12.11 Result Word Table for bit descriptions. 0xYF F700 ­ 0xYF F77E Result Word Table Left-Justified, Signed Result Register (LJSRR) See 5.12.11 Result Word Table for bit descriptions. 0xYF F780 ­ 0xYF F7FE Result Word Table Left-Justified, Unsigned Result Register (LJURR) See 5.12.11 Result Word Table for bit descriptions. S/U S/U S/U S/U NOTES: 1. S = Supervisor only 2. Access is restricted to supervisor only and factory test mode only. 3. S/U = Unrestricted or supervisor depending on the state of the SUPV bit in the QADC64MCR QADC64MCR. The QADC64 QADC64 has two global registers for configuring module operation: the module configuration register (QADC64MCR QADC64MCR) and the interrupt register (QADC64INT QADC64INT). The global registers are always defined to be in supervisor data space. The CPU allows software to establish the global registers in supervisor data space and the remaining registers and tables in user space. MC68F375 MC68F375 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MODULE-64 REFERENCE MANUAL Rev. 15 Oct 00 MOTOROLA 5-34 All QADC64 QADC64 analog channel/port pins that are not used for analog input channels can be used as digital port pins. Port values are read/written by accessing the port A and B data registers (PORTQA and PORTQB). Port A pins are specified as inputs or outputs by programming the port data direction register (DDRQA). Port B is an input only port. 5.12.1 QADC64 QADC64 Module Configuration Register QADC64MCR QADC64MCR - QADC64 QADC64 Module Configuration Register MSB 15 14 STOP FRZ 13 12 11 10 9 8 RESERVED 7 6 SUPV 0xYF F400 5 4 3 1 RESERVED LSB 0 0 2 0 IARB RESET: 0 0 0 0 0 0 0 0 1 0 0 0 0 0 Table 5-7 QADC64MCR QADC64MCR Bit Settings Bit(s) Name Description STOP Low-power stop mode enable. When the STOP bit is set, the clock signal to the QADC64 QADC64 is disabled, effectively turning off the analog circuitry. 0 = Enable QADC64 QADC64 clock. 1 = Disable QADC64 QADC64 clock. 14 FRZ FREEZE assertion response. The FRZ bit determines whether or not the QADC64 QADC64 responds to assertion of the IMB3 FREEZE signal. 0 = QADC64 QADC64 ignores the IMB3 FREEZE signal. 1 = QADC64 QADC64 finishes any current conversion, then freezes. 13:8 - 15 7 SUPV 6:4 - 3:0 IARB Reserved Supervisor/unrestricted data space. The SUPV bit designates the assignable space as supervisor or unrestricted. 0 = Only the module configuration register, test register, and interrupt register are designated as supervisor-only data space. Access to all other locations is unrestricted. 1 = All QADC64 QADC64 registers and tables are designated as supervisor-only data space. Reserved Interrupt arbitration number. IARB determines QADC64 QADC64 interrupt arbitration priority. An IARB field can be assigned a value from 0b0001 (lowest priority) to 0b1111 (highest value). Note that the logic associated with the IARB field is implemented for bus masters with interrupt acknowledge cycles (IACK). 5.12.2 QADC64 QADC64 Interrupt Register QADC64INT QADC64INT specifies the priority level of QADC64 QADC64 interrupt requests and the vector provided. The interrupt level for queue 1 and queue 2 may be different. The interrupt register is read/write accessible in supervisor data space only. The implemented interrupt register fields can be read and written, reserved bits read zero and writes have no effect. They are typically written once when the software initializes the QADC, and not changed afterwards. MC68F375 MC68F375 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MODULE-64 REFERENCE MANUAL Rev. 15 Oct 00 MOTOROLA 5-35 QADC64INT QADC64INT - QADC64 QADC64 Interrupt Register MSB 15 14 13 Reserved 12 11 10 9 Reserved IRL1 0xYF F404 8 7 6 5 3 IRL2 2 1 LSB 0 0 4 0 0 0 IVB RESET: 0 0 0 0 0 0 0 0 0 0 0 0 Table 5-8 QADC64INT QADC64INT Bit Settings Bit(s) Name 15 - 14:12 IRL1 11 - 10:8 IRL2 Interrupt level for queue 2. A value of 00000 provides an interrupt level of 0; 0b111 provides a level interrupt. All interrupts are presented on the IMB3. Interrupt level priority software determines which level has the highest priority request. IVB Interrupt vector base. Initialization software inputs the upper six IVB bits in the interrupt register. During interrupt arbitration, the vector provided to the bus master by the QADC is made up of the upper six IVB bits , plus two low-order bits provided to the QADC to identify one of four QADC interrupt requests. The interrupt vector number is independent of the interrupt level and the interrupt arbitration number. A 0x0F vector number corresponds to the uninitialized interrupt vector. After reset, the lower byte of the interrupt register reads as 0x0F. Once the IVB field is written, the two least significant bits always read as zeros. 7:0 Description Reserved Interrupt level for queue 1. A value of 00000 provides an interrupt level of 0; 0b111 provides a level interrupt. All interrupts are presented on the IMB3. Interrupt level priority software determines which level has the highest priority request. Reserved 5.12.3 Port A/B Data Register QADC64 QADC64 ports A and B are accessed through two 8-bit port data registers (PORTQA and PORTQB). PORTQA - Port QA Data Register PORTQB - Port QB Data Register 0xYF F406 MSB 15 14 13 12 11 PQA7 PQA6 PQA5 PQA4 PQA3 U U U U U U U U U U U U U U AN56 AN55 AN54 AN53 AN52 AN51 AN50 AN49 AN48 AN3 AN2 AN1 AN0 MA2 MA1 MA0 ANz ANy ANx ANw 10 9 8 7 6 5 4 3 2 1 LSB 0 PQA2 PQA1 PQA0 PQB7 PQB6 PQB5 PQB4 PQB3 PQB2 PQB1 PQB0 RESET: U U ANALOG CHANNEL: AN59 AN58 AN57 MULTIPLEXED ADDRESS OUTPUTS: MULTIPLEXED ANALOG INPUTS: MC68F375 MC68F375 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MODULE-64 REFERENCE MANUAL Rev. 15 Oct 00 MOTOROLA 5-36 Table 5-9 PORTQA, PORTQB Bit Settings Bit(s) Name Description 15:8 PQA[0:7] Port A pins are referred to as PQA when used as an 8-bit input/output port. Port A can also be used for analog inputs (AN[59:52]), and external multiplexer address outputs (MA[2:0]). 7:0 PQB[0:7] Port B pins are referred to as PQB when used as an 8-bit input only port. Port B can also be used for non-multiplexed (AN[51:48])/AN[3:0]) and multiplexed (ANz, ANy, ANx, ANw) analog inputs. 5.12.4 Port Data Direction Register DDRQA - Port QA Data Direction Register MSB 15 DDQ A7 14 13 12 11 10 9 8 0xYF F408 7 6 5 DDQA DDQA DDQA DDQA DDQA DDQA DDQA 6 5 4 3 2 1 0 4 3 2 1 LSB 0 0 0 0 RESERVED RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 5-10 DDRQA Bit Settings Bit(s) 15:8 Name Description Bits in this register control the direction of the port QA pin drivers when pins are configured for I/ DDQA[7:0] O. Setting a bit configures the corresponding pin as an output; clearing a bit configures the corresponding pin as an input. This register can be read or written at any time. 7:0 - Reserved 5.12.5 QADC64 QADC64 Control Register 0 (QACR0) Control register 0 establishes the QCLK with prescaler parameter fields and defines whether external multiplexing is enabled. All of the implemented control register fields can be read or written, reserved fields read zero and writes have no effect. They are typically written once when the software initializes the QADC64 QADC64, and not changed afterwards. QACR0 - QADC64 QADC64 Control Register 0 MSB 15 MUX 14 13 RESERVED 12 11 TRG 10 9 0xYF F40A 8 7 RESERVED 6 5 4 PSH 3 2 PSA 1 LSB 0 PSL RESET: 0 0 MC68F375 MC68F375 0 0 0 0 0 0 1 0 1 1 0 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MODULE-64 REFERENCE MANUAL Rev. 15 Oct 00 1 1 1 MOTOROLA 5-37 Table 5-11 QACR0 Bit Settings Bit(s) Name Description 15 MUX Externally multiplexed mode. The MUX bit configures the QADC64 QADC64 for externally multiplexed mode, which affects the interpretation of the channel numbers and forces the MA[2:0] pins to be outputs. 0 = Internally multiplexed, 16 possible channels. AMUX is disabled. 1 = Externally multiplexed, 41 possible channels. This enables the on-chip AMUX. 14:13 - Reserved Trigger assignment. TRG allows the software to assign the ETRIG[2:1] pins to queue 1 and queue 2. 0 = ETRIG1 triggers queue 1; ETRIG2 triggers queue 2 1 = ETRIG1 triggers queue 2; ETRIG2 triggers queue 1 12 TRG 11:9 - 8:4 PSH Prescaler clock high time. The PSH field selects the QCLK high time in the prescaler. PSH value plus 1 represents the high time in system clocks 3 PSA Note that this bit location is maintained for software compatibility with previous versions of the QADC64 QADC64. It serves no functional benefit in the MC68F375 MC68F375 and is not operational. 2:0 PSL Prescaler clock low time. The PSL field selects the QCLK low time in the prescaler. PSL value plus 1 represents the low time in system clocks Reserved 5.12.6 QADC64 QADC64 Control Register 1 (QACR1) Control register 1 is the mode control register for the operation of queue 1. The applications software defines the queue operating mode for the queue, and may enable a completion and/or pause interrupt. All of the control register fields are read/write data. However, the SSE1 bit always reads as zero unless the test mode is enabled. Most of the bits are typically written once when the software initializes the QADC64 QADC64, and not changed afterwards. QACR1 - Control Register 1 MSB 15 14 13 CIE1 PIE1 SSE1 0 0 12 11 0xYF F40C 10 9 8 7 6 5 MQ1 4 3 2 1 LSB 0 0 0 0 RESERVED RESET: 0 MC68F375 MC68F375 0 0 0 0 0 0 0 0 0 0 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MODULE-64 REFERENCE MANUAL Rev. 15 Oct 00 MOTOROLA 5-38 Table 5-12 QACR1 Bit Settings Bit(s) 15 14 13 Name Description CIE1 Queue 1 completion interrupt enable. CIE1 enables completion interrupts for queue 1. The interrupt request is generated when the conversion is complete for the last CCW in queue 1. 0 = Queue 1 completion interrupts disabled. 1 = Generate an interrupt request after completing the last CCW in queue 1. PIE1 Queue 1 pause interrupt enable. PIE1 enables pause interrupts for queue 1. The interrupt request is generated when the conversion is complete for a CCW that has the pause bit set. 0 = Queue 1 pause interrupts disabled. 1 = Generate an interrupt request after completing a CCW in queue 1 which has the pause bit set. SSE1 Queue 1 single-scan enable. SSE1 enables a single-scan of queue 1 after a trigger event occurs. The SSE1 bit may be set to a one during the same write cycle that sets the MQ1 bits for the single-scan queue operating mode. The single-scan enable bit can be written as a one or a zero, but is always read as a zero. The SSE1 bit allows a trigger event to initiate queue execution for any single-scan operation on queue 1. The QADC64 QADC64 clears SSE1 when the single-scan is complete. 12:8 MQ1 7:0 - Queue 1 operating mode. The MQ1 field selects the queue operating mode for queue 1. Table 5-13 shows the different queue 1 operating modes. Reserved Table 5-13 Queue 1 Operating Modes MQ1 Operating Modes 00000 Disabled mode, conversions do not occur 00001 Software triggered single-scan mode (started with SSE1) 00010 External trigger rising edge single-scan mode 00011 External trigger falling edge single-scan mode 00100 Interval timer single-scan mode: time = QCLK period x 27 00101 Interval timer single-scan mode: time = QCLK period x 28 00110 Interval timer single-scan mode: time = QCLK period x 29 00111 Interval timer single-scan mode: time = QCLK period x 210 01000 Interval timer single-scan mode: time = QCLK period x 211 01001 Interval timer single-scan mode: time = QCLK period x 212 01010 Interval timer single-scan mode: time = QCLK period x 213 01011 Interval timer single-scan mode: time = QCLK period x 214 01100 Interval timer single-scan mode: time = QCLK period x 215 01101 Interval timer single-scan mode: time = QCLK period x 216 01110 Interval timer single-scan mode: time = QCLK period x 217 01111 External gated single-scan mode (started with SSE1) 10000 Reserved mode 10001 External trigger rising edge continuous-scan mode 10011 External trigger falling edge continuous-scan mode 10100 MC68F375 MC68F375 Software triggered continuous-scan mode 10010 Periodic timer continuous-scan mode: time = QCLK period x 27 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MODULE-64 REFERENCE MANUAL Rev. 15 Oct 00 MOTOROLA 5-39 Table 5-13 Queue 1 Operating Modes (Continued) MQ1 Operating Modes 10101 Periodic timer continuous-scan mode: time = QCLK period x 28 10110 Periodic timer continuous-scan mode: time = QCLK period x 29 10111 Periodic timer continuous-scan mode: time = QCLK period x 210 11000 Periodic timer continuous-scan mode: time = QCLK period x 211 11001 Periodic timer continuous-scan mode: time = QCLK period x 212 11010 Periodic timer continuous-scan mode: time = QCLK period x 213 11011 Periodic timer continuous-scan mode: time = QCLK period x 214 11100 Periodic timer continuous-scan mode: time = QCLK period x 215 11101 Periodic timer continuous-scan mode: time = QCLK period x 216 11110 Periodic timer continuous-scan mode: time = QCLK period x 217 11111 External gated continuous-scan mode 5.12.7 QADC64 QADC64 Control Register 2 (QACR2) Control register 2 is the mode control register for the operation of queue 2. Software specifies the queue operating mode of queue 2, and may enable a completion and/or a pause interrupt. All control register fields are read/write data, except the SSE2 bit, which is readable only when the test mode is enabled. Most of the bits are typically written once when the software initializes the QADC64 QADC64, and not changed afterwards. QACR2 - Control Register 2 MSB 15 14 13 CIE2 PIE2 SSE2 0 0 12 11 0xYF F40E 10 9 8 7 6 5 4 RESUME MQ2 3 2 1 LSB 0 0 0 0 BQ2 RESET: 0 MC68F375 MC68F375 0 0 0 0 0 0 1 0 0 0 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MODULE-64 REFERENCE MANUAL Rev. 15 Oct 00 MOTOROLA 5-40 Table 5-14 QACR2 Bit Settings Bit(s) Name CIE2 PIE2 15 14 13 Description Queue 2 completion interrupt enable. CIE2 enables completion interrupts for queue 2. The interrupt request is generated when the conversion is complete for the last CCW in queue 2. 0 = Queue 2 completion interrupts disabled. 1 = Generate an interrupt request after completing the last CCW in queue 2. Queue 2 pause interrupt enable. PIE2 enables pause interrupts for queue 2. The interrupt request is generated when the conversion is complete for a CCW that has the pause bit set. 0 = Queue 2 pause interrupts disabled. 1 = Generate an interrupt request after completing a CCW in queue 2 which has the pause bit set. SSE2 Queue 2 single-scan enable bit. SSE2 enables a single-scan of queue 2 after a trigger event occurs. The SSE2 bit may be set to a one during the same write cycle that sets the MQ2 bits for the single-scan queue operating mode. The single-scan enable bit can be written as a one or a zero, but is always read as a zero. The SSE2 bit allows a trigger event to initiate queue execution for any single-scan operation on queue 2. The QADC64 QADC64 clears SSE2 when the single-scan is complete. MQ2 Queue 2 operating mode. The MQ2 field selects the queue operating mode for queue 2.Table 5-15 shows the bits in the MQ2 field which enable different queue 2 operating modes. RESUME Queue 2 resume. RESUME selects the resumption point after queue 2 is suspended by queue 1. If RESUME is changed during execution of queue 2, the change is not recognized until an endof-queue condition is reached, or the queue operating mode of queue 2 is changed. 0 = After suspension, begin execution with the first CCW in queue 2 or the current subqueue. 1 = After suspension, begin execution with the aborted CCW in queue 2. BQ2 Beginning of queue 2. The BQ2 field indicates the location in the CCW table where queue 2 begins. The BQ2 field also indicates the end-of-queue 1 and thus creates an end-of-queue condition for queue 1. Setting BQ2 to any value 64 (1000000) allows the entire RAM space for queue 1 CCW's. 12:8 7 6:0 MC68F375 MC68F375 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MODULE-64 REFERENCE MANUAL Rev. 15 Oct 00 MOTOROLA 5-41 Table 5-15 Queue 2 Operating Modes MQ2 Operating Modes 00000 Disabled mode, conversions do not occur 00001 Software triggered single-scan mode (started with SSE2) 00010 External trigger rising edge single-scan mode 00011 External trigger falling edge single-scan mode 00100 Interval timer single-scan mode: interval = QCLK period x 27 00101 Interval timer single-scan mode: interval = QCLK period x 28 00110 Interval timer single-scan mode: interval = QCLK period x 29 00111 Interval timer single-scan mode: interval = QCLK period x 210 01000 Interval timer single-scan mode: interval = QCLK period x 211 01001 Interval timer single-scan mode: interval = QCLK period x 212 01010 Interval timer single-scan mode: interval = QCLK period x 213 01011 Interval timer single-scan mode: interval = QCLK period x 214 01100 Interval timer single-scan mode: interval = QCLK period x 215 01101 Interval timer single-scan mode: interval = QCLK period x 216 01110 Interval timer single-scan mode: interval = QCLK period x 217 01111 Reserved mode 10000 Reserved mode 10001 Software triggered continuous-scan mode (started with SSE2) 10010 External trigger rising edge continuous-scan mode 10011 External trigger falling edge continuous-scan mode 10100 Periodic timer continuous-scan mode: period = QCLK period x 27 10101 Periodic timer continuous-scan mode: period = QCLK period x 28 10110 Periodic timer continuous-scan mode: period = QCLK period x 29 10111 Periodic timer continuous-scan mode: period = QCLK period x 210 11000 Periodic timer continuous-scan mode: period = QCLK period x 211 11001 Periodic timer continuous-scan mode: period = QCLK period x 212 11010 Periodic timer continuous-scan mode: period = QCLK period x 213 11011 Periodic timer continuous-scan mode: period = QCLK period x 214 11100 Periodic timer continuous-scan mode: period = QCLK period x 215 11101 Periodic timer continuous-scan mode: period = QCLK period x 216 11110 Periodic timer continuous-scan mode: period = QCLK period x 217 11111 Reserved mode 5.12.8 QADC64 QADC64 Status Register 0 (QASR0) QASR0 contains information about the state of each queue and the current A/D conversion. Except for the four flag bits (CF1, PF1, CF2, and PF2) and the two trigger overrun bits (TOR1 and TOR2), all of the status register fields contain read-only data. MC68F375 MC68F375 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MODULE-64 REFERENCE MANUAL Rev. 15 Oct 00 MOTOROLA 5-42 The four flag bits and the two trigger overrun bits are cleared by writing a zero to the bit after the bit was previously read as a one. QASR0 - QADC64 QADC64 Status Register MSB 15 14 13 12 CF1 PF1 CF2 PF2 0 0 0 11 10 9 0xYF F410 8 TOR1 TOR2 7 6 5 4 2 3 QS 1 LSB 0 0 0 0 CWP RESET: 0 0 0 0 0 0 0 0 0 0 Table 5-16 QASR0 Bit Settings Bit(s) 15 14 13 12 Name Description CF1 Queue 1 completion flag. CF1 indicates that a queue 1 scan has been completed. CF1 is set by the QADC64 QADC64 when the conversion is complete for the last CCW in queue 1, and the result is stored in the result table. 0 = Queue 1 scan is not complete. 1 = Queue 1 scan is complete. PF1 Queue 1 pause flag. PF1 indicates that a queue 1 scan has reached a pause. PF1 is set by the QADC64 QADC64 when the current queue 1 CCW has the pause bit set, the selected input channel has been converted, and the result has been stored in the result table. 0 = Queue 1 has not reached a pause. 1 = Queue 1 has reached a pause. CF2 Queue 2 completion flag. CF2 indicates that a queue 2 scan has been completed. CF2 is set by the QADC64 QADC64 when the conversion is complete for the last CCW in queue 2, and the result is stored in the result table. 0 = Queue 2 scan is not complete. 1 = Queue 2 scan is complete. PF2 Queue 2 pause flag. PF2 indicates that a queue 2 scan has reached a pause. PF2 is set by the QADC64 QADC64 when the current queue 2 CCW has the pause bit set, the selected input channel has been converted, and the result has been stored in the result table. 0 = Queue 2 has not reached a pause. 1 = Queue 2 has reached a pause. Queue 1 trigger overrun. TOR1 indicates that an unexpected queue 1 trigger event has occurred. TOR1 can be set only while queue 1 is active. 11 TOR1 A trigger event generated by a transition on ETRIG1/ETRIG2 may be recorded as a trigger overrun. TOR1 can only be set when using an external trigger mode. TOR1 cannot occur when the software initiated single-scan mode or the software initiated continuous-scan mode is selected. 0 = No unexpected queue 1 trigger events have occurred. 1 = At least one unexpected queue 1 trigger event has occurred. Queue 2 trigger overrun. TOR2 indicates that an unexpected queue 2 trigger event has occurred. TOR2 can be set when queue 2 is in the active, suspended, and trigger pending states. 10 MC68F375 MC68F375 TOR2 A trigger event generated by a transition depending on the value of TRG in QACR or ETRIG1/ ETRIG2 or by the periodic/interval timer may be recorded as a trigger overrun. TOR2 can only