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PWS1.1 Datasheet

Part Manufacturer Description PDF Type
PWS-1-104 Richco Clamps and Clips, Cables, Wires - Management, PICO WIRE SADDLE NATURAL Original

PWS1.1

Catalog Datasheet MFG & Type PDF Document Tags

337 BGA footprint

Abstract: AN-5058 DP[1:12] CMOS-I/O 12 LV-CMOSI/ODIRI CKREF CMOS-IN 1 LV-CMOSPLL STROBE CMOS-IN 1 LV-CMOS CKP CMOSOUT 1 LV-CMOS DSO+(DSI-) DSO-(DSI+) DIFF-I/O 2 , +, CKSO- DIFF-OUT 2 CTL CKSO+CKSO CKSO-CKSO S0, S1 CMOS-IN 1 DIRI=1PLLDIRI=0 I/O PLL0(PWS0) CMOS-IN 1 DIRI=1PLL0DIRI=0PWS0 CKP PLL1(PWS1) CMOS-IN 1 DIRI=1PLL1 DIRI=0PWS1 TEST / (XTRM) CMOS_IN 1 DIRI=1TEST=0DIRI=0 XTRM=0XTRM=1 CTL_ADJ (GND
Fairchild Semiconductor
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FIN212AC AN-5058 AN-5061 FIN212ACMLX FIN212ACGFX FIN212ACBFX 337 BGA footprint DP10 32MLPJEDEC MO-2205

Dp 104

Abstract: DSO20 CTLTM Isolates interface for signal integrity Up to 48MHz Camera Module Figure 1. Mobile Phone , Configure frequency range for the PLL. 0 Deserializer 1 Serializer 0 Low drive (low power) 1 High drive (high power) See Table 1 Serializer (DIRI=1) Control Pin. S1 Configure frequency range for the PLL. See Table 1 Serializer (DIRI=1) Control Pin. PLL0 Divide or adjust the serial frequency. See Table 1 Serializer (DIRI=1) Control Pin. PLL1 CKREF STROBE DP[1:10] CKSO+ / CKSODSO
Fairchild Semiconductor
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FIN210AC FIN210ACMLX FIN210ACGFX Dp 104 DSO20 FIN210 MO-195

FIN210AC

Abstract: 13M-pixel to 48MHz Camera Module Figure 1. Mobile Phone Example © 2009 Fairchild Semiconductor , PLL. 0 Deserializer 1 Serializer 0 Low drive (low power) 1 High drive (high power) See Table 1 Serializer (DIRI=1) Control Pin. S1 Configure frequency range for the PLL. See Table 1 Serializer (DIRI=1) Control Pin. PLL0 Divide or adjust the serial frequency. See Table 1 Serializer (DIRI=1) Control Pin. PLL1 CKREF STROBE DP[1:10] CKSO+ / CKSODSO+ / DSO- Divide or adjust the serial
Fairchild Semiconductor
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13M-pixel JESD22-A114 ckp5e PWS1.1 577ns
Abstract: -Bit Serializer Deserializer with Multiple Frequency Ranges Pin Definitions Pin DP[1:12] CKREF STROBE CKP DSO+(DSI-)(1) DSO-(DSI+) CKSI+, CKSICKSO+, CKSOS0, S1 PLL0(PWS0) PLL1(PWS1) TEST / (XTRM) CTL_ADJ (GND , CMOS-IN CMOS-IN CMOS-IN CMOS_IN CMOS_IN IN OUT Supply Supply Supply Supply # of Pins 12 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 0 Description of Signals LV-CMOS Parallel I/O. Direction controlled by DIRI pin , . CKSO+: Positive signal of CKSO pair; CKSO-: Negative signal of CKSO pair. DIRI=1: signals are used to Fairchild Semiconductor
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Abstract: -Bit Serializer Deserializer with Multiple Frequency Ranges Pin Definitions Pin DP[1:12] CKREF STROBE CKP DSO+(DSI-) DSO-(DSI+) (1) I/O type CMOS-I/O CMOS-IN CMOS-IN CMOSOUT DIFF-I/O DIFF-IN DIFF-OUT CMOS-IN CMOS-IN CMOS-IN CMOS_IN CMOS_IN IN OUT Supply Supply Supply Supply # of Pins 12 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 0 Description of Signals LV-CMOS Parallel I/O. Direction controlled by DIRI pin. LV-CMOS , +: Positive signal of CKSO pair; CKSO-: Negative signal of CKSO pair. DIRI=1: signals are used to define Fairchild Semiconductor
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Abstract: "¢ Isolates interface for signal integrity Up to 48MHz Camera Module Figure 1. Mobile Phone Example , Configure frequency range for the PLL. 0 Deserializer 1 Serializer 0 Low drive (low power) 1 High drive (high power) See Table 1 Serializer (DIRI=1) Control Pin. S1 Configure frequency range for the PLL. See Table 1 Serializer (DIRI=1) Control Pin. PLL0 Divide or adjust the serial frequency. See Table 1 Serializer (DIRI=1) Control Pin. PLL1 CKREF STROBE DP[1:10] CKSO+ / CKSODSO Fairchild Semiconductor
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Abstract: Deserializer with Multiple Frequency Ranges Pin Definitions Pin DP[1:12] CKREF STROBE CKP DSO+(DSI-) DSO-(DSI+) (1) I/O type CMOS-I/O CMOS-IN CMOS-IN CMOSOUT DIFF-I/O DIFF-IN DIFF-OUT CMOS-IN CMOS-IN CMOS-IN CMOS_IN CMOS_IN IN OUT Supply Supply Supply Supply # of Pins 12 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 , signal of CKSO pair; CKSO-: Negative signal of CKSO pair. DIRI=1: signals are used to define frequency , . DIRI=1: PLL0 signal is used to divide or adjust the serial frequency. DIRI=0: PWS0 signal is used to Fairchild Semiconductor
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FIN212AC

Abstract: FIN212ACGFX I/O type # of Pins DP[1:12] CMOS-I/O 12 LV-CMOS Parallel I/O. Direction controlled by DIRI pin. CKREF CMOS-IN 1 LV-CMOS clock input and PLL reference. STROBE CMOS-IN 1 LV-CMOS strobe input for latching data into the serializer. CKP CMOSOUT 1 LV-CMOS word clock output. DSO+(DSI-)(1) DSO-(DSI+) DIFF-I/O 2 CTL Differential serial I/O data , 1 DIRI=1: signals are used to define frequency range for the PLL. DIRI=0: Signals are used to
Fairchild Semiconductor
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MO-220 8/10-B

emi line filter 48MHz

Abstract: FIN210AC CTLTM Isolates interface for signal integrity Up to 48MHz Camera Module Figure 1. Mobile Phone , Configure frequency range for the PLL. 0 Deserializer 1 Serializer 0 Low drive (low power) 1 High drive (high power) See Table 1 Serializer (DIRI=1) Control Pin. S1 Configure frequency range for the PLL. See Table 1 Serializer (DIRI=1) Control Pin. PLL0 Divide or adjust the serial frequency. See Table 1 Serializer (DIRI=1) Control Pin. PLL1 CKREF STROBE DP[1:10] CKSO+ CKSODSO
Fairchild Semiconductor
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emi line filter 48MHz 30 pin flex cable lcd mobile camera interface microcontroller

DP1211

Abstract: 337 BGA footprint Isolates interface for signal integrity Up to 40MHz Camera Module Figure 1. Mobile Phone Example , DIRI=1) Pin Descriptions Pin Name DIRI CTL_ADJ S0 S1 PLL0 PLL1 CKREF STROBE DP[1:12] CKSO+ CKSODSO , Deserializer 1 Serializer 0 Low drive (low power) 1 High drive (high power) See Table 1 Serializer (DIRI=1) Control Pin. See Table 1 Serializer (DIRI=1) Control Pin. See Table 1 Serializer (DIRI=1) Control Pin. Divide or adjust the serial frequency. See Table 1 Serializer (DIRI=1) Control Pin. LV-CMOS clock input
Fairchild Semiconductor
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DP1211

577ns

Abstract: Isolates interface for signal integrity Up to 40MHz Camera Module Figure 1. Mobile Phone Example , DIRI=1) Pin Descriptions Pin Name DIRI CTL_ADJ S0 S1 PLL0 PLL1 CKREF STROBE DP[1:12] CKSO+ CKSODSO , Deserializer 1 Serializer 0 Low drive (low power) 1 High drive (high power) See Table 1 Serializer (DIRI=1) Control Pin. See Table 1 Serializer (DIRI=1) Control Pin. See Table 1 Serializer (DIRI=1) Control Pin. Divide or adjust the serial frequency. See Table 1 Serializer (DIRI=1) Control Pin. LV-CMOS clock input
Fairchild Semiconductor
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35x45mm

Abstract: 6X6 mlp 12-Bit Serializer Deserializer with Multiple Frequency Ranges Pin Definitions Pin DP[1:12] CKREF STROBE CKP DSI+(DSO-)(1) DSI-(DSO+) CKSI+, CKSICKSO+, CKSOS0, S1 PLL0(PWS0) PLL1(PWS1) TEST / (XTRM , DIFF-OUT CMOS-IN CMOS-IN CMOS-IN CMOS_IN CMOS_IN IN OUT Supply Supply Supply Supply # of Pins 12 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 0 Description of Signals LV-CMOS Parallel I/O. Direction controlled by DIRI , clock. CKSO+: Positive signal of CKSO pair; CKSO-: Negative signal of CKSO pair. DIRI=1: signals are
Fairchild Semiconductor
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35x45mm 6X6 mlp

AN-5058

Abstract: AN-5061 -Bit Serializer Deserializer with Multiple Frequency Ranges May 2008 Pin I/O type # of Pins DP[1 , 1 LV-CMOS clock input and PLL reference. STROBE CMOS-IN 1 LV-CMOS strobe input for latching data into the serializer. CKP CMOSOUT 1 LV-CMOS word clock output. DSO+(DSI-) DSO , of CKSO pair; CKSO-: Negative signal of CKSO pair. S0, S1 CMOS-IN 1 DIRI=1: signals are , deserializer parallel I/Os. PLL0(PWS0) CMOS-IN 1 DIRI=1: PLL0 signal is used to divide or adjust
Fairchild Semiconductor
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5M cmos camera

13M-pixel

Abstract: 202 ball bga to 40MHz Camera Module Figure 1. Mobile Phone Example © 2008 Fairchild Semiconductor , Deserializer 1 Serializer 0 Low drive (low power) 1 High drive (high power) See Table 1 Serializer (DIRI=1) Control Pin. S1 Configure frequency range for the PLL. See Table 1 Serializer (DIRI=1) Control Pin. PLL0 Divide or adjust the serial frequency. See Table 1 Serializer (DIRI=1) Control Pin. PLL1 CKREF STROBE DP[1:12] CKSO+ CKSODSO+ DSOCKSI+ CKSICKP Divide or adjust the serial
Fairchild Semiconductor
Original
202 ball bga dsi LCD driver ipc-SM-782
Abstract: interface for signal integrity Up to 40MHz Camera Module Figure 1. Mobile Phone Example © 2008 , frequency range for the PLL. 0 Deserializer 1 Serializer 0 Low drive (low power) 1 High drive (high power) See Table 1 Serializer (DIRI=1) Control Pin. S1 Configure frequency range for the PLL. See Table 1 Serializer (DIRI=1) Control Pin. PLL0 Divide or adjust the serial frequency. See Table 1 Serializer (DIRI=1) Control Pin. PLL1 CKREF STROBE DP[1:12] CKSO+ CKSODSO+ DSOCKSI Fairchild Semiconductor
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Abstract: .079 2 .049 1.3 .044 1.1 .065 1.7 .098 2.5 .076 1.9 .035 0.9 TO SNAP LOCK IN A .040±.002 [1.0±0.05] DIA. HOLE IN A .040 [1.0] THICK PANEL NOTES: 1. MATERIAL: FLAME RETARDANT NYLON 6/6 (RMS-104) 2. COLOR: NATURAL TITLE: CREATED USING SOLIDWORKS B A REV. SEE ECN #1091 , TOLERANCES UNLESS NOTED .XX=±.010 .XXX=±.005 FRAC.=±1/64 ANG.=±1° PICO WIRE SADDLE FILE #: PWS-1 SHEET: 1 OF 1 RE: SHEET SIZE: A RICHCO INC DWN: DLC DT: 12/06/02 APP: CHKD: DLC SJ Richco
Original

MPIC2111

Abstract: MPIC2111P ,. ": /1 \, MOTOROLA m SEMICONDUCTOR ~ POWER PRODUCTS DIVISION m TECHNICAL , ;\?.:.,:,:x, ~ .1:>, .:,\~ .+. v >t n .;:* ,Jy$. . *T:,.,.ii;$:.y .? , ,1}7 , ~ ",1 >t~'.~\'.' *J\ iji,i. .* $. :?i.b< \+,(%:' .':$a *S,.,. `.$*, >>\?i$* ,.,:, ` "+ , , ;,:{} > , 1 D SUF~X PWTIC PACWGE CASE 75742 S08 . ,?' * ;., .,\\.~-. , ~".; ~ V* ,
Motorola
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MPIC2111 MPIC2111P M070ROLA

2SK514

Abstract: d1352   4.0±0.2 j 2.0*0 2 1.271.27 0 45 « »> t 1 J â'¢ n V1 r r +f -H , 1.4 4.1 mS A f] , # 1: C j it VDS = 10 V, Vcs=0, f=1.0 MHz 6.0 8.0 PF » a & * C m VDS = 10 V, VGS , rnrnnratinn 1984 NEC 2SK514 1(TA = 25 T) 300 250 S 200 150 4H 100 50 TOTAL POWER DISSIPATION , \ \ \ \ \ 1 \ 50 75 100 mm a* Ta
-
OCR Scan
T460-8525 d1352 C982 M-0258 2sk514 transistor FT010 D13529JJ4VODSOO TC-5787B T10S-B001

A3810 M

Abstract: a3810 SPIM VS HS DE D0[7:0] D1[7:0] AD[7:6] IF[3:1] RSC[3:1] CS SCLK SDI SDO RESE Tcon with Zoom , 12/21/2006 REV:0.3 Email: service@aimtron.com.tw 1 AT3810 Preliminary Product Information CCIR , Email: service@aimtron.com.tw 2 1 TSTEN 6 OEV 5 STVD 4 STVU 3 STHL 2 STHR AT3810 , Description 1 2 TSTEN STHR1 STHL1 I IO 3 IO 4 STVU IO 5 6 7 8 9 10 11 12 13 14 15 , I IO Test mode enables. Active high. Internally pull down. Start pulse for source driver. (1)STHR
Aimtron
Original
A3810 M a3810 HCOS Large panel TCON TCON TV CCIR-656
Abstract: . 60 mA Peak Forward C urrent 1> .1 A Power Dissipation , Linearly from 25°C .3.5 mWA'C Notes: 1. Values applies for PwS1 ms, PRRS300 pps. 2. Measured between pins 1,2,3 and 4 shorted together and pins 5,6,7 and 8 shorted together. TA=25°C and duratk>n=1 second, RH=45%. 5-193 Characteristics (Each -
OCR Scan
3000V ILH200 ILH20Q
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