PSD913F2 PSD934F2 PSD954F2 PQFP52 PLCC52 J1850 80C251 68HC11 68HC16 68HC12 - Datasheet Archive

 

PSD934F2 PSD954F2 Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs PRELIMINARY DATA FEATURES SUMMARY s Single Supply

 

PSD913F2 PSD913F2 PSD934F2 PSD934F2 PSD954F2 PSD954F2 Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs PRELIMINARY DATA FEATURES SUMMARY s Single Supply Voltage: Figure 1. Packages ­ 5 V±10% for PSD9xxF2 ­ 3.3 V±10% for PSD9xxF2-V s Up to 2Mbit of Primary Flash Memory (8 uniform sectors) s 256Kbit Secondary Flash Memory (4 uniform sectors) s Up to 256Kbit SRAM s Over 2,000 Gates of PLD: DPLD s 27 Reconfigurable I/O ports s Enhanced JTAG Serial Port s Programmable power management s High Endurance: PQFP52 PQFP52 (T) ­ 100,000 Erase/Write Cycles of Flash Memory ­ 1,000 Erase/Write Cycles of PLD PLCC52 PLCC52 (K) January 2002 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/3 PSD9XX Family PSD913F2 PSD913F2 PSD934F2 PSD934F2 PSD954F2 PSD954F2 Configurable Memory System on a Chip for 8-Bit Microcontrollers Table of Contents Introduction.1 In-System Programming (ISP) JTAG.2 In-Application Programming (IAP) .2 Key Features .3 Block Diagram .4 PSD9XX Family.5 Architectural Overview.6 Memory .6 Page Register .6 PLDs .6 I/O Ports.7 Microcontroller Bus Interface .7 JTAG Port .7 In-System Programming .8 Power Management Unit .8 Development System .9 Pin Descriptions.10 Register Description and Address Offset .14 Functional Blocks .15 Memory Blocks .15 Main Flash and Secondary Flash Memory Description.15 SRAM.27 Memory Chip Selects .27 Page Register .30 PLDs .31 Decode PLD (DPLD).33 General Purpose PLD (GPLD).33 Microcontroller Bus Interface .35 Interface to a Multiplexed 8-bit Bus.35 Interface to a Non-multiplexed 8-bit Bus .35 Microcontroller Interface Examples.37 I/O Ports.42 General Port Architecture.42 Port Operating Modes .44 Port Configuration Registers (PCRs) .47 Port Data Registers.49 Ports A and B ­ Functionality and Structure .49 Port C ­ Functionality and Structure .51 Port D ­ Functionality and Structure .51 For additional information, Call 800-832-6974 Fax: 510-657-8495 Web Site: http://www.psdst.com E-mail: ask.psd@st.com i PSD9XX Family PSD913F2 PSD913F2 PSD934F2 PSD934F2 PSD954F2 PSD954F2 Configurable Memory System on a Chip for 8-Bit Microcontrollers Table of Contents Power Management.54 Automatic Power Down (APD) Unit and Power Down Mode .54 Other Power Savings Options.58 Reset and Power On Requirement .59 Programming In-Circuit using the JTAG Interface .60 Standard JTAG Signals.61 JTAG Extensions .61 Security and Flash Memories Protection .61 Absolute Maximum Ratings.62 Operating Range .62 Recommended Operating Conditions .62 AC/DC Parameters.63 Example of Typical Power Calculation at Vcc = 5.0 V .64 Example of Typical Power Calculation at Vcc = 5.0 V in Turbo Off Mode .65 DC Characteristics (5 V ± 10% versions) .66 Microcontroller Interface ­ AC/DC Parameters (5 V ± 10% versions).67 Read Timing .68 Write Timing.69 PLD Combinatorial Timing .69 Power Down Timing.70 Vstbyon Timing .70 Reset Pin Timing .70 Flash Program, Write and Erase Times.71 ISC Timing .71 PSD9XXFV DC Characteristics (3.0 V to 3.6 V Versions) Advance Information.72 Microcontroller Interface ­ AC/DC Parameters (3 V versions) .73 Read Timing (3 V versions) .73 Write Timing (3 V versions) .74 PLD Combinatorial Timing (3 V versions).74 Power Down Timing (3 V Versions) .75 Vstbyon Timing (3 V Versions) .75 Reset Pin Timing (3 V Versions).75 Flash Program, Write and Erase Times (3 V Versions) .76 ISC Timing (3 V Versions) .76 For additional information, Call 800-832-6974 Fax: 510-657-8495 Web Site: http://www.psdst.com E-mail: ask.psd@st.com ii PSD9XX Family PSD913F2 PSD913F2 PSD934F2 PSD934F2 PSD954F2 PSD954F2 Configurable Memory System on a Chip for 8-Bit Microcontrollers Table of Contents Timing Diagrams .77 Pin Capacitance .81 AC Testing Input/Output Waveforms.81 AC Testing Load Circuit.81 Programming .81 Pin Assignments.82 Package Information.84 Selector Guide.87 Part Number Construction .87 Ordering Information.88 Document Revisions.89 For additional information, Call 800-832-6974 Fax: 510-657-8495 Web Site: http://www.psdst.com E-mail: ask.psd@st.com iii PSD913F2 PSD913F2, PSD934F2 PSD934F2, PSD954F2 PSD954F2 Configurable Memory System on a Chip for 8-Bit Microcontrollers Preliminary Information 1.0 Introduction The PSD9XX family of Programmable System Devices (for 8-bit microcontrollers) brings In-System-Programmability (ISP) to Flash memory and programmable logic. The result is a simple and flexible solution for embedded designs. PSD9XX devices combine many of the peripheral functions found in MCU based applications: · Up to 2 Mbit of Flash memory · A secondary 256 Kbit Flash memory · Over 2,000 gates of Flash programmable logic · Up to 256 Kbit SRAM · Reconfigurable I/O ports · Programmable power management. 1 PSD9XX Family Preliminary Information 1.0 Introduction The PSD9XX family offers two methods to program PSD Flash memory while the PSD is soldered to a circuit board. (Cont.) t In-System Programming (ISP) JTAG An IEEE 1149.1 compliant JTAG interface is included on the PSD enabling the entire device (both flash memories, the PLD, and all configuration) to be rapidly programmed while soldered to the circuit board. This requires no MCU participation, which means the PSD can be programmed anytime, even while completely blank. The innovative JTAG interface to flash memories is an industry first, solving key problems faced by designers and manufacturing houses, such as: · First time programming ­ How do I get firmware into the flash the very first time? JTAG is the answer, program the PSD while blank with no MCU involvement. · Inventory build-up of pre-programmed devices ­ How do I maintain an accurate count of pre-programmed flash memory and PLD devices based on customer demand? How many and what version? JTAG is the answer, build your hardware with blank PSDs soldered directly to the board and then custom program just before they are shipped to customer. No more labels on chips and no more wasted inventory. · Expensive sockets ­ How do I eliminate the need for expensive and unreliable sockets? JTAG is the answer. Solder the PSD directly to the circuit board. Program first time and subsequent times with JTAG. No need to handle devices and bend the fragile leads. t In-Application Programming (IAP) Two independent flash memory arrays are included so the MCU can execute code from one memory while erasing and programming the other. Robust product firmware updates in the field are possible over any communication channel (CAN, Ethernet, UART, J1850 J1850, etc) using this unique architecture. Designers are relieved of these problems: · Simultaneous read and write to flash memory ­ How can the MCU program the same memory from which it is executing code? It cannot. The PSD allows the MCU to operate the two flash memories concurrently, reading code from one while erasing and programming the other during IAP. · Complex memory mapping ­ I have only a 64K-byte address space to start with. How can I map these two memories efficiently? A Programmable Decode PLD is the answer. The concurrent PSD memories can be mapped anywhere in MCU address space, segment by segment with extremely high address resolution. As an option, the secondary flash memory can be swapped out of the system memory map when IAP is complete. A built-in page register breaks the 64K-byte address limit. · Separate program and data space ­ How can I write to flash memory while it resides in "program" space during field firmware updates, my MCU won't allow it! The flash PSD provides means to "reclassify" flash memory as "data" space during IAP, then back to "program" space when complete. PSDsoft Express ­ ST's software development tool ­ guides you through the design process step-by-step making it possible to complete an embedded MCU design capable of ISP/IAP in just hours. Select your MCU and PSDsoft Express will take you through the remainder of the design with point and click entry, covering.PSD selection, pin definitions, programmable logic inputs and outputs, MCU memory map definition, ANSI C code generation for your MCU, and merging your MCU firmware with the PSD design. When complete, two different device programmers are supported directly from PSDsoft ­ FlashLINK (JTAG) and PSDpro. The PSD9XX is available in 52-pin PLCC and PQFP packages as well as a 64-pin TQFP package. 2 Preliminary Information 2.0 Key Features PSD9XX Family t A simple interface to 8-bit microcontrollers that use either multiplexed or non-multiplexed busses. The bus interface logic uses the control signals generated by the microcontroller automatically when the address is decoded and a read or write is performed. A partial list of the MCU families supported include: · · · · Intel 8031, 80196, 80186, 80C251 80C251 Motorola 68HC11 68HC11, 68HC16 68HC16, 68HC12 68HC12, and 683XX 683XX Philips 8031 and 8051XA 8051XA Zilog Z80, Z8, and Z180 t Internal 1 or 2 Mbit flash memory. This is the main Flash memory. It is divided into eight equal-sized blocks that can be accessed with user-specified addresses. t Internal secondary 256 Kbit Flash memory. It is divided into four equal-sized blocks that can be accessed with user-specified addresses. This secondary memory brings the ability to execute code and update the main Flash concurrently. t 16, 64 or 256 Kbit SRAM. The SRAM's contents can be protected from a power failure by connecting an external battery. t General Purpose PLD (GPLD) with 19 outputs. The GPLD may be used to implement external chip selects or combinatorial logic function. t Decode PLD (DPLD) that decodes address for selection of internal memory blocks. t 27 individually configurable I/O port pins that can be used for the following functions: · MCU I/Os · PLD I/Os · Latched MCU address output · Special function I/Os. · 16 of the I/O ports may be configured as open-drain outputs. t Standby current as low as 50 µA for 5 V devices. t Built-in JTAG compliant serial port allows full-chip In-System Programmability (ISP). With it, you can program a blank device or reprogram a device in the factory or the field. t Internal page register that can be used to expand the microcontroller address space by a factor of 256. t Internal programmable Power Management Unit (PMU) that supports a low power mode called Power Down Mode. The PMU can automatically detect a lack of microcontroller activity and put the PSD9XX into Power Down Mode. t Erase/Write cycles: · Flash memory ­ 100,000 minimum · PLD ­ 1,000 minimum · Data Retention: 15 years 3 4 AD0 ­ AD15 CNTL0, CNTL1, CNTL2 GLOBAL CONFIG. & SECURITY ADIO PORT PROG. MCU BUS INTRF. PLD INPUT BUS 57 57 PAGE REGISTER FLASH ISP PLD (GPLD) FLASH DECODE PLD (DPLD) 16, 64 OR 256 KBIT BATTERY BACKUP SRAM 256 KBIT SECONDARY FLASH MEMORY (BOOT OR DATA) 4 SECTORS 8 SECTORS 1 OR 2 MBIT MAIN FLASH MEMORY JTAG SERIAL CHANNEL GPLD OUTPUT GPLD OUTPUT GPLD OUTPUT RUNTIME CONTROL AND I/O REGISTERS PLD, CONFIGURATION & FLASH MEMORY LOADER I/O PORT PLD INPUT CSIOP SRAM SELECT SECTOR SELECTS SECTOR SELECTS EMBEDDED ALGORITHM ADDRESS/DATA/CONTROL BUS PORT D PROG. PORT PORT C PROG. PORT PORT B PROG. PORT PORT A PROG. PORT POWER MANGMT UNIT PD0 ­ PD2 PC0 ­ PC7 PB0 ­ PB7 PA0 ­ PA7 VSTDBY (PC2) PSD9XX Family Preliminary Information Figure 1. PSD9XX Block Diagram Preliminary Information 4.0 PSD9XX Family PSD9XX Family There are 2 variants in the PSD9XX family. All PSD9XX devices provide these base features: 1 or 2 Mbit main Flash Memory, JTAG port, GPLD, DPLD, power management, and 27 I/O pins. The following table summarizes all the devices in the PSD9XX family. Additional devices will be introduced. Table 1. PSD9XX Product Matrix Part # PSD9XX Family PSD9XX Device Flash Secondary Serial ISP Main Memory Flash Memory I/O No. of JTAG/ISC Kbit Kbit Pins GPLD Output Port (8 Sectors) (4 Sectors) SRAM Kbit Turbo Mode Supply Voltage PSD913F2 PSD913F2 27 19 Yes 1024 256 16 Yes 3V/5V PSD934F2 PSD934F2 27 19 Yes 2048 256 64 Yes 3V/5V PSD954F2 PSD954F2 27 19 Yes 2048 256 256 Yes 3V/5V 5 PSD9XX Family 5.0 PSD9XX Architectural Overview Preliminary Information PSD9XX devices contain several major functional blocks. Figure 1 shows the architecture of the PSD9XX device family. The functions of each block are described briefly in the following sections. Many of the blocks perform multiple functions and are user configurable. 5.1 Memory The PSD9XX contains the following memories: · A 1 or 2 Mbit Flash · A secondary 256 Kbit Flash memory · 16, 64 or 256 Kbit SRAM. Each of the memories is briefly discussed in the following paragraphs. A more detailed discussion can be found in section 9. The 1 or 2 Mbit Flash is the main memory of the PSD9XX. It is divided into eight equally-sized sectors that are individually selectable. The 256 Kbit secondary Flash memory is divided into four equally-sized sectors. Each sector is individually selectable. This memory can hold boot code or data. The SRAM is intended for use as a scratchpad memory or as an extension to the microcontroller SRAM. If an external battery is connected to the PSD9XX's Vstby pin, data will be retained in the event of a power failure. Each block of memory can be located in a different address space as defined by the user. The access times for all memory types includes the address latching and DPLD decoding time. 5.2 Page Register The eight-bit Page Register expands the address range of the microcontroller by up to 256 times.The paged address can be used as part of the address space to access external memory and peripherals or internal memory and I/O. The Page Register can also be used to change the address mapping of blocks of Flash memory into different memory spaces IAP. 5.3 PLDs The device contains two combinatorial PLD blocks, each optimized for a different function, as shown in Table 2. The functional partitioning of the PLDs reduces power consumption, optimizes cost/performance, and eases design entry. The Decode PLD (DPLD) is used to decode addresses and generate chip selects for the PSD9XX internal memory and registers. The General Purpose PLD (GPLD) can implement user-defined external chip selects and logic functions. The PLDs receive their inputs from the PLD Input Bus and are differentiated by their output destinations, number of Product Terms. The PLDs consume minimal power by using Zero-Power design techniques. The speed and power consumption of the PLD is controlled by the Turbo Bit in the PMMR0 register and other bits in the PMMR2 registers. These registers are set by the microcontroller at runtime. There is a slight penalty to PLD propagation time when invoking the non-Turbo bit. Table 2. PLD I/O Table Name Abbreviation Inputs Outputs Product Terms Decode PLD 57 15 39 General Purpose PLD 6 DPLD GPLD 57 19 114 Preliminary Information PSD9XX Architectural Overview (cont.) PSD9XX Family 5.4 I/O Ports The PSD9XX has 27 I/O pins divided among four ports (Port A, B, C, and D). Each I/O pin can be individually configured for different functions. Ports A, B, C and D can be configured as standard MCU I/O ports, PLD I/O, or latched address outputs for microcontrollers using multiplexed address/data busses. The JTAG pins can be enabled on Port C for In-System Programming (ISP). Port A can also be configured as a data port for a non-multiplexed bus. 5.5 Microcontroller Bus Interface The PSD9XX easily interfaces with most 8-bit microcontrollers that have either multiplexed or non-multiplexed address/data busses. The device is configured to respond to the microcontroller's control signals, which are also used as inputs to the PLDs. Section 9.3.5 contains microcontroller interface examples. 5.6 JTAG Port In-System Programming can be performed through the JTAG pins on Port C. This serial interface allows complete programming of the entire PSD9XX device. A blank device can be completely programmed. The JTAG signals (TMS, TCK, TSTAT, TERR, TDI, TDO) are enabled on Port C when selected or when a device is blank. Table 3 indicates the JTAG signals pin assignments. Table 3. JTAG Signals on Port C Port C Pins JTAG Signal PC0 TMS PC1 TCK PC3 TSTAT PC4 TERR PC5 TDI PC6 TDO 7 PSD9XX Family PSD9XX Architectural Overview (cont.) Preliminary Information 5.7 In-System Programming Using the JTAG signals on Port C, the entire PSD9XX device can be programmed or erased without the use of the microcontroller (ISP). The main Flash memory can also be programmed in-system by the microcontroller executing the programming algorithms out of the Secondary Flash memory, or SRAM (IAP). The Secondary Flash memory can be programmed the same way by executing out of the main Flash memory. The PLD logic or other PSD9XX configuration can be programmed through the JTAG port or a device programmer. Table 4 indicates which programming methods can program different functional blocks of the PSD9XX. Table 4. Methods of Programming Different Functional Blocks of the PSD9XX Functional Block JTAG-ISP Device Programmer IAP Main Flash Memory Yes Yes Yes Secondary Flash Memory Yes Yes Yes PLD Array (DPLD and GPLD) Yes Yes No PSD Configuration Yes Yes No 5.8 Power Management Unit The Power Management Unit (PMU) in the PSD9XX gives the user control of the power consumption on selected functional blocks based on system requirements. The PMU includes an Automatic Power Down unit (APD) that will turn off device functions due to microcontroller inactivity. The APD unit has a Power Down Mode that helps reduce power consumption. The PSD9XX also has some bits that are configured at run-time by the MCU to reduce power consumption of the PLD. The turbo bit in the PMMR0 register can be turned off and the PLD will latch its outputs and go to sleep until the next transition on its inputs. Additionally, bits in the PMMR2 register can be set by the MCU to block signals from entering the PLD to reduce power consumption. See section 9.5. 8 Preliminary Information 6.0 Development System PSD9XX Family The PSD9XX family is supported by PSDsoft Express, a Windows-based (95, 98, NT) software development tool. A PSD design is quickly and easily produced in a point and click environment. The designer does not need to enter Hardware Definition Language (HDL) equations to define PSD pin functions and memory map information. The general design flow is shown in Figure 2 below. PSDsoft Express is available free from our web site (www.psdst.com) or the Literature CD. PSDsoft Express directly supports two low cost device programmers from ST, PSDpro and FlashLINK (JTAG). Both of these programmers may be purchased through your local rep/distributor, or directly from our web site using a credit card. The PSD9XX is also supported by third party device programmers, see web site for current list. Figure 2. PSDsoft Development Tools Choose MCU and PSD Automatically configures MCU bus interface and other PSD attributes. Define PSD Pin and Node Functions C Code Generation Point and click definition of PSD pin functions, internal nodes, and MCU system memory map. Generate C Code specific to PSD functions. Merge MCU Firmware with PSD Configuration A composite object file is created containing MCU firmware and PSD configuration. MCU Firmware Hex or S-Record Format User's choice of Microcontroller Compiler/Linker *.OBJ File ST PSD Programmer PSDPro or FlashLINK (JTAG) *.OBJ file available for 3rd party programmers. (conventional or JTAG-ISC) 9 PSD9XX Family 7.0 Table 5. PSD9XX Pin Descriptions Preliminary Information The following table describes the pin names and pin functions of the PSD9XX. Pins that have multiple names and/or functions are defined using PSDsoft. Pin Name Pin* Type (PLCC) Description ADIO0-7 I/O This is the lower Address/Data port. Connect your MCU address or address/data bus according to the following rules: 1. If your MCU has a multiplexed address/data bus where the data is multiplexed with the lower address bits, connect AD[0:7] to this port. 2. If your MCU does not have a multiplexed address/data bus, or you are using an 80C251 80C251 in page mode, connect A[0:7] to this port. 3. If you are using an 80C51XA 80C51XA in burst mode, connect A4/D0 through A11/D7 A11/D7 to this port. ALE or AS latches the address. The PSD drives data out only if the read signal is active and one of the PSD functional blocks was selected. The addresses on this port are passed to the PLDs. ADIO8-15 ADIO8-15 39-46 I/O This is the upper Address/Data port. Connect your MCU address or address/data bus according to the following rules: 1. If your MCU has a multiplexed address/data bus where the data is multiplexed with the lower address bits, connect A[8:15] to this port. 2. If your MCU does not have a multiplexed address/data bus, connect A[8:15] to this port. 3. If you are using an 80C251 80C251 in page mode, connect AD[8:15] to this port. 4. If you are using an 80C51XA 80C51XA in burst mode, connect A12/D8 A12/D8 through A19/D15 A19/D15 to this port. ALE or AS latches the address. The PSD drives data out only if the read signal is active and one of the PSD functional blocks was selected. The addresses on this port are passed to the PLDs. CNTL0 47 I The following control signals can be connected to this port, based on your MCU: 1. WR - active-low write input. 2. R_W - active-high read/active low write input. This pin is connected to the PLDs. Therefore, these signals can be used in decode and other logic equations. CNTL1 10 30-37 50 I The following control signals can be connected to this port, based on your MCU: 1. RD - active-low read input. 2. E - E clock input. 3. DS - active-low data strobe input. 4. PSEN - connect PSEN to this port when it is being used as an active-low read signal. For example, when the 80C251 80C251 outputs more than 16 address bits, PSEN is actually the read signal. This pin is connected to the PLDs. Therefore, these signals can be used in decode and other logic equations. Preliminary Information Table 5. PSD9XX Pin Descriptions PSD9XX Family Pin Name Pin* Type (PLCC) Description CNTL2 49 I This pin can be used to input the PSEN (Program Select Enable) signal from any MCU that uses this signal for code exclusively. If your MCU does not output a Program Select Enable signal, this port can be used as a generic input. This port is connected to the PLDs. Reset 48 I Active low reset input. Resets I/O Ports and some of the configuration registers. Must be active at power up. (cont.) PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 29 28 27 25 24 23 22 21 I/O These pins make up Port A. These port pins are configurable and can have the following functions: 1. MCU I/O - write to or read from a standard output or input port. 2. General Purpose PLD outputs. 3. Inputs to the PLDs. 4. Latched address outputs (see Table 6). 5. Address inputs. For example, PA0-3 could be used for A[0:3] when using an 80C51XA 80C51XA in burst mode. 6. As the data bus inputs D[0:7] for non-multiplexed address/data bus MCUs. 7. D0/A16-D3/A19 D0/A16-D3/A19 in M37702M2 M37702M2 mode. Note: PA0-3 can only output CMOS signals with an option for high slew rate. However, PA4-7 can be configured as CMOS or Open Drain Outputs. PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 7 6 5 4 3 2 52 51 I/O These pins make up Port B. These port pins are configurable and can have the following functions: 1. MCU I/O - write to or read from a standard output or input port. 2. General Purpose PLD outputs. 3. Inputs to the PLDs. 4. Latched address outputs (see Table 6). Note: PB0-3 can only output CMOS signals with an option for high slew rate. However, PB4-7 can be configured as CMOS or Open Drain Outputs. PC0 20 I/O PC0 pin of Port C. This port pin can be configured to have the following functions: 1. MCU I/O - write to or read from a standard output or input port. 2. Input to the PLDs. 3. TMS Input for the JTAG Interface. This pin can be configured as a CMOS or Open Drain output. PC1 19 I/O PC1 pin of Port C. This port pin can be configured to have the following functions: 1. MCU I/O - write to or read from a standard output or input port. 2. Input to the PLDs. 3. TCK Input for the JTAG Interface. This pin can be configured as a CMOS or Open Drain output. 11 PSD9XX Family Table 5. PSD9XX Pin Descriptions Preliminary Information Pin Name Pin* Type (PLCC) Description PC2 18 I/O PC2 pin of Port C. This port pin can be configured to have the following functions: 1. MCU I/O - write to or read from a standard output or input port. 2. Input to the PLDs. 3. Vstby - SRAM standby voltage input for SRAM battery backup. This pin can be configured as a CMOS or Open Drain output. PC3 17 I/O PC3 pin of Port C. This port pin can be configured to have the following functions: 1. MCU I/O - write to or read from a standard output or input port. 2. Input to the PLDs. 3. TSTAT output for the JTAG interface. 4. Rdy/Bsy output for in-system parallel programming. This pin can be configured as a CMOS or Open Drain output. PC4 14 I/O PC4 pin of Port C. This port pin can be configured to have the following functions: 1. MCU I/O - write to or read from a standard output or input port. 2. Input to the PLDs. 3. TERR output for the JTAG interface. 4. Vbaton - battery backup indicator output. Goes high when power is being drawn from an external battery. This pin can be configured as a CMOS or Open Drain output. PC5 13 I/O PC5 pin of Port C. This port pin can be configured to have the following functions: 1. MCU I/O - write to or read from a standard output or input port. 2. Input to the PLDs. 3. TDI input for the JTAG interface. This pin can be configured as a CMOS or Open Drain output. PC6 12 I/O PC6 pin of Port C. This port pin can be configured to have the following functions: 1. MCU I/O - write to or read from a standard output or input port. 2. Input to the PLDs. 3. TDO output for the JTAG interface. This pin can be configured as a CMOS or Open Drain output. (cont.) 12 Preliminary Information Table 5. PSD9XX Pin Descriptions PSD9XX Family Pin Name Pin* Type (PLCC) Description PC7 11 I/O PC7 pin of Port C. This port pin can be configured to have the following functions: 1. MCU I/O - write to or read from a standard output or input port. 2. Input to the PLDs. 3. DBE - active-low Data Byte Enable input from 68HC912 68HC912 type MCUs. This pin can be configured as a CMOS or Open Drain output. PD0 10 I/O PD0 pin of Port D. This port pin can be configured to have the following functions: 1. ALE/AS input latches address output from the MCU. 2. MCU I/O - write or read from a standard output or input port. 3. Input to the PLDs. 4. General Purpose PLD output. PD1 9 I/O PD1 pin of Port D. This port pin can be configured to have the following functions: 1. MCU I/O - write to or read from a standard output or input port. 2. Input to the PLDs. 3. General Purpose PLD output 4. CLKIN - clock input to the automatic power-down unit's power-down counter, and the PLD AND array. PD2 8 I/O VCC GND 15, 38 1,16,26 PD2 pin of Port D. This port pin can be configured to have the following functions: 1. MCU I/O - write to or read from a standard output or input port. 2. Input to the PLDs. 3. General Purpose PLD output. 4. CSI - chip select input. When low, the MCU can access the PSD memory and I/O. When high, the PSD memory blocks are disabled to conserve power. Power pins Ground pins (cont.) *The pin numbers in this table are for the PLCC package only. See the package information section for pin numbers on other package types. Table 6. I/O Port Latched Address Output Assignments* Microcontroller Port A Port A (3:0) Port A (7:4) 8051XA 8051XA (8-bit) 80C251 80C251 (page mode) N/A N/A All other 8-bit multiplexed 8-bit non-multiplexed bus Address [3:0] Address [7:4] Address [3:0] Address [7:4] N/A Address [3:0] Address [7:4] Address [7:4] N/A N/A Port B Port B (3:0) Port B (7:4) Address [11:8] N/A Address [11:8] Address [15:12] N/A = Not Applicable * Refer to the I/O Port Section on how to enable the Latched Address Output function. 13 PSD9XX Family 8.0 PSD9XX Register Description and Address Offset Preliminary Information Table 7 shows the offset addresses to the PSD9XX registers relative to the CSIOP base address. The CSIOP space is the 256 bytes of address that is allocated by the user to the internal PSD9XX registers. Table 7 provides brief descriptions of the registers in CSIOP space. For a more detailed description, refer to section 9. Table 7. Register Address Offset Register Name Port A Port B Port C Port D Other* Reads Port pin as input, MCU I/O input mode Data In 00 01 Control 02 03 Data Out 04 05 12 13 Stores data for output to Port pins, MCU I/O output mode Direction 06 07 14 15 Configures Port pin as input or output 17 Configures Port pins as either CMOS or Open Drain on some pins, while selecting high slew rate on other pins. Drive Select 08 09 10 Description 11 Selects mode between MCU I/O or Address Out 16 Flash Protection C0 Read only ­ Flash Sector Protection Secondary Flash Protection C2 Read only ­ PSD Security and Secondary Flash Sector Protection PMMR0 B0 Power Management Register 0 PMMR2 B4 Power Management Register 2 Page E0 Page Register E2 Places PSD memory areas in Program and/or Data space on an individual basis. VM *Other registers that are not part of the I/O ports. 14 Preliminary Information 9.0 The PSD9XX Functional Blocks PSD9XX Family As shown in Figure 1, the PSD9XX consists of six major types of functional blocks: t t t t t t Memory Blocks PLD Blocks Bus Interface I/O Ports Power Management Unit JTAG Interface The functions of each block are described in the following sections. Many of the blocks perform multiple functions, and are user configurable. 9.1 Memory Blocks The PSD9XX has the following memory blocks: · The main Flash memory · Secondary Flash memory · SRAM. The memory select signals for these blocks originate from the Decode PLD (DPLD) and are user-defined in PSDsoft. Table 8 summarizes which versions of the PSD9XX contain which memory blocks. Table 8. Memory Blocks Device Main Flash Flash Size Sector Size Secondary Flash Block Block Size Sector Size SRAM PSD913F2 PSD913F2 128KB 128KB 16KB 32KB 8KB 2KB PSD934F2 PSD934F2 256KB 256KB 32KB 32KB 8KB 8KB PSD954F2 PSD954F2 256KB 256KB 32KB 32KB 8KB 32KB 9.1.1 Main Flash and Secondary Flash Memory Description The main Flash memory block is divided evenly into eight sectors. The secondary Flash memory is divided into four sectors of eight Kbytes each. Each sector of either memory can be separately protected from program and erase operations. Flash memory may be erased on a sector-by-sector basis and programmed byte-by-byte. Flash sector erasure may be suspended while data is read from other sectors of memory and then resumed after reading. During a program or erase of Flash, the status can be output on the Rdy/Bsy pin of Port C3. This pin is set up using PSDsoft. 15 PSD9XX Family The PSD9XX Functional Blocks (cont.) Preliminary Information 9.1.1.1 Memory Block Selects The decode PLD in the PSD9XX generates the chip selects for all the internal memory blocks (refer to the PLD section). Each of the eight Flash memory sectors have a Flash Select signal (FS0-FS7) which can contain up to three product terms. Each of the four secondary Flash memory sectors have a Select signal (CSBOOT0-3) which can contain up to three product terms. Having three product terms for each sector select signal allows a given sector to be mapped in different areas of system memory. When using a microcontroller with separate Program and Data space, these flexible select signals allow dynamic re-mapping of sectors from one space to the other when used with the VM Register (see section 9.1.3.1). 9.1.1.2 The Ready/Busy Pin (PC3) Pin PC3 can be used to output the Ready/Busy status of the PSD9XX. The output on the pin will be a `0' (Busy) when Flash memory blocks are being written to, or when the Flash memory block is being erased. The output will be a `1' (Ready) when no write or erase operation is in progress. 9.1.1.3 Memory Operation The main Flash and secondary Flash memories are addressed through the microcontroller interface on the PSD9XX device. The microcontroller can access these memories in one of two ways: t The microcontroller can execute a typical bus write or read operation just as it would if accessing a RAM or ROM device using standard bus cycles. t The microcontroller can execute a specific instruction that consists of several write and read operations. This involves writing specific data patterns to special addresses within the Flash to invoke an embedded algorithm. These instructions are summarized in Table 9. Typically, Flash memory can be read by the microcontroller using read operations, just as it would read a ROM device. However, Flash memory can only be erased and programmed with specific instructions. For example, the microcontroller cannot write a single byte directly to Flash memory as one would write a byte to RAM. To program a byte into Flash memory, the microcontroller must execute a program instruction sequence, then test the status of the programming event. This status test is achieved by a read operation or polling the Rdy/Busy pin (PC3). The Flash memory can also be read by using special instructions to retrieve particular Flash device information (sector protect status and ID). 16 Preliminary Information The PSD9XX Functional Blocks (cont.) PSD9XX Family 9.1.1.3.1 Instructions An instruction is defined as a sequence of specific operations. Each received byte is sequentially decoded by the PSD and not executed as a standard write operation. The instruction is executed when the correct number of bytes are properly received and the time between two consecutive bytes is shorter than the time-out value. Some instructions are structured to include read operations after the initial write operations. The sequencing of any instruction must be followed exactly. Any invalid combination of instruction bytes or time-out between two consecutive bytes while addressing Flash memory will reset the device logic into a read array mode (Flash memory reads like a ROM device). The PSD9XX main Flash and Secondary Flash support these instructions (see Table 9): t t t t t t t Erase memory by chip or sector Suspend or resume sector erase Program a byte Reset to read array mode Read Main Flash Identifier value Read sector protection status Bypass Instruction (PSD934F2 PSD934F2 and PSD954F2 PSD954F2 only) These instructions are detailed in Table 9. For efficient decoding of the instructions, the first two bytes of an instruction are the coded cycles and are followed by a command byte or confirmation byte. The coded cycles consist of writing the data AAh to address X555h during the first cycle and data 55h to address XAAAh during the second cycle. Address lines A15-A12 A15-A12 are don't care during the instruction write cycles. However, the appropriate sector select signal (FSi or CSBOOTi) must be selected. The main Flash and the Secondary Flash Block have the same set of instructions (except Read main Flash ID). The chip selects of the Flash memory will determine which Flash will receive and execute the instruction. The main Flash is selected if any one of the FS0-7 is active, and the secondary Flash Block is selected if any one of the CSBOOT0-3 is active. 17 PSD9XX Family The PSD9XX Functional Blocks Preliminary Information Table 9. Instructions Instruction FS0-7 or CSBOOT0-3 Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle5 Cycle 6 Cycle 7 AAh @555h 55h @AAAh 30h @SA 30h @next SA (Note 7) AAh @555h 55h @AAAh 10h @555h 1 "Read" RA RD Read Main Flash ID (Notes 6,13) 1 AAh @555h 55h @AAAh 90h @555h "Read" ID @x01h Read Sector Protection (Notes 6,8,13) 1 AAh @555h 55h @AAAh 90h @555h "Read" 00h or 01h @x02h Program a Flash Byte 1 AAh @555h 55h @AAAh A0h @555h PD@PA Erase One Flash Sector 1 AAh @555h 55h @AAAh 80h @555h Erase Flash Block (Bulk Erase) 1 AAh @555h 55h @AAAh 80h @555h Suspend Sector Erase (Note 11) 1 B0h @xxxh Resume Sector Erase (Note 12) 1 30h @xxxh Reset (Note 6) 1 F0 @ any address Unlock Bypass (Note 14) 1 AAh @555h 55h @AAAh 20h @555h Unlock Bypass Program (Note 9,14) 1 A0h @xxxh PD@PA Unlock Bypass Reset (Note 10,14) (cont.) Read (Note 5) 1 90h @xxxh 00h @xxxh X RA RD PA = = = = Don't Care. Address of the memory location to be read. Data read from location RA during read operation. Address of the memory location to be programmed. Addresses are latched on the falling edge of the WR# (CNTL0) pulse. PD = Data to be programmed at location PA. Data is latched o the rising edge of WR# (CNTL0) pulse. SA = Address of the sector to be erased or verified. The chip select (FS0-7 or CSBOOT0-3) of the sector to be erased must be active (high). NOTES: 1. All bus cycles are write bus cycle except the ones with the "read" label. 2. All values are in hexadecimal. 3. FS0-7 and CSBOOT0-3 are active high and are defined in PSDsoft. 4. Only Address bits A11-A0 A11-A0 are used in Instruction decoding. A15-12 A15-12 (or A16-A12 A16-A12) are don't care. 5. No unlock or command cycles required when device is in read mode. 6. The Reset command is required to return to the read mode after reading the Flash ID, Sector Protect status or if DQ5 (error flag) goes high. 7. Additional sectors to be erased must be entered within 80µs. 8. The data is 00h for an unprotected sector and 01h for a protected sector. In the fourth cycle, the sector chip select is active and (A1 = 1, A0 = 0). 9. The Unlock Bypass command is required prior to the Unlock Bypass Program command. 10. The Unlock Bypass Reset command is required to return to reading array data when the device is in the Unlock Bypass mode. 11. The system may read and program functions in non-erasing sectors, read the Flash ID or read the Sector Protect status, when in the Erase Suspend mode. The erase Suspend command is valid only during a sector erase operation. 12. The Erase Resume command is valid only during the Erase Suspend mode. 13. The MCU cannot invoke these instructions while executing code from the same Flash memory for which the instruction is intended. The MCU must fetch, for example, codes from the secondary block when reading the Sector Protection Status of the main Flash. 14. Available to PSD934F2 PSD934F2 and PSD954F2 PSD954F2 devices only. 18 Preliminary Information The PSD9XX Functional Blocks (cont.) PSD9XX Family 9.1.1.4 Power-Up Condition The PSD9XX Flash memory is reset upon power-up to the read array mode. The FSi and CSBOOTi select signals, along with the write strobe signal, must be in the false state during power-up for maximum security of the data contents and to remove the possibility of a byte being written on the first edge of a write strobe signal. Any write cycle initiation is locked when VCC is below VLKO. 9.1.1.5 Read Under typical conditions, the microcontroller may read the Flash, or Secondary Flash memories using read operations just as it would a ROM or RAM device. Alternately, the microcontoller may use read operations to obtain status information about a program or erase operation in progress. Lastly, the microcontroller may use instructions to read special data from these memories. The following sections describe these read functions. 9.1.1.5.1 Read the Contents of Memory Main Flash and Secondary Flash memories are placed in the read array mode after power-up, chip reset, or a Reset Flash instruction (see Table 9). The microcontroller can read the memory contents of main Flash or Secondary Flash by using read operations any time the read operation is not part of an instruction sequence. 9.1.1.5.2 Read the Main Flash Memory Identifier The main Flash memory identifier is read with an instruction composed of 4 operations: 3 specific write operations and a read operation (see Table 9). During the read operation, address bits A6, A1, and A0 must be 0,0,1, respectively, and the appropriate sector select signal (FSi) must be active. The PSD9XX main Flash memory ID is E7h (PSD934/954F2 PSD934/954F2) and E4h (PSD913F2 PSD913F2). 9.1.1.5.3 Read the Flash Memory Sector Protection Status The Flash memory sector protection status is read with an instruction composed of 4 operations: 3 specific write operations and a read operation (see Table 9). During the read operation, address bits A6, A1, and A0 must be 0,1,0, respectively, while the chip select (FSi or CSBOOTi) designates the Flash sector whose protection has to be verified. The read operation will produce 01h if the Flash sector is protected, or 00h if the sector is not protected. The sector protection status for all NVM blocks (main Flash or Secondary Flash) can also be read by the microcontroller accessing the Flash Protection and Secondary Flash Protection registers in PSD I/O space. See section 9.1.1.9.1 for register definitions. 9.1.1.5.4 Read the Erase/Program Status Bits The PSD9XX provides several status bits to be used by the microcontroller to confirm the completion of an erase or programming instruction of Flash memory. These status bits minimize the time that the microcontroller spends performing these tasks and are defined in Table 10. The status bits can be read as many times as needed. Table 10. Status Bits FSi/ CSBOOTi Flash VIH DQ7 Data Polling DQ6 Toggle Flag DQ5 Error Flag DQ4 DQ3 DQ2 DQ1 DQ0 X Erase Timeout X X X NOTES: 1. X = Not guaranteed value, can be read either 1 or 0. 2. DQ7-DQ0 represent the Data Bus bits, D7-D0. 3. FSi/CSBOOTi are active high. For Flash memory, the microcontroller can perform a read operation to obtain these status bits while an erase or program instruction is being executed by the embedded algorithm. See section 9.1.1.7 for details. 19 PSD9XX Family The PSD9XX Functional Blocks (cont.) Preliminary Information 9.1.1.5.5 Data Polling Flag DQ7 When Erasing or Programming the Flash memory bit DQ7 outputs the complement of the bit being entered for Programming/Writing on DQ7. Once the Program instruction or the Write operation is completed, the true logic value is read on DQ7 (in a Read operation). Flash memory specific features: t Data Polling is effective after the fourth Write pulse (for programming) or after the t t t sixth Write pulse (for Erase). It must be performed at the address being programmed or at an address within the Flash sector being erased. During an Erase instruction, DQ7 outputs a `0'. After completion of the instruction, DQ7 will output the last bit programmed (it is a `1' after erasing). If the byte to be programmed is in a protected Flash sector, the instruction is ignored. If all the Flash sectors to be erased are protected, DQ7 will be set to `0' for about 100 µs, and then return to the previous addressed byte. No erasure will be performed. 9.1.1.5.6 Toggle Flag DQ6 The PSD9XX offers another way for determining when the Flash memory Program instruction is completed. During the internal Write operation and when either the FSi or CSBOOTi is true, the DQ6 will toggle from `0' to `1' and `1' to `0' on subsequent attempts to read any byte of the memory. When the internal cycle is complete, the toggling will stop and the data read on the Data Bus D0-7 is the addressed memory byte. The device is now accessible for a new Read or Write operation. The operation is finished when two successive reads yield the same output data. Flash memory specific features: t The Toggle bit is effective after the fourth Write pulse (for programming) or after the t t sixth Write pulse (for Erase). If the byte to be programmed belongs to a protected Flash sector, the instruction is ignored. If all the Flash sectors selected for erasure are protected, DQ6 will toggle to `0' for about 100 µs and then return to the previous addressed byte. 9.1.1.5.7 Error Flag DQ5 During a correct Program or Erase, the Error bit will set to `0'. This bit is set to `1' when there is a failure during Flash byte programming, Sector erase, or Bulk Erase. In the case of Flash programming, the Error Bit indicates the attempt to program a Flash bit(s) from the programmed state (0) to the erased state (1), which is not a valid operation. The Error bit may also indicate a timeout condition while attempting to program a byte. In case of an error in Flash sector erase or byte program, the Flash sector in which the error occurred or to which the programmed byte belongs must no longer be used. Other Flash sectors may still be used. The Error bit resets after the Reset instruction. 9.1.1.5.8 Erase Time-out Flag DQ3 The Erase Timer bit reflects the time-out period allowed between two consecutive Sector Erase instructions. The Erase timer bit is set to `0' after a Sector Erase instruction for a time period of 100 µs + 20% unless an additional Sector Erase instruction is decoded. After this time period or when the additional Sector Erase instruction is decoded, DQ3 is set to `1'. 20 Preliminary Information The PSD9XX Functional Blocks (cont.) PSD9XX Family 9.1.1.6 Programming Flash Memory Flash memory must be erased prior to being programmed. The MCU may erase Flash memory all at once or by-sector, but not byte-by-byte. A byte of Flash memory erases to all logic ones (FF hex), and its bits are programmed to logic zeros. Although erasing Flash memory occurs on a sector basis, programming Flash memory occurs on a byte basis. The PSD9XX main Flash and Secondary Flash memories require the MCU to send an instruction to program a byte or perform an erase function (see Table 9). Once the MCU issues a Flash memory program or erase instruction, it must check for the status of completion. The embedded algorithms that are invoked inside the PSD9XX support several means to provide status to the MCU. Status may be checked using any of three methods: Data Polling, Data Toggle, or the Ready/Busy output pin. 9.1.1.6.1 Data Polling Polling on DQ7 is a method of checking whether a Program or Erase instruction is in progress or has completed. Figure 3 shows the Data Polling algorithm. When the MCU issues a programming instruction, the embedded algorithm within the PSD9XX begins. The MCU then reads the location of the byte to be programmed in Flash to check status. Data bit DQ7 of this location becomes the compliment of data bit 7of the original data byte to be programmed. The MCU continues to poll this location, comparing DQ7 and monitoring the Error bit on DQ5. When the DQ7 matches data bit 7 of the original data, and the Error bit at DQ5 remains `0', then the embedded algorithm is complete. If the Error bit at DQ5 is `1', the MCU should test DQ7 again since DQ7 may have changed simultaneously with DQ5 (see Figure 3). The Error bit at DQ5 will be set if either an internal timeout occurred while the embedded algorithm attempted to program the byte or if the MCU attempted to program a `1' to a bit that was not erased (not erased is logic `0'). It is suggested (as with all Flash memories) to read the location again after the embedded programming algorithm has completed to compare the byte that was written to Flash with the byte that was intended to be written. When using the Data Polling method after an erase instruction, Figure 3 still applies. However, DQ7 will be `0' until the erase operation is complete. A `1' on DQ5 will indicate a timeout failure of the erase operation, a `0' indicates no error. The MCU can read any location within the sector being erased to get DQ7 and DQ5. PSDsoft will generate ANSI C code functions which implement these Data Polling algorithms. 21 PSD9XX Family The PSD9XX Functional Blocks Preliminary Information Figure 3. Data Polling Flow Chart START (cont.) READ DQ5 & DQ7 at Valid Address DQ7 = DATA7 YES NO NO DQ5 =1 YES READ DQ7 DQ7 = DATA YES NO FAIL Program/Erase Operation Not Complete, Issue Reset Instruction PASS Program/Erase Operation is Complete 9.1.1.6.2 Data Toggle Checking the Data Toggle bit on DQ6 is a method of determining whether a Program or Erase instruction is in progress or has completed. Figure 4 shows the Data Toggle algorithm. When the MCU issues a programming instruction, the embedded algorithm within the PSD9XX begins. The MCU then reads the location of the byte to be programmed in Flash to check status. Data bit DQ6 of this location will toggle each time the MCU reads this location until the embedded algorithm is complete. The MCU continues to read this location, checking DQ6 and monitoring the Error bit on DQ5. When DQ6 stops toggling (two consecutive reads yield the same value), and the Error bit on DQ5 remains `0', then the embedded algorithm is complete. If the Error bit on DQ5 is `1', the MCU should test DQ6 again, since DQ6 may have changed simultaneously with DQ5 (see Figure 4). The Error bit at DQ5 will be set if either an internal timeout occurred while the embedded algorithm attempted to program the byte, or if the MCU attempted to program a `1' to a bit that was not erased (not erased is logic `0'). 22 Preliminary Information PSD9XX Family The PSD9XX Functional Blocks 9.1.1.6.2 Data Toggle (cont.) It is suggested (as with all Flash memories) to read the location again after the embedded programming algorithm has completed to compare the byte that was written to Flash with the byte that was intended to be written. (cont.) When using the Data Toggle method after an erase instructin, Figure 4 still applies. DQ6 will toggle until the erase operation is complete. A `1' on DQ5 will indicate a timeout failure of the erase operation, a `0' indicates no error. The MCU can read any location within the sector being erased to get DQ6 and DQ5. PSDsoft will generate ANSI C code functions which implement these Data Toggling algorithms. Figure 4. Data Toggle Flow Chart START READ DQ5 & DQ6 DQ6 = TOGGLE NO YES NO DQ5 =1 YES READ DQ6 DQ6 = TOGGLE NO YES FAIL Program/Erase Operation Not Complete, Issue Reset Instruction PASS Program/Erase Operation is Complete 23 PSD9XX Family The PSD9XX Functional Blocks (cont.) Preliminary Information 9.1.1.7 Unlock Bypass Instruction (PSD934F2 PSD934F2 and PSD954F2 PSD954F2 only) The unlock bypass feature allows the system to program bytes to the flash memories faster than using the standard program instruction. The unlock bypass instruction is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h (see Table 9). The flash memory then enters the unlock bypass mode. A two-cycle Unlock Bypass Program instruction is all that is required to program in this mode. The first cycle in this instruction contains the unlock bypass programm command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles requiredc in the standard program instruction, resulting in faster total programming time. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset instructions are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset instruction. The first cycle must contain the data 90h; the second cycle the data 00h. Addresses are don't care for both cycles. The falsh memory then returns to reading array data mode. 9.1.1.8 Erasing Flash Memory 9.1.1.8.1. Flash Bulk Erase Instruction The Flash Bulk Erase instruction uses six write operations followed by a Read operation of the status register, as described in Table 9. If any byte of the Bulk Erase instruction is wrong, the Bulk Erase instruction aborts and the device is reset to the Read Flash memory status. During a Bulk Erase, the memory status may be checked by reading status bits DQ5, DQ6, and DQ7, as detailed in section 9.1.1.6. The Error bit (DQ5) returns a `1' if there has been an Erase Failure (maximum number of erase cycles have been executed). It is not necessary to program the array with 00h because the PSD9XX will automatically do this before erasing to 0FFh. During execution of the Bulk Erase instruction, the Flash memory will not accept any instructions. 9.1.1.8.2 Flash Sector Erase Instruction The Sector Erase instruction uses six write operations, as described in Table 9. Additional Flash Sector Erase confirm commands and Flash sector addresses can be written subsequently to erase other Flash sectors in parallel, without further coded cycles, if the additional instruction is transmitted in a shorter time than the timeout period of about 100 µs. The input of a new Sector Erase instruction will restart the time-out period. The status of the internal timer can be monitored through the level of DQ3 (Erase time-out bit). If DQ3 is `0', the Sector Erase instruction has been received and the timeout is counting. If DQ3 is `1', the timeout has expired and the PSD9XX is busy erasing the Flash sector(s). Before and during Erase timeout, any instruction other than Erase suspend and Erase Resume will abort the instruction and reset the device to Read Array mode. It is not necessary to program the Flash sector with 00h as the PSD9XX will do this automatically before erasing (byte=FFh). During a Sector Erase, the memory status may be checked by reading status bits DQ5, DQ6, and DQ7, as detailed in section 9.1.1.6. During execution of the erase instruction, the Flash block logic accepts only Reset and Erase Suspend instructions. Erasure of one Flash sector may be suspended, in order to read data from another Flash sector, and then resumed. 24 Preliminary Information The PSD9XX Functional Blocks (cont.) PSD9XX Family 9.1.1.8.3 Flash Erase Suspend Instruction When a Flash Sector Erase operation is in progress, the Erase Suspend instruction will suspend the operation by writing 0B0h to any address when an appropriate Chip Select (FSi or CSBOOTi) is true. (See Table 9). This allows reading of data from another Flash sector after the Erase operation has been suspended. Erase suspend is accepted only during the Flash Sector Erase instruction execution and defaults to read array mode. An Erase Suspend instruction executed during an Erase timeout will, in addition to suspending the erase, terminate the time out. The Toggle Bit DQ6 stops toggling when the PSD9XX internal logic is suspended. The toggle Bit status must be monitored at an address within the Flash sector being erased. The Toggle Bit will stop toggling between 0.1 µs and 15 µs after the Erase Suspend instruction has been executed. The PSD9XX will then automatically be set to Read Flash Block Memory Array mode. If an Erase Suspend instruction was executed, the following rules apply: · Attempting to read from a Flash sector that was being erased will output invalid data. · Reading from a Flash sector that was not being erased is valid. · The Flash memory cannot be programmed, and will only respond to Erase Resume and Reset instructions (read is an operation and is OK). · If a Reset instruction is received, data in the Flash sector that was being erased will be invalid. 9.1.1.8.4 Flash Erase Resume Instruction If an Erase Suspend instruction was previously executed, the erase operation may be resumed by this instruction. The Erase Resume instruction consists of writing 030h to any address while an appropriate Chip Select (FSi or CSBOOTi) is true. (See Table 9.) 9.1.1.9 Specific Features 9.1.1.9.1 Flash and Secondary Flash Sector Protect Each Flash and Secondary Flash sector can be separately protected against Program and Erase functions. Sector Protection provides additional data security because it disables all program or erase operations. This mode can be activated through the JTAG Port or a Device Programmer. Sector protection can be selected for each sector using the PSDsoft Configuration program. This will automatically protect selected sectors when the device is programmed through the JTAG Port or a Device Programmer. Flash sectors can be unprotected to allow updating of their contents using the JTAG Port or a Device Programmer. The microcontroller can read (but cannot change) the sector protection bits. Any attempt to program or erase a protected Flash sector will be ignored by the device. The Verify operation will result in a read of the protected data. This allows a guarantee of the retention of the Protection status. The sector protection status can be read by the MCU through the Flash protection and Secondary Flash protection registers (CSIOP). See Table 11. 25 PSD9XX Family The PSD9XX Functional Blocks (cont.) Preliminary Information Table 11. Sector Protection/Security Bit Definition Flash Protection Register Bit 7 Sec7_Prot Bit 6 Bit 5 Bit 4 Sec6_Prot Sec5_Prot Sec4_Prot Bit Definitions: Sec_Prot Sec_Prot Bit 3 Bit 2 Bit 1 Bit 0 Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot 1 = Main Flash Sector is write protected. 0 = Main Flash Sector is not write protected. Secondary Flash Protection Register Bit 7 Bit 5 Bit 4 Security_ Bit *: Bit 6 * * * Bit 3 Bit 2 Bit 1 Bit 0 Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot Not used. Bit Definitions: Sec_Prot Sec_Prot Security_Bit 1 = Secondary Flash Sector is write protected. 0 = Secondary Flash Sector is not write protected. 0 = Security Bit in device has not been set. 1 = Security Bit in device has been set. 9.1.1.9.2 Reset Instruction ­ PSD913F2 PSD913F2 The Reset instruction consists of one write cycle (see Table 9). It can also be optionally preceded by the standard two write decoding cycles (writing AAh to 555h and 55h to AAAh). The Reset instruction must be executed after: 1. Reading the Flash Protection status or Flash ID 2. When an error condition occurs (DQ5 goes high) during a Flash programming or erase cycle. The Reset instruction will reset the Flash to normal Read Mode. It may take the Flash memory up to few msec to complete the reset cycle. The Reset instruction is ignored when it is issued during a Flash programming or Bulk Erase cycle. During Sector Erase cycle, the Reset instruction will abort the on going sector erase cycle and return the Flash to normal Read Mode in up to few msec. 9.1.1.9.3 Reset Instruction ­ PSD934F2 PSD934F2, PSD954F2 PSD954F2 The Reset instruction consists of one write cycle (see Table 9). It can also be optionally preceded by the standard two write decoding cycles (writing AAh to 555h and 55h to AAAh). The Reset instruction must be executed after: 1. Reading the Flash Protection status or Flash ID 2. When an error condition occurs (DQ5 goes high) during a Flash programming or erase cycle. The Reset instruction will immediately reset the Flash to normal Read Mode. However, if there is an error condition (DQ5 goes high), the Flash memory will return to the Read Mode in 25 µsec after the Reset instruction is issued. The Reset instruction is ignored when it is issued during a Flash programming or Bulk Erase cycle. The Reset instruction will abort the on going sector erase cycle and return the Flash memory to normal Read Mode in 25 µsec. 26 Preliminary Information The PSD9XX Functional Blocks (cont.) PSD9XX Family 9.1.1.9.4 Reset Pin Input ­ PSD934F2 PSD934F2, PSD954F2 PSD954F2 The reset pulse input from the pin will abort any operation in progress and reset the Flash memory to Read Mode. When the reset occurs during a programming or erase cycle, the Flash memory will take up to 25 µsec to return to Read Mode. It is recommended that the reset pulse (except power on reset, see Reset Section) be at least 25 µSec such that the Flash memory will always be ready for the MCU to fetch the boot codes after reset is over. 9.1.2 SRAM The SRAM is enabled when RS0- the SRAM chip select output from the DPLD- is high. RS0 can contain up to two product terms, allowing flexible memory mapping. The SRAM can be backed up using an external battery. The external battery should be connected to the Vstby pin (PC2). If you have an external battery connected to the PSD9XX, the contents of the SRAM will be retained in the event of a power loss. The contents of the SRAM will be retained so long as the battery voltage remains at 2V or greater. If the supply voltage falls below the battery voltage, an internal power switchover to the battery occurs. Pin PC4 can be configured as an output that indicates when power is being drawn from the external battery. This Vbaton signal will be high with the supply voltage falls below the battery voltage and the battery on PC2 is supplying power to the internal SRAM. The chip select signal (RS0) for the SRAM, Vstby, and Vbaton are all configured using PSDsoft. 9.1.3 Memory Select Signals The main Flash (FSi), Secondary Flash (CSBOOTi), and SRAM (RS0) memory select signals are all outputs of the DPLD. They are setup by entering equations for them in PSDsoft. The following rules apply to the equations for the internal chip select signals: 1. Main Flash memory and Secondary Flash memory sector select signals must not be larger than the physical sector size. 2. Any main Flash memory sector must not be mapped in the same memory space as another Main Flash sector. 3. A Secondary Flash memory sector must not be mapped in the same memory space as another Secondary Flash sector. 4. SRAM, I/O, and Peripheral I/O spaces must not overlap. 5. A Secondary Flash memory sector may overlap a main Flash memory sector. In case of overlap, priority will be given to the Secondary Flash sector. 6. SRAM, I/O, and Peripheral I/O spaces may overlap any other memory sector. Priority will be given to the SRAM, I/O, or Peripheral I/O. Example FS0 is valid when the address is in the range of 8000h to BFFFh, CSBOOT0 is valid from 8000h to 9FFFh, and RS0 is valid from 8000h to 87FFh. Any address in the range of RS0 will always access the SRAM. Any address in the range of CSBOOT0 greater than 87FFh (and less than 9FFFh) will automatically address Boot memory segment 0. Any address greater than 9FFFh will access the Flash memory segment 0. You can see that half of the Flash memory segment 0 and one-fourth of Boot segment 0 can not be accessed in this example. Also note that an equation that defined FS1 to anywhere in the range of 8000h to BFFFh would not be valid. Figure 5 shows the priority levels for all memory components. Any component on a higher level can overlap and has priority over any component on a lower level. Components on the same level must not overlap. Level one has the highest priority and level 3 has the lowest. 27 PSD9XX Family The PSD9XX Functional Blocks Preliminary Information Figure 5. Priority Level of Memory and I/O Components Highest Priority (cont.) Level 1 SRAM, I /O Level 2 Secondary Flash Memory Level 3 Main Flash Memory Lowest Priority 9.1.3.1. Memory Select Configuration for MCUs with Separate Program and Data Spaces The 8031 and compatible family of microcontrollers, which includes the 80C51 80C51, 80C151 80C151, 80C251 80C251, 80C51XA 80C51XA, and the C500 family have separate address spaces for code memory (selected using PSEN) and data memory (selected using RD). Any of the memories within the PSD9XX can reside in either space or both spaces. This is controlled through manipulation of the VM register that resides in the PSD's CSIOP space. The VM register is set using PSDsoft to have an initial value. It can subsequently be changed by the microcontroller so that memory mapping can be changed on-the-fly. For example, you may wish to have SRAM and Flash in Data Space at boot, and Boot Block in Program Space at boot, and later swap Boot Block and Flash. This is easily done with the VM register by using PSDsoft to configure it for boot up and having the microcontroller change it when desired. Table 13 describes the VM Register. Table 13. VM Register Bit 7* Bit 6* Bit 5* Bit 4 Bit 3 FL_Data Boot_Data Bit 2 FL_Code Bit 1 Bit 0 Boot_Code SRAM_Code * * * 0 = RD can't access Flash 0 = RD can't access Secondary Flash 0 = PSEN can't access Flash 0 = PSEN can't access Secondary Flash 0 = PSEN can't access SRAM * * * 1 = RD access Flash 1 = RD access Secondary Flash 1 = PSEN 1 = PSEN access access Flash Secondary Flash 1 = PSEN access SRAM NOTE: Bits 5-7 are not used, should set to "0". 28 Preliminary Information The PSD9XX Functional Blocks (cont.) PSD9XX Family 9.1.3.2 Configuration Modes for MCUs with Separate Program and Data Spaces 9.1.3.2.1 Separate Space Modes Code memory space is separated from data memory space. For example, the PSEN signal is used to access the program code from the Flash Memory, while the RD signal is used to access data from the Boot memory, SRAM and I/O Ports. This configuration requires the VM register to be set to 0Ch. 9.1.3.2.2 . Combined Space Modes The program and data memory spaces are combined into one space that allows the main Flash Memory, Boot memory, and SRAM to be accessed by either PSEN or RD. For example, to configure the main Flash memory in combined space mode, bits 2 and 4 of the VM register are set to "1". 9.1.3.3 80C31 80C31 Memory Map Example See Application Note for examples. Figure 6. 8031 Memory Modes ­ Separate Space Mode DPLD SRAM SECONDARY FLASH BLOCK MAIN FLASH RS0 CSBOOT0-3 FS0-7 CS CS OE CS OE OE PSEN RD Figure 7. 80C31 80C31 Memory Mode ­ Combined Space Mode DPLD RD RS0 SECONDARY FLASH BLOCK MAIN FLASH SRAM CSBOOT0-3 FS0-7 CS CS OE CS OE OE VM REG BIT 3 VM REG BIT 4 PSEN VM REG BIT 1 VM REG BIT 2 RD VM REG BIT 0 29 PSD9XX Family The PSD9XX Functional Blocks (cont.) Preliminary Information 9.1.4 Page Register The eight bit Page Register increases the addressing capability of the microcontroller by a factor of up to 256. The contents of the register can also be read by the microcontroller. The outputs of the Page Register (PGR0-PGR7) are inputs to the PLD and can be included in the Flash Memory, Secondary Flash Block, and SRAM chip select equations. If memory paging is not needed, or if not all 8 page register bits are needed for memory paging, then these bits may be used in the PLD for general logic. See Application Note. Figure 8 shows the Page Register. The eight flip flops in the register are connected to the internal data bus D0-D7. The microcontroller can write to or read from the Page Register. The Page Register can be accessed at address location CSIOP + E0h. Figure 8. Page Register RESET D0 Q0 D1 D2 Q2 D3 D0 - D7 Q1 Q3 D4 Q4 D5 PGR2 PGR3 PGR4 DPLD AND GPLD Q6 D7 INTERNAL SELECTS AND LOGIC PGR1 Q5 D6 PGR0 Q7 PGR5 PGR6 PGR7 R/W PAGE REGISTER 30 FLASH PLDs Preliminary Information PSD9XX Family The PSD9XX Functional Blocks 9.2 PLDs (cont.) The PSD9XX contains two PLDs: the Decode PLD (DPLD), and the General Purpose PLD (GPLD). The PLDs are briefly discussed in the next few paragraphs, and in more detail in sections 9.2.1 and 9.2.2. Figure 10 shows the configuration of the PLDs. The PLDs bring programmable logic functionality to the PSD9XX. After specifying the chip selects or logic equations for the PLDs in PSDsoft, the logic is programmed into the device and available upon power-up. The DPLD performs address decoding for internal components, such as memory, registers, and I/O port selects. The GPLD can be used to generate external chip selects, control signals or logic functions. The GPLD has 19 outputs that are connected to Ports A, B and D. The AND array is used to form product terms. These product terms are specified using PSsoft. An Input Bus consisting of 57 signals is connected to the PLDs. The signals are shown in Table 15. The complement of the 57 signals are also available as input to the AND array. Table 15. DPLD and GPLD Inputs Input Source Input Name Number of Signals MCU Address Bus A[15:0]* 16 MCU Control Signals CNTL[2:0] 3 Reset RST 1 Power Down PDN 1 Port A Input PA[7-0] 8 Port B Input PB[7-0] 8 Port C Input PC[7-0] 8 Port D Inputs PD[2:0] 3 Page Register PGR(7:0) 8 Flash Programming Status Bit Rdy/Bsy 1 NOTE: The address inputs are A[19:4] in 80C51XA 80C51XA mode. The Turbo Bit The PLDs in the PSD9XX can minimize power consumption by switching off when inputs remain unchanged for an extended time of about 70 ns. Setting the Turbo mode bit to off (Bit 3 of the PMMR0 register) automatically places the PLDs into standby if no inputs are changing. Turbo-off mode increases propagation delays while reducing power consumption. Refer to the Power Management Unit section on how to set the Turbo Bit. Additionally, five bits are available in the PMMR2 register to block MCU control signals from entering the PLDs. This reduces power consumption and can be used only when these MCU control signals are not used in PLD logic equations. 31 PSD9XX Family Preliminary Information Figure 9. PLD Block Diagrams 8 PAGE REGISTER DATA BUS 8 DECODE PLD 57 FLASH MEMORY SELECTS 4 SECONDARY FLASH MEMORY SELECTS 1 SRAM SELECT PLD INPUT BUS 1 CSIOP SELECT GENERAL PURPOSE PLD GPLD PLD OUT 8 PLD OUT 8 PLD OUT 3 PORT A 57 PORT B PORT D PORT C PLD INPUT 8 PORT A PLD INPUT 8 PORT B PLD INPUT 8 PORT D PLD INPUT 3 PORT C Figure 10. DPLD Logic Array 3 CSBOOT 0 3 CSBOOT 1 3 CSBOOT 2 3 CSBOOT 3 3 4 SECONDARY FLASH MEMORY SECTOR SELECTS FS0 3 (INPUTS) I /O PORTS (PORT A,B,C) 3 (24) 3 PGR0 - PGR7 8 FLASH MEMORY SECTOR SELECTS (8) 3 A[15:0] * (16) 3 PD[2:0] (ALE,CLKIN,CSI) (3) PDN (APD OUTPUT) (1) CNTRL[2:0] (READ/WRITE CONTROL SIGNALS) (3) RESET (1) RD_BSY (1) 3 3 2 FS7 RS0 CSIOP *NOTE: The address inputs are A[19:4] in 80C51XA 80C51XA mode. 32 SRAM SELECT I/O DECODER SELECT Preliminary Information The PSD9XX Functional Blocks (cont.) PSD9XX Family 9.2.1 Decode PLD (DPLD) The DPLD, shown in Figure 10, is used for decoding the address for internal PSD components. The DPLD can generate the following chip selects: · · · · 8 4 1 1 sector selects for the main Flash memory (three product terms each) sector selects for the Secondary Flash memory (three product terms each) internal SRAM select (two product terms) internal CSIOP select (select PSD registers, one product term) Inputs to the DPLD chip selects may include address inputs, Page Register inputs and other user defined external inputs from Ports A, B, C or D. 9.2.2 General Purpose PLD (GPLD) The General Purpose PLD implements user defined system combinatorial logic function or chip selects for external devices. Figure 11 shows how the GPLD is connected to the I/O Ports. The GPLD has 19 outputs and each are routed to a port pin. The port pin can also be configured as input tot eh GPLD. When it is not used as GPLD output or input, the pin can be configured to perform other I/O functions. The GPLD outputs are identical except in the number of available product terms for logic implementation. Select the pin that can best meet the product term requirement of your logic function or chip selects. The outputs can be configured as active high or low outputs. Table 16 shows the number of product terms that are assigned to the PLD outputs on the I/O Ports. When PSD9XX is connected to a MCU with non-multiplexed bus, Port A will be configured as the Data Port and the GPLD outputs will not be available. Table 16. GPLD Output Product Term GPLD Output on Port Pin Number of Product Terms Port A, pins PA0-3 3 Port A, pins PA4-7 9 Port B, pins PB0-3 4 Port B, pins PB4-7 7 Port D, pins PD0-2 1 33 34 PLD INPUT BUS AND ARRAY AND ARRAY AND ARRAY *Pin PD0-2 has 1 PT PRODUCT TERM * Pin PB4-7 has 7 PT *Pin PB0-3 has 4 PT PRODUCT TERMS * Pin PA4-7 has 9 PT *Pin PA0-3 has 3 PT PRODUCT TERMS * POLARITY SELECT POLARITY SELECT POLARITY SELECT GENERAL PURPOSE PLD (GPLD) PLD OUTPUT PLD OUTPUT PLD OUTPUT PLD INPUT OTHER I/O FUNCTIONS PLD INPUT OTHER I/O FUNCTIONS PLD INPUT OTHER I/O FUNCTIONS MUX MUX MUX PORT D PORT B PORT A REPRESENTS A SINGLE PIN FROM EACH I /O PORT I/O PORT PSD9XX Family Preliminary Information Figure 11. General Purpose PLD and I/O Port Preliminary Information The PSD9XX Functional Blocks (cont.) PSD9XX Family 9.3 Microcontroller Bus Interface The "no-glue logic" PSD9XX Microcontroller Bus Interface can be directly connected to most popular microcontrollers and their control signals. Key 8-bit microcontrollers with their bus types and control signals are shown in Table 17. The interface type is specified using the PSDsoft. Table 17. Microcontrollers and their Control Signals Data Bus Width CNTL0 CNTL1 CNTL2 PC7 PD0* ADIO0 8031/8051 8 WR RD PSEN ALE A0 * 80C51XA 80C51XA 8 WR RD PSEN ALE A4 A3-A0 80C251 80C251 8 WR PSEN * ALE A0 80C251 80C251 8 WR RD PSEN ALE A0 80198 8 WR RD ALE A0 68HC11 68HC11 8 R/W E AS A0 68HC05C0 68HC05C0 8 WR RD AS A0 68HC912 68HC912 8 R/W E DBE AS A0 * * * * * * * * * * * * * * Z80 8 WR RD A0 D3-D0 D7-D4 8 R/W DS AS A0 68330 8 R/W DS AS A0 * * * * M37702M2 M37702M2 8 R/W E * * * * * Z8 * * * * * * * * * * * * * * * ALE A0 D3-D0 D7-D4 MCU PA3-PA0 PA7-PA4 *Unused CNTL2 pin can be configured as PLD input. Other unused pins (PC7, PD0, PA3-0) can be *configured for other I/O functions. *ALE/AS input is optional for microcontrollers with a non-multiplexed bus 9.3.1. PSD9XX Interface to a Multiplexed 8-Bit Bus Figure 12 shows an example of a system using a microcontroller with an 8-bit multiplexed bus and a PSD9XX. The ADIO port on the PSD9XX is connected directly to the microcontroller address/data bus. ALE latches the address lines internally. Latched addresses can be brought out to Port A or B. The PSD9XX drives the ADIO data bus only when one of its internal resources is accessed and the RD input is active. Should the system address bus exceed sixteen bits, Ports A, B, C, or D may be used as additional address inputs. 9.3.2. PSD9XX Interface to a Non-Multiplexed 8-Bit Bus Figure 13 shows an example of a system using a microcontroller with an 8-bit non-multiplexed bus and a PSD9XX. The address bus is connected to the ADIO Port, and the data bus is connected to Port A. Port A is in tri-state mode when the PSD9XX is not accessed by the microcontroller. Should the system address bus exceed sixteen bits, Ports B, C, or D may be used for additional address inputs. 35 PSD9XX Family The PSD9XX Functional Blocks Preliminary Information Figure 12. An Example of a Typical 8-Bit Multiplexed Bus Interface (cont.) PSD9XXF MICRO CONTROLLER AD [ 7:0] A [ 7: 0] PORT A A[ 15:8] WR (OPTIONAL) A [ 15: 8] WR (CNTRL0) RD (OPTIONAL) PORT B ADIO PORT RD (CNTRL1) PORT C RST ALE ALE (PD0) PORT D RESET Figure 13. An Example of a Typical 8-Bit Non-Multiplexed Bus Interface PSD9XXF D [ 7:0] MICRO CONTROLLER ADIO PORT PORT A D [ 7:0] A [ 15:0] PORT B WR WR (CNTRL0) RD RD (CNTRL1) RST ALE ALE (PD0) PORT D RESET 36 PORT C A[ 23:16] (OPTIONAL) Preliminary Information The PSD9XX Functional Blocks PSD9XX Family 9.3.3 Microcontroller Interface Examples Figures 14 through 18 show examples of the basic connections between the PSD9XX and some popular microcontrollers. The PSD9XX Control input pins are labeled as to the microcontroller function for which they are configured. The MCU interface is specified using the PSDsoft. (cont.) 9.3.3.1 80C31 80C31 Figure 14 shows the interface to the 80C31 80C31, which has an 8-bit multiplexed address/data bus. The lower address byte is multiplexed with the data bus. The microcontroller control signals PSEN, RD, and WR may be used for accessing the internal memory components and I/O Ports. The ALE input (pin PD0) latches the address. 9.3.3.2 80C251 80C251 The Intel 80C251 80C251 microcontroller features a user-configurable bus interface with four possible bus configurations, as shown in Table 19. Configuration 1 is 80C31 80C31 compatible, and the bus interface to the PSD9XX is identical to that shown in Figure 14. Configurations 2 and 3 have the same bus connection as shown in Figure 15. There is only one read input (PSEN) connected to the Cntl1 pin on the PSD9XX. The A16 connection to the PA0 pin allows for a larger address input to the PSD9XX. Configuration 4 is shown in Figure 16. The RD signal is connected to Cntl1 and the PSEN signal is connected to the CNTL2. The 80C251 80C251 has two major operating modes: Page Mode and Non-Page Mode. In Non-Page Mode, the data is multiplexed with the lower address byte, and ALE is active in every bus cycle. In Page Mode, data D[7:0] is multiplexed with address A[15:8]. In a bus cycle where there is a Page hit, the ALE signal is not active and only addresses A[7:0] are changing. The PSD9XX supports both modes. In Page Mode, the PSD bus timing is identical to Non-Page Mode except the address hold time and setup time with respect to ALE is not required. The PSD access time is measured from address A[7:0] valid to data in valid. 37 PSD9XX Family The PSD9XX Functional Blocks Preliminary Information Table 19. 80C251 80C251 Configurations Configuration Connecting to PSD9XX Pins Page Mode 1 WR RD PSEN CNTL0 CNTL1 CNTL2 Non-Page Mode, 80C31 80C31 compatible A [7:0] multiplex with D [7:0} 2 WR PSEN only CNTL0 CNTL1 Non-Page Mode A [7:0] multiplex with D [7:0} 3 WR PSEN only CNTL0 CNTL1 Page Mode A [15:8] multiplex with D [7:0} WR RD PSEN CNTL0 CNTL1 CNTL2 Page Mode A [15:8] multiplex with D [7:0} (cont.) 4 80C251 80C251 Read/Write Pins 9.3.3.3 80C51XA 80C51XA The Philips 80C51XA 80C51XA microcontroller family supports an 8- or 16-bit multiplexed bus that can have burst cycles. Address bits A[3:0] are not multiplexed, while A[19:4] are multiplexed with data bits D[15:0] in 16-bit mode. In 8-bit mode, A[11:4] are multiplexed with data bits D[7:0]. The 80C51XA 80C51XA can be configured to operate in eight-bit data mode. (shown in Figure 17). The 80C51XA 80C51XA improves bus throughput and performance by executing Burst cycles for code fetches. In Burst Mode, address A19-4 A19-4 are latched internally by the PSD9XX, while the 80C51XA 80C51XA changes the A3-0 lines to fetch up to 16 bytes of code. The PSD access time is then measured from address A3-A0 valid to data in valid. The PSD bus timing requirement in Burst Mode is identical to the normal bus cycle, except the address setup and hold time with respect to ALE does not apply. 9.3.3.4 68HC11 68HC11 Figure 18 shows an interface to a 68HC11 68HC11 where the PSD9XX is configured in 8-bit multiplexed mode with E and R/W settings. The DPLD can generate the READ and WR signals for external devices. 38 Preliminary Information PSD9XX Family Figure 14. Interfacing the PSD9XX with an 80C31 80C31 AD [ 7:0] PSD9XXF 80C31 80C31 31 19 18 9 RESET 12 13 14 15 EA/VP X1 X2 RESET INT0 INT1 T0 T1 1 2 3 4 5 6 7 8 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 AD[ 7:0 ] P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 RD WR PSEN ALE/P TXD RXD AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 30 31 32 33 34 35 36 37 39 38 37 36 35 34 33 32 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 21 22 23 24 25 26 27 28 A8 A9 A10 A11 A12 A13 A14 A15 39 40 41 42 43 44 45 46 17 RD WR 47 16 29 50 PSEN ALE 30 49 11 10 10 9 8 RESET 48 RESET ADIO0 ADIO1 ADIO2 ADIO3 ADIO4 ADIO5 ADIO6 ADIO7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 ADIO8 ADIO9 ADIO10 ADIO10 ADIO11 ADIO11 ADIO12 ADIO12 ADIO13 ADIO13 ADIO14 ADIO14 ADIO15 ADIO15 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 CNTL0 (WR) PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 CNTL1(RD) CNTL2 (PSEN) PD0-ALE PD1 PD2 29 28 27 25 24 23 22 21 7 6 5 4 3 2 52 51 20 19 18 17 14 13 12 11 RESET Figure 15. Interfacing the PSD9XX to the 80C251 80C251, with One Read Input PSD9XXF 80C251SB 80C251SB A17 2 3 4 5 6 7 8 9 21 20 11 13 14 15 16 17 RESET 10 35 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 X1 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 X2 P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 RST EA ALE PSEN WR RD/A16 RD/A16 A0 A1 A2 A3 A4 A5 A6 A7 30 31 32 33 34 35 36 37 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 39 40 41 42 43 44 45 46 43 42 41 40 39 38 37 36 A0 A1 A2 A3 A4 A5 A6 A7 24 25 26 27 28 29 30 31 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 33 ALE 47 32 RD 50 18 WR 19 A16 49 10 9 8 RESET RESET 48 * ADIO0 ADIO1 ADIO2 ADIO3 ADIO4 ADIO5 ADIO6 ADIO7 ADIO8 ADIO9 ADIO10 ADIO10 ADIO11 ADIO11 ADIO12 ADIO12 ADIO13 ADIO13 ADIO14 ADIO14 ADIO15 ADIO15 CNTL0 ( WR) CNTL1( RD) CNTL 2(PSEN) PD0- ALE PD1 PD2 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 29 A16 28 27 25 24 23 22 21 * A17 * 7 6 5 4 3 2 52 51 20 19 18 17 14 13 12 11 RESET *Connection is optional. *Non-page mode: AD[7:0] - ADIO[7:0]. 39 PSD9XX Family Preliminary Information Figure 16. Interfacing the PSD9XX to the 80C251 80C251, with Read and PSEN Inputs 80C251SB 80C251SB 2 3 4 5 6 7 8 9 21 20 11 13 14 15 16 17 RESET 10 35 PSD9XXF P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 X1 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 RST AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 30 31 32 33 34 35 36 37 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 39 40 41 42 43 44 45 46 33 ALE 47 32 RD 50 18 WR 19 ALE PSEN WR RD/A16 RD/A16 EA A0 A1 A2 A3 A4 A5 A6 A7 24 25 26 27 28 29 30 31 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 X2 A0 A1 A2 A3 A4 A5 A6 A7 43 42 41 40 39 38 37 36 PSEN 49 10 9 8 RESET RESET 48 ADIO0 ADIO1 ADIO2 ADIO3 ADIO4 ADIO5 ADIO6 ADIO7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 ADIO8 ADIO9 ADIO10 ADIO10 ADIO11 ADIO11 ADIO12 ADIO12 ADIO13 ADIO13 ADIO14 ADIO14 ADIO15 ADIO15 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 CNTL0 ( WR) CNTL1( RD) PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 CNTL 2(PSEN) PD0- ALE PD1 PD2 29 28 27 25 24 23 22 21 7 6 5 4 3 2 52 51 20 19 18 17 14 13 12 11 RESET Figure 17. Interfacing the PSD9XX to the 80C51XA 80C51XA, 8-Bit Data Bus PSD9XXF 80C51XA 80C51XA 21 20 11 13 6 7 9 8 16 RESET 10 14 15 XTAL1 XTAL2 RXD0 TXD0 RXD1 TXD1 T2EX T2 T0 RST INT0 INT1 A0/WRH A1 A2 A3 A4D0 A5D1 A6D2 A7D3 A8D4 A9D5 A10D6 A10D6 A11D7 A11D7 A12D8 A12D8 A13D9 A13D9 A14D10 A14D10 A15D11 A15D11 A16D12 A16D12 A17D13 A17D13 A18D14 A18D14 A19D15 A19D15 2 3 4 5 43 42 41 40 39 38 37 36 24 25 26 27 28 29 30 31 A0 A1 A2 A3 A4D0 A5D1 A6D2 A7D3 A8D4 A9D5 A10D6 A10D6 A11D7 A11D7 A12 A13 A14 A15 A16 A17 A18 A19 A4D0 A5D1 A6D2 A7D3 A8D4 A9D5 A10D6 A10D6 A11D7 A11D7 30 31 32 33 34 35 36 37 A12 A13 A14 A15 A16 A17 A18 A19 39 ADIO8 40 ADIO9 41 ADIO10 ADIO10 42 ADIO11 ADIO11 43 AD1012 AD1012 44 AD1013 AD1013 45 ADIO14 ADIO14 46 ADIO15 ADIO15 47 50 35 17 EA/WAIT BUSW PSEN RD WRL ALE 32 PSEN 49 19 RD WR ALE 10 8 9 18 33 48 RESET 40 ADIO0 ADIO1 ADIO2 ADIO3 AD104 AD104 AD105 AD105 ADIO6 ADIO7 CNTL0 (WR) CNTL1(RD) CNTL 2 (PSEN) PD0-ALE PD1 PD2 RESET PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 29 28 27 25 24 23 22 21 7 6 5 4 3 2 52 51 20 19 18 17 14 13 12 11 A0 A1 A2 A3 Preliminary Information PSD9XX Family Figure 18. Interfacing the PSD9XX with a 68HC11 68HC11 (Muxed Address/Data Bus) AD[7:0] AD[7:0] PSD9XXF 31 30 29 28 27 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 30 31 32 33 34 35 36 37 42 41 40 39 38 37 36 35 A8 A9 A10 A11 A12 A13 A14 A15 39 40 41 42 43 44 45 46 68HC11 68HC11 8 7 RESET 17 19 18 2 34 33 32 43 44 45 46 47 48 49 50 52 51 XT EX RESET IRQ XIRQ MODB PA0 PA1 PA2 PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 VRH VRL PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PD0 PD1 PD2 PD3 PD4 PD5 MODA E AS R/W 9 10 11 12 13 14 15 16 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 20 21 22 23 24 25 47 50 49 10 9 8 48 ADIO0 ADIO1 ADIO2 ADIO3 AD104 AD104 AD105 AD105 ADIO6 ADIO7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 ADIO8 ADIO9 ADIO10 ADIO10 ADIO11 ADIO11 AD1012 AD1012 AD1013 AD1013 ADIO14 ADIO14 ADIO15 ADIO15 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 CNTL0 (R _W) CNTL1(E) CNTL 2 PD0 ­ AS PD1 PD2 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 29 28 27 25 24 23 22 21 7 6 5 4 3 2 52 51 20 19 18 17 14 13 12 11 RESET 3 5 E 4 AS 6 R/W RESET 41 PSD9XX Family The PSD9XX Functional Blocks (cont.) Preliminary Information 9.4 I/O Ports There are four programmable I/O ports: Ports A, B, C, and D. Each of the ports is eight bits except Port D, which is 3 bits. Each port pin is individually user configurable, thus allowing multiple functions per port. The ports are configured using PSDsoft or by the microcontroller writing to on-chip registers in the CSIOP address space. The topics discussed in this section are: · General Port Architecture · Port Operating Modes · Port Configuration Registers · Port Data Registers · Individual Port Functionality. 9.4.1 General Port Architecture The general architecture of the I/O Port is shown in Figure 19. Individual Port architectures