PSD4235G2 TQFP80 AD0-AD15 AI04916 AI04943 J1850 80C51XA AI04990 AI04919 - Datasheet Archive

 

Flash In-System Programmable (ISP) Peripherals For 16-bit MCUs (5V Supply) PRELIMINARY DATA FEATURES SUMMARY PSD provides an

 

PSD4235G2 PSD4235G2 Flash In-System Programmable (ISP) Peripherals For 16-bit MCUs (5V Supply) PRELIMINARY DATA FEATURES SUMMARY PSD provides an integrated solution to 16-bit MCU based applications that includes configurable memories, PLD logic and I/O: s Dual Bank Flash Memories s Programmable power management s High Endurance: ­ 100,000 Erase/Write Cycles of Flash Memory ­ 1,000 EraseWrite Cycles of PLD ­ 4 Mbit of Primary Flash Memory (8 uniform sectors, 32K x 16) ­ 15 Year Data Retention ­ 256 Kbit Secondary Flash Memory with 4 sectors s ­ Concurrent operation: read from one memory while erasing and writing the other s s PLD with macrocells ­ 5V ±10% Memory Speed ­ 70ns Flash memory and SRAM access time 64 Kbit SRAM (Battery Backed) s Single Supply Voltage Figure 1. Packages ­ Over 3000 Gates of PLD: CPLD and DPLD ­ CPLD with 16 Output Macrocells (OMCs) and 24 Input Macrocells (IMCs) ­ DPLD ­ user defined internal chip select decoding s Seven l/O Ports with 52 I/O pins ­ 52 individually configurable I/O port pins that can be used for the following functions: ­ MCU I/Os ­ PLD I/Os ­ Latched MCU address output ­ Special function l/Os ­ l/O ports may be configured as open-drain outputs s TQFP80 TQFP80 (U) In-System Programming (ISP) with JTAG ­ Built-in JTAG compliant serial port allows fullchip In-System Programmability ­ Efficient manufacturing allow easy product testing and programming ­ Use low cost FlashLINK cable with PC s Page Register ­ Internal page register that can be used to expand the microcontroller address space by a factor of 256 December 2001 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/89 PSD4235G2 PSD4235G2 TABLE OF CONTENTS Summary Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 In-System Programming (ISP) via JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 In-Application Programming (IAP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PSDsoft Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 PSD Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 MCU Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 ISP via JTAG Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 In-System Programming (ISP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 In-Application Programming (IAP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power Management Unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Development System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 PSD Register Description and Address Offsets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Register Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Detailed Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Memory Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Reading Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Programming Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Erasing Flash Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Flash Memory Sector Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Memory Select Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2/89 PSD4235G2 PSD4235G2 Memory ID Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Decode PLD (DPLD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Complex PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 MCU Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Port Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Ports A, B and C ­ Functionality and Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Port D ­ Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Port E ­ Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Port F ­ Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Port G ­ Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 PLD Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 PSD Chip Select Input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Power On Reset, Warm Reset and Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Programming In-Circuit using the JTAG Serial Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Initial Delivery State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 AC/DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table. Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table. CPLD Combinatorial Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table. CPLD Macrocell Synchronous Clock Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table. CPLD Macrocell Asynchronous Clock Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table. Input Macrocell Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table. Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table. Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Table. Port F Peripheral Data Mode Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table. Port F Peripheral Data Mode Write Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table. Reset (Reset)Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table. VSTBYON Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table. Program, Write and Erase Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table. ISC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table. Power-down Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 3/89 PSD4235G2 PSD4235G2 Package Mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Table. TQFP80 TQFP80 - 80 lead Plastic Quad Flatpack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Table. Pin Assignments ­ TQFP80 TQFP80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 4/89 PSD4235G2 PSD4235G2 SUMMARY DESCRIPTION The PSD family of memory systems for microcontrollers (MCUs) brings In-System-Programmability (ISP) to Flash memory and programmable logic. The result is a simple and flexible solution for embedded designs. PSD devices combine many of the peripheral functions found in MCU based applications. PSD devices integrate an optimized Macrocell logic architecture. The Macrocell was created to address the unique requirements of embedded system designs. It allows direct connection between the system address/data bus, and the internal PSD registers, to simplify communication between the MCU and other supporting devices. Figure 2. Logic Diagram VCC 8 PA0-PA7 8 PB0-PB7 3 8 CNTL0CNTL2 Table 1. Pin Names PC0-PC7 4 PA0-PA7 Port-A PB0-PB7 Port-B PC0-PC7 Port-C PD0-PD3 Port-D PE0-PE7 Port-E PF0-PF7 Port-F PG0-PG7 Port-G AD0-AD15 AD0-AD15 Address/Data CNTL0-CNTL2 Control RESET Reset VCC Supply Voltage VSS Ground PD0-PD3 PSD4xxxGx 16 8 PE0-PE7 AD0-AD15 AD0-AD15 8 PF0-PF7 RESET 8 PG0-PG7 The PSD family offers two methods to program the PSD Flash memory while the PSD is soldered to the circuit board: In-System Programming (ISP) via JTAG, and In-Application Programming (IAP). In-System Programming (ISP) via JTAG An IEEE 1149.1 compliant JTAG In-System Programming (ISP) interface is included on the PSD enabling the entire device (Flash memories, PLD, configuration) to be rapidly programmed while soldered to the circuit board. This requires no MCU participation, which means the PSD can be programmed anytime, even when completely blank. The innovative JTAG interface to Flash memories is an industry first, solving key problems faced by designers and manufacturing houses, such as: VSS AI04916 AI04916 First time programming. How do I get firmware into the Flash memory the very first time? JTAG is the answer. Program the blank PSD with no MCU involvement. Inventory build-up of pre-programmed devices. How do I maintain an accurate count of preprogrammed Flash memory and PLD devices based on customer demand? How many and what version? JTAG is the answer. Build your hardware with blank PSDs soldered directly to the board and then custom program just before they are shipped to the customer. No more labels on chips, and no more wasted inventory. Expensive sockets. How do I eliminate the need for expensive and unreliable sockets? JTAG is the answer. Solder the PSD directly to the circuit board. Program first time and subsequent times with JTAG. No need to handle devices and bend the fragile leads. 5/89 PSD4235G2 PSD4235G2 61 PB0 62 PB1 63 PB2 64 PB3 65 PB4 66 PB5 67 PB6 69 VCC 68 PB7 70 GND 71 PE0 72 PE1 73 PE2 74 PE3 75 PE4 76 PE5 77 PE6 78 PE7 79 PD0 80 PD1 Figure 3. TQFP Connections 43 PC2 AD14 19 42 PC1 AD15 20 41 PC0 CNTL2 40 44 PC3 AD13 18 RESET 39 45 PC4 AD12 17 PF7 38 46 PC5 AD11 16 PF6 37 47 PC6 AD10 15 PF5 36 48 PC7 AD9 14 PF4 35 49 GND AD8 13 PF3 34 AD7 12 PF2 33 50 GND PF1 32 51 PA0 AD6 11 PF0 31 52 PA1 AD5 10 VCC 29 GND 30 53 PA2 VCC 9 PG7 28 54 PA3 GND 8 PG6 27 55 PA4 AD4 7 PG5 26 56 PA5 AD3 6 PG4 25 57 PA6 AD2 5 PG3 24 58 PA7 AD1 4 PG2 23 59 CNTL0 AD0 3 PG1 22 60 CNTL1 PD3 2 PG0 21 PD2 1 AI04943 AI04943 In-Application Programming (IAP) Two independent Flash memory arrays are included so that the MCU can execute code from one while erasing and programming the other. Robust product firmware updates in the filed are possible over any communication channel (CAN, Ethernet, UART, J1850 J1850, etc) using this unique architecture. Designers are relieved of these problems: Simultaneous read and write to Flash memory. How can the MCU program the same memory from which it executing code? It cannot. The PSD allows the MCU to operate the two Flash memory blocks concurrently, reading code from one while erasing and programming the other during IAP. Complex memory mapping. How can I map these two memories efficiently? A programmable 6/89 Decode PLD (DPLD) is embedded in the PSD. The concurrent PSD memories can be mapped anywhere in MCU address space, segment by segment with extermely high address resolution. As an option, the secondary Flash memory can be swapped out of the system memory map when IAP is complete. A built-in page register breaks the MCU address limit. Separate Program and Data space. How can I write to Flash memory while it resides in Program space during field firmware updates? My 80C51XA 80C51XA will not allow it. The PSD provides means to reclassify Flash memory as Data space during IAP, then back to Program space when complete. PG0 ­ PG7 CLKIN PORT G PROG. PORT PORT F PROG. PORT ADIO PORT PROG. MCU BUS INTRF. CLKIN 82 8 CSIOP GLOBAL CONFIG. & SECURITY CLKIN PLD, CONFIGURATION & FLASH MEMORY LOADER JTAG SERIAL CHANNEL PORT A ,B & C 24 INPUT MACROCELLS PORT A & B 16 OUTPUT MACROCELLS 8 EXT CS TO PORT C or F PORT F 64 KBIT BATTERY BACKUP SRAM 256 KBIT SECONDARY FLASH MEMORY (BOOT OR DATA) 4 SECTORS 16 SECTORS 4 MBIT PRIMARY FLASH MEMORY RUNTIME CONTROL AND I/O REGISTERS PERIP I/O MODE SELECTS SRAM SELECT SECTOR SELECTS FLASH ISP CPLD (CPLD) FLASH DECODE PLD (DPLD) SECTOR SELECTS EMBEDDED ALGORITHM MACROCELL FEEDBACK OR PORT INPUT 82 PAGE REGISTER PORT E PROG. PORT PORT D PROG. PORT PORT C PROG. PORT PORT B PROG. PORT PORT A PROG. PORT POWER MANGMT UNIT PE0 ­ PE7 PD0 ­ PD3 PC0 ­ PC7 PB0 ­ PB7 PA0 ­ PA7 VSTDBY (PE6) PSDsoft Express PSDsoft Express, a software development tool from ST, guides you through the design process step-by-step making it possible to complete an embedded MCU design capable of ISP/IAP in just hours. Select your MCU and PSDsoft Express takes you through the remainder of the design with point and click entry, covering PSD selection, pin PF0 ­ PF7 AD0 ­ AD15 CNTL0, CNTL1, CNTL2 PLD INPUT BUS ADDRESS/DATA/CONTROL BUS PSD4235G2 PSD4235G2 definitions, programmable logic inputs and outpus, MCU memory map definition, ANSI-C code generation for your MCU, and merging your MCU firmware with the PSD design. When complete, two different device programmers are supported directly from PSDsoft Express: FlashLINK (JTAG) and PSDpro. Figure 4. PSD Block Diagram Note: Additional address lines can be brought in to the device via Port A, B, C, D or F. AI04990 AI04990 7/89 PSD4235G2 PSD4235G2 PSD ARCHITECTURAL OVERVIEW PSD devices contain several major functional blocks. Figure 4 shows the architecture of the PSD device family. The functions of each block are described briefly in the following sections. Many of the blocks perform multiple functions and are user configurable. Memory Each of the memory blocks is briefly discussed in the following paragraphs. A more detailed discussion can be found in the section entitled "Memory Blocks" on page 20. The 4 Mbit primary Flash memory is the main memory of the PSD. It is divided into 8 equallysized sectors that are individually selectable. The 256 Kbit secondary Flash memory is divided into 4 equally-sized sectors. Each sector is individually selectable. The 64 Kbit SRAM is intended for use as a scratch-pad memory or as an extension to the MCU SRAM. If an external battery is connected to the PSD's Voltage Stand-by (VSTBY, PE6) signal, data is retained in the event of power failure. Each memory block can be located in a different address space as defined by the user. The access times for all memory types includes the address latching and DPLD decoding time. PLDs The device contains two PLD blocks, the Decode PLD (DPLD) and the Complex PLD (CPLD), as shown in Table 2, each optimized for a different function. The functional partitioning of the PLDs reduces power consumption, optimizes cost/performance, and eases design entry. The DPLD is used to decode addresses and to generate Sector Select signals for the PSD internal memory and registers. The DPLD has combinatorial outputs, while the CPLD can implement more general user-defined logic functions. The CPLD has 16 Output Macrocells (OMC) and 8 combinatorial outputs. The PSD also has 24 Input Macrocells (IMC) that can be configured as inputs to the PLDs. The PLDs receive their inputs from the PLD Input Bus and are differentiated by their output destinations, number of product terms, and Macrocells. The PLDs consume minimal power. The speed and power consumption of the PLD is controlled by the Turbo bit in PMMR0 and other bits in PMMR2. These registers are set by the MCU at run-time. There is a slight penalty to PLD propagation time when not in the Turbo mode. I/O Ports The PSD has 52 I/O pins divided among seven ports (Port A, B, C, D, E, F and G). Each I/O pin can be individually configured for different func8/89 tions. Ports can be configured as standard MCU I/ O ports, PLD I/O, or latched address outputs for MCUs using multiplexed address/data buses The JTAG pins can be enabled on Port E for InSystem Programming (ISP). Table 2. PLD I/O Inputs Outputs Product Terms Decode PLD (DPLD) 82 17 43 Complex PLD (CPLD) 82 24 150 Name MCU Bus Interface The PSD easily interfaces easily with most 16-bit MCUs, either with multiplexed or non-multiplexed address/data buses. The device is configured to respond to the MCU's control pins, which are also used as inputs to the PLDs. ISP via JTAG Port In-System Programming (ISP) can be performed through the JTAG signals on Port E. This serial interface allows complete programming of the entire PSD device. A blank device can be completely programmed. The JTAG signals (TMS, TCK, TSTAT, TERR, TDI, TDO) can be multiplexed with other functions on Port E. Table 3 indicates the JTAG pin assignments. In-System Programming (ISP) Using the JTAG signals on Port E, the entire PSD device (memory, logic, configuration) can be programmed or erased without the use of the MCU. Table 3. JTAG SIgnals on Port E Port E Pins JTAG Signal PE0 TMS PE1 TCK PE2 TDI PE3 TDO PE4 TSTAT PE5 TERR In-Application Programming (IAP) The primary Flash memory can also be programmed, or re-programmed, in-system by the MCU executing the programming algorithms out of the secondary Flash memory, or SRAM. The secondary Flash memory can be programmed the same way by executing out of the primary Flash memory. Table 4 indicates which programming methods can program different functional blocks of the PSD. PSD4235G2 PSD4235G2 Page Register The 8-bit Page Register expands the address range of the MCU by up to 256 times. The paged address can be used as part of the address space to access external memory and peripherals, or internal memory and I/O. The Page Register can also be used to change the address mapping of the Flash memory blocks into different memory spaces for IAP. Power Management Unit (PMU) The Power Management Unit (PMU) gives the user control of the power consumption on selected functional blocks based on system requirements. The PMU includes an Automatic Power-down (APD) Unit that turns off device functions during MCU inactivity. The APD Unit has a Power-down mode that helps reduce power consumption. The PSD also has some bits that are configured at run-time by the MCU to reduce power consumption of the CPLD. The Turbo bit in PMMR0 can be reset to 0 and the CPLD latches its outputs and goes to Stand-by mode until the next transition on its inputs. Additionally, bits in PMMR2 can be set by the MCU to block signals from entering the CPLD to reduce power consumption. See the section entitled "Power Management" on page 59 for more details. Table 4. Methods of Programming Different Functional Blocks of the PSD Functional Block JTAG-ISP Device Programmer IAP Primary Flash Memory Yes Yes Yes Secondary Flash memory Yes Yes Yes PLD Array (DPLD and CPLD) Yes Yes No PSD Configuration Yes Yes No 9/89 PSD4235G2 PSD4235G2 DEVELOPMENT SYSTEM The PSD family is supported by PSDsoft Express, a Windows-based software development tool (Windows-95, Windows-98, Windows-2000, Windows-NT). A PSD design is quickly and easily produced in a point and click environment. The designer does not need to enter Hardware Description Language (HDL) equations, unless desired, to define PSD pin functions and memory map information. The general design flow is shown in Figure 5. PSDsoft Express is available from our web site (the address is given on the back page of this data sheet) or other distribution channels. PSDsoft Express directly supports two low cost device programmers form ST: PSDpro and FlashLINK (JTAG). Both of these programmers may be purchased through your local distributor/ representative, or directly from our web site using a credit card. The PSD is also supported by thid party device programmers. See our web site for the current list. Figure 5. PSDsoft Express Development Tool Choose MCU and PSD Automatically configures MCU bus interface and other PSD attributes Define PSD Pin and Node Functions Point and click definition of PSD pin functions, internal nodes, and MCU system memory map Define General Purpose Logic in CPLD C Code Generation Point and click definition of combinatorial and registered logic in CPLD. Access HDL is available if needed GENERATE C CODE SPECIFIC TO PSD FUNCTIONS Merge MCU Firmware with PSD Configuration A composite object file is created containing MCU firmware and PSD configuration MCU FIRMWARE HEX OR S-RECORD FORMAT USER'S CHOICE OF MICROCONTROLLER COMPILER/LINKER *.OBJ FILE PSD Programmer PSDPro, or FlashLINK (JTAG) *.OBJ FILE AVAILABLE FOR 3rd PARTY PROGRAMMERS (CONVENTIONAL or JTAG-ISC) AI04919 AI04919 10/89 PSD4235G2 PSD4235G2 PIN DESCRIPTION Table 5 describes the signal names and signal functions of the PSD. Those that have multiple names or functions are defined using PSDsoft Express. Table 5. Pin Description (for the TQFP package) Pin Name ADIO0ADIO7 ADIO8ADIO15 ADIO8ADIO15 CNTL0 CNTL1 Pin 3-7 10-12 13-20 59 60 Type Description I/O This is the lower Address/Data port. Connect your MCU address or address/data bus according to the following rules: 1. If your MCU has a multiplexed address/data bus where the data is multiplexed with the lower address bits, connect AD0-AD7 to this port. 2. If your MCU does not have a multiplexed address/data bus, connect A0-A7 to this port. 3. If you are using an 80C51XA 80C51XA in burst mode, connect A4/D0 through A11/D7 A11/D7 to this port. ALE or AS latches the address. The PSD drives data out only if the read signal is active and one of the PSD functional blocks has been selected. The addresses on this port are passed to the PLDs. I/O This is the upper Address/Data port. Connect your MCU address or address/data bus according to the following rules: 1. If your MCU has a multiplexed address/data bus where the data is multiplexed with the upper address bits, connect A8-A15 A8-A15 to this port. 2. If your MCU does not have a multiplexed address/data bus, connect A8-A15 A8-A15 to this port. 3. If you are using an 80C51XA 80C51XA in burst mode, connect A12/D8 A12/D8 through A19/D15 A19/D15 to this port. ALE or AS latches the address. The PSD drives data out only if the read signal is active and one of the PSD functional blocks has been selected. The addresses on this port are passed to the PLDs. I The following control signals can be connected to this pin, based on your MCU: 1. WR ­ active Low, Write Strobe input. 2. R_W ­ active High, read/active Low write input. 3. WRL ­ active Low, Write to Low-byte. This pin is connected to the PLDs. Therefore, these signals can be used in decode and other logic equations. I The following control signals can be connected to this pin, based on your MCU: 1. RD ­ active Low, Read Strobe input. 2. E ­ E clock input. 3. DS ­ active Low, Data Strobe input. 4. LDS ­ active Low, Strobe for low data byte. This pin is connected to the PLDs. Therefore, these signals can be used in decode and other logic equations. CNTL2 40 I Read or other Control input pin, with multiple configurations. Depending on the MCU interface selected, this pin can be: 1. PSEN ­ Program Select Enable, active Low in code fetch bus cycle (80C51XA 80C51XA mode). 2. BHE ­ High-byte enable, 16-bit data bus. 3. UDS ­ active Low, Strobe for high data byte, 16-bit data bus mode. 4. SIZ0 ­ Byte enable input. 5. LSTRB ­ Low Strobe input. This pin is also connected to the PLDs. Reset 39 I Active Low input. Resets I/O Ports, PLD Macrocells and some of the Configuration Registers and JTAG registers. Must be Low at Power-up. Reset also aborts any Flash memory Program or Erase cycle that is currently in progress. 11/89 PSD4235G2 PSD4235G2 Pin Name PA0-PA7 PB0-PB7 PC0-PC7 PD0 PD1 PD2 PD3 PE0 PE1 PE2 12/89 Pin Type Description 51-58 I/O CMOS or Open Drain These pins make up Port A. These port pins are configurable and can have the following functions: 1. MCU I/O ­ standard output or input port. 2. CPLD Macrocell (McellA0-McellA7) outputs. 3. Latched, transparent or registered PLD inputs (can also be PLD input for address A16 and above). 61-68 I/O CMOS or Open Drain These pins make up Port B. These port pins are configurable and can have the following functions: 1. MCU I/O ­ standard output or input port. 2. CPLD Macrocell (McellB0-McellB7) outputs. 3. Latched, transparent or registered PLD inputs (can also be PLD input for address A16 and above). 41-48 I/O CMOS or Slew Rate These pins make up Port C. These port pins are configurable and can have the following functions: 1. MCU I/O ­ standard output or input port. 2. External Chip Select (ECS0-ECS7) outputs. 3. Latched, transparent or registered PLD inputs (can also be PLD input for address A16 and above). 79 I/O CMOS or Open Drain PD0 pin of Port D. This port pin can be configured to have the following functions: 1. ALE/AS input ­ latches address on ADIO0-ADIO15 ADIO0-ADIO15. 2. AS input ­ latches address on ADIO0-ADIO15 ADIO0-ADIO15 on the rising edge. 3. MCU I/O ­ standard output or input port. 4. Transparent PLD input (can also be PLD input for address A16 and above). 80 I/O CMOS or Open Drain PD1 pin of Port D. This port pin can be configured to have the following functions: 1. MCU I/O ­ standard output or input port. 2. Transparent PLD input (can also be PLD input for address A16 and above). 3. CLKIN ­ clock input to the CPLD Macrocells, the APD Unit's Power-down counter, and the CPLD AND Array. 1 I/O CMOS or Open Drain PD2 pin of Port D. This port pin can be configured to have the following functions: 1. MCU I/O ­ standard output or input port. 2. Transparent PLD input (can also be PLD input for address A16 and above). 3. PSD Chip Select Input (CSI). When Low, the MCU can access the PSD memory and I/O. When High, the PSD memory blocks are disabled to conserve power. The falling edge of this signal can be used to get the device out of Power-down mode. 2 I/O CMOS or Open Drain PD3 pin of Port D. This port pin can be configured to have the following functions: 1. MCU I/O ­ standard output or input port. 2. Transparent PLD input (can also be PLD input for address A16 and above). 3. WRH ­ for 16-bit data bus, write to high byte, active low. 71 I/O CMOS or Open Drain PE0 pin of Port E. This port pin can be configured to have the following functions: 1. MCU I/O ­ standard output or input port. 2. Latched address output. 3. TMS Input for the JTAG Serial Interface. 72 I/O CMOS or Open Drain PE1 pin of Port E. This port pin can be configured to have the following functions: 1. MCU I/O ­ standard output or input port. 2. Latched address output. 3. TCK Input for the JTAG Serial Interface. 73 I/O CMOS or Open Drain PE2 pin of Port E. This port pin can be configured to have the following functions: 1. MCU I/O ­ standard output or input port. 2. Latched address output. 3. TDI input for the JTAG Serial Interface. PSD4235G2 PSD4235G2 Pin Name Pin Type Description 74 I/O CMOS or Open Drain PE3 pin of Port E. This port pin can be configured to have the following functions: 1. MCU I/O ­ standard output or input port. 2. Latched address output. 3. TDO output for the JTAG Serial Interface. 75 I/O CMOS or Open Drain PE4 pin of Port E. This port pin can be configured to have the following functions: 1. MCU I/O ­ standard output or input port. 2. Latched address output. 3. TSTAT output for the JTAG Serial Interface. 4. Ready/Busy output for parallel In-System Programming (ISP). 76 I/O CMOS or Open Drain PE5 pin of Port E. This port pin can be configured to have the following functions: 1. MCU I/O ­ standard output or input port. 2. Latched address output. 3. TERR active Low output for the JTAG Serial Interface. 77 I/O CMOS or Open Drain PE6 pin of Port E. This port pin can be configured to have the following functions: 1. MCU I/O ­ standard output or input port. 2. Latched address output. 3. VSTBY ­ SRAM stand-by voltage input for SRAM battery backup. 78 I/O CMOS or Open Drain PE7 pin of Port E. This port pin can be configured to have the following functions: 1. MCU I/O ­ standard output or input port. 2. Latched address output. 3. Battery-on Indicator (VBATON). Goes High when power is being drawn from the external battery. 31-38 I/O CMOS or Open Drain These pins make up Port F. These port pins are configurable and can have the following functions: 1. MCU I/O ­ standard output or input port. 2. External Chip Select (ECS0-ECS7) outputs, or inputs to CPLD. 3. Latched address outputs. 4. Address A1-A3 inputs in 80C51XA 80C51XA mode (PF0 is grounded) 5. Data bus port (D0-D7) in a non-multiplexed bus configuration. 6. Peripheral I/O mode. 7. MCU reset mode. PG0-PG7 21-28 I/O CMOS or Open Drain These pins make up Port G. These port pins are configurable and can have the following functions: 1. MCU I/O ­ standard output or input port. 2. Latched address outputs. 3. Data bus port (D8-D15 D8-D15) in a non-multiplexed bus configuration. 4. MCU reset mode. VCC 9, 29, 69 Supply Voltage GND 8, 30, 49, 50, 70 Ground pins PE3 PE4 PE5 PE6 PE7 PF0-PF7 13/89 PSD4235G2 PSD4235G2 PSD REGISTER DESCRIPTION AND ADDRESS OFFSETS Table 6 provides brief descriptions of the registers Table 6 shows the offset addresses to the PSD registers relative to the CSIOP base address. The in CSIOP space. The following sections give a CSIOP space is the 256 bytes of address that is almore detailed description. located by the user to the internal PSD registers. Table 6. Register Address Offset Register Name Data In Port Port Port Port Port Port Port 1 A B C D E F G Other 00 01 10 11 Description 40 41 Reads Port pin as input, MCU I/O input mode 32 Control 30 42 43 Selects mode between MCU I/O or Address Out Data Out 04 05 14 15 34 44 45 Stores data for output to Port pins, MCU I/O output mode Direction 06 07 16 17 36 46 47 Configures Port pin as input or output Drive Select 08 09 18 19 38 48 49 Configures Port pins as either CMOS or Open Drain on some pins, while selecting high slew rate on other pins. Input Macrocell 0A 0B Enable Out 0C 0D Output Macrocells A 20 Output Macrocells B Mask Macrocells A Mask Macrocells B 1A 1C Reads Input Macrocells Reads the status of the output enable to the I/O Port driver 4C Read ­ reads output of Macrocells A Write ­ loads Macrocell Flip-flops Read ­ reads output of Macrocells B Write ­ loads Macrocell Flip-flops 21 22 Blocks writing to the Output Macrocells A 23 Blocks writing to the Output Macrocells B Flash Memory Protection C0 Read only ­ Primary Flash Sector Protection Flash Boot Protection C2 Read only ­ PSD Security and Secondary Flash memory Sector Protection JTAG Enable C7 Enables JTAG Port PMMR0 B0 Power Management Register 0 PMMR2 B4 Power Management Register 2 Page E0 Page Register VM E2 Places PSD memory areas in Program and/ or Data space on an individual basis. Memory_ID0 F0 Read only ­ SRAM and Primary memory size Memory_ID1 F1 Read only ­ Secondary memory type and size Note: 1. Other registers that are not part of the I/O ports. 14/89 PSD4235G2 PSD4235G2 REGISTER BIT DEFINITION All the registers of the PSD are included here, for reference. Detailed descriptions of these registers can be found in the following sections. Table 7. Data-In Registers ­ Ports A, B, C, D, E, F, G Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Port pin 7 Port pin 6 Port pin 5 Port pin 4 Port pin 3 Port pin 2 Port pin 1 Port pin 0 Note: Bit Definiti ons (Read-only registers): Read Port pin status when Port is in MCU I/O input mode. Table 8. Data-Out Registers ­ Ports A, B, C, D, E, F, G Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Port pin 7 Port pin 6 Port pin 5 Port pin 4 Port pin 3 Port pin 2 Port pin 1 Port pin 0 Note: Bit Definiti ons: Latched data for output to Port pin when pin is configured in MCU I/O output mode. Table 9. Direction Registers ­ Ports A, B, C, D, E, F, G Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Port pin 7 Port pin 6 Port pin 5 Port pin 4 Port pin 3 Port pin 2 Port pin 1 Port pin 0 Note: Bit Definiti ons: Port pin 0 = Port pin is configured in Input mode (default). Port pin 1 = Port pin is configured in Output mode. Table 10. Control Registers ­ Ports E, F, G Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Port pin 7 Port pin 6 Port pin 5 Port pin 4 Port pin 3 Port pin 2 Port pin 1 Port pin 0 Note: Bit Definiti ons: Port pin 0 = Port pin is configured in MCU I/O mode (default). Port pin 1 = Port pin is configured in Latched Address Out mode. Table 11. Drive Registers ­ Ports A, B, D, E, G Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Port pin 7 Port pin 6 Port pin 5 Port pin 4 Port pin 3 Port pin 2 Port pin 1 Port pin 0 Note: Bit Definiti ons: Port pin 0 = Port pin is configured for CMOS Output driver (default). Port pin 1 = Port pin is configured for Open Drain output driver. Table 12. Drive Registers ­ Ports C, F Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Port pin 7 Port pin 6 Port pin 5 Port pin 4 Port pin 3 Port pin 2 Port pin 1 Port pin 0 Note: Bit Definiti ons: Port pin 0 = Port pin is configured for CMOS Output driver (default). Port pin 1 = Port pin is configured in Slew Rate mode. 15/89 PSD4235G2 PSD4235G2 Table 13. Enable-Out Registers ­ Ports A, B, C, F Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Port pin 7 Port pin 6 Port pin 5 Port pin 4 Port pin 3 Port pin 2 Port pin 1 Port pin 0 Note: Bit Definiti ons (Read-only registers): Port pin 0 = Port pin is in tri-state driver (default). Port pin 1 = Port pin is enabled. Table 14. Input Macrocells ­ Ports A, B, C Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IMcell 7 IMcell 6 IMcell 5 IMcell 4 IMcell 3 IMcell 2 IMcell 1 IMcell 0 Note: Bit Definiti ons (Read-only registers): Read Input Macrocell (IMC7-IMC0) status on Ports A, B and C. Table 15. Output Macrocells A Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mcella 7 Mcella 6 Mcella 5 Mcella 4 Mcella 3 Mcella 2 Mcella 1 Mcella 0 Note: Bit Definiti ons: Write Register: Load MCellA7-MCellA0 with 0 or 1. Read Register: Read MCellA7-MCellA 0 output status. Table 16. Output Macrocells B Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mcellb 7 Mcellb 6 Mcellb 5 Mcellb 4 Mcellb 3 Mcellb 2 Mcellb 1 Mcellb 0 Note: Bit Definiti ons: Write Register: Load MCellB7-MCellB0 with 0 or 1. Read Register: Read MCellB7-MCellB 0 output status. Table 17. Mask Macrocells A Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mcella 7 Mcella 6 Mcella 5 Mcella 4 Mcella 3 Mcella 2 Mcella 1 Mcella 0 Note: Bit Definiti ons: McellA_Prot 0 = Allow MCellA flip-flop to be loaded by MCU (default). McellA_Prot 1 = Prevent MCellA flip-flop from being loaded by MCU. Table 18. Mask Macrocells B Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mcellb 7 Mcellb 6 Mcellb 5 Mcellb 4 Mcellb 3 Mcellb 2 Mcellb 1 Mcellb 0 Note: Bit Definiti ons: McellB _Prot 0 = Allow MCellB fli p-flop to be loaded by MCU (default). McellB _Prot 1 = Prevent MCellB flip-flop from being loaded by MCU. Table 19. Flash Memory Protection Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Sec7_Prot Sec6_Prot Sec5_Prot Sec4_Prot Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot Note: Bit Definiti ons (Read-only register): Sec_Prot 1 = Primary Flash memory Sector is write protected. Sec_Prot 0 = Primary Flash memory Sector is not write protected. 16/89 PSD4235G2 PSD4235G2 Table 20. Flash Boot Protection Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Security_Bit not used not used not used Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot Note: Bit Definiti ons: Sec_Prot 1 = Secondary Flash memory Sector is write protected. Sec_Prot 0 = Secondary Flash memory Sector is not write protected. Security_Bit 0 = Security Bit in device has not been set. Security_Bit 1 = Security Bit in device has been set. Table 21. JTAG Enable Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 not used not used not used not used not used not used not used JTAGEnable Note: Bit Definiti ons: JTAGEnable 1 = JTAG Port is enabled. JTAGEnable 0 = JTAG Port is disabled. Table 22. Page Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PGR 7 PGR 6 PGR 5 PGR 4 PGR 3 PGR 2 PGR 1 PGR 0 Note: Bit Definiti ons: Configure Page input to PLD. Default is PGR7-PGR0=0. 17/89 PSD4235G2 PSD4235G2 Table 23. PMMR0 Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 not used (set to 0) not used (set to 0) PLD MCells CLK PLD Array CLK PLD Turbo not used (set to 0) APD Enable not used (set to 0) Note: The bits of this register are cleared to zero following Power-up. Subsequent Reset (Reset) pulses do not clear the registers. Note: Bit Definiti ons: APD Enable 0 = Automatic Power-down (APD) is disabled. 1 = Automatic Power-down (APD) is enabled. PLD Turbo 0 = PLD Turbo is on. 1 = PLD Turbo is off, saving power. PLD Array CLK 0 = CLKIN to the PLD AND array is connected. Every CLKIN change powers up the PLD when Turbo bit is off. 1 = CLKIN to the PLD AND array is disconnected, saving power. PLD MCells CLK 0 = CLKIN to the PLD Macrocells is connected. 1 = CLKIN to the PLD Macrocells is disconnected, saving power. Table 24. PMMR2 Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 not used (set to 0) PLD Array WRH PLD Array ALE PLD Array CNTL2 PLD Array CNTL1 PLD Array CNTL0 not used (set to 0) PLD Array Addr Note: For Bit 4, Bit 3, Bit 2: See Table 34 for the signals that are blocked on pins CNTL0-CNTL2. Note: Bit Definiti ons: PLD Array Addr 0 = Address A7-A0 are connected to the PLD array. 1 = Address A7-A0 are blocked from the PLD array, saving power. (Note: in XA mode, A3-A0 come from PF3-PF0, and A7-A4 come from ADIO7-ADIO4) PLD Array CNTL2 0 = CNTL2 input to the PLD AND array is connected. 1 = CNTL2 input to the PLD AND array is disconnected, saving power. PLD Array CNTL1 0 = CNTL1 input to the PLD AND array is connected. 1 = CNTL1 input to the PLD AND array is disconnected, saving power. PLD Array CNTL0 0 = CNTL0 input to the PLD AND array is connected. 1 = CNTL0 input to the PLD AND array is disconnected, saving power. PLD Array ALE 0 = ALE input to the PLD AND array is connected. 1 = ALE input to the PLD AND array is disconnected, saving power. PLD Array WRH 0 = WRH/DBE input to the PLD AND array is connected. 1 = WRH/DBE input to the PLD AND array is disconnected, saving power. Table 25. VM Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Peripheral mode not used (set to 0) not used (set to 0) FL_data Boot_data FL_code Boot_code SR_code Note: On reset, Bit1-Bit4 are loaded to configurations that are selected by the user in PSDsoft Express. Bit0 and Bit7 are always cleared on reset. Bit0-Bit4 are active only when the device is configured in Philips 80C51XA 80C51XA mode. Note: Bit Definiti ons: SR_code 0 = PSEN cannot access SRAM in 80C51XA 80C51XA modes. 1 = PSEN can access SRAM in 80C51XA 80C51XA modes. Boot_code 0 = PSEN cannot access Secondary NVM in 80C51XA 80C51XA modes. 1 = PSEN can access Secondary NVM in 80C51XA 80C51XA modes. FL_code 0 = PSEN cannot access Primary Flash memory in 80C51XA 80C51XA modes. 1 = PSEN can access Primary Flash memory in 80C51XA 80C51XA modes. Boot_data 0 = RD cannot access Secondary NVM in 80C51XA 80C51XA modes. 1 = RD can access Secondary NVM in 80C51XA 80C51XA modes. FL_data 0 = RD cannot access Primary Flash memory in 80C51XA 80C51XA modes. 1 = RD can access Primary Flash memory in 80C51XA 80C51XA modes. Peripheral mode 0 = Peripheral mode of Port F is disabled. 1 = Peripheral mode of Port F is enabled. 18/89 PSD4235G2 PSD4235G2 Table 26. Memory_ID0 Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 S_size 3 S_size 2 S_size 1 S_size 0 F_size 3 F_size 2 F_size 1 F_size 0 Note: Bit Definiti ons: F_size[3:0] S_size[3:0] 0h = There is no Primary Flash memory 1h = Primary Flash memory size is 256 Kbit 2h = Primary Flash memory size is 512 Kbit 3h = Primary Flash memory size is 1 Mbit 4h = Primary Flash memory size is 2 Mbit 5h = Primary Flash memory size is 4 Mbit 6h = Primary Flash memory size is 8 Mbit 0h = There is no SRAM 1h = SRAM size is 16 Kbit 2h = SRAM size is 32 Kbit 3h = SRAM size is 64 Kbit 4h = SRAM size is 128 Kbit 5h = SRAM size is 256 Kbit Table 27. Memory_ID1 Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 not used (set to 0) not used (set to 0) B_type 1 B_type 0 B_size 3 B_size 2 B_size 1 B_size 0 Note: Bit Definiti ons: B_size[3:0] B_type[1:0] 0h = There is no Secondary NVM 1h = Secondary NVM size is 128 Kbit 2h = Secondary NVM size is 256 Kbit 3h = Secondary NVM size is 512 Kbit 0h = Secondary NVM is Flash memory 1h = Secondary NVM is EEPROM 19/89 PSD4235G2 PSD4235G2 DETAILED OPERATION As shown in Figure 4, the PSD consists of six major types of functional blocks: s Memory Blocks s PLD Blocks s MCU Bus Interface s I/O Ports s Power Management Unit (PMU) s JTAG-ISP Interface The functions of each block are described in the following sections. Many of the blocks perform multiple functions, and are user configurable. Memory Blocks The PSD has the following memory blocks: ­ Primary Flash memory ­ Secondary Flash memory ­ SRAM The Memory Select signals for these blocks originate from the Decode PLD (DPLD) and are userdefined in PSDsoft Express. Table 28 sumamarizes the sizes and organisations of the memory blocks. Table 28. Memory Block Size and Organization Primary Flash Memory Secondary Flash Memory SRAM Sector Number Sector Size (x16) Sector Select Signal Sector Size (x16) Sector Select Signal SRAM Size (x16) SRAM Select Signal 0 32K FS0 4K CSBOOT0 4K RS0 1 32K FS1 4K CSBOOT1 2 32K FS2 4K CSBOOT2 3 32K FS3 4K CSBOOT3 4 32K FS4 5 32K FS5 6 32K FS6 7 32K FS7 Totals 512KByte 8 Sectors 32KByte 4 Sectors 20/89 8KByte PSD4235G2 PSD4235G2 Primary Flash Memory and Secondary Flash memory Description. The primary Flash memory is divided evenly into 8 sectors. The secondary Flash memory is divided evenly into 4 sectors. Each sector of either memory block can be separately protected from Program and Erase cycles. Flash memory may be erased on a sector-by-sector basis, and programmed word-by-word. Flash sector erasure may be suspended while data is read from other sectors of the block and then resumed after reading. During a Program or Erase cycle in Flash memory, the status can be output on the Ready/Busy pin (PE4). This pin is set up using PSDsoft Express. Memory Block Select Signals. The DPLD generates the Select signals for all the internal memory blocks (see the section entitled "PLDs", on page 31). Each of the sectors of the primary Flash memory has a Select signal (FS0-FS7) which can contain up to three product terms. Each of the sectors of the secondary Flash memory has a Select signal (CSBOOT0-CSBOOT3) which can contain up to three product terms. Having three product terms for each Select signal allows a given sector to be mapped in different areas of system memory. When using a MCU with separate Program and Data space (80C51XA 80C51XA), these flexible Select signals allow dynamic re-mapping of sectors from one memory space to the other before and after IAP. The SRAM block has a single Select signal (RS0). Ready/Busy (PE4). This signal can be used to output the Ready/Busy status of the PSD. The out- put is a 0 (Busy) when a Flash memory block is being written to, or when a Flash memory block is being erased. The output is a 1 (Ready) when no Write or Erase cycle is in progress. Memory Operation. The primary Flash memory and secondary Flash memory are addressed through the MCU Bus Interface. The MCU can access these memories in one of two ways: s The MCU can execute a typical bus Write or Read operation just as it would if accessing a RAM or ROM device using standard bus cycles. s The MCU can execute a specific instruction that consists of several Write and Read operations. This involves writing specific data patterns to special addresses within the Flash memory to invoke an embedded algorithm. These instructions are summarized in Table 29. Typically, the MCU can read Flash memory using Read operations, just as it would read a ROM device. However, Flash memory can only be erased and programmed using specific instructions. For example, the MCU cannot write a single byte directly to Flash memory as one would write a byte to RAM. To program a word into Flash memory, the MCU must execute a Program instruction, then test the status of the Programming event. This status test is achieved by a Read operation or polling Ready/Busy (PE4). Flash memory can also be read by using special instructions to retrieve particular Flash device information (sector protect status and ID). 21/89 PSD4235G2 PSD4235G2 Table 29. Instructions FS0-FS7 or CSBOOT0CSBOOT3 Cycle 1 Read5 1 "Read" RD @ RA Read Main Flash ID6 1 Read Sector Protection6,8,13 Instruction14 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 AAh@ XAAAh 55h@ X554h 90h@ XAAAh Read ID @ XX02h 1 AAh@ XAAAh 55h@ X554h 90h@ XAAAh Read 00h or 01h @ XX04h Program a Flash Word13 1 AAh@ XAAAh 55h@ X554h A0h@ XAAAh PD@ PA Flash Sector Erase7,13 1 AAh@ XAAAh 55h@ X554h 80h@ XAAAh AAh@ XAAAh 55h@ X554h 30h@ SA 30h 7@ next SA Flash Bulk Erase13 1 AAh@ XAAAh 55h@ X554h 80h@ XAAAh AAh@ XAAAh 55h@ X554h 10h@ XAAAh Suspend Sector Erase11 1 B0h@ XXXXh Resume Sector Erase12 1 30h@ XXXXh Reset6 1 F0h@ XXXXh Unlock Bypass 1 AAh@ XAAAh 55h@ X554h 20h@ XAAAh Unlock Bypass Program9 1 A0h@ XXXXh PD@ PA Unlock Bypass Reset10 1 90h@ XXXXh 00h@ XXXXh Note: 1. All bus cycles are write bus cycles, except the ones with the "Read" label 2. All values are in hexadecimal: X = Don't Care. Addresses of the form XXXXh, in this table, must be even addresses RA = Address of the memory location to be read RD = Data read from location RA during the Read cycle PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of Write Strobe (WR, CNTL0). PA is an even address for PSD in word programming mode. PD = Data word to be programmed at location PA. Data is latched on the rising edge of Write Strobe (WR, CNTL0) SA = Address of the sector to be erased or verified. The Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) of the sector to be erased, or verified, must be Active (High). 3. Sector Select (FS0 to FS7 or CSBOOT0 to CSBOOT3) signals are active High, and are defined in PSDsoft Express. 4. Only address bits A11-A0 A11-A0 are used in instruction decoding. 5. No Unlock or instruction cycles are required when the device is in the Read mode 6. The Reset instruction is required to return to the Read mode after reading the Flash ID, or after reading the Sector Protection Status, or if the Error Flag (DQ5/DQ13 DQ5/DQ13) bit goes High. 7. Additional sectors to be erased must be written at the end of the Sector Erase instruction within 80 µs. 8. The data is 00h for an unprotected sector, and 01h for a protected sector. In the fourth cycle, the Sector Select is active, and (A1,A0)=(1,0) 9. The Unlock Bypass instruction is required prior to the Unlock Bypass Program instruction. 10. The Unlock Bypass Reset Flash instruction is required to return to reading memory data when the device is in the Unlock Bypass mode. 11. The system may perform Read and Program cycles in non-erasing sectors, read the Flash ID or read the Sector Protection Status when in the Suspend Sector Erase mode. The Suspend Sector Erase instruction is valid only during a Sector Erase cycle. 12. The Resume Sector Erase instruction is valid only during the Suspend Sector Erase mode. 13. The MCU cannot invoke these instructions while executing code from the same Flash memory as that for which the instruction is intended. The MCU must fetch, for example, the code from the secondary Flash memory when reading the Sector Protection Status of the primary Flash memory. 14. All write bus cycles in an instruction are byte write to an even address (XA4Ah or X554h). A Flash memory Program bus cycle writes a word to an even address. 22/89 PSD4235G2 PSD4235G2 Instructions An instruction consists of a sequence of specific operations. Each received byte is sequentially decoded by the PSD and not executed as a standard Write operation. The instruction is executed when the correct number of bytes are properly received and the time between two consecutive bytes is shorter than the time-out period. Some instructions are structured to include Read operations after the initial Write operations. The instruction must be followed exactly. Any invalid combination of instruction bytes or time-out between two consecutive bytes while addressing Flash memory resets the device logic into Read mode (Flash memory is read like a ROM device). The PSD supports the instructions summarized in Table 29: s Erase memory by chip or sector s Suspend or resume sector erase s Program a Word s Reset to Read mode s Read primary Flash Identifier value s Read Sector Protection Status s Bypass These instructions are detailed in Table 29. For efficient decoding of the instructions, the first two bytes of an instruction are the coded cycles and are followed by an instruction byte or confirmation byte. The coded cycles consist of writing the data AAh to address XAAAh during the first cycle and data 55h to address X554h during the second cycle (unless the Bypass instruction feature is used, as described later). Address signals A15-A12 A15-A12 are Don't Care during the instruction Write cycles. However, the appropriate Sector Select signal (FS0-FS7, or CSBOOT0-CSBOOT3) must be selected. The primary and secondary Flash memories have the same instruction set (except for Read Primary Flash Identifier). The Sector Select signals determine which Flash memory is to receive and execute the instruction. The primary Flash memory is selected if any one of its Sector Select signals (FS0-FS7) is High, and the secondary Flash memory is selected if any one of its Sector Select signals (CSBOOT0-CSBOOT3) is High. Power-up Condition. The PSD internal logic is reset upon Power-up to the Read mode. Sector Select (FS0-FS7 and CSBOOT0-CSBOOT3) must be held Low, and Write Strobe (WR/WRL, CNTL0) High, during Power-up for maximum security of the data contents and to remove the possibility of data being written on the first edge of Write Strobe (WR/WRL, CNTL0). Any Write cycle initiation is locked when VCC is below VLKO. Reading Flash Memory Under typical conditions, the MCU may read the primary Flash memory, or secondary Flash memory, using Read operations just as it would a ROM or RAM device. Alternately, the MCU may use Read operations to obtain status information about a Program or Erase cycle that is currently in progress. Lastly, the MCU may use instructions to read special data from these memory blocks. The following sections describe these Read functions. Read Memory Contents. Primary Flash memory and secondary Flash memory are placed in the Read mode after Power-up, chip reset, or a Reset Flash instruction (see Table 29). The MCU can read the memory contents of the primary Flash memory, or the secondary Flash memory by using Read operations any time the Read operation is not part of an instruction. Read Primary Flash Identifier. The primary Flash memory identifier is read with an instruction composed of 4 operations: 3 specific Write operations and a Read operation (see Table 29). The identifier for the primary Flash memory is E8h. The secondary Flash memory does not support this instruction. Read Memory Sector Protection Status. The Flash memory Sector Protection Status is read with an instruction composed of four operations: three specific Write operations and a Read operation (see Table 29). The Read operation produces 01h if the Flash memory sector is protected, or 00h if the sector is not protected. The sector protection status for all NVM blocks (primary Flash memory, or secondary Flash memory) can be read by the MCU accessing the Flash Protection and Flash Boot Protection registers in PSD I/O space. See the section entitled "Flash Memory Sector Protect", on page 27, for register definitions. Reading the Erase/Program Status Bits. The PSD provides several status bits to be used by the MCU to confirm the completion of an Erase or Program cycle of Flash memory. These status bits minimize the time that the MCU spends performing these tasks and are defined in Table 30. The status byte resides in an even location, and can be read as many times as needed. Also note that DQ15-DQ8 DQ15-DQ8 is an even byte for Motorola MCUs with a 16-bit data bus. For Flash memory, the MCU can perform a Read operation to obtain these status bits while an Erase or Program instruction is being executed by the embedded algorithm. See the section entitled "Programming Flash Memory", on page 25, for details. 23/89 PSD4235G2 PSD4235G2 Table 30. Status Bits DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 Data Polling Toggle Flag Error Flag X Erase Timeout X X X Table 31. Status Bits for Motorola DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 Data Polling Toggle Flag Error Flag X Erase Timeout X X X Note: 1. X = Not guaranteed value, can be read either 1 or 0. 2. DQ15-DQ0 DQ15-DQ0 represent the Data Bus bits, D15-D0 D15-D0. 3. FS0-FS7/CSBOOT0-CSBOO T3 are active High. Data Polling (DQ7) ­ DQ15 for Motorola. When erasing or programming in Flash memory, the Data Polling (DQ7/DQ15 DQ7/DQ15) bit outputs the complement of the bit being entered for programming/ writing on the DQ7/DQ15 DQ7/DQ15 bit. Once the Program instruction or the Write operation is completed, the true logic value is read on the Data Polling (DQ7/ DQ15) bit (in a Read operation). s Data Polling is effective after the fourth Write pulse (for a Program instruction) or after the sixth Write pulse (for an Erase instruction). It must be performed at the address being programmed or at an address within the Flash memory sector being erased. s During an Erase cycle, the Data Polling (DQ7/ DQ15) bit outputs a 0. After completion of the cycle, the Data Polling (DQ7/DQ15 DQ7/DQ15) bit outputs the last bit programmed (it is a 1 after erasing). s If the location to be programmed is in a protected Flash memory sector, the instruction is ignored. s If all the Flash memory sectors to be erased are protected, the Data Polling (DQ7/DQ15 DQ7/DQ15) bit is reset to 0 for about 100 µs, and then returns to the value from the previously addressed location. No erasure is performed. Toggle Flag (DQ6) ­ DQ14 for Motorola. The PSD offers another way for determining when the Flash memory Program cycle is completed. During the internal Write operation and when either FS0FS7 or CSBOOT0-CSBOOT3 is true, the Toggle Flag (DQ6/DQ14 DQ6/DQ14) bit toggles from 0 to 1 and 1 to 0 on subsequent attempts to read any word of the memory. When the internal cycle is complete, the toggling stops and the data read on the Data Bus D0-D7 is the value from the addressed memory location. The device is now accessible for a new Read or 24/89 Write operation. The cycle is finished when two successive Reads yield the same output data. s The Toggle Flag (DQ6/DQ14 DQ6/DQ14) bit is effective after the fourth Write pulse (for a Program instruction) or after the sixth Write pulse (for an Erase instruction). s If the location to be programmed belongs to a protected Flash memory sector, the instruction is ignored. s If all the Flash memory sectors selected for erasure are protected, the Toggle Flag (DQ6/ DQ14) bit toggles to 0 for about 100 µs and then returns to the value from the previously addressed location. Error Flag (DQ5) ­ DQ13 for Motorola. During a normal Program or Erase cycle, the Error Flag (DQ5/DQ13 DQ5/DQ13) bit is reset to 0. This bit is set to 1 when there is a failure during a Flash memory Program, Sector Erase, or Bulk Erase cycle. In the case of Flash memory programming, the Error Flag (DQ5/DQ13 DQ5/DQ13) bit indicates the attempt to program a Flash memory bit, or bits, from the programmed state, 0, to the erased state, 1, which is not a valid operation. The Error Flag (DQ5/DQ13 DQ5/DQ13) bit may also indicate a Time-out condition while attempting to program a word. In case of an error in a Flash memory Sector Erase or Word Program cycle, the Flash memory sector in which the error occurred or to which the programmed location belongs must no longer be used. Other Flash memory sectors may still be used. The Error Flag (DQ5/DQ13 DQ5/DQ13) bit is reset after a Reset instruction. A Reset instruction is required after detecting an error on the Error Flag (DQ5/ DQ13) bit. Erase Time-out Flag (DQ3) ­ DQ11 for Motorola. The Erase Time-out Flag (DQ3/DQ11 DQ3/DQ11) bit reflects the time-out period allowed between two consecutive Sector Erase instructions. The Erase Time-out Flag (DQ3/DQ11 DQ3/DQ11) bit is reset to 0 after a PSD4235G2 PSD4235G2 Sector Erase cycle for a period of 100 µs + 20% unless an additional Sector Erase instruction is decoded. After this period, or when the additional Sector Erase instruction is decoded, the Erase Time-out Flag (DQ3/DQ11 DQ3/DQ11) bit is set to 1. Programming Flash Memory Flash memory must be erased prior to being programmed. The MCU may erase Flash memory all at once or by-sector. Although erasing Flash memory occurs on a sector or device basis, programming Flash memory occurs on a word basis. The primary and secondary Flash memories require the MCU to send an instruction to program a word or to erase sectors (see Table 29). Once the MCU issues a Flash memory Program or Erase instruction, it must check the status bits for completion. The embedded algorithms that are invoked inside the PSD support several means to provide status to the MCU. Status may be checked using any of three methods: Data Polling, Data Toggle, or Ready/Busy (PE4) signal. Data Polling. Polling on the Data Polling (DQ7/ DQ15) bit is a method of checking whether a Program or Erase cycle is in progress or has completed. Figure 6 shows the Data Polling algorithm. When the MCU issues a Program instruction, the embedded algorithm within the PSD begins. The MCU then reads the location of the word to be programmed in Flash memory to check the status. The Data Polling (DQ7/DQ15 DQ7/DQ15) bit becomes the complement of the corresponding bit of the original data word to be programmed. The MCU continues to poll this location, comparing data and monitoring the Error Flag (DQ5/DQ13 DQ5/DQ13) bit. When the Data Polling (DQ7/DQ15 DQ7/DQ15) bit matches the corresponding bit of the original data, and the Error Flag (DQ5/DQ13 DQ5/DQ13) bit remains 0, the embedded algorithm is complete. If the Error Flag (DQ5/DQ13 DQ5/DQ13) bit is 1, the MCU should test the Data Polling (DQ7/ DQ15) bit again since the Data Polling (DQ7/ DQ15) bit may have changed simultaneously with the Error Flag (DQ5/DQ13 DQ5/DQ13) bit (see Figure 6). The Error Flag (DQ5/DQ13 DQ5/DQ13) bit is set if either an internal time-out occurred while the embedded algorithm attempted to program the location or if the MCU attempted to program a 1 to a bit that was not erased (not erased is logic 0). It is suggested (as with all Flash memories) to read the location again after the embedded programming algorithm has completed, to compare the word that was written to the Flash memory with the word that was intended to be written. When using the Data Polling method during an Erase cycle, Figure 6 still applies. However, the Data Polling (DQ7/DQ15 DQ7/DQ15) bit is 0 until the Erase cycle is complete. A 1 on the Error Flag (DQ5/ DQ13) bit indicates a time-out condition on the Erase cycle, a 0 indicates no error. The MCU can read any even location within the sector being erased to get the Data Polling (DQ7/DQ15 DQ7/DQ15) bit and the Error Flag (DQ5/DQ13 DQ5/DQ13) bit. PSDsoft Express generates ANSI C code functions that implement these Data Polling algorithms. Figure 6. Data Polling Flowchart START READ DQ5 and DQ7 (DQ13 and DQ15) at Valid Even Address DQ7 (DQ15) = Data7 (Data15) Yes No No DQ5 (DQ13) =1 Yes READ DQ7 (DQ15) DQ7 (DQ15) = Data7 (Data15) Yes No Program or Erase Cycle failed Program or Erase Cycle is complete Issue RESET instruction AI04920 AI04920 Data Toggle. Checking the Toggle Flag (DQ6/ DQ14) bit is another method of determining whether a Program or Erase cycle is in progress or has completed. Figure 7 shows the Data Toggle algorithm. When the MCU issues a Program instruction, the embedded algorithm within the PSD begins. The MCU then reads the location to be programmed in Flash memory to check the status. The Toggle Flag (DQ6/DQ14 DQ6/DQ14) bit toggles each time the MCU 25/89 PSD4235G2 PSD4235G2 reads this location until the embedded algorithm is complete. The MCU continues to read this location, checking the Toggle Flag (DQ6/DQ14 DQ6/DQ14) bit and monitoring the Error Flag (DQ5/DQ13 DQ5/DQ13) bit. When the Toggle Flag (DQ6/DQ14 DQ6/DQ14) bit stops toggling (two consecutive reads yield the same value), and the Error Flag (DQ5/DQ13 DQ5/DQ13) bit remains 0, the embedded algorithm is complete. If the Error Flag (DQ5/DQ13 DQ5/DQ13) bit is 1, the MCU should test the Toggle Flag (DQ6/DQ14 DQ6/DQ14) bit again, since the Toggle Flag (DQ6/DQ14 DQ6/DQ14) bit may have changed simultaneously with the Error Flag (DQ5/DQ13 DQ5/DQ13) bit (see Figure 7). Figure 7. Data Toggle Flowchart START READ DQ5 and DQ6 (DQ13 and DQ14) at Valid Even Address DQ6 (DQ14) = Toggle No Yes No DQ5 (DQ13) =1 Yes READ DQ6 (DQ14) DQ6 (DQ14) = Toggle No Yes Program or Erase Cycle failed Program or Erase Cycle is complete Issue RESET instruction AI04921 AI04921 The Error Flag (DQ5/DQ13 DQ5/DQ13) bit is set if either an internal time-out occurred while the embedded algorithm attempted to program, or if the MCU 26/89 attempted to program a 1 to a bit that was not erased (not erased is logic 0). It is suggested (as with all Flash memories) to read the location again after the embedded programming algorithm has completed, to compare the word that was written to Flash memory with the word that was intended to be written. When using the Data Toggle method after an Erase cycle, Figure 7 still applies. the Toggle Flag (DQ6/DQ14 DQ6/DQ14) bit toggles until the Erase cycle is complete. A 1 on the Error Flag (DQ5/DQ13 DQ5/DQ13) bit indicates a time-out condition on the Erase cycle, a 0 indicates no error. The MCU can read any even location within the sector being erased to get the Toggle Flag (DQ6/DQ14 DQ6/DQ14) bit and the Error Flag (DQ5/DQ13 DQ5/DQ13) bit. PSDsoft Express generates ANSI C code functions which implement these Data Toggling algorithms. Unlock Bypass. The Unlock Bypass instruction allows the system to program words to the Flash memories faster than using the standard Program instruction. The Unlock Bypass mode is entered by first initiating two Unlock cycles. This is followed by a third Write cycle containing the Unlock Bypass command, 20h (as shown in Table 29). The Flash memory then enters the Unlock Bypass mode. A two-cycle Unlock Bypass Program instruction is all that is required to program in this mode. The first cycle in this instruction contains the Unlock Bypass Program command, A0h. The second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispense with the initial two Unlock cycles required in the standard Program instruction, resulting in faster total programming time. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset instructions are valid. To exit the Unlock Bypass mode, the system must issue the two-cycle Unlock Bypass Reset instruction. The first cycle must contain the data 90h; the second cycle the data 00h. Addresses are Don't Care for both cycles. The Flash memory then returns to Read mode. Erasing Flash Memory Flash Bulk Erase. The Flash Bulk Erase instruction uses six Write operations followed by a Read operation of the status register, as described in Table 29. If any byte of the Bulk Erase instruction is wrong, the Bulk Erase instruction aborts and the device is reset to the Read Memory mode. During a Bulk Erase, the memory status may be checked by reading the Error Flag (DQ5/DQ13 DQ5/DQ13) bit, the Toggle Flag (DQ6/DQ14 DQ6/DQ14) bit, and the Data Polling (DQ7/DQ15 DQ7/DQ15) bit, as detailed in the section PSD4235G2 PSD4235G2 entitled "Programming Flash Memory", on page 25. The Error Flag (DQ5/DQ13 DQ5/DQ13) bit returns a 1 if there has been an Erase Failure (maximum number of Erase cycles have been executed). It is not necessary to program the memory with 00h because the PSD automatically does this before erasing to 0FFh. During execution of the Bulk Erase instruction, the Flash memory does not accept any instructions. Flash Sector Erase. The Sector Erase instruction uses six Write operations, as described in Table 29. Additional Flash Sector Erase confirm commands and Flash memory sector addresses can be written subsequently to erase other Flash memory sectors in parallel, without further coded cycles, if the additional commands are transmitted in a shorter time than the time-out period of about 100 µs. The input of a new Sector Erase command restarts the time-out period. The status of the internal timer can be monitored through the level of the Erase Time-out Flag (DQ3/ DQ11) bit. If the Erase Time-out Flag (DQ3/DQ11 DQ3/DQ11) bit is 0, the Sector Erase instruction has been received and the time-out period is counting. If the Erase Time-out Flag (DQ3/DQ11 DQ3/DQ11) bit is 1, the time-out period has expired and the PSD is busy erasing the Flash memory sector(s). Before and during Erase time-out, any instruction other than Suspend Sector Erase and Resume Sector Erase, abort the cycle that is currently in progress, and reset the device to Read mode. It is not necessary to program the Flash memory sector with 00h as the PSD does this automatically before erasing. During a Sector Erase, the memory status may be checked by reading the Error Flag (DQ5/DQ13 DQ5/DQ13) bit, the Toggle Flag (DQ6/DQ14 DQ6/DQ14) bit, and the Data Polling (DQ7/DQ15 DQ7/DQ15) bit, as detailed in the section entitled "Programming Flash Memory", on page 25. During execution of the Erase cycle, the Flash memory accepts only Reset and Suspend Sector Erase instructions. Erasure of one Flash memory sector may be suspended, in order to read data from another Flash memory sector, and then resumed. Suspend Sector Erase. When a Sector Erase cycle is in progress, the Suspend Sector Erase instruction can be used to suspend the cycle by writing 0B0h to any even address when an appropriate Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) is High. (See Table 29). This allows reading of data from another Flash memory sector after the Erase cycle has been suspended. Suspend Sector Erase is accepted only during the Flash Sector Erase instruction execution and defaults to Read mode. A Suspend Sector Erase instruction executed during an Erase time-out period, in addition to suspending the Erase cycle, terminates the time out period. The Toggle Flag (DQ6/DQ14 DQ6/DQ14) bit stops toggling when the PSD internal logic is suspended. The status of this bit must be monitored at an address within the Flash memory sector being erased. The Toggle Flag (DQ6/DQ14 DQ6/DQ14) bit stops toggling between 0.1 µs and 15 µs after the Suspend Sector Erase instruction has been executed. The PSD is then automatically set to Read mode. If an Suspend Sector Erase instruction was executed, the following rules apply: ­ Attempting to read from a Flash memory sector that was being erased outputs invalid data. ­ Reading from a Flash memory sector that was not being erased is valid. ­ The Flash memory cannot be programmed, and only responds to Resume Sector Erase and Reset instructions (Read is an operation and is allowed). ­ If a Reset instruction is received, data in the Flash memory sector that was being erased is invalid. Resume Sector Erase. If a Suspend Sector Erase instruction was previously executed, the Erase cycle may be resumed with this instruction. The Resume Sector Erase instruction consists of writing 030h to any even address while an appropriate Sector Select (FS0-FS7 or CSBOOT0CSBOOT3) is High. (See Table 29.) Flash Memory Sector Protect Each sector of Primary or Secondary Flash memory can be separately protected against Program and Erase cycles. Sector Protection provides additional data security because it disables all Program or Erase cycles. This mode can be activated (or deactivated) through the JTAG-ISP Port or a Device Programmer. Sector protection can be selected for each sector using the PSDsoft Express program. This automatically protects selected sectors when the device is programmed through the JTAG Port or a Device Programmer. Flash memory sectors can be unprotected to allow updating of their contents using the JTAG Port or a Device Programmer. The MCU can read (but cannot change) the sector protection bits. Any attempt to program or erase a protected Flash memory sector is ignored by the device. The Verify operation results in a read of the protected data. This allows a guarantee of the retention of the Protection status. The sector protection status can be read by the MCU through the Flash memory protection and Secondary Flash memory protection registers (in 27/89 PSD4235G2 PSD4235G2 the CSIOP block) or use the Read Sector Protection instruction. See Table 19 to Table 20. Reset The Reset instruction consists of one Write cycle (see Table 29). It can also be optionally preceded by the standard two write decoding cycles (writing AAh to AAAh, and 55h to 554h). The Reset instruction must be executed after: ­ Reading the Flash Protection Status or Flash ID ­ An Error condition has occurred (and the device has set the Error Flag (DQ5/DQ13 DQ5/DQ13) bit to 1) during a Flash memory Program or Erase cycle. The Reset instruction immediately puts the Flash memory back into normal Read mode. However, if there is an error condition (with the Error Flag (DQ5/DQ13 DQ5/DQ13) bit set to 1) the Flash memory will return to the Read mode in 25 µs after the Reset instruction is issued. The Reset instruction is ignored when it is issued during a Program or Bulk Erase cycle of the Flash memory. The Reset instruction aborts any on-going Sector Erase cycle, and returns the Flash memory to the normal Read mode in 25 µs. Reset (RESET) Pin. A pulse on the Reset (RESET) pin aborts any cycle that is in progress, and resets the Flash memory to the Read mode. When the reset occurs during a Program or Erase cycle, the Flash memory takes up to 25 µs to return to the Read mode. It is recommended that the Reset (RESET) pulse (except for Power On Reset, as described on page 62) be at least 25 µs so that the Flash memory is always ready for the MCU to fetch the bootstrap instructions after the Reset cycle is complete. SRAM The SRAM is enabled when SRAM Select (RS0) from the DPLD is High. SRAM Select (RS0) can contain up to three product terms, allowing flexible memory mapping. The SRAM can be backed up using an external battery. The external battery should be connected to the Voltage Stand-by (VSTBY, PE6) line. If you have an external battery connected to the PSD, the contents of the SRAM are retained in the event of a power loss. The contents of the SRAM are retained so long as the battery voltage remains at 2 V or greater. If the supply voltage falls below the battery voltage, an internal power switch-over to the battery occurs. PE7 can be configured as an output that indicates when power is being drawn from the external battery. This Battery-on Indicator (VBATON, PE7) signal is High when the supply voltage falls below the battery voltage and the battery on Voltage Stand-by (VSTBY, PE6) is supplying power to the internal SRAM. 28/89 SRAM Select (RS0), Voltage Stand-by (VSTBY, PE6) and Battery-on Indicator (VBATON, PE7) are all configured using PSDsoft Express. Memory Select Signals The Primary Flash Memory Sector Select (FS0FS7), Secondary Flash Memory Sector Select (CSBOOT0-CSBOOT3) and SRAM Select (RS0) signals are all outputs of the DPLD. They are defined using PSDsoft Express. The following rules apply to the equations for these signals: 1. Primary Flash memory and secondary Flash memory Sector Select signals must not be larger than the physical sector size. 2. Any primary Flash memory sector must not be mapped in the same memory space as another Flash memory sector. 3. A secondary Flash memory sector must not be mapped in the same memory space as another secondary Flash memory sector. 4. SRAM, I/O, and Peripheral I/O spaces must not overlap. 5. A secondary Flash memory sector may overlap a primary Flash memory sector. In case of overlap, priority is given to the secondary Flash memory sector. 6. SRAM, I/O, and Peripheral I/O spaces may overlap any other memory sector. Priority is given to the SRAM, I/O, or Peripheral I/O. Figure 8. Priority Level of Memory and I/O Components Highest Priority Level 1 SRAM, I/O, or Peripheral I/O Level 2 Secondary Non-Volatile Memory Level 3 Primary Flash Memory Lowest Priority AI02867D AI02867D Example. FS0 is valid when the address is in the range of 8000h to BFFFh, CSBOOT0 is valid from 8000h to 9FFFh, and RS0 is valid from 8000h to 87FFh. Any address in the range of RS0 always accesses the SRAM. Any address in the range of CSBOOT0 greater than 87FFh (and less than 9FFFh) automatically addresses secondary Flash memory segment 0. Any address greater than 9FFFh accesses the primary Flash memory seg- PSD4235G2 PSD4235G2 ment 0. You can see that half of the primary Flash memory segment 0 and one-fourth of secondary Flash memory segment 0 cannot be accessed in this example. Also note that an equation that defined FS1 to anywhere in the range of 8000h to BFFFh would not be valid. Figure 8 shows the priority levels for all memory components. Any component on a higher level can overlap and has priority over any component on a lower level. Components on the same level must not overlap. Level 1 has the highest priority and level 3 has the lowest. Memory Select Configuration for MCUs with Separate Program and Data Spaces. The 80C51XA 80C51XA and compatible family of MCUs, can be configured to have separate address spaces for Program memory (selected using Program Select Enable (PSEN, CNTL2) and Data memory (selected using Read Strobe (RD, CNTL1). Any of the memories within the PSD can reside in either space or both spaces. This is controlled through manipulation of the VM register that resides in the CSIOP space. The VM register is set using PSDsoft Express to have an initial value. It can subsequently be changed by the MCU so that memory mapping can be changed on-the-fly. For example, you may wish to have SRAM and primary Flash memory in the Data space at Boot-up, and secondary Flash memory in the Program space at Boot-up, and later swap the secondary Flash memory and primary Flash memory. This is easily done with the VM register by using PSDsoft Express to configure it for Boot-up and having the MCU change it when desired. Table 25 describes the VM Register. Separate Space Modes. Program space is separated from Data space. For example, Program Select Enable (PSEN, CNTL2) is used to access the program code from the primary Flash memory, while Read Strobe (RD, CNTL1) is used to access data from the secondary Flash memory, SRAM and I/O Port blocks. This configuration requires the VM register to be set to 0Ch (see Figure 9). Figure 9. 8031 Memory Modules ­ Separate Space DPLD RS0 Primary Flash Memory Secondary Flash Memory SRAM CSBOOT0-3 FS0-FS7 CS CS OE CS OE OE PSEN RD AI02869C AI02869C Combined Space Modes. The Program and Data spaces are combined into one memory space that allows the primary Flash memory, secondary Flash memory, and SRAM to be accessed by either Program Select Enable (PSEN, CNTL2) or Read Strobe (RD, CNTL1). For example, to configure the primary Flash memory in Combined space, bits 2 and 4 of the VM register are set to 1 (see Figure 10). 80C51XA 80C51XA Memory Map Example. See the Application Notes for examples. 29/89 PSD4235G2 PSD4235G2 Figure 10. 8031 Memory Modules ­ Combined Space DPLD RD Primary Flash Memory RS0 Secondary Flash Memory SRAM CSBOOT0-3 FS0-FS7 CS CS OE CS OE OE VM REG BIT 3 VM REG BIT 4 PSEN VM REG BIT 1 RD VM REG BIT 2 VM REG BIT 0 AI02870C AI02870C Page Register The 8-bit Page Register increases the addressing capability of the MCU by a factor of up to 256. The contents of the register can also be read by the MCU. The outputs of the Page Register (PGR0PGR7) are inputs to the DPLD decoder and can be included in the Sector Select (FS0-FS7, CSBOOT0-CSBOOT3), and SRAM Select (RS0) equations. If memory paging is not needed, or if not all eight page register bits are needed for memory paging, these bits may be used in the CPLD for general logic. See Application Note AN1154 AN1154. Table 22 and Figure 11 show the Page Register. The eight flip-flops in the register are connected to the internal data bus (D0-D7). The MCU can write to or read from the Page Register. The Page Register can be accessed at address location CSIOP + E0h. Figure 11. Page Register RESET D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q6 D7 INTERNAL SELECTS AND LOGIC PGR1 Q5 D6 D0 - D7 PGR0 Q7 PGR2 PGR3 PGR4 DPLD AND CPLD PGR5 PGR6 PGR7 R /W PAGE REGISTER 30/89 PLD AI02871B AI02871B PSD4235G2 PSD4235G2 Memory ID Registers The 8-bit read-only Memory Status Registers are included in the CSIOP space. The user can determine the memory configuration of the PSD device by reading the Memory ID0 and Memory ID1 registers. The content of the registers is defined as shown in Table 26 and Table 27. PLDs The PLDs bring programmable logic functionality to the PSD. After specifying the logic for the PLDs using PSDsoft Express, the logic is programmed into the device and available upon Power-up. Table 32. DPLD and CPLD Inputs Input Source Input Name Number of Signals MCU Address Bus1 A15-A0 A15-A0 16 MCU Control Signals CNTL0-CNTL2 3 Reset RST 1 Power-down PDN 1 Port A Input Macrocells PA7-PA0 8 Port B Input Macrocells PB7-PB0 8 Port C Input Macrocells PC7-PC0 8 Port D Inputs PD3-PD0 4 Port F Inputs PF7-PF0 8 Page Register PGR7-PGR0 8 Macrocell A Feedback MCELLA.FB7-FB0 8 Macrocell B Feedback MCELLB.FB7-FB0 8 Flash memory Program Status Bit Ready/Busy The PSD contains two PLDs: the Decode PLD (DPLD), and the Complex PLD (CPLD). The PLDs are briefly discussed in the next few paragraphs, and in more detail in the following sections. Figure 12 shows the configuration of the PLDs. The DPLD performs address decoding for internal components, such as memory, registers, and I/O ports Select signals. The CPLD can be used for logic functions, such as loadable counters and shift registers, state machines, and encoding and decoding logic. These logic functions can be constructed using the 16 Output Macrocells (OMC), 24 Input Macrocells (IMC), and the AND Array. The CPLD can also be used to generate External Chip Select (ECS0ECS2) signals. The AND Array is used to form product terms. These product terms are specified using PSDsoft Express. An Input Bus consisting of 82 signals is connected to the PLDs. The signals are shown in Table 32. The Turbo Bit in PSD. The PLDs in the PSD4235G2 PSD4235G2 can minimize power consumption by switching to standby when inputs remain unchanged for an extended time of about 70 ns. Resetting the Turbo bit to 0 (Bit 3 of the PMMR0 register) automatically places the PLDs into standby if no inputs are changing. Turning the Turbo mode off increases propagation delays while reducing power consumption. See the section entitled "Power Management", on page 59, on how to set the Turbo bit. Additionally, five bits are available in the PMMR2 register to block MCU control signals from entering the PLDs. This reduces power consumption and can be used only when these MCU control signals are not used in PLD logic equations. Each of the two PLDs has unique characteristics suited for its applications. They are described in the following sections. 1 Note: 1. The address inputs are A19-A4 A19-A4 in 80C51XA 80C51XA mode. 31/89 32/89 16 1 2 1 3 4 8 CPLD PT ALLOC. OUTPUT MACROCELL FEEDBACK DECODE PLD PAGE REGISTER 24 INPUT MACROCELL (PORT A,B,C) INPUT MACROCELL & INPUT PORTS PORT D and PORT F INPUTS 24 12 MACROCELL ALLOC. 8 8 MCELLB TO PORT B EXTERNAL CHIP SELECTS TO PORT C or PORT F 8 MCELLA TO PORT A DIRECT MACROCELL ACCESS FROM MCU DATA BUS JTAG SELECT PERIPHERAL SELECTS CSIOP SELECT SRAM SELECT SECONDARY NON-VOLATILE MEMORY SELECTS PRIMARY FLASH MEMORY SELECTS 16 OUTPUT MACROCELL DIRECT MACROCELL INPUT TO MCU DATA BUS 82 82 8 I/O PORTS DATA BUS AI05737 AI05737 PSD4235G2 PSD4235G2 Figure 12. PLD Diagram PLD INPUT BUS PSD4235G2 PSD4235G2 DECODE PLD (DPLD) The DPLD, shown in Figure 13, is used for decoding the address for internal and external components. The DPLD can be used to generate the following decode signals: s 8 Sector Select (FS0-FS7) signals for the primary Flash memory (three product terms each) s 4 Sector Select (CSBOOT0-CSBOOT3) signals for the secondary Flash memory (three product terms each) s 1 internal SRAM Select (RS0) signal (three product terms) s 1 internal CSIOP Select (PSD Configuration Register) signal s 1 JTAG Select signal (enables JTAG-ISP on Port E) s 2 internal Peripheral Select signals (Peripheral I/O mode). Figure 13. DPLD Logic Array 3 3 CSBOOT 2 3 (INPUTS) CSBOOT 1 3 I /O PORTS (PORT A,B,F) CSBOOT 0 CSBOOT 3 3 FS0 (32) 3 MCELLAB.FB [7:0] (FEEDBACKS) FS1 (8) 3 MCELLBC.FB [7:0] (FEEDBACKS) FS2 (8) 3 PGR0 -PGR7 FS3 (8) 3 A[15:0] * (16) 3 PD[3:0] (ALE,CLKIN,CSI) FS5 (4) PDN (APD OUTPUT) (1) 3 FS6 3 CNTRL[2:0] (READ/WRITE CONTROL SIGNALS) (1) RD_BSY FS7 (3) RESET 8 PRIMARY FLASH MEMORY SECTOR SELECTS FS4 (1) 3 RS0 1 CSIOP 1 PSEL0 1 PSEL1 1 JTAGSEL SRAM SELECT I/O DECODER SELECT PERIPHERAL I/O MODE SELECT AI05738 AI05738 Note: 1. The address inputs are A19-A4 A19-A4 when in 80C51XA 80C51XA mode 2. Additional address lines can be brought ino the PSD via Port A, B, C, D, or F. 33/89 PSD4235G2 PSD4235G2 COMPLEX PLD (CPLD) The CPLD can be used to implement system logic functions, such as loadable counters and shift registers, system mailboxes, handshaking protocols, state machines, and random logic. The CPLD can also be used to generate eight External Chip Select (ECS0-ECS7), routed to Port C or Port F. Although External Chip Select (ECS0-ECS7) can be produced by any Output Macrocell (OMC), these eight External Chip Select (ECS0-ECS7) on Port C or Port F do not consume any Output Macrocells (OMC). As shown in Figure 12, the CPLD has the following blocks: s 24 Input Macrocells (IMC) s 16 Output Macrocells (OMC) s s AND Array capable of generating up to 196 product terms s Four I/O Ports. Each of the blocks are described in the sections that follow. The Input Macrocells (IMC) and Output Macrocells (OMC) are connected to the PSD internal data bus and can be directly accessed by the MCU. This enables the MCU software to load data into the Output Macrocells (OMC) or read data from both the Input and Output Macrocells (IMC and OMC). This feature allows efficient implementation of system logic and eliminates the need to connect the data bus to the AND Array as required in most standard PLD macrocell architectures. Product Term Allocator Figure 14. Macrocell and I/O Port PLD INPUT BUS PRODUCT TERMS FROM OTHER MACROCELLS MCU ADDRESS / DATA BUS CPLD MACROCELLS I/O PORTS DATA LOAD CONTROL PT PRESET MCU DATA IN PRODUCT TERM ALLOCATOR LATCHED ADDRESS OUT DATA MCU LOAD I/O PIN D Q MUX POLARITY SELECT MUX AND ARRAY WR UP TO 10 PRODUCT TERMS CPLD OUTPUT PR DI LD D/T MUX PT CLOCK PLD INPUT BUS MACROCELL OUT TO MCU GLOBAL CLOCK SELECT Q D/T/JK FF SELECT COMB. /REG SELECT PDR INPUT CK CL CLOCK SELECT D WR Q DIR REG. PT CLEAR PT OUTPUT ENABLE (OE) MACROCELL FEEDBACK INPUT MACROCELLS MUX I/O PORT INPUT ALE/AS MUX PT INPUT LATCH GATE/CLOCK Q D Q D G AI04945 AI04945 34/89 PSD4235G2 PSD4235G2 Output Macrocell (OMC). Eight of the Output Macrocells (OMC) are connected to Ports A pins and are named as McellA0-McellA7. The other eight Macrocells are connected to Ports B pins and are named as McellB0-McellB7. The Output Macrocell (OMC) architecture is shown in Figure 15. As shown in the figure, there are native product terms available from the AND Array, and borrowed product terms available (if unused) from other Output Macrocells (OMC). The polarity of the product term is controlled by the XOR gate. The Output Macrocell (OMC) can implement either sequential logic, using the flip-flop element, or combinatorial logic. The multiplexer selects between the sequential or combinatorial logic outputs. The multiplexer output can drive a port pin and has a feedback path to the AND Array inputs. The flip-flop in the Output Macrocell (OMC) block can be configured as a D, T, JK, or SR type in the PSDsoft Express program. The flip-flop's clock, preset, and clear inputs may be driven from a product term of the AND Array. Alternatively, the external CLKIN (PD1) signal can be used for the clock input to the flip-flop. The flip-flop is clocked on the rising edge of CLKIN (PD1). The preset and clear are active High inputs. Each clear input can use up to two product terms. Table 33. Output Macrocell Port and Data Bit Assignments Output Macrocell Port Assignment Native Product Terms Maximum Borrowed Product Terms Data Bit for Loading or Reading Motorola 16-Bit MCU for Loading or Reading McellA0 Port A0 3 6 D0 D8 McellA1 Port A1 3 6 D1 D9 McellA2 Port A2 3 6 D2 D10 McellA3 Port A3 3 6 D3 D11 McellA4 Port A4 3 6 D4 D12 McellA5 Port A5 3 6 D5 D13 McellA6 Port A6 3 6 D6 D14 McellA7 Port A7 3 6 D7 D15 McellB0 Port B0 4 5 D8 D0 McellB1 Port B1 4 5 D9 D1 McellB2 Port B2 4 5 D10 D2 McellB3 Port B3 4 5 D11 D3 McellB4 Port B4 4 6 D12 D4 McellB5 Port B5 4 6 D13 D5 McellB6 Port B6 4 6 D14 D6 McellB7 Port B7 4 6 D15 D7 35/89 PSD4235G2 PSD4235G2 Figure 15. CPLD Output Macrocell MASK REG. MACROCELL CS INTERNAL DATA BUS RD PT ALLOCATOR WR DIRECTION REGISTER ENABLE (.OE) AND ARRAY PLD INPUT BUS PRESET(.PR) COMB/REG SELECT PT PT DIN PR MUX PT LD POLARITY SELECT IN CLEAR (.RE) PORT DRIVER CLR PROGRAMMABLE FF (D/ T/JK /SR) PT CLK CLKIN I/O PIN Q MUX FEEDBACK (.FB) PORT INPUT INPUT MACROCELL AI04946 AI04946 Product Term Allocator. The CPLD has a Product Term Allocator. PSDsoft Express, uses the Product Term Allocator to borrow and place product terms from one Macrocell to another. The following list summarizes how product terms are allocated: s McellA0-McellA7 all have three native product terms and may borrow up to six more s McellB0-McellB3 all have four native product terms and may borrow up to five more s McellB4-McellB7 all have four native product terms and may borrow up to six more. Each Macrocell may only borrow product terms from certain other Macrocells. Product terms already in use by one Macrocell are not available for another Macrocell. If an equation requires more product terms than are available to it, then "external" product terms are required, which consume other Output Macrocells (OMC). If external product terms are used, extra delay is added for the equation that required the extra product terms. This is called product term expansion. PSDsoft Express performs this expansion as needed. 36/89 Loading and Reading the Output Macrocells (OMC). The Output Macrocells (OMC) block occupies a memory location in the MCU address space, as defined by the CSIOP (see the section entitled "I/O Ports", on page 50). The flip-flops in each of the 16 Output Macrocells (OMC) can be loaded from the data bus by a MCU. Loading the Output Macrocells (OMC) with data from the MCU takes priority over internal functions. As such, the preset, clear, and clock inputs to the flip-flop can be overridden by the MCU. The ability to load the flip-flops and read them back is useful in such applications as loadable counters and shift registers, mailboxes, and handshaking protocols. Data is loaded to the Output Macrocells (OMC) on the trailing edge of Write Strobe (WR/WRL, CNTL0). The OMC Mask Register. There is one Mask Register for each of the two groups of eight Output Macrocells (OMC). The Mask Registers can be used to block the loading of data to individual Output Macrocells (OMC). The default value for the Mask Registers is 00h, which allows loading of the Output Macrocells (OMC). When a given bit in a Mask Register is set to a 1, the MCU is blocked from writing to the associated Output Macrocells PSD4235G2 PSD4235G2 (OMC). For example, suppose McellA0-McellA3 are being used for a state machine. You would not want a MCU write to McellA to overwrite the state machine registers. Therefore, you would want to load the Mask Register for McellA (Mask Macrocell A) with the value 0Fh. The Output Enable of the OMC. The Output Macrocells (OMC) can be connected to an I/O port pin as a PLD output. The output enable of each port pin driver is controlled by a single product term from the AND Array, ORed with the Direction Register output. The pin is enabled upon Powerup if no output enable equation is defined and if the pin is declared as a PLD output in PSDsoft Express. If the Output Macrocell (OMC) output is declared as an internal node and not as a port pin output in the PSDabel file, then the port pin can be used for other I/O functions. The internal node feedback can be routed as an input to the AND Array. Input Macrocells (IMC). The CPLD has 24 Input Macrocells (IMC), one for each pin on Ports A, B, and C. The architecture of the Input Macrocells (IMC) is shown in Figure 16. The Input Macrocells (IMC) are individually configurable, and can be used as a latch, register, or to pass incoming Port signals prior to driving them onto the PLD input bus. The outputs of the Input Macrocells (IMC) can be read by the MCU through the internal data bus. The enable for the latch and clock for the register are driven by a multiplexer whose inputs are a product term from the CPLD AND Array or the MCU Address Strobe (ALE/AS). Each product term output is used to latch or clock four Input Macrocells (IMC). Port inputs 3-0 can be controlled by one product term and 7-4 by another. Configurations for the Input Macrocells (IMC) are specified by PSDsoft Express (see Application Note AN1171 AN1171). Outputs of the Input Macrocells (IMC) can be read by the MCU via the IMC buffer. See the section entitled "I/O Ports", on page 50. Input Macrocells (IMC) can use Address Strobe (ALE/AS, PD0) to latch address bits higher than A15. Any latched addresses are routed to the PLDs as inputs. Input Macrocells (IMC) are particularly useful with handshaking communication applications where two processors pass data back and forth through a common mailbox. Figure 18 shows a typical configuration where the Master MCU writes to the Port A Data Out Register. This, in turn, can be read by the Slave MCU via the activation of the "SlaveRead" output enable product term. The Slave can also write to the Port A Input Macrocells (IMC) and the Master can then read the Input Macrocells (IMC) directly. Note that the "S