PS015304-0203 128KB 128KB/64KB ADDR21 ADDR22 ADDR23 ADDR10 ADDR11 ADDR12 ADDR13 - Datasheet Archive

 

eZ80F92/eZ80F93 Product Specification PRELIMINARY PS015304-0203 ZiLOG Worldwide Headquarters · 532 Race Street ·

 

eZ80Acclaim! Flash Microcontrollers eZ80F92/eZ80F93 Product Specification PRELIMINARY PS015304-0203 PS015304-0203 ZiLOG Worldwide Headquarters · 532 Race Street · San Jose, CA 95126 Telephone: 408.558.8500 · Fax: 408.558.8300 · www.ZiLOG.com This publication is subject to replacement by a later edition. To determine whether a later edition exists, or to request copies of publications, contact: ZiLOG Worldwide Headquarters 532 Race Street San Jose, CA 95126 Telephone: 408.558.8500 Fax: 408.558.8300 www.zilog.com ZiLOG® is a registered trademark of ZiLOG Inc. in the United States and in other countries. All other products and/or service names mentioned herein may be trademarks of the companies with which they are associated. Document Disclaimer ©2003 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Except with the express written approval ZiLOG, use of information, devices, or technology as critical components of life support systems is not authorized. No licenses or other rights are conveyed, implicitly or otherwise, by this document under any intellectual property rights. PS015304-0203 PS015304-0203 PRELIMINARY eZ80Acclaim! Flash Microcontrollers eZ80F92/eZ80F93 Product Specification iii Table of Contents List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .vii List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 eZ80® CPU Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Voltage Brown-Out Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 SLEEP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 HALT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Clock Peripheral Power-Down Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 38 General-Purpose Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 GPIO Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 GPIO Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 GPIO Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 GPIO Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Nonmaskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Chip Selects and Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Memory and I/O Chip Selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Memory Chip Select Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 I/O Chip Select Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 WAIT Input Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Chip Selects During Bus Request/Bus Acknowledge Cycles . . . . . . . . . . . 54 Bus Mode Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 eZ80 Bus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 PS015304-0203 PS015304-0203 PRELIMINARY Table of Contents eZ80Acclaim! Flash Microcontrollers eZ80F92/eZ80F93 Product Specification iv Z80 Bus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Intel Bus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Motorola Bus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Chip Select Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Watch-Dog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Watch-Dog Timer Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Watch-Dog Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Watch-Dog Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Programmable Reload Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Programmable Reload Timers Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Programmable Reload Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Programmable Reload Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Real-Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Real-Time Clock Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Real-Time Clock Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Real-Time Clock Oscillator and Source Selection . . . . . . . . . . . . . . . . . . . . 91 Real-Time Clock Battery Backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Real-Time Clock Recommended Operation . . . . . . . . . . . . . . . . . . . . . . . . 91 Real-Time Clock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Universal Asynchronous Receiver/Transmitter . . . . . . . . . . . . . . . . . . . . . . . . 106 UART Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 UART Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 UART Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 UART Recommended Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 BRG Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 UART Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Infrared Encoder/Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Receiver Frequency Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Infrared Encoder/Decoder Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Loopback Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 SPI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 SPI Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 SPI Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 SPI Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 PS015304-0203 PS015304-0203 PRELIMINARY Table of Contents eZ80Acclaim! Flash Microcontrollers eZ80F92/eZ80F93 Product Specification v Data Transfer Procedure with SPI Configured as the Master . . . . . . . . . . Data Transfer Procedure with SPI Configured as a Slave . . . . . . . . . . . . SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2C Serial I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I I2C General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transferring Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZiLOG Debug Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZDI-Supported Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZDI Clock and Data Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZDI Start Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZDI Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZDI Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZDI Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation of the eZ80F92 Device During ZDI Breakpoints . . . . . . . . . . . . Bus Requests During ZDI DEBUG Mode . . . . . . . . . . . . . . . . . . . . . . . . . ZDI Write Only Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZDI Read Only Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZDI Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Instrumentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction to On-Chip Instrumentation . . . . . . . . . . . . . . . . . . . . . . . . . . OCI Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OCI Information Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Random Access Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Memory Arrangement in the eZ80F92 . . . . . . . . . . . . . . . . . . . . . . . Flash Memory Arrangement in the eZ80F93 . . . . . . . . . . . . . . . . . . . . . . . Flash Memory Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Erasing Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . eZ80® CPU Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Op-Code Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 MHz Primary Crystal Oscillator Operation . . . . . . . . . . . . . . . . . . . . . . PS015304-0203 PS015304-0203 PRELIMINARY 136 136 136 141 141 143 144 146 153 162 162 163 164 164 165 166 167 168 169 170 171 171 187 187 187 188 189 190 191 193 193 194 194 195 197 198 207 211 218 218 Table of Contents eZ80Acclaim! Flash Microcontrollers eZ80F92/eZ80F93 Product Specification vi 32 KHz Real-Time Clock Crystal Oscillator Operation . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . POR and VBO Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Current Consumption Under Various Operating Conditions . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Memory Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Memory Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External I/O Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External I/O Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait State Timing for Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait State Timing for Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . General Purpose I/O Port Input Sample Timing . . . . . . . . . . . . . . . . . . . . External Bus Acknowledge Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External System Clock Driver (PHI) Timing . . . . . . . . . . . . . . . . . . . . . . . ZiLOG Debug Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Part Number Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Precharacterization Product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Document Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Document Number Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Change Log . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Customer Feedback Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PS015304-0203 PS015304-0203 PRELIMINARY 219 221 221 221 223 223 228 229 230 232 233 234 235 236 237 237 237 239 240 241 241 242 242 242 252 Table of Contents eZ80Acclaim! Flash Microcontrollers eZ80F92/eZ80F93 Product Specification vii List of Figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. PS015304-0203 PS015304-0203 eZ80F92 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 100-Pin LQFP Configuration of the eZ80F92 Device . . . . . . . . . . . . 4 Power-On Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Voltage Brown-Out Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . 36 GPIO Port Pin Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Example: Memory Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Wait Input Sampling Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 53 Example: Wait State Operation Read Operation . . . . . . . . . . . . . . . 54 Example: Z80 Bus Mode Read Timing . . . . . . . . . . . . . . . . . . . . . . 56 Example: Z80 Bus Mode Write Timing . . . . . . . . . . . . . . . . . . . . . . 57 Intel Bus Mode Signal and Pin Mapping . . . . . . . . . . . . . . . . . . . . . 58 Example: Intel Bus Mode Read Timing- Separate Address and Data Buses . . . . . . . . . . . . . . . . . . . . . . . . . 60 Example: Intel Bus Mode Write Timing- Separate Address and Data Buses . . . . . . . . . . . . . . . . . . . . . . . . . 61 Example: Intel Bus Mode Read Timing- Multiplexed Address and Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . 63 Example: Intel Bus Mode Write Timing- Multiplexed Address and Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . 64 Motorola Bus Mode Signal and Pin Mapping . . . . . . . . . . . . . . . . . 65 Example: Motorola Bus Mode Read Timing . . . . . . . . . . . . . . . . . . 67 Example: Motorola Bus Mode Write Timing . . . . . . . . . . . . . . . . . . 68 Watch-Dog Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Programmable Reload Timer Block Diagram . . . . . . . . . . . . . . . . . 78 PRT Single Pass Mode Operation Example . . . . . . . . . . . . . . . . . . 80 PRT Continuous Mode Operation Example . . . . . . . . . . . . . . . . . . 81 PRT Timer Output Operation Example . . . . . . . . . . . . . . . . . . . . . . 83 Real-Time Clock and 32KHz Oscillator Block Diagram . . . . . . . . . . 90 UART Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Infrared System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Infrared Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Infrared Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 SPI Master Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 SPI Slave Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 PRELIMINARY List of Figures eZ80Acclaim! Flash Microcontrollers eZ80F92/eZ80F93 Product Specification viii Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. PS015304-0203 PS015304-0203 I2C Clock and Data Relationship . . . . . . . . . . . . . . . . . . . . . . . . . . START and STOP Conditions In I2C Protocol . . . . . . . . . . . . . . . . I2C Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Synchronization In I2C Protocol . . . . . . . . . . . . . . . . . . . . . . Typical ZDI Debug Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Schematic For Building a Target Board ZPAKII Connector . . . . . ZDI Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZDI Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZDI Address Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZDI Single-Byte Data Write Timing . . . . . . . . . . . . . . . . . . . . . . . . ZDI Block Data Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZDI Single-Byte Data Read Timing . . . . . . . . . . . . . . . . . . . . . . . . ZDI Block Data Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . eZ80F92 On-Chip RAM Memory Addressing Example . . . . . . . . . eZ80F93 On-Chip RAM Memory Addressing Example . . . . . . . . . eZ80F92 Flash Memory Arrangement . . . . . . . . . . . . . . . . . . . . . . eZ80F93 Flash Memory Arrangement . . . . . . . . . . . . . . . . . . . . . . Flash Memory Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Crystal Oscillator Configuration (20MHz operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Crystal Oscillator Configuration (32KHz operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ICC Versus WAIT States as a Function of Frequency . . . . . . . . . ICC Versus Frequency as a Function of WAIT States . . . . . . . . . ICC Versus Temperature as a Function of Frequency . . . . . . . . . ICC Versus Frequency in HALT Mode . . . . . . . . . . . . . . . . . . . . . ICC Versus Temperature in SLEEP Mode . . . . . . . . . . . . . . . . . . External Memory Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . External Memory Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . External I/O Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External I/O Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait State Timing for Read Operations . . . . . . . . . . . . . . . . . . . . . Wait State Timing for Write Operations . . . . . . . . . . . . . . . . . . . . . Port Input Sample Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZDI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100-Lead Plastic Low-Profile Quad Flat Package (LQFP) . . . . . . PRELIMINARY 142 142 143 144 145 162 163 164 165 166 166 167 168 168 190 191 193 194 195 218 219 224 225 226 227 228 229 230 232 233 234 235 236 237 239 List of Figures eZ80Acclaim! Flash Microcontrollers eZ80F92/eZ80F93 Product Specification ix List of Tables Table 1. 100-Pin LQFP Pin Identification of the eZ80F92 Device . . . . . . . . . . . . 5 Table 2. Pin Characteristics of the eZ80F92 Device . . . . . . . . . . . . . . . . . . . . . 20 Table 3. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 4. Clock Peripheral Power-Down Register 1 . . . . . . . . . . . . . . . . . . . . . . 39 Table 5. Clock Peripheral Power-Down Register 2 . . . . . . . . . . . . . . . . . . . . . . 40 Table 6. GPIO Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 7. Port x Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 8. Port x Data Direction Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 9. Port x Alternate Registers 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 10. Port x Alternate Registers 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 11. Interrupt Vector Sources by Priority . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 12. Vectored Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 13. Register Values for Memory Chip Select Example in Figure 6 . . . . . 52 Table 14. Z80 Bus Mode Read States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 15. Z80 Bus Mode Write States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 16. Intel Bus Mode Read States (Separate Address and Data Buses) . . 58 Table 17. Intel Bus Mode Write States (Separate Address and Data Buses) . . 59 Table 18. Intel Bus Mode Read States (Multiplexed Address and Data Bus) . . 62 Table 19. Intel Bus Mode Write States (Multiplexed Address and Data Bus) . . 62 Table 20. Motorola Bus Mode Read States . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 21. Motorola Bus Mode Write States . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 22. Chip Select x Lower Bound Register . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 23. Chip Select x Upper Bound Register . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 24. Chip Select x Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 25. Chip Select x Bus Mode Control Register . . . . . . . . . . . . . . . . . . . . . 72 Table 26. Watch-Dog Timer Approximate Time-Out Delays . . . . . . . . . . . . . . . 75 Table 27. Watch-Dog Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 28. Watch-Dog Timer Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 29. PRT Single Pass Mode Operation Example . . . . . . . . . . . . . . . . . . . 80 Table 30. PRT Continuous Mode Operation Example . . . . . . . . . . . . . . . . . . . 81 Table 31. PRT Timer Out Operation Example . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 32. Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 33. Timer Data Register-Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Table 34. Timer Data Register-High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table 35. Timer Reload Register-Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . 86 PS015304-0203 PS015304-0203 PRELIMINARY List of Tables eZ80Acclaim! Flash Microcontrollers eZ80F92/eZ80F93 Product Specification x Table 36. Timer Reload Register-High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 37. Timer Input Source Select Register . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 38. Real-Time Clock Seconds Register . . . . . . . . . . . . . . . . . . . . . . . . . 92 Table 39. Real-Time Clock Minutes Register . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Table 40. Real-Time Clock Hours Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Table 41. Real-Time Clock Day-of-the-Week Register . . . . . . . . . . . . . . . . . . . 95 Table 42. Real-Time Clock Day-of-the-Month Register . . . . . . . . . . . . . . . . . . 96 Table 43. Real-Time Clock Month Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Table 44. Real-Time Clock Year Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Table 45. Real-Time Clock Century Register . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Table 46. Real-Time Clock Alarm Seconds Register . . . . . . . . . . . . . . . . . . . 100 Table 47. Real-Time Clock Alarm Minutes Register . . . . . . . . . . . . . . . . . . . . 101 Table 48. Real-Time Clock Alarm Hours Register . . . . . . . . . . . . . . . . . . . . . 102 Table 49. Real-Time Clock Alarm Day-of-the-Week Register . . . . . . . . . . . . . 103 Table 50. Real-Time Clock Alarm Control Register . . . . . . . . . . . . . . . . . . . . 104 Table 51. Real-Time Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Table 52. UART Baud Rate Generator Register-High Bytes . . . . . . . . . . . . 113 Table 53. UART Baud Rate Generator Register-Low Bytes . . . . . . . . . . . . . 113 Table 54. UART Transmit Holding Registers . . . . . . . . . . . . . . . . . . . . . . . . . 114 Table 55. UART Receive Buffer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Table 56. UART Interrupt Enable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Table 57. UART Interrupt Identification Registers . . . . . . . . . . . . . . . . . . . . . . 116 Table 58. UART Interrupt Status Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Table 59. UART FIFO Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Table 60. UART Line Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Table 61. UART Character Parameter Definition . . . . . . . . . . . . . . . . . . . . . . 119 Table 62. Parity Select Definition for Multidrop Communications . . . . . . . . . . 119 Table 63. UART Modem Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Table 64. UART Line Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Table 65. UART Modem Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Table 66. UART Scratch Pad Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Table 67. IrDA Physical Layer 1.4 Pulse Durations Specifications . . . . . . . . . 128 Table 68. Frequency Divider Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Table 69. GPIO Mode Selection when using the IrDA Encoder/Decoder . . . . 129 Table 70. Infrared Encoder/Decoder Control Registers . . . . . . . . . . . . . . . . . 130 Table 71. SPI Clock Phase and Clock Polarity Operation . . . . . . . . . . . . . . . . 133 Table 72. SPI Baud Rate Generator Register-High Byte . . . . . . . . . . . . . . . 137 Table 73. SPI Baud Rate Generator Register-Low Byte . . . . . . . . . . . . . . . . 137 PS015304-0203 PS015304-0203 PRELIMINARY List of Tables eZ80Acclaim! Flash Microcontrollers eZ80F92/eZ80F93 Product Specification xi Table 74. SPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 75. SPI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 76. SPI Receive Buffer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 77. SPI Transmit Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 78. I2C Master Transmit Status Codes . . . . . . . . . . . . . . . . . . . . . . . . . Table 79. I2C 10-Bit Master Transmit Status Codes . . . . . . . . . . . . . . . . . . . . Table 80. I2C Master Transmit Status Codes For Data Bytes . . . . . . . . . . . . . Table 81. I2C Master Receive Status Codes . . . . . . . . . . . . . . . . . . . . . . . . . . Table 82. I2C Master Receive Status Codes For Data Bytes . . . . . . . . . . . . . Table 83. I2C Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 84. I2C Slave Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 85. I2C Extended Slave Address Registers . . . . . . . . . . . . . . . . . . . . . . Table 86. I2C Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 87. I2C Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 88. I2C Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 89. I2C Status Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 90. I2C Clock Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 91. I2C Software Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 92. Recommended ZDI Clock vs. System Clock Frequency . . . . . . . . . Table 93. ZDI Write Only Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 94. ZDI Read Only Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 95. ZDI Address Match Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 96. ZDI BREAK Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 97. ZDI Master Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 98. ZDI Read/Write Control Register Functions . . . . . . . . . . . . . . . . . . Table 99. ZDI Write Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 100. ZDI Bus Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 101. Instruction Store 4:0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 102. eZ80 Product ID Low Byte Register . . . . . . . . . . . . . . . . . . . . . . . Table 103. ZDI Write Memory Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 104. eZ80 Product ID Revision Register . . . . . . . . . . . . . . . . . . . . . . . . Table 105. eZ80 Product ID High Byte Register . . . . . . . . . . . . . . . . . . . . . . . Table 106. ZDI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 107. ZDI Read Register Low, High and Upper . . . . . . . . . . . . . . . . . . . Table 108. ZDI Bus Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 109. ZDI Read Memory Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 110. OCI Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 111. RAM Address Upper Byte Register . . . . . . . . . . . . . . . . . . . . . . . . PS015304-0203 PS015304-0203 PRELIMINARY 138 139 140 140 147 148 149 150 151 153 154 155 155 157 158 158 160 161 163 170 171 172 173 175 176 176 178 180 181 181 182 182 183 184 185 186 188 192 List of Tables eZ80Acclaim! Flash Microcontrollers eZ80F92/eZ80F93 Product Specification xii Table 112. RAM Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 113. Flash Key Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 114. Flash Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 115. Flash Address Upper Byte Register . . . . . . . . . . . . . . . . . . . . . . . Table 116. Flash Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 117. Flash Frequency Divider Values . . . . . . . . . . . . . . . . . . . . . . . . . . Table 118. Flash Frequency Divider Register . . . . . . . . . . . . . . . . . . . . . . . . . Table 119. Flash Write/Erase Protection Register . . . . . . . . . . . . . . . . . . . . . Table 120. Flash Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . Table 121. Flash Page Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 122. Flash Row Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 123. Flash Column Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 124. Flash Program Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . Table 125. Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 126. Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 127. Block Transfer and Compare Instructions . . . . . . . . . . . . . . . . . . . Table 128. Exchange Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 129. Input/Output Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 130. Load Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 131. Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 132. Processor Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 133. Program Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 134. Rotate and Shift Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 135. Op Code Map-First Op Code . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 136. Op Code Map-Second Op Code after 0CBh . . . . . . . . . . . . . . . . Table 137. Op Code Map-Second Op Code After 0DDh . . . . . . . . . . . . . . . Table 138. Op Code Map-Second Op Code After 0EDh . . . . . . . . . . . . . . . Table 139. Op Code Map-Second Op Code After 0FDh . . . . . . . . . . . . . . . Table 140. Op Code Map-Fourth Byte After 0DDh, 0CBh, and dd . . . . . . . . Table 141. Op Code Map-Fourth Byte After 0FDh, 0CBh, and dd . . . . . . . . Table 142. Recommended Crystal Oscillator Specifications (20MHz Operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 143. Recommended Crystal Oscillator Specifications (32KHz Operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 144. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 145. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 146. POR and VBO Electrical Characteristics . . . . . . . . . . . . . . . . . . . . Table 147. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PS015304-0203 PS015304-0203 PRELIMINARY 192 198 199 199 200 201 201 202 203 204 205 205 206 207 207 207 208 208 209 209 209 210 210 211 212 213 214 215 216 217 219 220 221 222 223 229 List of Tables eZ80Acclaim! Flash Microcontrollers eZ80F92/eZ80F93 Product Specification xiii Table 148. External Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 149. External Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 150. External I/O Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 151. External I/O Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 152. GPIO Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 153. Bus Acknowledge Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 154. PHI System Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 155. ZDI Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 156. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PS015304-0203 PS015304-0203 PRELIMINARY 230 231 232 233 236 237 237 238 240 List of Tables eZ80Acclaim! Flash Microcontrollers eZ80F92/eZ80F93 Product Specification 1 Architectural Overview The eZ80F92 device is a high-speed single-cycle instruction-fetch microcontroller with a maximum clock speed of 20MHz. It is the first member of ZiLOG's new eZ80Acclaim! product family, which offers on-chip Flash program memory. The eZ80F92 device can operate in Z80-compatible addressing mode (64KB) or full 24-bit addressing mode (16MB). The rich peripheral set of the eZ80F92 device makes it suitable for a variety of applications including industrial control, embedded communication, and point-of-sale terminals. Note: Additionally, ZiLOG offers the eZ80F93 device, which features scaleddown memory options. For purposes of clarity, this document refers to both devices collectively as the eZ80F92 device, unless otherwise specified. Features · · · · · · · · · · Single-cycle instruction fetch, high-performance, pipelined eZ80® CPU core1 eZ80F92 contains 128KB 128KB Flash memory and 8KB SRAM eZ80F93 contains 64KB Flash memory and 4KB SRAM Low power features including SLEEP mode, HALT mode, and selective peripheral power-down control Two UARTs with independent baud rate generators SPI with independent clock rate generator I2C with independent clock rate generator IrDA-compliant infrared encoder/decoder New DMA-like CPU instructions for efficient block data transfer Glueless external peripheral interface with 4 Chip Selects, individual Wait State generators, and an external WAIT input pin-supports Z80-, Intel-, and Motorola-style buses · Fixed-priority vectored interrupts (both internal and external) and interrupt controller · Real-Time Clock with on-chip 32KHz oscillator, selectable 50/60Hz input, and separate VDD pin for battery backup · Six 16-bit Counter/Timers with prescalers and direct input/output drive 1. For simplicity, the term eZ80® CPU is referred to as CPU for the bulk of this document. PS015304-0203 PS015304-0203 PRELIMINARY Architectural Overview eZ80Acclaim! Flash Microcontrollers eZ80F92/eZ80F93 Product Specification 2 · · · · · · Watch-Dog Timer 24 bits of General-Purpose I/O JTAG and ZDI debug interfaces 100-pin LQFP package 3.0­3.6V supply voltage with 5V tolerant inputs Operating Temperature Range: ­ Standard: 0ºC to +70ºC ­ High: 0ºC to +105ºC Note: All signals with an overline are active Low. For example, B/W, for which WORD is active Low, and B/W, for which BYTE is active Low. Power connections follow these conventional descriptions: Connection Circuit Device Power VCC VDD Ground GND VSS Block Diagram Figure 1 illustrates a block diagram of the eZ80F92 processor. PS015304-0203 PS015304-0203 PRELIMINARY Architectural Overview eZ80Acclaim! Flash Microcontrollers eZ80F92/eZ80F93 Product Specification 3 Real-Time Clock and 32KHz Oscillator RTC_VDD RTC_XIN RTC_XOUT I2C Serial Interface SCL SDA BUSACK BUSREQ INSTRD IORQ MREQ RD WR DATA[7:0] Bus Controller SCK SPI Serial Parallel Interface SS 128KB/64KB 128KB/64KB Flash Memory ADDR[23:0] MISO MOSI CTS0/1 NMI RESET eZ80® CPU HALT_SLP JTAG/ZDI Debug Interface JTAG / ZDI Signals (5) WAIT DCD0/1 DSR0/1 8KB/4KB SRAM UART Universal Asynchronous Receiver/ Transmitter (2) DTR0/1 RI0/1 RTS0/1 Interrupt Vector [7:0] Interrupt Controller Chip Select & Wait State Generator CS0 CS1 CS2 CS3 DATA[7:0] RXD0/1 TXD0/1 ADDR[23:0] WDT Watchdog Timer T4_OUT T5_OUT Programmable Reload Timer/Counter (6) T0_IN T1_IN T2_IN T3_IN Crystal Oscillator and System Clock Generator XIN XOUT PHI PD[7:0] PC[7:0] PB[7:0] IR_RxD IR_TxD IrDA Encoder/ Decoder GPIO 8-bit General Purpose I/O Port (3) Figure 1. eZ80F92 Block Diagram PS015304-0203 PS015304-0203 PRELIMINARY Architectural Overview eZ80Acclaim! Flash Microcontrollers eZ80F92/eZ80F93 Product Specification 4 Pin Description 100-Pin LQFP 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PD7/RI0 PD6/DCD0 PD5/DSR0 PD4/DTR0 PD3/CTS0 PD2/RTS0 PD1/RxD0/IR_RxD PD0/TxD0/IR_TxD VDD TDO TDI TRIGOUT TCK TMS VSS RTC_VDD RTC_XOUT RTC_XIN VSS VDD HALT_SLP BUSACK BUSREQ NMI RESET ADDR21 ADDR21 ADDR22 ADDR22 ADDR23 ADDR23 CS0 CS1 CS2 CS3 VDD VSS DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 VDD VSS IORQ MREQ RD WR INSTRD WAIT ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 VDD VSS ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR10 ADDR11 ADDR11 ADDR12 ADDR12 ADDR13 ADDR13 ADDR14 ADDR14 VDD VSS ADDR15 ADDR15 ADDR16 ADDR16 ADDR17 ADDR17 ADDR18 ADDR18 ADDR19 ADDR19 ADDR20 ADDR20 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PHI SCL SDA VSS VDD PB7/MOSI PB6/MISO PB5/T5_OUT PB4/T4_OUT PB3/SCK PB2/SS PB1/T1_IN PB0/T0_IN VDD XOUT XIN VSS PC7/RI1 PC6/DCD1 PC5/DSR1 PC4/DTR1 PC3/CTS1 PC2//RTS1 PC1/RxD1 PC0/TxD1 Figure 2 illustrates the pin layout of the eZ80F92 device in the 100-pin LQFP package. Table 1 describes the pins and their functions. Figure 2. 100-Pin LQFP Configuration of the eZ80F92 Device PS015304-0203 PS015304-0203 PRELIMINARY Architectural Overview eZ80Acclaim! Flash Microcontrollers eZ80F92/eZ80F93 Product Specification 5 Table 1. 100-Pin LQFP Pin Identification of the eZ80F92 Device Pin # Symbol Function Signal Direction Description 1 ADDR0 Address Bus Bidirectional Configured as an output in normal operation. The address bus selects a location in memory or I/O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select/Wait State Generator block to generate Chip Selects. 2 ADDR1 Address Bus Bidirectional Configured as an output in normal operation. The address bus selects a location in memory or I/O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select/Wait State Generator block to generate Chip Selects. 3 ADDR2 Address Bus Bidirectional Configured as an output in normal operation. The address bus selects a location in memory or I/O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select/Wait State Generator block to generate Chip Selects. 4 ADDR3 Address Bus Bidirectional Configured as an output in normal operation. The address bus selects a location in memory or I/O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select/Wait State Generator block to generate Chip Selects. 5 ADDR4 Address Bus Bidirectional Configured as an output in normal operation. The address bus selects a location in memory or I/O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select/Wait State Generator block to generate Chip Selects. 6 ADDR5 Address Bus Bidirectional Configured as an output in normal operation. The address bus selects a location in memory or I/O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select/Wait State Generator block to generate Chip Selects. PS015304-0203 PS015304-0203 PRELIMINARY Architectural Overview eZ80Acclaim! Flash Microcontrollers eZ80F92/eZ80F93 Product Specification 6 Table 1. 100-Pin LQFP Pin Identification of the eZ80F92 Device (Continued) Pin # Symbol Function 7 VDD Power Supply Power Supply. 8 VSS Ground Ground. 9 ADDR6 Address Bus Bidirectional Configured as an output in normal operation. The address bus selects a location in memory or I/O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select/Wait State Generator block to generate Chip Selects. 10 ADDR7 Address Bus Bidirectional Configured as an output in normal operation. The address bus selects a location in memory or I/O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select/Wait State Generator block to generate Chip Selects. 11 ADDR8 Address Bus Bidirectional Configured as an output in normal operation. The address bus selects a location in memory or I/O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select/Wait State Generator block to generate Chip Selects. 12 ADDR9 Address Bus Bidirectional Configured as an output in normal operation. The address bus selects a location in memory or I/O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select/Wait State Generator block to generate Chip Selects. 13 ADDR10 ADDR10 Address Bus Bidirectional Configured as an output in normal operation. The address bus selects a location in memory or I/O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select/Wait State Generator block to generate Chip Selects. PS015304-0203 PS015304-0203 Signal Direction Description PRELIMINARY Architectural Overview eZ80Acclaim! Flash Microcontrollers eZ80F92/eZ80F93 Product Specification 7 Table 1. 100-Pin LQFP Pin Identification of the eZ80F92 Device (Continued) Pin # Symbol Function Signal Direction Description 14 ADDR11 ADDR11 Address Bus Bidirectional Configured as an output in normal operation. The address bus selects a location in memory or I/O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select/Wait State Generator block to generate Chip Selects. 15 ADDR12 ADDR12 Address Bus Bidirectional Configured as an output in normal operation. The address bus selects a location in memory or I/O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select/Wait State Generator block to generate Chip Selects. 16 ADDR13 ADDR13 Address Bus Bidirectional Configured as an output in normal operation. The address bus selects a location in memory or I/O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select/Wait State Generator block to generate Chip Selects. 17 ADDR14 ADDR14 Address Bus Bidirectional Configured as an output in normal operation. The address bus selects a location in memory or I/O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select/Wait State Generator block to generate Chip Selects. 18 VDD Power Supply Power Supply. 19 VSS Ground Ground. 20 ADDR15 ADDR15 Address Bus PS015304-0203 PS015304-0203 Bidirectional Configured as an output in normal operation. The address bus selects a location in memory or I/O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select/Wait State Generator block to generate Chip Selects. PRELIMINARY Architectural Overview eZ80Acclaim! Flash Microcontrollers eZ80F92/eZ80F93 Product Specification 8 Table 1. 100-Pin LQFP Pin Identification of the eZ80F92 Device (Continued) Pin # Symbol Function Signal Direction Description 21 ADDR16 ADDR16 Address Bus Bidirectional Configured as an output in normal operation. The address bus selects a location in memory or I/O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select/Wait State Generator block to generate Chip Selects. 22 ADDR17 ADDR17 Address Bus Bidirectional Configured as an output in normal operation. The address bus selects a location in memory or I/O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select/Wait State Generator block to generate Chip Selects. 23 ADDR18 ADDR18 Address Bus Bidirectional Configured as an output in normal operation. The address bus selects a location in memory or I/O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select/Wait State Generator block to generate Chip Selects. 24 ADDR19 ADDR19 Address Bus Bidirectional Configured as an output in normal operation. The address bus selects a location in memory or I/O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select/Wait State Generator block to generate Chip Selects. 25 ADDR20 ADDR20 Address Bus Bidirectional Configured as an output in normal operation. The address bus selects a location in memory or I/O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select/Wait State Generator block to generate Chip Selects. 26 ADDR21 ADDR21 Address Bus Bidirectional Configured as an output in normal operation. The address bus selects a location in memory or I/O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select/Wait State Generator block to generate Chip Selects. PS015304-0203 PS015304-0203 PRELIMINARY Architectural Overview eZ80Acclaim! Flash Microcontrollers eZ80F92/eZ80F93 Product Specification 9 Table 1. 100-Pin LQFP Pin Identification of the eZ80F92 Device (Continued) Pin # Symbol Function Signal Direction Description 27 ADDR22 ADDR22 Address Bus Bidirectional Configured as an output in normal operation. The address bus selects a location in memory or I/O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select/Wait State Generator block to generate Chip Selects. 28 ADDR23 ADDR23 Address Bus Bidirectional Configured as an output in normal operation. The address bus selects a location in memory or I/O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select/Wait State Generator block to generate Chip Selects. 29 CS0 Chip Select 0 Output, Active Low CS0 Low indicates that an access is occurring in the defined CS0 memory or I/O address space. 30 CS1 Chip Select 1 Output, Active Low CS1 Low indicates that an access is occurring in the defined CS1 memory or I/O address space. 31 CS2 Chip Select 2 Output, Active Low CS2 Low indicates that an access is occurring in the defined CS2 memory or I/O address space. 32 CS3 Chip Select 3 Output, Active Low CS3 Low indicates that an access is occurring in the defined CS3 memory or I/O address space. 33 VDD Power Supply Power Supply. 34 VSS Ground Ground. 35 DATA0 Data Bus Bidirectional The data bus transfers data to and from I/O and memory devices. The eZ80Acclaim! drives these lines only during Write cycles when the CPU is the bus master. 36 DATA1 Data Bus Bidirectional The data bus transfers data to and from I/O and memory devices. The CPU drives these lines only during Write cycles when the CPU is the bus master. PS015304-0203 PS015304-0203 PRELIMINARY Architectural Overview eZ80Acclaim! Flash Microcontrollers eZ80F92/eZ80F93 Product Specification 10 Table 1. 100-Pin LQFP Pin Identification of the eZ80F92 Device (Continued) Pin # Symbol Function Signal Direction Description 37 DATA2 Data Bus Bidirectional The data bus transfers data to and from I/O and memory devices. The CPU drives these lines only during Write cycles when the CPU is the bus master. 38 DATA3 Data Bus Bidirectional The data bus transfers data to and from I/O and memory devices. The CPU drives these lines only during Write cycles when the CPU is the bus master. 39 DATA4 Data Bus Bidirectional The data bus transfers data to and from I/O and memory devices. The CPU drives these lines only during Write cycles when the CPU is the bus master. 40 DATA5 Data Bus Bidirectional The data bus transfers data to and from I/O and memory devices. The CPU drives these lines only during Write cycles when the CPU is the bus master. 41 DATA6 Data Bus Bidirectional The data bus transfers data to and from I/O and memory devices. The CPU drives these lines only during Write cycles when the CPU is the bus master. 42 DATA7 Data Bus Bidirectional The data bus transfers data to and from I/O and memory devices. The CPU drives these lines only during Write cycles when the CPU is the bus master. 43 VDD Power Supply Power Supply. 44 VSS Ground Ground. 45 IORQ Input/Output Request Bidirectional, Active Low IORQ indicates that the CPU is accessing a location in I/O space. RD and WR indicate the type of access. The CPU does not drive this line during RESET. It is an input in bus acknowledge cycles. 46 MREQ Memory Request Bidirectional, Active Low MREQ Low indicates that the CPU is accessing a location in memory. The RD, WR, and INSTRD signals indicate the type of access. The CPU does not drive this line during RESET. It is an input in bus acknowledge cycles. PS015304-0203 PS015304-0203 PRELIMINARY Architectural Overview eZ80Acclaim! Flash Microcontrollers eZ80F92/eZ80F93 Product Specification 11 Table 1. 100-Pin LQFP Pin Identification of the eZ80F92 Device (Continued) Pin # Symbol Function Signal Direction Description 47 RD Read Output, Active Low RD Low indicates that the CPU is reading from the current address location. This pin is tristated during bus acknowledge cycles. 48 WR Write Output, Active Low WR indicates that the CPU is writing to the current address location. This pin is tristated during bus acknowledge cycles. 49 INSTRD Instruction Output, Active Low Read Indicator INSTRD (with MREQ and RD) indicates the CPU is fetching an instruction from memory. This pin is tristated during bus acknowledge cycles. 50 WAIT WAIT Request Input, Active Low Driving the WAIT pin Low forces the CPU to wait additional clock cycles for an external peripheral or external memory to complete its Read or Write operation. 51 RESET System Reset Schmitt Trigger Input, This signal is used to initialize the CPU. Active Low This input must be Low for a minimum of 3 system clock cycles, and must be held Low until the clock is stable. This input includes a Schmitt trigger to allow RC rise times. 52 NMI Nonmaskable Interrupt Schmitt Trigger Input, The NMI input is a higher priority input than Active Low the maskable interrupts. It is always recognized at the end of an instruction, regardless of the state of the interrupt enable control bits. This input includes a Schmitt trigger to allow RC rise times. 53 BUSREQ Bus Request Input, Active Low External devices can request the CPU to release the memory interface bus for their use, by driving this pin Low. 54 BUSACK Bus Acknowledge Output, Active Low The CPU responds to a Low on BUSREQ, by tristating the address, data, and control signals, and by driving the BUSACK line Low. During bus acknowledge cycles ADDR[23:0], IORQ, and MREQ are inputs. 55 HALT_SLP HALT and SLEEP Indicator Output, Active Low A Low on this pin indicates that the CPU has entered either HALT or SLEEP mode because of execution of either a HALT or SLP instruction. 56 VDD Power Supply Power Supply. 57 VSS Ground Ground. PS015304-0203 PS015304-0203 PRELIMINARY Architectural Overview eZ80Acclaim! Flash Microcontrollers eZ80F92/eZ80F93 Product Specification 12 Table 1. 100-Pin LQFP Pin Identification of the eZ80F92 Device (Continued) Pin # Symbol Function Signal Direction Description 58 RTC_XIN Real-Time Clock Crystal Input Input This pin is the input to the low-power 32KHz crystal oscillator for the Real-Time Clock. 59 RTC_XOUT Real-Time Clock Crystal Output Bidirectional This pin is the output from the low-power 32KHz crystal oscillator for the Real-Time Clock. This pin is an input when the RTC is configured to operate from 50/60Hz input clock signals and the 32KHz crystal oscillator is disabled. 60 RTC_VDD Real-Time Clock Power Supply Power supply for the Real-Time Clock and associated 32KHz oscillator. Isolated from the power supply to the remainder of the chip. A battery can be connected to this pin to supply constant power to the Real-Time Clock and 32KHz oscillator. 61 VSS Ground Ground. 62 TMS JTAG Test Mode Select Input JTAG Mode Select Input. 63 TCK JTAG Test Clock Input JTAG and ZDI clock input. 64 TRIGOUT JTAG Test Output Trigger Output Active High trigger event indicator. 65 TDI JTAG Test Data In Bidirectional JTAG data input pin. Functions as ZDI data I/O pin when JTAG is disabled. 66 TDO JTAG Test Data Out Output JTAG data output pin. 67 VDD Power Supply PS015304-0203 PS015304-0203 Power Supply. PRELIMINARY Architectural Overview eZ80Acclaim! Flash Microcontrollers eZ80F92/eZ80F93 Product Specification 13 Table 1. 100-Pin LQFP Pin Identification of the eZ80F92 Device (Continued) Pin # Symbol Function Signal Direction Description 68 PD0 GPIO Port D Bidirectional This pin can be used for general-purpose I/ O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port D pin, when programmed as output, can be selected to be an open-drain or opensource output. Port D is multiplexed with one UART. TxD0 UART Output Transmit Data This pin is used by the UART to transmit asynchronous serial data. This signal is multiplexed with PD0. IR_TxD IrDA Transmit Data Output This pin is used by the IrDA encoder/ decoder to transmit serial data. This signal is multiplexed with PD0. PD1 GPIO Port D Bidirectional This pin can be used for general-purpose I/ O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port D pin, when programmed as output, can be selected to be an open-drain or opensource output. Port D is multiplexed with one UART. RxD0 Receive Data Input This pin is used by the UART to receive asynchronous serial data. This signal is multiplexed with PD1. IR_RxD IrDA Receive Data Input This pin is used by the IrDA encoder/ decoder to receive serial data. This signal is multiplexed with PD1. PD2 GPIO Port D Bidirectional This pin can be used for general-purpose I/ O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port D pin, when programmed as output, can be selected to be an open-drain or opensource output. Port D is multiplexed with one UART. RTS0 Request To Send Output, Active Low Modem control signal from UART. This signal is multiplexed with PD2. 69 70 PS015304-0203 PS015304-0203 PRELIMINARY Architectural Overview eZ80Acclaim! Flash Microcontrollers eZ80F92/eZ80F93 Product Specification 14 Table 1. 100-Pin LQFP Pin Identification of the eZ80F92 Device (Continued) Pin # Symbol Function Signal Direction Description 71 PD3 GPIO Port D Bidirectional This pin can be used for general-purpose I/ O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port D pin, when programmed as output, can be selected to be an open-drain or opensource output. Port D is multiplexed with one UART. CTS0 Clear To Send Input, Active Low Modem status signal to the UART. This signal is multiplexed with PD3. PD4 GPIO Port D This pin can be used for general-purpose I/ O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port D pin, when programmed as output, can be selected to be an open-drain or opensource output. Port D is multiplexed with one UART. DTR0 Data Terminal Output, Active Low Ready Modem control signal to the UART. This signal is multiplexed with PD4. PD5 GPIO Port D Bidirectional This pin can be used for general-purpose I/ O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port D pin, when programmed as output, can be selected to be an open-drain or opensource output. Port D is multiplexed with one UART. DSR0 Data Set Ready Input, Active Low Modem status signal to the UART. This signal is multiplexed with PD5. PD6 GPIO Port D Bidirectional This pin can be used for general-purpose I/ O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port D pin, when programmed as output, can be selected to be an open-drain or opensource output. Port D is multiplexed with one UART. DCD0 Data Carrier Detect Input, Active Low Modem status signal to the UART. This signal is multiplexed with PD6. 72 73 74 PS015304-0203 PS015304-0203 Bidirectional PRELIMINARY Architectural Overview eZ80Acclaim! Flash Microcontrollers eZ80F92/eZ80F93 Product Specification 15 Table 1. 100-Pin LQFP Pin Identification of the eZ80F92 Device (Continued) Pin # Symbol Function Signal Direction Description 75 PD7 GPIO Port D Bidirectional This pin can be used for general-purpose I/ O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port D pin, when programmed as output, can be selected to be an open-drain or opensource output. Port D is multiplexed with one UART. RI0 Ring Indicator Input, Active Low Modem status signal to the UART. This signal is multiplexed with PD7. PC0 GPIO Port C Bidirectional This pin can be used for general-purpose I/ O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port C pin, when programmed as output, can be selected to be an open-drain or opensource output. Port C is multiplexed with one UART. TxD1 Transmit Data Output This pin is used by the UART to transmit asynchronous serial data. This signal is multiplexed with PC0. PC1 GPIO Port C Bidirectional This pin can be used for general-purpose I/ O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port C pin, when programmed as output, can be selected to be an open-drain or opensource output. Port C is multiplexed with one UART. RxD1 Receive Data Input This pin is used by the UART to receive asynchronous serial data. This signal is multiplexed with PC1. 76 77 PS015304-0203 PS015304-0203 PRELIMINARY Architectural Overview eZ80Acclaim! Flash Microcontrollers eZ80F92/eZ80F93 Product Specification 16 Table 1. 100-Pin LQFP Pin Identification of the eZ80F92 Device (Continued) Pin # Symbol Function Signal Direction Description 78 PC2 GPIO Port C Bidirectional This pin can be used for general-purpose I/ O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port C pin, when programmed as output, can be selected to be an open-drain or opensource output. Port C is multiplexed with one UART. RTS1 Request To Send Output, Active Low Modem control signal from UART. This signal is multiplexed with PC2. PC3 GPIO Port C Bidirectional This pin can be used for general-purpose I/ O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port C pin, when programmed as output, can be selected to be an open-drain or opensource output. Port C is multiplexed with one UART. CTS1 Clear To Send Input, Active Low Modem status signal to the UART. This signal is multiplexed with PC3. PC4 GPIO Port C This pin can be used for general-purpose I/ O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port C pin, when programmed as output, can be selected to be an open-drain or opensource output. Port C is multiplexed with one UART. DTR1 Data Terminal Output, Active Low Ready Modem control signal to the UART. This signal is multiplexed with PC4. PC5 GPIO Port C Bidirectional This pin can be used for general-purpose I/ O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port C pin, when programmed as output, can be selected to be an open-drain or opensource output. Port C is multiplexed with one UART. DSR1 Data Set Ready Input, Active Low Modem status signal to the UART. This signal is multiplexed with PC5. 79 80 81 PS015304-0203 PS015304-0203 Bidirectional PRELIMINARY Architectural Overview eZ80Acclaim! Flash Microcontrollers eZ80F92/eZ80F93 Product Specification 17 Table 1. 100-Pin LQFP Pin Identification of the eZ80F92 Device (Continued) Pin # Symbol Function Signal Direction Description 82 PC6 GPIO Port C Bidirectional This pin can be used for general-purpose I/ O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port C pin, when programmed as output, can be selected to be an open-drain or opensource output. Port C is multiplexed with one UART. DCD1 Data Carrier Detect Input, Active Low Modem status signal to the UART. This signal is multiplexed with PC6. PC7 GPIO Port C Bidirectional This pin can be used for general-purpose I/ O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port C pin, when programmed as output, can be selected to be an open-drain or opensource output. Port C is multiplexed with one UART. RI1 Ring Indicator Input, Active Low Modem status signal to the UART. This signal is multiplexed with PC7. 84 VSS Ground Ground. 85 XIN System Clock Input Oscillator Input This pin is the input to the onboard crystal oscillator for the primary system clock. If an external oscillator is used, its clock output should be connected to this pin. When a crystal is used, it should be connected between XIN and XOUT. 86 XOUT System Clock Oscillator Output This pin is the output of the onboard crystal oscillator. When used, a crystal should be connected between XIN and XOUT. 87 VDD Power Supply 83 PS015304-0203 PS015304-0203 Output Power Supply. PRELIMINARY Architectural Overview eZ80Acclaim! Flash Microcontrollers eZ80F92/eZ80F93 Product Specification 18 Table 1. 100-Pin LQFP Pin Identification of the eZ80F92 Device (Continued) Pin # Symbol Function Signal Direction Description 88 PB0 GPIO Port B Bidirectional This pin can be used for general-purpose I/ O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port B pin, when programmed as output, can be selected to be an open-drain or opensource output. T0_IN Timer 0 In Input Alternate clock source for Programmable Reload Timers 0 and 2. This signal is multiplexed with PB0. PB1 GPIO Port B Bidirectional This pin can be used for general-purpose I/ O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port B pin, when programmed as output, can be selected to be an open-drain or opensource output. T1_IN Timer 1 In Input Alternate clock source for Programmable Reload Timers 1 and 3. This signal is multiplexed with PB1. PB2 GPIO Port B Bidirectional This pin can be used for general-purpose I/ O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port B pin, when programmed as output, can be selected to be an open-drain or opensource output. SS Slave Select Input, Active Low The slave select input line is used to select a slave device in SPI mode. This signal is multiplexed with PB2. PB3 GPIO Port B Bidirectional This pin can be used for general-purpose I/ O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port B pin, when programmed as output, can be selected to be an open-drain or opensource output. SCK SPI Serial Clock Bidirectional SPI serial clock. This signal is multiplexed with PB3. 89 90 91 PS015304-0203 PS015304-0203 PRELIMINARY Architectural Overview eZ80Acclaim! Flash Microcontrollers eZ80F92/eZ80F93 Product Specification 19 Table 1. 100-Pin LQFP Pin Identification of the eZ80F92 Device (Continued) Pin # Symbol Function Signal Direction Description 92 PB4 GPIO Port B Bidirectional This pin can be used for general-purpose I/ O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port B pin, when programmed as output, can be selected to be an open-drain or opensource output. T4_OUT Timer 4 Out Output Programmable Reload Timer 4 timer-out signal. This signal is multiplexed with PB4. PB5 GPIO Port B Bidirectional This pin can be used for general-purpose I/ O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port B pin, when programmed as output, can be selected to be an open-drain or opensource output. T5_OUT Timer 5 Out Output Programmable Reload Timer 5 timer-out signal. This signal is multiplexed with PB5. PB6 GPIO Port B Bidirectional This pin can be used for general-purpose I/ O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port B pin, when programmed as output, can be selected to be an open-drain or opensource output. MISO Master In, Slave Out Bidirectional The MISO line is configured as an input when the CPU is an SPI master device and as an output when CPU is an SPI slave device. This signal is multiplexed with PB6. PB7 GPIO Port B Bidirectional This pin can be used for general-purpose I/ O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port B pin, when programmed as output, can be selected to be an open-drain or opensource output. MOSI Master Out, Slave In Bidirectional The MOSI line is configured as an output when the CPU is an SPI master device and as an input when the CPU is an SPI slave device. This signal is multiplexed with PB7. 93 94 95 PS015304-0203 PS015304-0203 PRELIMINARY Architectural Overview eZ80Acclaim! Flash Microcontrollers eZ80F92/eZ80F93 Product Specification 20 Table 1. 100-Pin LQFP Pin Identification of the eZ80F92 Device (Continued) Pin # Symbol Function Signal Direction Description 96 VDD Power Supply Power Supply. 97 VSS Ground Ground. 98 SDA I2C Serial Data Bidirectional This pin carries the I2C data signal. 99 SCL I2C Serial Clock Bidirectional This pin is used to receive and transmit the I2C clock. 100 PHI System Clock Output This pin is an output driven by the internal system clock. Pin Characteristics Table 2 describes the characteristics of each pin in the eZ80F92 device's 100-pin LQFP package. Table 2. Pin Characteristics of the eZ80F92 Device Pin # Symbol Reset Direction Direction Active Low/High Tristate Pull Output Up/Down Schmitt Trigger Input Open Drain/ Source 1 ADDR0 I/O O N/A Yes No No No 2 ADDR1 I/O O N/A Yes No No No 3 ADDR2 I/O O N/A Yes No No No 4 ADDR3 I/O O N/A Yes No No No 5 ADDR4 I/O O N/A Yes No No No 6 ADDR5 I/O O N/A Yes No No No 7 VDD 8 VSS 9 ADDR6 I/O O N/A Yes No No No 10 ADDR7 I/O O N/A Yes No No No 11 ADDR8 I/O O N/A Yes No No No 12 ADDR9 I/O O N/A Yes No No No 13 ADDR10 ADDR10 I/O O N/A Yes No No No 14 ADDR11 ADDR11 I/O O N/A Yes No No No 15 ADDR12 ADDR12 I/O O N/A Yes No No No PS015304-0203 PS015304-0203 PRELIMINARY Architectural Overview eZ80Acclaim! Flash Microcontrollers eZ80F92/eZ80F93 Product Specification 21 Table 2. Pin Characteristics of the eZ80F92 Device (Continued) Pin # Symbol Reset Direction Direction Active Low/High Tristate Pull Output Up/Down Schmitt Trigger Input Open Drain/ Source 16 ADDR13 ADDR13 I/O O N/A Yes No No No 17 ADDR14 ADDR14 I/O O N/A Yes No No No 18 VDD 19 VSS 20 ADDR15 ADDR15 I/O O N/A Yes No No No 21 ADDR16 ADDR16 I/O O N/A Yes No No No 22 ADDR17 ADDR17 I/O O N/A Yes No No No 23 ADDR18 ADDR18 I/O O N/A Yes No No No 24 ADDR19 ADDR19 I/O O N/A Yes No No No 25 ADDR20 ADDR20 I/O O N/A Yes No No No 26 ADDR21 ADDR21 I/O O N/A Yes No No No 27 ADDR22 ADDR22 I/O O N/A Yes No No No 28 ADDR23 ADDR23 I/O O N/A Yes No No No 29 CS0 O O Low No No No No 30 CS1 O O Low No No No No 31 CS2 O O Low No No No No 32 CS3 O O Low No No No No 33 VDD 34 VSS 35 DATA0 I/O I N/A Yes No No No 36 DATA1 I/O I N/A Yes No No No 37 DATA2 I/O I N/A Yes No No No 38 DATA3 I/O I N/A Yes No No No 39 DATA4 I/O I N/A Yes No No No 40 DATA5 I/O I N/A Yes No No No 41 DATA6 I/O I N/A Yes No No No 42 DATA7 I/O I N/A Yes No No No 43 VDD PS015304-0203 PS015304-0203 PRELIMINARY Architectural Overview eZ80Acclaim! Flash Microcontrollers eZ80F92/eZ80F93 Product Specification 22 Table 2. Pin Characteristics of the eZ80F92 Device (Continued) Pin # Symbol Reset Direction Direction Active Low/High Tristate Pull Output Up/Down Schmitt Trigger Input Open Drain/ Source 44 VSS 45 IORQ I/O O Low Yes No No No 46 MREQ I/O O Low Yes No No No 47 RD O O Low No No No No 48 WR O O Low No No No No 49 INSTRD O O Low No No No No 50 WAIT I I Low N/A No No N/A 51 RESET I I Low N/A No Yes N/A 52 NMI I I Low N/A No Yes N/A 53 BUSREQ I I Low N/A No No N/A 54 BUSACK O O Low No No No No 55 HALT_SLP O O Low No No No No 56 VDD 57 VSS 58 RTC_XIN I I N/A N/A No No N/A 59 RTC_XOUT I/O U N/A N/A No No No 60 RTC_VDD 61 VSS 62 TMS I I N/A N/A Up No N/A 63 TCK I I Rising (In) Falling (Out) N/A Up No N/A 64 TRIGOUT I/O O High Yes No No No 65 TDI I/O I N/A Yes No No No 66 TDO O O N/A Yes No No No 67 VDD 68 PD0 I/O I N/A Yes No No OD & OS 69 PD1 I/O I N/A Yes No No OD & OS 70 PD2 I/O I N/A Yes No No OD & OS 71 PD3 I/O I N/A Yes No No OD & OS PS015304-0203 PS015304-0203 PRELIMINARY Architectural Overview eZ80Acclaim! Flash Microcontrollers eZ80F92/eZ80F93 Product Specification 23 Table 2. Pin Characteristics of the eZ80F92 Device (Continued) Pin # Symbol Reset Direction Direction Active Low/High Tristate Pull Output Up/Down Schmitt Trigger Input Open Drain/ Source 72 PD4 I/O I N/A Yes No No OD & OS 73 PD5 I/O I N/A Yes No No OD & OS 74 PD6 I/O I N/A Yes No No OD & OS 75 PD7 I/O I N/A Yes No No OD & OS 76 PC0 I/O I N/A Yes No No OD & OS 77 PC1 I/O I N/A Yes No No OD & OS 78 PC2 I/O I N/A Yes No No OD & OS 79 PC3 I/O I N/A Yes No No OD & OS 80 PC4 I/O I N/A Yes No No OD & OS 81 PC5 I/O I N/A Yes No No OD & OS 82 PC6 I/O I N/A Yes No No OD & OS 83 PC7 I/O I N/A Yes No No OD & OS 84 VSS 85 XIN I I N/A N/A No No N/A 86 XOUT O O N/A No No No No 87 VDD 88 PB0 I/O I N/A Yes No No OD & OS 89 PB1 I/O I N/A Yes No No OD & OS 90 PB2 I/O I N/A Yes No No OD & OS 91 PB3 I/O I N/A Yes No No OD & OS 92 PB4 I/O I N/A Yes No No OD & OS 93 PB5 I/O I N/A Yes No No OD & OS 94 PB6 I/O I N/A Yes No No OD & OS 95 PB7 I/O I N/A Yes No No OD & OS 96 VDD 97 VSS 98 SDA I/O I N/A Yes Up No OD PS015304-0203 PS015304-0203 PRELIMINARY Architectural Overview eZ80Acclaim! Flash Microcontrollers eZ80F92/eZ80F93 Product Specification 24 Table 2. Pin Characteristics of the eZ80F92 Device (Continued) Pin # Symbol Reset Direction Direction Active Low/High Tristate Pull Output Up/Down Schmitt Trigger Input Open Drain/ Source 99 SCL I/O I N/A Yes Up No OD 100 PHI O O N/A Yes No No No PS015304-0203 PS015304-0203 PRELIMINARY Architectural Overview eZ80Acclaim! Flash Microcontrollers eZ80F92/eZ80F93 Product Specification 25 Register Map All on-chip peripheral registers are accessed in the I/O address space. All I/O operations employ 16-bit addresses. The upper byte of the 24-bit address bus is undefined during all I/O operations (ADDR[23:16] = UU). All I/O operations using 16-bit addresses within the range 0080h­00FFh are routed to the on-chip peripherals. External I/O Chip Selects are not generated if the address space programmed for the I/O Chip Selects overlaps the 0080h­00FFh address range. Registers at unused addresses within the 0080h­00FFh range assigned to onchip peripherals are not implemented. Read access to such addresses returns unpredictable values and Write access produces no effect. Table 3 diagrams the register map for the eZ80F92 device. Table 3. Register Map Address (hex) Mnemonic Reset (hex) Name CPU Page Access # Programmable Reload Counter/Timers 0080 TMR0_CTL Timer 0 Control Register 00 R/W 84 0081 TMR0_DR_L Timer 0 Data Register-Low Byte 00 R 85 TMR0_RR_L Timer 0 Reload Register-Low Byte 00 W 86 TMR0_DR_H Timer 0 Data Register-High Byte 00 R 86 TMR0_RR_H Timer 0 Reload Register-High Byte 00 W 87 0083 TMR1_CTL Timer 1 Control Register 00 R/W 84 0084 TMR1_DR_L Timer 1 Data Register-Low Byte 00 R 85 TMR1_RR_L Timer 1 Reload Register-Low Byte 00 W 86 TMR1_DR_H Timer 1 Data Register-High Byte 00 R 86 TMR1_RR_H Timer 1 Reload Register-High Byte 00 W 87 TMR2_CTL Timer 2 Control Register 00 R/W 84 0082 0085 0086 Programmable Reload Counter/Timers (continued) Notes: 1. After an external pin reset, the Watch-Dog Timer Control register is reset to 00h. After a Watch-Dog Timer timeout reset, the Watch-Dog Timer Control register is reset to 20h. 2. When the CPU reads this register, the current sampled value of the port is read. 3. Read Only if RTC registers are locked; Read/Write if RTC registers are unlocked. 4. After an external pin reset or a Watch-Dog Timer reset, the RTC Control register is reset to x0xxxx00b. After an RTC Alarm sleep-mode recovery reset, the RTC Control register is reset to x0xxxx10b. 5. Read Only if Flash Memory is locked. Read/Write if Flash Memory is unlocked. PS015304-0203 PS015304-0203 PRELIMINARY Register Map eZ80Acclaim! Flash Microcontrollers eZ80F92/eZ80F93 Product Specification 26 Table 3. Register Map (Continued) Address (hex) Mnemonic Name 0087 TMR2_DR_L Timer 2 Data Register-Low Byte 00 R 85 TMR2_RR_L Timer 2 Reload Register-Low Byte 00 W 86 TMR2_DR_H Timer 2 Data Register-High Byte 00 R 86 TMR2_RR_H Timer 2 Reload Register-High Byte 00 W 87 0089 TMR3_CTL Timer 3 Control Register 00 R/W 84 008A TMR3_DR_L Timer 3 Data Register-Low Byte 00 R 85 TMR3_RR_L Timer 3 Reload Register-Low Byte 00 W 86 TMR3_DR_H Timer 3 Data Register-High Byte 00 R 86 TMR3_RR_H Timer 3 Reload Register-High Byte 00 W 87 008C TMR4_CTL Timer 4 Control Register 00 R/W 84 008D TMR4_DR_L Timer 4 Data Register-Low Byte 00 R 85 TMR4_RR_L Timer 4 Reload Register-Low Byte 00 W 86 TMR4_DR_H Timer 4 Data Register-High Byte 00 R 86 TMR4_RR_H Timer 4 Reload Register-High Byte 00 W 87 008F TMR5_CTL Timer 5 Control Register 00 R/W 84 0090 TMR5_DR_L Timer 5 Data Register-Low Byte 00 R 85 TMR5_RR_L Timer 5 Reload Register-Low Byte 00 W 86 TMR5_DR_H Timer 5 Data Register-High Byte 00 R 86 TMR5_RR_H Timer 5 Reload Register-High Byte 00 W 87 TMR_ISS Timer Input Source Select Register 00 R/W 88 00/20 R/W 76 XX W 77 0088 008B 008E 0091 0092 Reset (hex) CPU Page Access # Watch-Dog Timer 0093 WDT_CTL Watch-Dog Timer Control Register1 0094 WDT_RR Watch-Dog Timer Reset Register Notes: 1. After an external pin reset, the Watch-Dog Timer Control register is reset to 00h. After a Watch-Dog Timer timeout reset, the Watch-Dog Timer Control register is reset to 20h. 2. When the CPU reads this register, the current sampled value of the port is read. 3. Read Only if RTC registers are locked; Read/Write if RTC registers are unlocked. 4. After an external pin reset or a Watch-Dog Timer reset, the RTC Control register is reset to x0xxxx00b. After an RTC Alarm sleep-mode recovery reset, the RTC Control register is reset to x0xxxx10b. 5. Read Only if Flash Memory is locked. Read/Write if Flash Memory is unlocked. PS015304-0203 PS015304-0203 PRELIMINARY Register Map eZ80Acclaim! Flash Microcontrollers eZ80F92/eZ80F93 Product Specification 27 Table 3. Register Map (Continued) Address (hex) Mnemonic Reset (hex) Name CPU Page Access # General-Purpose Input/Output Ports 009A PB_DR Port B Data Register2 XX R/W 45 009B PB_DDR Port B Data Direction Register FF R/W 46 009C PB_ALT1 Port B Alternate Register 1 00 R/W 46 009D PB_ALT2 Port B Alternate Register 2 00 R/W 46 009E PC_DR Port C Data Register2 XX R/W 45 009F PC_DDR Port C Data Direction Register FF R/W 46 00A0 PC_ALT1 Port C Alternate Register 1 00 R/W 46 00A1 PC_ALT2 Port C Alternate Register 2 00 R/W 46 00A2 PD_DR Port D Data Register2 XX R/W 45 00A3 PD_DDR Port D Data Direction Register FF R/W 46 00A4 PD_ALT1 Port D Alternate Register 1 00 R/W 46 00A5 PD_ALT2 Port D Alternate Register 2 00 R/W 46 Chip Select/Wait State Generator 00A8 CS0_LBR Chip Select 0 Lower Bound Register 00 R/W 69 00A9 CS0_UBR Chip Select 0 Upper Bound Register FF R/W 70 00AA CS0_CTL Chip Select 0 Control Register E8 R/W 71 00AB CS1_LBR Chip Select 1 Lower Bound Register 00 R/W 69 00AC CS1_UBR Chip Select 1 Upper Bound Register 00 R/W 70 00AD CS1_CTL Chip Select 1 Control Register 00 R/W 71 Chip Select/Wait State Generator (continued) 00AE CS2_LBR Chip Select 2 Lower Bound Register 00 R/W 69 00AF CS2_UBR Chip Select 2 Upper Bound Register 00 R/W 70 Notes: 1. After an external pin reset, the Watch-Dog Timer Control register is reset to 00h. After a Watch-Dog Timer timeout reset, the Watch-Dog Timer Control register is reset to 20h. 2. When the CPU reads this register, the current sampled value of the port is read. 3. Read Only if RTC registers are locked; Read/Write if RTC registers are unlocked. 4. After an external pin reset or a Watch-Dog Timer reset, the RTC Control register is reset to x0xxxx00b. After an RTC Alarm sleep-mode recovery reset, the RTC Control register is reset to x0xxxx10b. 5. Read Only if Flash Memory is locked. Read/Write if Flash Memory is unlocked. PS015304-0203 PS015304-0203 PRELIMINARY Register Map eZ80Acclaim! Flash Microcontrollers eZ80F92/eZ80F93 Product Specification 28 Table 3. Register Map (Continued) Address (hex) Mnemonic Name Reset (hex) CPU Page Access # 00B0 CS2_CTL Chip Select 2 Control Register 00 R/W 71 00B1 CS3_LBR Chip Select 3 Lower Bound Register 00 R/W 69 00B2 CS3_UBR Chip Select 3 Upper Bound Register 00 R/W 70 00B3 CS3_CTL Chip Select 3 Control Register 00 R/W 71 On-Chip RAM Control 00B4 RAM_CTL RAM Control Register 80 R/W 192 00B5 RAM_ADDR_U RAM Address Upper Byte Register FF R/W 192 Serial Peripheral Interface (SPI) Block 00B8 SPI_BRG_L SPI Baud Rate Generator Register-Low Byte 02 R/W 137 00B9 SPI_BRG_H SPI Baud Rate Generator Register-High Byte 00 R/W 137 00BA SPI_CTL SPI Control Register 04 R/W 138 00BB SPI_SR SPI Status Register 00 R 139 00BC SPI_TSR SPI Transmit Shift Register XX W 140 SPI_RBR SPI Receive Buffer Register XX R 140 00 R/W 130 Infrared Encoder/Decoder Block 00BF IR_CTL Infrared Encoder/Decoder Control Universal Asynchronous Receiver/Transmitter 0 (UART0) Block 00C0 UART0_RBR UART 0 Receive Buffer Register XX R 114 UART0_THR UART 0 Transmit Holding Register XX W 114 UART0_BRG_L UART 0 Baud Rate Generator Register- Low Byte 02 R/W 113 Notes: 1. After an external pin reset, the Watch-Dog Timer Control register is reset to 00h. After a Watch-Dog Timer timeout reset, the Watch-Dog Timer Control register is reset to 20h. 2. When the CPU reads this register, the current sampled value of the port is read. 3. Read Only if RTC registers are locked; Read/Write if RTC registers are unlocked. 4. After an external pin reset or a Watch-Dog Timer reset, the RTC Control register is reset to x0xxxx00b. After an RTC Alarm sleep-mode recovery reset, the RTC Control register is reset to x0xxxx10b. 5. Read Only if Flash Memory is locked. Read/Write if Flash Memory is unlocked. PS015304-0203 PS015304-0203 PRELIMINARY Register Map eZ80Acclaim! Flash Microcontrollers eZ80F92/eZ80F93 Product Specification 29 Table 3. Register Map (Continued) Address (hex) Mnemonic Name 00C1 UART0_IER UART 0 Interrupt Enable Register 00 R/W 115 UART0_BRG_H UART 0 Baud Rate Generator Register- High Byte 00 R/W 113 UART0_IIR UART 0 Interrupt Identification Register 01 R 116 UART0_FCTL UART 0 FIFO Control Register 00 W 117 00C3 UART0_LCTL UART 0 Line Control Register 00 R/W 118 00C4 UART0_MCTL UART 0 Modem Control Register 00 R/W 120 00C5 UART0_LSR UART 0 Line Status Register 60 R 121 00C6 UART0_MSR UART 0 Modem Status Register XX R 123 00C7 UART0_SPR UART 0 Scratch Pad Register 00 R/W 124 00C8 I2C_SAR I2C Slave Address Register 00 R/W 154 00C9 I2C_XSAR I2C Extended Slave Address Register 00 R/W 155 00CA I2C_DR I2C Data Register 00 R/W 155 00CB I2C_CTL I2C Control Register 00 R/W 157 I2C_SR I2C Status Register F8 R 158 I2C_CCR I2C Clock Control Register 00 W 160 I2C_SRR I2C Software Reset Register XX W 161 00C2 Reset (hex) CPU Page Access # I2C Block 00CC 00CD Universal Asynchronous Receiver/Transmitter 1 (UART1) Block 00D0 UART1_RBR UART 1 Receive Buffer Register XX R 114 UART1_THR UART 1 Transmit Holding Register XX W 114 UART1_BRG_L UART 1 Baud Rate Generator Register- Low Byte 02 R/W 113 Notes: 1. After an external pin reset, the Watch-Dog Timer Control register is reset to 00h. After a Watch-Dog Timer timeout reset, the Watch-Dog Timer Control register is reset to 20h. 2. When the CPU reads this register, the current sampled value of the port is read. 3. Read Only if RTC registers are locked; Read/Write if RTC registers are unlocked. 4. After an external pin reset or a Watch-Dog Timer reset, the RTC Control register is reset to x0xxxx00b. After an RTC Alarm sleep-mode recovery reset, the RTC Control register is reset to x0xxxx10b. 5. Read Only if Flash Memory is locked. Read/Write if Flash Memory is unlocked. PS015304-0203 PS015304-0203 PRELIMINARY Register Map eZ80Acclaim! Flash Microcontrollers eZ80F92/eZ80F93 Product Specification 30 Table 3. Register Map (Continued) Address (hex) Mnemonic Name 00D1 UART1_IER UART 1 Interrupt Enable Register 00 R/W 115 UART1_BRG_H UART 1 Baud Rate Generator Register- High Byte 00 R/W 113 UART1_IIR UART 1 Interrupt Identification Register 01 R 116 UART1_FCTL UART 1 FIFO Control Register 00 W 117 00D3 UART1_LCTL UART 1 Line Control Register 00 R/W 118 00D4 UART1_MCTL UART 1 Modem Control Register 00 R/W 120 00D5 UART1_LSR UART 1 Line Status Register 60 R/W 121 00D6 UART1_MSR UART 1 Modem Status Register XX R/W 123 00D7 UART1_SPR UART 1 Scratch Pad Register 00 R/W 124 00D2 Reset (hex) CPU Page Access # Low-Power Control 00DB CLK_PPD1 Clock Peripheral Power-Down Register 1 00 R/W 39 00DC CLK_PPD2 Clock Peripheral Power-Down Register 2 00 R/W 40 Real-Time Clock 00E0 RTC_SEC RTC Seconds Register3 XX R/W 92 00E1 RTC_MIN RTC Minutes Register3 XX R/W 93 Register3 XX R/W 94 0X R/W 95 00E2 RTC_HRS RTC Hours 00E3 RTC_DOW RTC Day-of-the-Week Register3 Notes: 1. After an external pin reset, the Watch-Dog Timer Control register is reset to 00h. After a Watch-Dog Timer timeout reset, the Watch-Dog Timer Control register is reset to 20h. 2. When the CPU reads this register, the current sampled value of the port is read. 3. Read Only if RTC registers are locked; Read/Write if RTC registers are unlocked. 4. After an external pin reset or a Watch-Dog Timer reset, the RTC Control register is reset to x0xxxx00b. After an RTC Alarm sleep-mode recovery reset, the RTC Control register is reset to x0xxxx10b. 5. Read Only if Flash Memory is locked. Read/Write if Flash Memory is unlocked. PS015304-0203 PS015304-0203 PRELIMINARY Register Map eZ80Acclaim! Flash Microcontrollers eZ80F92/eZ80F93 Product Specification 31 Table 3. Register Map (Continued) Address (hex) Mnemonic Reset (hex) Name CPU Page Access # Real-Time Clock (continued) RTC_DOM RTC Day-of-the-Month Register3 XX R/W 96 00E5 RTC_MON RTC Month Register3 XX R/W 97 00E6 RTC_YR RTC Year Register3 XX R/W 98 XX R/W 99 00E4 Register3 00E7 RTC_CEN RTC Century 00E8 RTC_ASEC RTC Alarm Seconds Register XX R/W 100 00E9 RTC_AMIN RTC Alarm Minutes Register XX R/W 101 00EA RTC_AHRS RTC Alarm Hours Register XX R/W 102 00EB RTC_ADOW RTC Alarm Day-of-the-Week Register 0X R/W 103 00EC RTC_ACTRL RTC Alarm Control Register 00 R/W 104 x0xxx000b/ x0xxxx10b R/W 105 00ED RTC_CTRL RTC Control Register4 Chip Select Bus Mode Control 00F0 CS0_BMC Chip Select 0 Bus Mode Control Register 02 R/W 72 00F1 CS1_BMC Chip Select 1 Bus Mode Control Register 02 R/W 72 00F2 CS2_BMC Chip Select 2 Bus Mode Control Register 02 R/W 72 00F3 CS3_BMC Chip Select 3 Bus Mode Control Register 02 R/W 72 Flash Memory Control Registers 00F5 FLASH_KEY Flash Key Register 00 W 198 00F6 FLASH_DATA Flash Data Register XX R/W 199 00F7 FLASH_ADDR_U Flash Address Upper Byte Register 0 R/W 199 00F8 FLASH_CTRL Flash Control Register 88 R/W 200 00F9 FLASH_FDIV Flash Frequency Divider Register5 01 R/W 201 FF R/W 202 00FA FLASH_PROT Flash Write/Erase Protection Register5 Notes: 1. After an external pin reset, the Watch-Dog Timer Control register is reset to 00h. After a Watch-Dog Timer timeout reset, the Watch-Dog Timer Control register is reset to 20h. 2. When the CPU reads this register, the current sampled value of the port is read. 3. Read Only if RTC register