Z86D990/Z86D991 Z86L990/Z86L991 PS003802-0901 Z86L99/Z86D99 P456CON TC16H TC16L - Datasheet Archive

 

Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC Preliminary Product Specification PS003802-0901 ZiLOG Worldwide

 

Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC Preliminary Product Specification PS003802-0901 PS003802-0901 ZiLOG Worldwide Headquarters · 910 E. Hamilton Avenue · Campbell, CA 95008 Telephone: 408.558.8500 · Fax: 408.558.8300 · www.ZiLOG.com This publication is subject to replacement by a later edition. To determine whether a later edition exists, or to request copies of publications, contact: ZiLOG Worldwide Headquarters 910 E. Hamilton Avenue Campbell, CA 95008 Telephone: 408.558.8500 Fax: 408.558.8300 www.ZiLOG.com Windows is a registered trademark of Microsoft Corporation. Document Disclaimer © 2001 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. 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P R E L I M I N A R Y PS003802-0901 PS003802-0901 Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC iii Table of Contents Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Counter/Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input/Output and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . User-Programmable Option Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 2 3 3 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pins Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Central Processing Unit (CPU) Description . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Memory (ROM/OTP and RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Clock Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Reset Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers (Grouped by Function) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 52 54 55 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Standard Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog-to-Digital Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 85 85 86 89 91 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Precharacterization Product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 PS003802-0901 PS003802-0901 P R E L I M I N A R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC iv List of Figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. PS003802-0901 PS003802-0901 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 48-Pin SSOP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 40-Pin DIP Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 28-Pin SOIC/DIP Pin Assignment-User Mode . . . . . . . . . . . . . . . . 7 Program Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Standard Z8 Register File (Working Reg. Groups 0­F, Bank 0) . . . 13 Z8 Expanded Register File Architecture . . . . . . . . . . . . . . . . . . . . . 14 Interrupt Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 External Interrupt Sources IRQ0­IRQ2 Block Diagram . . . . . . . . . . 17 IRQ Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Interrupt Request Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 General Input/Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Analog Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Low-Pass Filter (with 8-MHz Crystal) . . . . . . . . . . . . . . . . . . . . . . . 30 Active Glitch/Power Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 I-V Characteristics for the Current Sink Pad P43 . . . . . . . . . . . . . . . 34 T1 Counter/Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Prescaler 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Counter/Timer 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Timer Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Starting the Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Counting Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Timer Mode Register TOUT Operation . . . . . . . . . . . . . . . . . . . . . . . 40 Counter/Timer Output Using TOUT . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Internal Clock Output Using TOUT . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Timer Mode Register TIN Operation . . . . . . . . . . . . . . . . . . . . . . . . 42 Prescaler 1 TIN Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 External Clock Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Gated Clock Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Triggered Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Counter/Timer Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Transmit Mode Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 P R E L I M I N A R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC v Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. PS003802-0901 PS003802-0901 Demodulation Mode Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Load Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48-Pin SSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-Pin PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-Pin PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P R E L I M I N A R Y 50 86 91 92 92 93 Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC vi List of Tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. PS003802-0901 PS003802-0901 Z86L99/Z86D99 Z86L99/Z86D99 Feature Comparison . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Interrupt Types, Sources, and Vectors . . . . . . . . . . . . . . . . . . . . . . 15 Interrupt Edge Select for External Interrupts . . . . . . . . . . . . . . . . . . 17 Control and Status Register Reset Conditions . . . . . . . . . . . . . . . . 20 Clock Status in Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Special Port Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Active Glitch/Filter Specifications (Preliminary) . . . . . . . . . . . . . . . . 32 Current Sink Pad P43 Specifications (Preliminary) . . . . . . . . . . . . . 33 I/O Port Registers (Group 0, Bank 0, Registers 0­F) . . . . . . . . . . . 52 Timer Control Registers (Group 0, Bank D, Registers 0­F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Control and Status Registers (Group F, Bank 0, Registers 0­F) . . . 53 SMR and Port Mode Registers (Group 0, Bank F, Registers 0­F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Register Description Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 FLAGS Register [Group/Bank F0h, Register C (R252)] . . . . . . . . . 57 RP Register [Group/Bank F0h, Register D (R253)] . . . . . . . . . . . . . 58 SP Register [Group/Bank F0h, Register F (R255)] . . . . . . . . . . . . . 59 LB Register (Group/Bank 0Dh, Register C) . . . . . . . . . . . . . . . . . . . 60 ADCCTRL Register (Group/Bank 0Fh, Register 8) . . . . . . . . . . . . . 61 ADCDATA Register (Group/Bank 00h, Register 7) . . . . . . . . . . . . . 62 IMR (Group/Bank 0Fh, Register B) . . . . . . . . . . . . . . . . . . . . . . . . . 63 IPR (Group/Bank 0Fh, Register 9) . . . . . . . . . . . . . . . . . . . . . . . . . 64 IRQ (Group/Bank 0Fh, Register A) . . . . . . . . . . . . . . . . . . . . . . . . . 65 P456CON P456CON Register (Group/Bank 0Fh, Register 0) . . . . . . . . . . . . . 67 P2 Register [Group/Bank 00h, Register 2 (R2)] . . . . . . . . . . . . . . . 68 P2M Register [Group/Bank F0h, Register 6 (R246)] . . . . . . . . . . . . 68 P3M Register [Group/Bank F0h, Register 7 (R247)] . . . . . . . . . . . . 68 P4 Register [Group/Bank 00h, Register 4 (R4)] . . . . . . . . . . . . . . . 69 P4M Register (Group/Bank 0Fh, Register 2) . . . . . . . . . . . . . . . . . . 69 P5 Register [Group/Bank 00h, Register 5 (R5)] . . . . . . . . . . . . . . . 70 P5M Register (Group/Bank 0Fh, Register 4) . . . . . . . . . . . . . . . . . . 70 P6 Register [Group/Bank 00h, Register 6 (R6)] . . . . . . . . . . . . . . . 71 P R E L I M I N A R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC vii Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. PS003802-0901 PS003802-0901 P6M Register (Group/Bank 0Fh, Register 7) . . . . . . . . . . . . . . . . . . T1 Register [Group/Bank F0h, Register 2 (R242)] . . . . . . . . . . . . . TMR Register [Group/Bank F0h, Register 1 (R241)] . . . . . . . . . . . . PRE1 Register [Group/Bank F0h, Register 3 (R243)] . . . . . . . . . . . CTR1 Register (In Transmit Mode) (Group/Bank 0Dh, Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CTR1 Register (in Demodulation Mode) (Group/Bank 0Dh, Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CTR3 Register (Group/Bank 0Dh, Register 3) . . . . . . . . . . . . . . . . CTR0 Register (Group/Bank 0Dh, Register 0) . . . . . . . . . . . . . . . . HI8 Register (Group/Bank 0Dh, Register B) . . . . . . . . . . . . . . . . . . LO8 Register (Group/Bank 0Dh, Register A) . . . . . . . . . . . . . . . . . . TC8H Register (Group/Bank 0Dh, Register 5) . . . . . . . . . . . . . . . . TC8L Register (Group/Bank 0Dh, Register 4) . . . . . . . . . . . . . . . . . CTR2 Register (Group/Bank 0Dh, Register 2) . . . . . . . . . . . . . . . . HI16 Register (Group/Bank 0Dh, Register 9) . . . . . . . . . . . . . . . . . LO16 Register (Group/Bank 0Dh, Register 8) . . . . . . . . . . . . . . . . . TC16H TC16H Register (Group/Bank 0Dh, Register 7) . . . . . . . . . . . . . . . TC16L TC16L Register (Group/Bank 0Dh, Register 6) . . . . . . . . . . . . . . . . SMR Register (Group/Bank 0Fh, Register B) . . . . . . . . . . . . . . . . . P2SMR Register (Group/Bank 0Fh, Register 1) . . . . . . . . . . . . . . . P5SMR Register (Group/Bank 0Fh, Register 5) . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics for the Z86D99X Z86D99X (OTP Only) . . . . . . . . . . . . . . DC Characteristics for the Z86L99X Z86L99X (Mask Only) . . . . . . . . . . . . . . Analog-to-Digital Converter Characteristics . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P R E L I M I N A R Y 71 72 72 73 74 75 76 77 78 78 79 79 80 81 81 82 82 83 84 84 85 87 88 89 90 Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 1 Architectural Overview The Z86D99 Z86D99 is a low-voltage general-purpose one-time programmable (OTP) Z8® microcontroller with an integrated four-channel 8-bit sigma delta analog-to-digital converter. The Z86L99 Z86L99 is the read-only memory (ROM) version of this controller. The Z86D99/Z86L99 Z86D99/Z86L99 family is designed to be used in a wide variety of embedded control applications including battery chargers, home appliances, infrared (IR) remote controls, security systems, and wireless keyboards. It has three counter/timers, a general-purpose 8-bit counter/timer with a 6-bit prescaler and an 8-bit/16-bit counter/timer pair that can be used individually for general-purpose timing or as a pair to automate the generation and reception of complex pulses or signals. Unique features of the Z86D99/Z86L99 Z86D99/Z86L99 family of products include 489 bytes of general-purpose random-access memory (RAM), 256 bytes of which are mapped into the program memory space and can be used to store data variables or as executable RAM, a low-battery detection flag, and a controlled current output pin, which is a regulated current source that sinks a predefined current (ICCO). Table 1 highlights the basic product features of these microcontrollers. Table 1. Z86L99/Z86D99 Z86L99/Z86D99 Feature Comparison Pins I/O Memory (Bytes) Operating Voltage (V) ADC Timers Watch-Dog Timer Z86D990 Z86D990 40/48 32 32K OTP 3.0­5.5 4 channel 3 Yes Z86D991 Z86D991 28 24 32K OTP 3.0­5.5 - 3 Yes Z86L990 Z86L990 40/48 32 16K ROM 2.3­5.5 4 channel 3 Yes Z86L991 Z86L991 28 24 16K ROM 2.3­5.5 - 3 Yes The Z8 microcontroller core offers more flexibility and performance than accumulator-based microcontrollers. All 256 general-purpose registers, including dedicated input/output (I/O) port registers, can be used as accumulators. This unique register-to-register architecture avoids accumulator bottlenecks for high code efficiency. The registers can be used as address pointers for indirect addressing, as index registers, or for implementing an on-chip stack. The Z8 has a sophisticated interrupt structure and automatically saves the program counter and status flags on the stack for fast context-switching. Speed of execution and smooth programming are also supported by a "working register area" with short 4-bit register addresses. The Z8 instruction set, consisting of 43 basic instructions, is optimized for highcode density and reduced execution time. It is similar in form to the ZiLOG Z80 PS003802-0901 PS003802-0901 P R E L I M I N A R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 2 instruction set. The eight instruction types and six addressing modes together with the ability to operate on bits, 4-bit nibbles or binary coded decimal (BCD) digits, 8-bit bytes, and 16-bit words, make for a code-efficient, flexible microcontroller. Features · Four-channel, 8-bit sigma delta analog-to-digital (A/D) converter with external voltage references (not available in the 28-pin configuration) · · · Two independent analog comparators · · 32 Kbytes of OTP memory (Z86D99X Z86D99X) Controlled current output 489 bytes of RAM ­ 233 bytes of general-purpose register-based RAM ­ 256 bytes of RAM mapped into the program memory space that can be used as data RAM or executable RAM 16 Kbytes of ROM (Z86L99X Z86L99X) Counter/Timers · Special architecture to automate generation and reception of complex pulses or signals: ­ Programmable 8-bit counter/timer (T8) with two 8-bit capture registers and two 8-bit load registers ­ Programmable 16-bit counter/timer (T16) with one 16-bit capture register pair and one 16-bit load register pair ­ Programmable input glitch filter for pulse reception · One general-purpose 8-bit counter/timer (T1) with 6-bit prescaler Input/Output and Interrupts · · · PS003802-0901 PS003802-0901 Thirty-two I/Os, twenty-nine of which are bidirectional I/Os with programmable resistive pull-up transistors (24 I/Os are available in the 28-pin configuration) Sixteen I/Os are selectable as stop-mode recovery sources Six interrupt vectors with nine interrupt sources ­ Three external sources ­ Two comparator interrupts ­ Three timer interrupts P R E L I M I N A R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 3 ­ One low-battery detector flag Operating Characteristics · · · · 8-MHz operation · · Low-battery detection flag · 3.0 V to 5.5 V operating voltage (Z86D990/Z86D991 Z86D990/Z86D991) 2.3 V to 5.5 V operating voltage (Z86L990/Z86L991 Z86L990/Z86L991) Low power consumption with three standby modes: ­ Stop ­ Halt ­ Low Voltage Standby Low-voltage protection circuit (also known as VBO, or voltage brownout, circuit) Watch-dog timer and power-on reset circuits User-Programmable Option Bits · · · · · · · · · · · Clock source-RC/other (LC, resonator, or crystal) Watch-dog timer permanently enable 32-kHz crystal Port 20­27 pull-up resistive transistor Port 40­42 pull-up resistive transistor Port 44­47 pull-up resistive transistor Port 50­51 pull-up resistive transistor Port 54­57 pull-up resistive transistor Port 60­63 pull-up resistive transistor (not available in Z86D991/Z86L991 Z86D991/Z86L991) Port 64­67 pull-up resistive transistor (not available in Z86D991/Z86L991 Z86D991/Z86L991) P43 high impedance in STOP mode (available in OTP only) Force P43 to output a 1 in the open-drain configuration PS003802-0901 PS003802-0901 P R E L I M I N A R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 4 Functional Block Diagram Figure 1 shows the functional block diagram for the microcontrollers. Expanded Register File Register File 256 x 8-bit 8 Program Memory 7 Port 2 7 * Port 4 Machine Timing and Instruction Control Z8 Core 256 Bytes 0 VDD_padring* VDD_CORE Power Filter P52 P53 CIN2 CREF2 XTAL 1 XTAL 2 Two Analog Comparators Controlled Current Output 0 CIN1 CREF1 P51 P50 8 P43 7 Port 5 16-Bit C/T (Modulation) 8-Bit C/T (Carrier) 0 7 8-Bit C/T (General) 8-Bit A/D Port 6 * VRef+ MUX VRef­ ADC is only in the Z86L990/Z86D990 Z86L990/Z86D990. 0 Program memory is as follows: Z86D990 Z86D990 32K OTP Z86D991 Z86D991 32K OTP Z86L990 Z86L990 16K ROM Z86L991 Z86L991 16K ROM *Controlled Current Output *P6 is only in the Z86L990/Z86D990 Z86L990/Z86D990. *In the 28-pin package, VDD_padring and VDD_CORE are bonded together. Figure 1. Functional Block Diagram PS003802-0901 PS003802-0901 ADC0/P44 ADC0/P44 ADC1/P45 ADC1/P45 ADC2/P46 ADC2/P46 ADC3/P47 ADC3/P47 P R E L I M I N A R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 5 Pin Descriptions Figure 2 through Figure 4 show the pin names and locations. .< &< VDD_CORE VDD_padring XTAL2 XTAL1 NC P51 P52 P53 P54 P64 P61 P60 P24 P23 P22 NC NC P21 P20 P43 VSS VSS P42 P41 P40 P50 P56 NC NC P57 P55 P67 P66 P65 P62 P63 P25 P26 P27 NC AVSS VREFP44 VREFP44 P45 P46 P47 VREF+ AVDD Notes: 1. Both VSS pins must be connected to ground. 2. NC is no connection to the die. 3. AVDD must be connected to VDD_CORE and a 10-µF capacitor for good A/D conversion. 4. Power must be connected to VDD_padring. Current passes to VDD_CORE through the internal power filter. Figure 2. 48-Pin SSOP Pin Assignments PS003802-0901 PS003802-0901 P R E L I M I N A R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 6 P62 P63 P25 P26 P27 AV SS VRef­ 1 2 3 4 5 6 Z86D990/ Z86D990/ Z86L990 Z86L990 7 8 9 10 11 12 13 14 P44/ADC0 P44/ADC0 P45/ADC1 P45/ADC1 P46/ADC2 P46/ADC2 P47/ADC3 P47/ADC3 VRef+ AVDD/VDD_CORE VDD_padring XTAL2 XTAL1 P51/CIN1/Captive Timer Input P52/CIN2/T1 P52/CIN2/T1 Timer Input (TIN) P53/CREF2 P53/CREF2 P54/COUT1 P54/COUT1 P61 P60 P24 P23 P22 P21 P20 P43/Combined T8 T16 Output 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 15 16 17 18 19 20 VSS P42 P41/T16 P41/T16 Output P40/T8 P40/T8 Output P50/CREF1 P50/CREF1 P56/T1 P56/T1 Timer Output P57 P55/COUT2 P55/COUT2 P67 P66 P65 P64 Notes: 1. AVDD must be connected to VDD_CORE and a 10-µF capacitor for good A/D conversion. 2. Power must be connected to VDD_padring. Current passes to VDD_CORE through the internal power filter. Figure 3. 40-Pin DIP Pin Assignment PS003802-0901 PS003802-0901 P R E L I M I N A R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 7 P25 P26 P27 P44/ADC0 P44/ADC0 P45/ADC1 P45/ADC1 P46/ADC2 P46/ADC2 P47/ADC3 P47/ADC3 VDD* 1 2 3 4 5 6 7 8 9 10 11 12 13 14 XTAL2 XTAL1 P51/CIN1/Capture Timer Input P52/CIN2/T1 P52/CIN2/T1 Timer Input P53/CREF2 P53/CREF2 P54/COUT1 P54/COUT1 Z86D991/ Z86D991/ Z86L991 Z86L991 28 27 26 25 24 23 22 21 20 19 18 17 16 15 P24 P23 P22 P21 P20 P43/Combined T8 T16 Output VSS* P42 P41/T16 P41/T16 Output P40/T8 P40/T8 Output P50/CREF1 P50/CREF1 P56/T1 P56/T1 Timer Output P57 P55/COUT2 P55/COUT2 Notes: 1. P43 is a controlled current output. 2. P54, P55, P56, and P57 are high drive outputs. * VDD = VDD_CORE + VDD_padring + AVDD Figure 4. 28-Pin SOIC/DIP Pin Assignment-User Mode Pins Configuration Table 2 describes the pins. Table 2. Pin Descriptions Symbol P20 P21 P22 P23 P24 P25 P26 P27 P40 PS003802-0901 PS003802-0901 Pin # 28 PDIP/SOIC 24 25 26 27 28 1 2 3 19 40 PDIP 34 35 36 37 38 3 4 5 29 48 SSOP 40 41 44 45 46 3 4 5 34 P R Direction I/O I/O I/O I/O I/O I/O I/O I/O I/O E L I Description Port 2 Bit 0 Port 2 Bit 1 Port 2 Bit 2 Port 2 Bit 3 Port 2 Bit 4 Port 2 Bit 5 Port 2 Bit 6 Port 2 Bit 7 Port 4 Bit 0, T8 Output M I N A R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 8 Table 2. Pin Descriptions (Continued) Pin # 28 40 48 Symbol PDIP/SOIC PDIP SSOP Direction Description P41 20 30 35 I/O Port 4 Bit 1, T16 Output P42 21 31 36 I/O Port 4 Bit 2 P43 23 33 39 Output T8/T16 T8/T16 Output, Controlled current output P44 4 8 9 I/O Port 4 Bit 4, A/D Channel 0* P45 5 9 10 I/O Port 4 Bit 5, A/D Channel 1* P46 6 10 11 I/O Port 4 Bit 6, A/D Channel 2* P47 7 11 12 I/O Port 4 Bit 7, A/D Channel 3* P50, CREF1 18 28 33 I/O Port 5 Bit 0, Comparator 1 reference P51, CIN1 11 17 20 I/O Port 5 Bit 1, Capture timer input, IRQ2 P52, CIN2 12 18 21 Input Port 5 Bit 2, Timer 1 timer input, IRQ0 P53, CREF2 13 19 22 Input Port 5 Bit 3, Comparator 2 reference, IRQ1 P54 14 20 23 I/O Port 5 Bit 4, High drive output P55 15 25 28 I/O Port 5 Bit 5, High drive output P56 17 27 32 I/O Port 5 Bit 6, Timer 1 output, High drive output P57 16 26 29 I/O Port 5 Bit 7, High drive output P60 39 47 I/O Port 6 Bit 0 P61 40 48 I/O Port 6 Bit 1 P62 1 1 I/O Port 6 Bit 2 P63 2 2 I/O Port 6 Bit 3 P64 21 24 I/O Port 6 Bit 4 P65 22 25 I/O Port 6 Bit 5 P66 23 26 I/O Port 6 Bit 6 P67 24 27 I/O Port 6 Bit 7 XTAL1 10 16 18 Input Crystal, Oscillator clock XTAL2 9 15 17 Output Crystal, Oscillator clock AVDD 13 14 Analog power supply VDD_CORE 13 15 Z8 core power supply AVSS 6 7 Analog ground VRef­ 7 8 Input A/D converter lower reference VRef+ 12 13 Input A/D converter upper reference VDD_padring 8* 14 16 Power supply (pad ring) VSS 22* 32 37, 38 Ground Notes: *A/D converter is not available in the 28-pin configuration. *In the 28-pin configuration, all three (core, pad ring, and analog) powers are tied together. PS003802-0901 PS003802-0901 P R E L I M I N A R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 9 Operational Description Central Processing Unit (CPU) Description The Z8 architecture is characterized by a flexible I/O scheme, an efficient register and address space structure and a number of ancillary features for cost-sensitive, high-volume embedded control applications. ROM-based products are geared for high-volume production (where the software is stable) and one-time programmable equivalents for prototyping as well as volume production where time to market or code flexibility is critical. Architecture Type The Z8 register-oriented architecture centers around an internal register file composed of 256 consecutive bytes, known as the standard register file. The standard register file consists of 4 I/O port registers (R2, R4, R5, and R6), 12 control and status registers, 233 general-purpose registers, and 7 registers reserved for future expansion. In addition to the standard register file, the Z86D99/Z86L99 Z86D99/Z86L99 family uses 21 control and status registers located in the Z8 expanded register file. Any general-purpose register can be used as an accumulator and address pointer or an index, data, or stack register. All active registers can be referenced or modified by any instruction that accesses an 8-bit register, without the requirement for special instructions. Registers accessed as 16 bits are treated as even-odd register pairs. In this case, the data's most significant byte (MSB) is stored in the even-numbered register, while the least significant byte (LSB) goes into the next higher odd-numbered register. The Z8 CPU has an instruction set designed for the large register file. The instruction set provides a full compliment of 8-bit arithmetic and logical operations. BCD operations are supported using a decimal adjustment of binary values, and 16-bit quantities for addresses and counters can be incremented and decremented. Bit manipulation and Rotate and Shift instructions complete the data-manipulation capabilities of the Z8 CPU. No special I/O instructions are necessary because the I/O is mapped into the register file. CPU Control Registers The standard Z8 control registers govern the operation of the CPU. Any instruction which references the register file can access these control registers. The following are available control registers: · · · PS003802-0901 PS003802-0901 Register Pointer (RP) Stack Pointer (SP) Program Control Flags (FLAGS) P R E L I M I N A R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 10 · · · Interrupt Control (IPR, IMR, and IRQ) Stop Mode Recovery (SMR, P2SMR, and P5SMR) Low-Battery Detect (LB) Flag The Z8 uses a 16-bit Program Counter (PC) to determine the sequence of current program instructions. The PC is not an addressable register. Peripheral registers are used to transfer data, configure the operating mode, and control the operation of the on-chip peripherals. Any instruction that references the register file can access the peripheral registers. The following are peripheral control registers: · · · · · Analog/Digital Converter (ADCCTRL and ADCDATA) T1 Timer/Counter (TMR, T1, and PRE1) T8 Timer/Counter (CTR0, HI8, LO8, TC8H, and TC8L) T16 Timer/Counter (CTR2, HI16, LO16, TC16H TC16H, and TC16L TC16L) T8/T16 T8/T16 Control Registers (CTR1and CTR3) In addition, the four port registers are considered to be peripheral registers. The following are port control registers: · · · · · Port Configuration Registers (P456CON P456CON and P3M) Port 2 Control and Mode Registers (P2 and P2M) Port 4 Control and Mode Registers (P4 and P4M) Port 5 Control and Mode Registers (P5 and P5M) Port 6 Control and Mode Registers (P6 and P6M) The functions and applications of the control and peripheral registers are explained in "Control and Status Registers" on page 52. Memory (ROM/OTP and RAM) There are four basic address spaces available to support a wide range of configurations: · · · · Program memory (on-chip) Standard register file Expanded register file Executable RAM The Z8 standard register file totals up to 256 consecutive bytes organized as 16 groups of 16 eight-bit registers. These registers consist of I/O port registers, PS003802-0901 PS003802-0901 P R E L I M I N A R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 11 general-purpose RAM registers, and control and status registers. Every RAM register acts like an accumulator, speeding instruction execution and maximizing coding efficiency. Working register groups allow fast context switching. The standard register file of the Z8 (known as Bank 0) has been expanded to form 16 expanded register file (ERF) banks. The expanded register file allows for additional system control registers and for the mapping of additional peripheral devices into the register area. Each ERF bank can potentially consist of up to 256 registers (the same amount as in the standard register file) that can then be divided into 16 working register groups. Currently, only Group 0 of ERF Banks F and D (0Fh and 0Dh) has been implemented. In addition to the standard program memory and the RAM register files, the Z86D99/Z86L99 Z86D99/Z86L99 family also has 256 bytes of executable RAM that has been mapped into the upper 256 bytes of the program memory address space (FF00h­ FFFFh). Data can be written to the executable RAM by using the LDC instruction. Program Memory Structure The first 12 bytes of program memory are reserved for the interrupt vectors. These locations contain six 16-bit vectors that correspond to the six available interrupts (IRQ0 through IRQ5.) Address 12 (0Ch) up to 32,767 (7FFFh) consists of on-chip one-time programmable memory. The Z86L99X Z86L99X only has the 16K ROM size. After any reset operation (power-on reset, watch-dog timer time out, and stop mode recovery), program execution resumes with the initial instruction fetch from location 000Ch. After a reset, the first routine executed must be one that initializes the control registers to the required system configuration. A unique feature of the Z86D99/Z86L99 Z86D99/Z86L99 family is the presence of 256 bytes of onchip executable RAM. This random-access memory is in addition to the standard Z8 register file memory available on all Z8 microcontrollers. As illustrated in Figure 5, the executable RAM is mapped into the upper 256 bytes of the 64K program memory address space (FF00h­FFFFh). Data can be written to the executable RAM by using the LDC instruction. Memory locations between 8000h and FEFFh have not been implemented on this microcontroller. The Z86D99/Z86L99 Z86D99/Z86L99 family does not have the capability of accessing external memory. PS003802-0901 PS003802-0901 P R E L I M I N A R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 12 Location (Hex) FFFF 256 bytes Executable RAM FF00 Not Implemented 3FFF/7FFF (ROM)/(OTP) 000C 000B 000A 0009 0008 0007 0006 0005 0004 0003 0002 0001 0000 PROGRAM MEMORY Location of the first byte of the initial instruction executed after RESET IRQ5 (lower byte) IRQ5 (upper byte) IRQ4 (lower byte) IRQ4 (upper byte) IRQ3 (lower byte) IRQ3 (upper byte) IRQ2 (lower byte) IRQ2 (upper byte) IRQ1 (lower byte) IRQ1 (upper byte) IRQ0 (lower byte) IRQ0 (upper byte) Figure 5. Program Memory Map Z8 Standard Register File (Bank 0) Bank 0 of the Z8 expanded register file architecture is known as the standard register file of the Z8. As shown in Figure 6, the Z8 standard register file consists of 16 groups of sixteen 8-bit registers known as Working Register (WR) groups. Working Register Group F contains various control and status registers. The lower half of Working Register Group 0 consists of I/O port registers (R0 to R7), the upper eight registers are available for use as general-purpose RAM registers. Working Register Group 1 through Group E of the standard register file are available to be used as general-purpose RAM registers. The user can use 233 bytes of general-purpose RAM registers in the standard Z8 register file (Bank 0). PS003802-0901 PS003802-0901 P R E L I M I N A R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 13 Grp/Bnk (F0h) (E0h) (D0h) (C0h) (B0h) (A0h) (90h) (80h) (70h) (60h) (50h) (40h) (30h) (20h) (10h) (00h) Reg r0 to 15 r0 to 15 r0 to 15 r0 to 15 r0 to 15 r0 to 15 r0 to 15 r0 to 15 r0 to 15 r0 to 15 r0 to 15 r0 to 15 r0 to 15 r0 to 15 r0 to 15 r8 to 15 r0 to 7 Working Register Group Function Control and Status Registers General-purpose RAM registers General-purpose RAM registers General-purpose RAM registers General-purpose RAM registers General-purpose RAM registers General-purpose RAM registers General-purpose RAM registers General-purpose RAM registers General-purpose RAM registers General-purpose RAM registers General-purpose RAM registers General-purpose RAM registers General-purpose RAM registers General-purpose RAM registers General-purpose RAM registers I/O Port Registers Figure 6. Standard Z8 Register File (Working Reg. Groups 0­F, Bank 0) Z8 Expanded Register File In addition to the Standard Z8 Register File (Bank 0), Expanded Register File Banks F and D of Working Register Group 0 have been implemented on the Z86D99/Z86L99 Z86D99/Z86L99. Figure 7 illustrates the Z8 Expanded Register File architecture. These two expanded register file banks of Working Register Group 0 provide a total of 32 additional RAM control and status registers. The Z86D99/Z86L99 Z86D99/Z86L99 family has implemented 21 of the 32 available registers. PS003802-0901 PS003802-0901 P R E L I M I N A R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 14 Z8 Expanded Register Files Z8 Standard Register File Group 0, Bank F Working Register Groups F E D C B A 9 8 7 6 5 4 3 2 1 0 Control and Status Reg. Stop Mode Recovery and Port Mode Registers General-Purpose RAM Registers Bank F Group 0, Bank D Timer Control Registers Banks 2 through C are Reserved-Not Implemented (Bank E is also reserved) I/O Port Registers Bank 0 Figure 7. Z8 Expanded Register File Architecture Clock Circuit Description The Z8 derives its timing from on-board clock circuitry connected to pins XTAL1 and XTAL2. The clock circuitry consists of an oscillator, a divide-by-two shaping circuit, and a clock buffer. The oscillator's input is XTAL1, and the oscillator's output is XTAL2. The clock can be driven by a crystal, a ceramic resonator, LC clock, RC, or an external clock source. Clock Control The Z8 offers software control of the internal system clock using programming register bits in the SMR register. This register selects the clock divide value and determines the mode of STOP Mode Recovery. The default setting is external clock divide-by-two. When bits 1 and 0 of the SMR register are set to 0, the System Clock (SCLK) and Timer Clock (TCLK) are equal to the external clock frequency divided by two. When bit 1 of the SMR register is set to 1, then SCLK and TCLK equal the external clock frequency. Refer to Table 53 on page 85 for the maximum clock frequency. A divide-by-16 prescaler of SCLK and TCLK allows the user to selectively reduce device power consumption during normal processor execution (under SCLK control) and/or HALT mode, where TCLK sources counter/timers and interrupt logic. Combining the divide-by-two circuitry with the divide-by-16 prescaler allows the external clock to be divided by 32. PS003802-0901 PS003802-0901 P R E L I M I N A R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 15 Interrupts The Z86D99/Z86L99 Z86D99/Z86L99 family allows up to six different interrupts, three external and three internal, from nine possible sources. The six interrupts are assigned as follows: · Three edge-triggered external interrupts (P51, P52, and P53), two of which are shared with the two analog comparators · · · One internal interrupt assigned to the T8 Timer One internal interrupt assigned to the T16 Timer One internal interrupt shared between the Low-Battery Detect flag and the T1 Timer Table 3 presents the interrupt types, the interrupt sources, and the location of the specific interrupt vectors. Table 3. Interrupt Types, Sources, and Vectors Name IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 Notes: Vector Location Comments 0,1 External interrupt (P52) is triggered by either rising or falling edge; internal interrupt generated by Comparator 2 is mapped into IRQ0 P53 (F) 2,3 External interrupt (P53) is triggered by a falling edge P51 (R/F), Comparator 1 4,5 External interrupt (P51) is triggered by either a rising or falling edge; internal interrupt generated by Comparator 1 is mapped into IRQ2 T16 Timer 6,7 Internal interrupt T8 Timer 8,9 Internal interrupt LVD, T1 Timer 10,11 Internal interrupt, LVD flag is multiplexed with T1 Timer End-ofCount interrupt F = Falling-edge triggered; R = Rising-edge triggered. When LVD is enabled, IRQ5 is triggered only by low-voltage detection. Timer 1 does not generate an interrupt. Source P52 (F/R), Comparator 2 These interrupts can be masked and their priorities set by using the Interrupt Mask Register (IMR) and Interrupt Priority Register (IPR) (Figure 8.) When more than one interrupt is pending, priorities are resolved by a priority encoder, controlled by the IPR. PS003802-0901 PS003802-0901 P R E L I M I N A R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 16 EI Instruction Interrupt Request Register (IRQ,FAH) S R Reset Power-On Reset (POR) Figure 8. Interrupt Block Diagram Interrupt requests are stored in the Interrupt Request Register (IRQ), which can also be used for polling. When an interrupt request is granted, the Z8 enters an "interrupt machine cycle" that globally disables all other interrupts, saves the program counter (the address of the next instruction to be executed) and status flags, and finally branches to the vector location for the interrupt granted. It is only at this point that control passes to the interrupt service routine for the specific interrupt. All six interrupts can be globally disabled by resetting the master Interrupt Enable (bit 7 of the IMR) with a Disable Interrupts (DI) instruction. Interrupts are globally enabled by setting the same bit with an Enable Interrupts (EI) instruction. Descriptions of three interrupt control registers-the Interrupt Request Register, the Interrupt Mask Register, and the Interrupt Priority Register-are provided in "Register Summary" on page 52. The Z8 family supports both vectored and polled interrupt handling. External Interrupt Sources External sources involve interrupt request lines P51, P52, and P53 (IRQ2, IRQ0, and IRQ1, respectively.) IRQ0, IRQ1, and IRQ2 are generated by a transition on the corresponding port pin. As shown in Figure 9, when the appropriate port pin (P51, P52, or P53) transitions, the first flip-flop is set. The next two flip-flops synchronize the request to the internal clock and delay it by two internal clock periods. The output of the most recent flip-flop (IRQ0, IRQ1, or IRQ2) sets the corresponding Interrupt Request Register bit. PS003802-0901 PS003802-0901 P R E L I M I N A R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 17 Figure 9. External Interrupt Sources IRQ0­IRQ2 Block Diagram The programming bits for the Interrupt Edge Select function are located in the IRQ register, bits 6 and 7. The configuration of these bits and the resulting interrupt edge is shown in Table 4. Table 4. Interrupt Edge Select for External Interrupts Interrupt Request Register Bit 7 Bit 6 0 0 0 1 1 0 1 1 Interrupt Edge IRQ2 (P51) IRQ0 (P52) Falling Falling Falling Rising Rising Falling Rising/Falling Rising/Falling Note: Although interrupts are edge triggered, minimum interrupt request Low and High times must be observed for proper operation. See "Electrical Characteristics" on page 85 for exact timing requirements (TWIL, TWIH) on external interrupt requests. Internal Interrupt Sources Internal sources are ORed with the external sources, so that either an internal or external source can trigger the interrupt. Interrupt Request Register Logic and Timing Figure 10 shows the logic diagram for the Interrupt Request Register. The leading edge of an interrupt request sets the first flip-flop. It remains set until the interrupt requests are sampled. PS003802-0901 PS003802-0901 P R E L I M I N A R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 18 Figure 10. IRQ Logic Internal interrupt requests are sampled during the most recent clock cycle before an Op Code fetch (see Figure 11.) External interrupt requests are sampled two internal clocks earlier than internal interrupt requests because of the synchronizing flip-flops shown in Figure 9. Figure 11. Interrupt Request Timing At sample time, the interrupt request is transferred to the second flip-flop shown in Figure 10, which drives the interrupt mask and priority logic. When an interrupt cycle occurs, this flip-flop is reset only for the highest priority level that is enabled. The user has direct access to the second flip-flop by reading and writing to the IRQ. The IRQ is read by specifying it as the source register of an instruction, and the IRQ is written by specifying it as the destination register. Interrupt Initialization After RESET, all interrupts are disabled and must be re-initialized before vectored or polled interrupt processing can begin. The Interrupt Priority Register, Interrupt Mask Register, and Interrupt Request Register must be initialized, in that order, to PS003802-0901 PS003802-0901 P R E L I M I N A R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 19 start the interrupt process. However, the IPR does not have to be initialized for polled processing. Interrupts must be globally enabled using the EI instruction. Setting bit 7 of the IMR is not sufficient. Subsequent to this EI instruction, interrupts can be enabled either by IMR manipulation or by use of the EI instruction, with equivalent effects. Additionally, interrupts must be disabled by executing a DI instruction before the IPRs or IMRs can be modified. Interrupts can then be enabled by executing an EI instruction. IRQ Software Interrupt Generation IRQ can be used to generate software interrupts by specifying IRQ as the destination of any instruction referencing the Z8 Standard Register File. These Software Interrupts (SWIs) are controlled in the same manner as hardware-generated requests (the IPR and the IMR control the priority and enabling of each SWI level). To generate a SWI, the request bit in the IRQ is set as follows: OR IRQ, #NUMBER where the immediate data, NUMBER, has a 1 in the bit position corresponding to the appropriate level of the SWI. For example, for an SWI on IRQ5, NUMBER has a 1 in bit 5. With this instruction, if the interrupt system is globally enabled, IRQ5 is enabled, and there are no higher priority pending requests, control is transferred to the service routine pointed to by the IRQ5 vector. Reset Conditions A system reset overrides all other operating conditions and puts the Z8 into a known state. The control and status registers are reset to their default conditions after a power-on reset (POR) or a Watch-Dog Timer (WDT) time-out while in RUN mode. The control and status registers are not reset to their default conditions after Stop Mode Recovery (SMR) while in HALT or STOP mode. General-purpose registers are undefined after the device is powered up. Resetting the Z8 does not affect the contents of the general-purpose registers. The registers keep their most recent value after any reset, as long as the reset occurs in the specified VCC operating range. Registers do not keep their most recent state from a VLV reset, if VCC drops below VRAM (see Table 54 on page 87). Following a reset (see Table 5), the first routine executed must be one that initializes the control registers to the required system configuration. PS003802-0901 PS003802-0901 P R E L I M I N A R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 20 Table 5. Control and Status Register Reset Conditions Address Register Function Reset Value R/W 7 6 5 4 3 2 1 0 Register Pointer Grp/Bnk Register F0h r13 (R253) RP Symbol R/W 0 0 0 0 0 0 0 0 Stack Pointer F0h r15 (R255) SP R/W X X X X X X X X Program Control Flags F0h r12 (R252) Flags R/W X X X X X X X X Low Battery Detect 0Dh r12 LB R/W 1 1 1 1 1 X 0 0 ADC Control 0Fh r8 ADCCTRL R/W 0 0 0 0 0 0 0 0 ADC Data 00h r7 (R7) ADCDATA R 0 0 0 0 0 0 0 0 Interrupt Mask F0h r11 (R251) IMR R/W 0 0 0 0 0 0 0 0 Interrupt Priority F0h r9 (R249) IPR W 0 0 0 0 0 0 0 0 Interrupt Request F0h r10 (R250) IRQ R/W 0 0 0 0 0 0 0 0 Port Configuration (A) 0Fh r0 R/W 0 0 0 0 0 1 1 1 Port Configuration (B) F0h r7 (R247) P3M W 1 1 1 1 1 1 1 1 R/W X X X X X X X X W 1 1 1 1 1 1 1 1 P456CON P456CON Port 2 Data 00h r2 (R2) Port 2 Mode F0h r6 (R246) P2M P2 Port 4 Data 00h r4 (R4) P4 R/W X X X X X X X X Port 4 Mode 0Fh r2 P4M R/W 1 1 1 1 1* 1 1 1 Port 5 Data 00h r5 (R5) P5 R/W X X X X X X X X Port 5 Mode 0Fh r4 P5M R/W 1 1 1 1 1 1 1 1 Port 6 Data 00h r6 (R6) P6 R/W X X X X X X X X Port 6 Mode 0Fh r6 P6M R/W 1 1 1 1 1 1 1 1 T1 Timer Data F0h r2 (R242) T1 R/W 0 0 0 0 0 0 0 0 T1 Timer Mode F0h r1 (R241) TMR R/W 0 0 0 0 0 0 1 1 T1 Timer Prescale F0h r3 (R243) PRE1 R/W 0 0 0 0 0 0 0 0 T8/T16 T8/T16 Control (A) 0Dh r1 CTR1 R/W 0 0 0* 0* 0 0 0 0 T8/T16 T8/T16 Control (B) 0Dh r3 CTR3 R/W 0 0 0* X X X X X T8 Timer Control 0Dh r0 CTR0 R/W 0 0 0* 0* 0* 0* 0* 0 RW 0 0 0 0 0 0 0 0 T8 High Capture T8 Low Capture 0Dh 0Dh r11 HI8 r10 LO8 R/W 0 0 0 0 0 0 0 0 T8 High Load 0Dh r5 TC8H R/W 0 0 0 0 0 0 0 0 T8 Low Load 0Dh r4 TC8L R/W 0 0 0 0 0 0 0 0 T16 Timer Control 0Dh r2 CTR2 R/W 0 0 0 0 0 0 0 0 r9 HI16 R/W 0 0 0 0 0 0 0 0 T16 High Capture 0Dh T16 Low Capture 0Dh r8 LO16 R/W 0 0 0 0 0 0 0 0 T16 High Load 0Dh r7 TC16H TC16H R/W 0 0 0 0 0 0 0 0 r6 R/W 0 0 0 0 0 0 0 0 T16 Low Load PS003802-0901 PS003802-0901 0Dh P TC16L TC16L R E L I M I N A R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 21 Table 5. Control and Status Register Reset Conditions (Continued) Address Register Function Reset Value Grp/Bnk Register Symbol R/W 7 6 5 4 3 2 1 0 Stop Mode Recovery 0Fh r11 SMR R/W 0 0 1 0 0 0 0 0 Port 2 SMR Source 0Fh r1 P2SMR R/W 0 0 0 0 0 0 0 0 0Fh r5 P5SMR R/W 0 0 0 0 0 0 0 0 Port 5 SMR Source Notes: This register is not reset following Stop Mode Recovery (SMR). *This bit is not reset following SMR. X means this bit is undefined at POR and is not reset following SMR. *In OTP, the default for P43 is open-drain output at power up; you need to initialize the P43 data. In the mask part, the P43 output is disabled until it is configured as output. Power-On Reset A POR (cold start) always resets the Z8 control and status registers to their default conditions. A POR sets bit 7 of the Stop Mode Recovery register to 0 to indicate that a cold start has occurred. A timer circuit clocked by a dedicated on-board RC oscillator is used for the Power-On Reset Timer (TPOR) function. The POR time is specified as TPOR. TPOR time allows VCC and the oscillator circuit to stabilize before instruction execution begins. The POR delay timer circuit is a one-shot timer triggered by one of three conditions: · Power Fail to Power OK status including recovery from Low Voltage (VLV) Standby mode · · STOP-Mode Recovery (when bit 5 of the SMR register = 1) WDT time-out Under normal operating conditions, a stop mode recovery event always triggers the POR delay timer. This delay is necessary to allow the external oscillator time to stabilize. When using an RC or LC oscillator (with a low Q factor), the shorter wake-up time means the delay can be eliminated. Bit 5 of the SMR register selects whether the POR timer delay is used after StopMode Recovery or is bypassed. If bit 5 =1, then the POR timer delay is used. If bit 5 = 0, then the POR timer delay is bypassed. In this case, the SMR source must be held in the recovery state for 5 TpC to pass the Reset signal internally. Watch-Dog Timer (WDT) The WDT is a retriggerable one-shot timer that resets the Z8 if it reaches its terminal count. When operating in the RUN modes, a WDT reset is functionally PS003802-0901 PS003802-0901 P R E L I M I N A R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 22 equivalent to a hardware POR reset. If the mask option of the permanently enabled watch-dog timer is selected, it runs when power up. If the option is not selected, the WDT is initially enabled by executing the WDT instruction and refreshed on subsequent executions of the WDT instruction. The WDT instruction does not affect the Zero (Z), Sign (S), and Overflow (V) flags. Permanently enabled WDTs are always enabled, and the WDT instruction is used to refresh it. The WDT cannot be disabled after it has been initially enabled. The WDT is off during both HALT and STOP modes. The WDT circuit is driven by an on-board RC oscillator. The time-out period for the WDT is fixed to a typical value (see Table 57 on page 90). Power Management In addition to the standard RUN mode, the Z8 supports three power-down modes to minimize device current consumption. The following three modes are supported: · · · HALT STOP Low-Voltage Standby Table 6 shows the status of the internal CPU clock (SCLK), the internal Timer clock (TCLK), the external oscillator, and the Watch-Dog Timer during the RUN mode and three low-power modes. Table 6. Clock Status in Operating Modes Operating Mode SCLK TCLK External OSC RUN On On On HALT Off On On STOP Off Off Off Low-Voltage Standby Off Off Off Note: * When WDT is enabled by the mask option bit WDT* On Off Off Off Using the Power-Down Modes In order to enter HALT or STOP mode, it is necessary to first flush the instruction pipeline to avoid suspending execution in mid-instruction. You can flush the PS003802-0901 PS003802-0901 P R E L I M I N A R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 23 instruction pipeline by executing a NOP (Op Code = FFh) immediately before the appropriate sleep instruction. For example: Mnemonic Comment NOP ; clear the pipeline STOP ; enter STOP mode Op Code Mnemonic Comment NOP ; clear the pipeline HALT ; enter HALT mode Op Code FFh 6Fh or FFh 7Fh HALT HALT mode suspends instruction execution and turns off the internal CPU clock (SCLK). The on-chip oscillator circuit remains active, so the internal Timer clock (TCLK) continues to run and is applied to the counter/timers and interrupt logic. An interrupt request, either internally or externally generated, must be executed (enabled) to exit HALT mode. After the interrupt service routine, the program continues from the instruction immediately following the HALT. The HALT mode can also be exited by a POR. In this case, the program execution restarts at the reset address 000Ch. STOP STOP mode provides the lowest possible device standby current. This instruction turns off both the internal CPU clock (SCLK) and internal Timer clock (TCLK) and reduces the standby current to the minimum. The STOP mode is terminated by a POR or SMR source. Terminating the STOP mode causes the processor to restart the application program at address 000Ch. Stop Mode Recovery Sources Exiting STOP mode using an SMR source is greatly simplified in the Z86D99/ Z86D99/ Z86L99 Z86L99 family. The Z86D99/Z86L99 Z86D99/Z86L99 family of products allows 16 individual I/O pins (Ports 2 and 5) to be used as stop-mode recovery sources. The STOP mode is exited when one of these SMR sources is toggled. A transition from either low to high or high to low on any pin of Port 2 or Port 5 if the pin is identified as an SMR source will effect an SMR. PS003802-0901 PS003802-0901 P R E L I M I N A R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 24 There are three registers that control STOP mode recovery: · · · Stop Mode Recovery Port 2 Stop Mode Recovery (P2SMR) Port 5 Stop Mode Recovery (P5SMR) The functions and applications of these registers are explained in "Stop-Mode Recovery Control Registers" on page 82. Low-Voltage Standby An on-chip voltage comparator checks that the VCC level is at the required level for correct operation of the Z8. When VCC falls below the low-voltage trip voltage (VLV), reset is globally driven, and then the device is put in a low-current standby mode with the external oscillator stopped. If the VCC remains above VRAM, the RAM content is preserved. When the power level rises above the VLV level, the device performs a POR and functions normally. The minimum operating voltage varies with temperature and operating frequency, while VLV varies with temperature only. I/O Ports The Z86D99/Z86L99 Z86D99/Z86L99 family has up to 32 lines dedicated to input and output in the 40-pin configuration. These lines are grouped into four 8-bit ports known as Port 2, Port 4, Port 5, and Port 6. All four ports are bit programmable as either inputs or outputs with the exception of P52, P53, and P43. P52 and P53 are input only as they are used in OTP programming. P43 is the controlled current output and is therefore output only. All ports have push-pull CMOS outputs. In addition, the push-pull outputs can be turned off for open-drain operation using the P456CON P456CON register. Internal resistive pull-up transistors are available as a user-defined OTP/mask option on all ports. For Ports 4, 5, and 6, the pull-ups are nibble selectable. For Port 2, the pull-up option applies to all eight I/O lines. Note: Internal pull-ups are disabled on any given pin or group of port pins when those pins are programmed as outputs. Mode Registers Each port has an associated Mode Register that determines the port's functions and allows dynamic change in port functions during program execution. Port and Mode Registers are mapped into the Standard Register File. Because of their close association, Port and Mode Registers are treated like any other PS003802-0901 PS003802-0901 P R E L I M I N A R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 25 general-purpose register. There are no special instructions for port manipulation. Any instruction that addresses a register can address the ports. Data can be directly accessed in the Port Register, with no extra moves. Input and Output Registers Each of the four ports (Ports 2, 4, 5, and 6) has an input register, an output register, and associated buffer and control logic. Because there are separate input and output registers associated with each port, writing bits defined as inputs store the data in the output register. This data cannot be read as long as the bits are defined as inputs. However, if the bits are reconfigured as output, the data stored in the output register is reflected on the output pins and can then be read. This mechanism allows the user to initialize the outputs before driving their loads. Because port inputs are asynchronous to the Z8 internal clock, a READ operation could occur during an input transition. In this case, the logic level might be uncertain (somewhere between a logic 1 and 0). General Port I/O The eight I/O lines of each port (except P43, P52, and P53) can be configured under software control to be either input or output, independently. Bits programmed as outputs can be globally programmed as either push-pull or opendrain. See Figure 12. OTP/Mask VCC Option Pull-Up * Open-Drain I/O Pad Out Note: * Pull-up resistance is about 200 K at 2.3 V and 75 K at 5.0 V with +50% tolerance. In Figure 12. General Input/Output Pin PS003802-0901 PS003802-0901 P R E L I M I N A R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 26 Read/Write Operations The ports are accessed as general-purpose registers. Port registers are written by specifying the port register as an instruction's destination register. Writing to a port causes data to be stored in the output register of the port, and reflected externally on any bit configured as an output. Ports are read by specifying the port register as the source register of an instruction. When an output bit is read, data on the external pin is returned. Under normal loading conditions, returning data on the external pin is equivalent to reading the output register. However, if a bit is defined as an open-drain output, the data returned is the value forced on the output pin by the external system. This value might not be the same as the data in the output register. Reading input bits also returns data on the external pins. PS003802-0901 PS003802-0901 P R E L I M I N A R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 27 Special Functions Table 7 defines the special functions of Ports 4 and 5. Table 7. Special Port Pin Functions Function Pin Analog Comparator Inputs Analog Comparator Outputs ADC Channels External Interrupts TIN External Clock Input Capture Timer Input T1 Timer Output T8 Output T16 Output Combined T8/T16 T8/T16 Output Controlled Current Output ZiLOG Test Mode P R E P51 P52 P50 P53 P54 P55 P44 P45 P46 P47 P52 P53 P51 P52 P51 P56 P40 P41 P43 CIN1 CIN2 CREF1 CREF2 COUT1 COUT2 ADC0 ADC1 ADC2 ADC3 IRQ0 IRQ1 IRQ2 TIN Demodulator_Input T1OUT P40_Out P41_Out P43_Out P41 P42 Analog Comparator References PS003802-0901 PS003802-0901 Signal DSn Enable ASn Enable L I M I N A R Configuration Register P456CON P456CON P456CON P456CON ADCCTRL ADCCTRL ADCCTRL ADCCTRL IMR and IRQ IMR and IRQ IMR and IRQ TMR and PRE1 CTR1 TMR CTR0 CTR2 CTR1 P456CON P456CON P456CON P456CON Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 28 Peripherals Analog Comparators The Z86D99/Z86L99 Z86D99/Z86L99 family includes two independent on-chip general-purpose analog comparators as shown in Figure 13. The comparators are multiplexed with a digital input signal by the P456CON P456CON register. They can also be used to generate interrupts IRQ0 and IRQ2. The comparators are turned off in STOP mode. IRQ2, P51 Data Latch P51 (CIN1) + P50 (CREF1) ­ P456CON P456CON Bit5 1 = comparator 0 = digital Comparator 1 IRQ0, P52 Data Latch P52 (CIN2) + P456CON P456CON Bit4 1 = comparator 0 = digital ­ P53 (CREF2) Comparator 2 Figure 13. Analog Comparators Analog/Digital Converter (ADC) The Z86D99/Z86L99 Z86D99/Z86L99 family incorporates an 8-bit ADC that uses a sigma delta architecture (Figure 14) comprised of a modulator and a digital filter. The input is selected (bit 3,2 from ADCCTRL) with an analog mux from 4 (P47­P44) pins that can be configured as analog inputs (bit 7­4 from ADCCTRL). Note: Whenever an input pin has an analog value, the digital input buffer has to be disabled in order to reduce the current through the device. PS003802-0901 PS003802-0901 P R E L I M I N A R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 29 Figure 14. ADC Block Diagram The low-pass filter transfer function is presented in Figure 15 with the ­3-dB frequency given by the formula: f 3db = 0.0021 f ADC where fADC is the sampling frequency of the modulator. PS003802-0901 PS003802-0901 P R E L I M I N A R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 30 Filter response 0 2 4 Out/In[db] 6 8 10 12 14 16 18 20 0 0.5 1 1.5 2 2.5 log10(f) 3 3.5 4 4.5 5 Figure 15. Low-Pass Filter (with 8-MHz Crystal) The sampling frequency of the modulator fADC can be selected between fSCLK and fSCLK/2 (bit1 from ADCCTRL). Reducing the clock frequency lowers the power dissipated in the ADC block. The ADC can be enabled or disabled. When enabled, the converter tracks the input voltage. When switching between the channels (step response), the required time to reach the final value is given by the time constant of the low-pass filter: 2 2 952 T delay = - = - = -0.0021f ADC f ADC f 3db When available, the reference for the ADC is set externally with the Vref+ and Vrefpins. The output code represents the following ratio: Vin ­ VRefD out = - × 256 VRef+ ­ VRef - PS003802-0901 PS003802-0901 P R E L I M I N A R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 31 Though the ADC functions for smaller input voltage range (VRef+­VRef-), the noise and offsets remain constant over the specified electrical range. The errors of the converter increase due to small input signals. For fast access to the output of the ADC, the current data is available in the ADC result register (r8, bank00). To reduce the interference between the digital part and the analog part, separate AVSS and AVDD pins are available on the packages where the ADC can be used. Note: In the smaller packages, which do not support the ADC, the user must keep the converter not active in order to not have power dissipated in the ADC block. By default, ADC is off. Active Glitch Filter The Z86D99/Z86L99 Z86D99/Z86L99 family incorporates an active power/glitch filter that can be used to improve the quality of the power supply when the device is operating in noisy environments. The chips use three separate power buses: · pad ring power bus (all the output drivers plus the crystal/RC oscillator) called VDD_padring · · core power bus (all digital circuitry) called VDD_CORE analog power bus (all analog circuitry) called AVDD Depending on the pin availability, one or more of the power buses are connected together. The active power filter can be used in the packages that have the VDD separate. Figure 16 shows the internal schematic. PS003802-0901 PS003802-0901 P R E L I M I N A R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 32 VDD_padring Z86D99/Z86L99 Z86D99/Z86L99 Figure 16. Active Glitch/Power Filter When the internal power/glitch filter is not used, both VDD_padring and VDD_CORE must be connected together externally to the power supply. When the internal circuitry is used, the VDD_padring has to be connected to the power supply and the VDD_CORE has to be connected to an external energy storage capacitor (1-10 µF range). The core is connected only to this capacitor during power supply glitches. Table 8 describes the active glitch/filter specifications. Table 8. Active Glitch/Filter Specifications (Preliminary) Parameter Diff. stage gain Diff. stage bandwidth Rise time Fall time Rdson Max Min 75 dB 15 MHz Condition 255 ns 214 ns 10 50 mV pulse 50 mV pulse On the wafer level, all three power buses are available. Depending on the number of pins of the package, one or more power buses are connected together. The active glitch/power filter effectively increases the noise immunity for batteryoperated designs where the controller is driving high current loads (for example, IR LED). PS003802-0901 PS003802-0901 P R E L I M I N A R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 33 Controlled Current Output P43 is an open-drain output only pin. To function properly, Bit 3 of P4M must be set to zero to configure the pin as an open-drain output. The data at Port 4 must be initialized as it is undefined at power-on reset. The current output is a controlled current source that is controlled by the output of the value of P43 (see Table 9). P43 cannot be configured as input, and if P43 is read, P43 always returns the state of the output value (1 for no sink and 0 for sink). P43 uses internal current reference and will draw current if it outputs a low logic even without external connection. This applies to both Run mode and Stop mode. Table 9. Current Sink Pad P43 Specifications (Preliminary) Parameter Min Max Conditions Rise time 0.4 µ LED load Fall time 0.02 µ LED load Voutmin 0.54 V @27C Comparator response 0.2 µ Regulated current 80 mA 120 mA 80 Internal resistance The pad driver can function in two modes: · controlled current output, when the voltage on the pad is over a minimum value V pad > V out min · resistive pull down when the driver cannot regulate the current; in this mode, the gate of the NMOS pull down is raised to the power rail. The I-V characteristics of the pad are presented in Figure 17. PS003802-0901 PS003802-0901 P R E L I M I N A R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 34 Figure 17. I-V Characteristics for the Current Sink Pad P43 The CPU reads the mode of the pad driver by reading bit number 2 from the LB register. This bit is the output of a Set-Reset flip-flop that sets whenever the voltage on the pad is lower than Voutmin and is reset by a CPU write to the respective register. T1 Timer The Z86D99/Z86L99 Z86D99/Z86L99 family provides one general-purpose 8-bit counter/timer, T 1, driven by its own 6-bit prescaler, PRE1. The T 1 counter/timer is independent of the processor instruction sequence, which relieves software from time-critical operations such as interval timing and event counting. The T 1 counter/timer operates in either single-pass or continuous mode. At the end-of-count, counting either stops or the initial value is reloaded and counting continues. Under software control, new values are loaded immediately or when the end-of-count is reached. Software also controls the counting mode, how the counter/timer is started or stopped, and the counter/timer's use of I/O lines. Both the counter and prescaler registers can be altered while the counter/timer is running. PS003802-0901 PS003802-0901 P R E L I M I N A R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 35 Counter/timer 1 is driven by a timer clock generated by dividing the internal clock by four. The divide-by-four stage, the 6-bit prescaler, and the 8-bit counter/timer form a synchronous 16-bit divide chain. Counter/timer T 1 can also be driven by an external input (TIN) using Port P52. Port P56 can serve as a timer output (TOUT) through which T 1 or the internal clock can be output. The timer output toggles at the end-of-count. Figure 18 is a block diagram of the counter/timer. OSC +2 Internal Clock +2 TOUT P56 External Clock Clock Logic +4 Internal Clock Gated Clock Triggered Clock T1 Initial Value Register PRE1 Initial Value Register Internal Data Bus Figure 18. T1 Counter/Timer Block Diagram PS003802-0901 PS003802-0901 T1 Current Value Register Read Write Write TINP31 TINP31 IRQ5 8-Bit Down Counter 6-Bit Down Counter P R E L I M I N A R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 36 The counter/timer, prescaler, and associated mode registers are mapped into the register file as shown in Figure 19. The software uses the counter/timer as a general-purpose register, which eliminates the need for special instructions. DEC Hex identifiers 243 242 241 T1 prescaler Timer/counter 1 Timer mode F3 PRE1 F2 T1 F1 TMR Figure 19. Register File Prescaler and Counter/Timer The prescaler PRE1 (F3h) consists of an 8-bit register and a 6-bit down-counter as shown in Figure 18 on page 35. The prescaler register is a read-write register. Figure 20 shows the prescaler register. R243 PRE1 Prescaler 1 Register (F3h; Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Count mode 1 = T1 modulo-N 0 = T1 single pass Clock source 1 = T1 internal 0 = T1 external (TIN) Prescaler modulo (range: 1­64 decimal, 01h­00h) Figure 20. Prescaler 1 Register PS003802-0901 PS003802-0901 P R E L I M I N A R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 37 The six most significant bits (D2­D7) of PRE1 hold the prescaler count modulo, a value from 11 to 64 decimal. The prescaler register also contains control bits that specify T1 counting modes. These bits also indicate whether the clock source for T1 is internal or external. The counter/timer T1 (F2h) consists of an 8-bit down-counter, a write-only register that holds the initial count value, and a read-only register that holds the current count value (see Figure 18 on page 35). The initial value can range from 1 to 256 decimal (01h, 02h, ., 00h). Figure 21 illustrates the counter/timer register. R242 T1 Counter/Timer 1 Register (F2h; Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Initial value when written (range 1­256 decimal, 01h­00h) Current value when read Figure 21. Counter/Timer 1 Register Counter/Timer Operation Under software control, T1 is started and stopped using the Timer Mode register (F1h) bits D 2­D3: a Load bit and an Enable Count bit. See Figure 22. R241 TMR Timer Mode Register (F1h; Read/Write) D3 D2 D1 D0 Reserved 0 = No function 1 = Load T1 0 = Disable T1 count 1 = Enable T1 count Figure 22. Timer Mode Register PS003802-0901 PS003802-0901 P R E L I M I N A R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 38 Load and Enable Count Bits Setting the Load bit D2 to 1 transfers the initial values in the prescaler and the counter/timer registers into their respective down-counters. The next internal clock resets bit D2 to 0, readying the Load bit for the next load operation. The initial values can be loaded into the down-counters at any time. If the counter/timer is running, the counter/timer continues to run and starts the count over with the initial value. Therefore, the Load bit actually functions as a software re-trigger. The T 1 counter/timer remains at rest as long as the Enable Count bit D3 is 0. To enable counting, the Enable Count bit D3 must be set to 1. Counting actually starts when the Enable Count bit is written by an instruction. The first decrement occurs four internal clock periods after the Enable Count bit has been set. The Load and Enable Count bits can be set at the same time. For example, using the instruction OR TMR #%0C sets both D2 and D 3 of TMR to 1. The initial values of PRE1 and T1 are loaded into their respective counters, and the count is started after the M2T2 machine state after the operand is fetched as shown in Figure 23. M3 T1 T2 M1 T3 T1 M2 T2 T3 #03 is fetched T1 T2 Mn T3 T1 TMR is written; counter/timers are loaded T2 T3 first decrement occurs four clocks later Figure 23. Starting the Count Prescaler Operations During counting, the programmed clock source drives the prescaler 6-bit counter. The counter is counted down from the value specified by bits D2­D7 of the corresponding prescaler register, PRE0 or PRE1 (Figure 24). When the prescaler counter reaches its end-of-count, the initial value is reloaded and counting continues. The prescaler never actually reaches zero. For example, if the prescaler is set to divide by three, the count sequence is as follows: 3-2-1-3-2-1-3-2. PS003802-0901 PS003802-0901 P R E L I M I N A R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 39 R243 PRE1 Prescaler 1 Register (F3h; Read/Write) D0 Count mode 1 = T1 modulo-N 0 = T1 single pass Figure 24. Counting Modes When the PRE1 register is loaded with 000000 in the six most significant bits, the prescaler divides by 64. If that number is 000001, the prescaler does not divide and passes its clock on to T 1. Each time the prescaler reaches its end-of-count, a carry is generated, which allows the counter/timer to decrement by one on the next timer clock input. When T1 and PRE1 both reach their end-of-count, an interrupt request is generated- IRQ5 for T 1. Depending on the counting mode selected, the counter/timer either comes to rest with its value at 00h (single-pass mode), or the initial value is automatically reloaded and counting continues (continuous mode). In single-pass mode, the prescaler still continues to decrement when the timer T 1 has reached its end-of-count. The prescaler always starts from its programmed value upon restarting the counter. The counting modes are controlled by bit D 0 of PRE1, with D0 cleared to 0 for single-pass counting mode or set to 1 for continuous mode. The counter/timer can be stopped at any time by setting the Enable Count bit to 0 and restarted by setting the Enable Count bit back to 1. The T1 counter/timer continues its count value at the time it was stopped. The current value in the T 1 counter/timer can be read at any time without affecting the counting operation. New initial values can be written to the prescaler or the counter/timer registers at any time. These values are transferred to their respective down-counters on the next load operation. If the counter/timer mode is continuous, the next load occurs on the timer clock following an end-of-count. New initial values must be written before the load operation because the prescaler always effectively operates in continuous count mode. If the value loaded in the T1 register is 01h, the timer is actually not timing or counting at all; the timer is passing the prescaler end-of-count through. Because the prescaler is continuously running, regardless of the single-pass/continuous mode operation, the 8-bit timer continuously times out at the rate of the prescaler end-of-count if the T 1 timer value is programmed to 01h. PS003802-0901 PS003802-0901 P R E L I M I N A R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 40 The time interval (i) until end-of-count, is given by i=txpxv where t is 8 divided by XTAL frequency, p is the prescaler value (1 ­ 64), and v is the counter/timer value (1 ­ 256). The prescaler and counter/timer are true divideby-n counters. TOUT Modes The Timer Mode register TMR (F1h) (Figure 25) is used in conjunction with the Port 5 Mode register P5M to configure P56 for TOUT operation. In order for TOUT to function, P56 must be defined as an output line by setting P5M bit D6 to 0. Output is controlled by one of the counter/timers (T0 or T1) or the internal clock. R241 TMR Timer Mode Register (F1h; Read/Write) D7 D6 D2 0 = No function 1 = Load T1 TOUT modes TOUT off = 00 Reserved = 01 T1 out = 10 Internal clock out = 11 Figure 25. Timer Mode Register TOUT Operation The P56 output is selected by TMR bits D7 and D6. T1 is selected by setting D 7 and D 6 to 1 and 0, respectively. The counter/timer TOUT mode is turned off by setting TMR bits D 7 and D6 both to 0, freeing P36 to be a data output line. TOUT is initialized to a logic 1 whenever the TMR Load bit D2 is set to 1. At end-of-count, the interrupt request line IRQ5 clocks a toggle flip-flop. The output of this flip-flop drives the TOUT line P56. In all cases, when the counter/timer reaches its end-of-count, TOUT toggles to its opposite state (see Figure 26). If, for example, the counter/timer is in continuous counting mode, TOUT has a 50% duty cycle output. You can control the duty cycle by varying the initial values after each end-of-count. PS003802-0901 PS003802-0901 P R E L I M I N A R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 41 +2 TOUT P56 IRQ5 (T1 end-of-count) Figure 26. Counter/Timer Output Using TOUT The internal clock can be selected as output instead of T1 by setting TMR bits D7 and D6 both to 1. The internal clock (XTAL frequency/2) is then directly output on P56 (Figure 27). Internal clock OSC P56 +2 TOUT TMR TMR Figure 27. Internal Clock Output Using TOUT While programmed as TOUT, P56 cannot be modified by a write to port register P5. However, the Z8 software can examine P56's current output by reading the port register. TIN Modes The Timer Mode register TMR (F1h) (Figure 28) is used in conjunction with the Prescaler register PRE1 (F3h) (Figure 29) to configure P52 as TIN. TIN is used in conjunction with T1 in one of four modes: · · · · PS003802-0901 PS003802-0901 External clock input Gated internal clock Triggered internal clock Retriggerable internal clock P R E L I M I N A R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 42 R241 TMR Timer Mode Register (F1h; Read/Write) D5 D4 TIN modes External clock input = 00 Gate input = 01 Trigger input = 10 (non-retriggerable) Trigger input = 11 (retriggerable) Figure 28. Timer Mode Register TIN Operation R243 PRE1 Prescaler 1 Register (F3h; Write Only) D1 Clock source 1 = T1 internal 0 = T1 external (TIN) Figure 29. Prescaler 1 TIN Operation The T 1 counter/timer clock source must be configured for external by setting PRE1 bit D2 to 0. The Timer Mode register bits D5 and D4 can then be used to select the T IN operation. For T1 to start counting as a result of a TIN input, the Enable Count bit D3 in TMR must be set to 1. When using TIN as an external clock or a gate input, the initial values must be loaded into the down-counters by setting the Load bit D2 in TMR to 1 before counting begins. Initial values are automatically loaded in Trigger and Retrigger modes, so software loading is unnecessary. Configure P52 as an input line by setting P5M bit D2 to 1. PS003802-0901 PS003802-0901 P R E L I M I N A R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 43 Each High-to-Low transition on T IN generates interrupt request IRQ0, regardless of the selected TIN mode or the enabled/disabled state of T1. IRQ0 must therefore be masked or enabled according to the needs of the application. External Clock Input Mode The T IN External Clock Input mode (TMR bits D5 and D4 both set to 0) supports the counting of external events, where an event is considered to be a High-to-Low transition on TIN (see Figure 30) occurrence (single-pass mode) or on every nth occurrence (continuous mode) of that event. TMR D5­D 4 = 00 TIN clock P52 D D PRE1 T1 IRQ5 Internal clock IRQ0 Figure 30. External Clock Input Mode Gated Internal Clock Mode The T IN Gated Internal Clock mode (TMR bits D 5 and D4 set to 0 and 1, respectively) measures the duration of an external event. In this mode, the T1 prescaler is driven by the internal timer clock, gated by a High level on TIN (see Figure 31). T1 counts while T IN is High and stops counting when TIN is Low. Interrupt request IRQ0 is generated on the High-to-Low transition of TIN, signaling the end of the gate input. Interrupt request IRQ5 is generated if T1 reaches its end-of-count. OSC +2 Internal clock TMR D5­D 4 = 01 PRE1 +4 TIN gate P52 D D P IRQ5 IRQ0 Figure 31. Gated Clock Input Mode PS003802-0901 PS003802-0901 T1 R E L I M I N A R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 44 Triggered Input Mode The T IN Triggered Input mode (TMR bits D5 and D4 set to 1 and 0, respectively) causes T1 to start counting as the result of an external event (see Figure 32). T1 is then loaded and clocked by the internal timer clock following the first High-to-Low transition on the TIN input. Subsequent TIN transitions do not affect T1. In the single-pass mode, the Enable bit is reset whenever T1 reaches its end-of-count. Further T IN transitions have no effect on T1 until software sets the Enable Count bit again. In continuous mode, when T 1 is triggered, counting continues until software resets the Enable Count bit. Interrupt request IRQ5 is generated when T1 reaches its end-of-count. OSC +2 Internal clock TMR D5 = 1 PRE1 +4 T1 IRQ5 Edge trigger TIN trigger P52 D D TMR D5­D4 = 11 IRQ0 Figure 32. Triggered Clock Mode Retriggerable Input Mode The TIN Retriggerable Input mode (TMR bits D 5 and D4 both set to 1) causes T1 to load and start counting on every occurrence of a High-to-Low transition on TIN (see Figure 32). Interrupt request IRQ5 is generated if the programmed time interval (determined by T1 prescaler and counter/timer register initial values) has elapsed since the last High-to-Low transition on TIN. In single-pass mode, the end-of-count resets the Enable Count bit. Subsequent TIN transitions do not cause T1 to load and start counting until software sets the Enable Count bit again. In continuous mode, counting continues when T1 is triggered until software resets the Enable Count bit. When enabled, each High-to-Low TIN transition causes T1 to PS003802-0901 PS003802-0901 P R E L I M I N A R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 45 reload and restart counting. Interrupt request IRQ5 is generated on every end-ofcount. T8 and T16 Timer Operation The T8 timer is a programmable 8-bit counter/timer with two 8-bit capture registers and two 8-bit load registers. The T16 timer is a programmable 16-bit counter/ timer with one 16-bit capture register pair and one 16-bit load register pair. See Figure 33. The T8 and T16 counters/timers have two modes of operation: · · PS003802-0901 PS003802-0901 The transmit mode is used to generate complex waveforms. There are two submodes: ­ The normal mode can be used in single-pass or modulo-N (repeating) mode. ­ The ping-pong mode is used when the T8 timer counts down, enables the T16 timer that counts down, enabling T8, and so on, until the mode is disabled. The demodulation mode is used to capture and demodulate complex waveforms. P R E L I M I N A R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 46 HI16 LO16 8 8 16-Bit T16 Timer 16 1 2 4 8 Input 16 Glitch Filter 8 TC16L TC16L Timer 8/16 LO8 HI8 Edge Detect Circuit And/Or Logic T16 Clocked 8 TC16H TC16H Clock Divider SCLK 8 8 8-Bit T8 Timer 8 1 2 4 8 8 8 TC8H TC8L SCLK Clock Divider T8 Clock Divider Figure 33. Counter/Timer Architecture T8 Transmit Mode Before T8 is enabled, the output of T8 depends on CTR1, D1. If CTR1, D1 is 0, T8_OUT is 1. If CTR1, D1 is 1, T8_OUT is 0. When T8 is enabled, the output T8_OUT switches to the initial value (CTR1 D1). If the initial value (CTR1 D1) is 0, TC8L is loaded; otherwise, TC8H is loaded into the counter. In single-pass mode (CTR0 D6), T8 counts down to 0 and stops, T8_OUT toggles, the time-out status bit (CTR0 D5) is set, and a time-out interrupt can be generated if it is enabled (CTR0 D1). In modulo-N mode, upon reaching terminal count, T8_OUT is toggled, but no interrupt is generated. Then T8 loads a new count (if T8_OUT level is 0), TC8L is loaded; if T8_OUT is 1, TC8H is loaded. PS003802-0901 PS003802-0901 P R E L I M I N A R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 47 T8 counts down to 0, toggles T8_OUT, sets the time-out status bit (CTR0 D5), and generates an interrupt if enabled (CTR0 D1). This completes one cycle. T8 then loads from TC8H or TC8L, according to the T8_OUT level, and repeats the cycle. The user can modify the values in TC8H or TC8L at any time.The new values take effect when they are loaded. Do not write these registers at the time the values are to be loaded into the counter/timer. An initial count of 1 is not allowed. An initial count of 0 causes TC8 to count from 0 to FFh to FEh. Transition from 0 to FFh is not a time-out condition (see Figure 34). PS003802-0901 PS003802-0901 P R E L I M I N A R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 48 T8 (8-Bit) Transmit Mode No T8_Enable Bit Set CTR0 D7 Yes Reset T8_Enable Bit 0 1 CTR1 D1 Value Load TC8H Set T8_OUT Load TC8L Reset T8_OUT Set Time-out Status Bit (CTR0 D5) and Generate Timeout_Int. if Enabled Enable T8 No T8_Timeout Yes Single Pass Single Pass? Modulo-N 1 0 T8_OUT Value Load TC8L Reset T8_OUT Load TC8H Set T8_OUT Enable T8 No Set Time-out Status Bit (CTR0 D5) and Generate Timeout_Int. if Enabled T8_Timeout Yes Disable T8 Figure 34. Transmit Mode Flowchart PS003802-0901 PS003802-0901 P R E L I M I N A R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 49 Note: Do not use the same instructions for stopping the counter/ timers and setting the status bits. Two successive commands are necessary-the first command for stopping counter/timers and the second command for resetting the status bits- because one counter/timer clock interval must complete for the initiated event to actually occur. T8 Demodulation Mode Program TC8L and TC8H to FFh. After T8 is enabled, when the first edge (rising, falling, or both, depending on CTR1 D5, D4) is detected, it starts to count down. When a subsequent edge (rising, falling, or both, depending on CTR1 D5, D4) is detected during counting, the current value of T8 is one's complemented and put into one of the capture registers. If T8 is a positive edge, data is placed in LO8. If T8 is a negative edge, data is placed in H18. One of the edge-detect status bits (CTR1 D1, D0) is set, and an interrupt can be generated if enabled (CTR0 D2). Meanwhile, T8 is loaded with TC8H and starts counting again. If T8 reaches 0, the time-out status bit (CTR0 D5) is set, and an interrupt can be generated if enabled (CTR0 D1), and T8 continues counting from FFh (see Figure 35). PS003802-0901 PS003802-0901 P R E L I M I N A R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 50 T8 (8-Bit) Demodulation Mode T8 Enable CTR0, D7 No Yes FFh TC8 First Edge Present No Yes Enable TC8 Disable TC8 T8_Enable Bit Set No Yes No Edge Present Yes No T8 Time Out Set Edge Present Status Bit and Trigger Data Capture Int. if Enabled Yes Set Time-out Status Bit and Trigger Time Out Int. if Enabled Continue Counting Figure 35. Demodulation Mode Flowchart PS003802-0901 PS003802-0901 P R E L I M I N A R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 51 T16 Transit Mode In normal or ping-pong mode, the output of T16, when not enabled, is dependent on CTR1, D0. If CTR1, D0 is a 0, T16_OUT is a 1; if CTR1, D0 is a 1, T16_OUT is 0. The user can force the output of T16 to either a 0 or 1, whether it is enabled or not, by programming CTR1 D3, D2 to a 10 or 11. When T16 is enabled, TC16H TC16H * 256 + TC16L TC16L is loaded, and T16_OUT is switched to its initial value (CTR1 d0). When T16 counts down to 0, T16_OUT is toggled (in normal or ping-pong mode), an interrupt is generated if enabled (CTR2 D1), and a status bit (CTR2 D5) is set. If it is in modulo-N mode, it is loaded with TC16H TC16H * 256 + TC16L TC16L, and the counting continues. The user can modify the values in TC16H TC16H and TC16L TC16L at any time. The new values take effect when they are loaded. Do not load these registers at the time the values are to be loaded into the counter/timer. An initial count of 1 is not allowed. An initial count of 0 causes T16 to count from 0 to FFFFh to FFFEh. Transition from 0 to FFFFh is not a time-out condition. T16 Demodulation Mode Program TC16L TC16L and TC16H TC16H to FFh. After T16 is enabled, when the first edge (rising, falling, or both, depending on CTR1 D5, D4) is detected, T16 captures HI16 and LO16, reloads, and begins counting. Ping-Pong Mode This operation mode is only valid in transmit mode. T8 and T16 must be programmed in single-pass mode (CTR0 D6, CTR2 D6), and ping-pong mode must be programmed in CTR1 D3, D2. The user can begin the operation by enabling either T8 or T16 (CTR0 D7 or CTR2 D7). For example, if T8 is enabled, T8_OUT is set to this initial value (CTR1 D1). According to T8_OUT's level, TC8H or TC8L is loaded into T8. After the terminal count is reached, T8 is disabled, and T16 is enabled. T16_OUT switches to its initial value (CTR1 D0), data from TC16H TC16H and TC16L TC16L is loaded, and T16 starts to count. After T16 reaches the terminal count, it stops. T8 is enabled again, and the whole cycle repeats. Interrupts can be allowed when T8 or T16 reaches terminal control (CTR0 D1, CTR2 D1). To stop the pingpong operation, write 00 to bits D3 and D2 or CTR1. Note: Enabling ping-pong operation while the counters/timers are running can cause intermittent counter/timer function. Disable the counters/timers, then reset the status flags before starting the ping-pong mode. PS003802-0901 PS003802-0901 P R E L I M I N A R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 52 Control and Status Registers The Z86D99/Z86L99 Z86D99/Z86L99 family has 4 I/O port registers, 33 status and control registers, and 233 general-purpose RAM registers. The I/O port and control registers are included in the general-purpose register memory to allow any Z8 instruction to process I/O or control information directly, thus eliminating the requirement for special I/O or control instructions. The Z8 instruction set permits direct access to any of these 37 registers. In addition, each of the 233 general-purpose registers can also function as an accumulator, an address pointer, or an index register. Registers identified as "Reserved" do not exist or have not been implemented in this design. Register Summary Table 10 through Table 13 summarize the name and location of all registers. The register-by-register descriptions follow this section. Table 10. I/O Port Registers (Group 0, Bank 0, Registers 0­F) Grp/Bnk Reg (00h) rF (00h) rE (00h) rD (00h) rC (00h) rB (00h) rA (00h) r9 (00h) r8 (00h) r7 (00h) r6 (00h) r5 (00h) r4 (00h) r3 (00h) r2 (00h) r1 (00h) r0 PS003802-0901 PS003802-0901 Register Function General-Purpose RAM Register General-Purpose RAM Register General-Purpose RAM Register General-Purpose RAM Register General-Purpose RAM Register General-Purpose RAM Register General-Purpose RAM Register General-Purpose RAM Register Analog/Digital Converted Data Port 6 Control Register Port 5 Control Register Port 4 Control Register Reserved Port 2 Control Register Reserved Reserved P R E L I M I N A R Identifier GPR GPR GPR GPR GPR GPR GPR GPR ADCDATA P6 P5 P4 P2 Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 53 Table 11. Control and Status Registers (Group F, Bank 0, Registers 0­F) Grp/Bnk Reg (F0h) rF (F0h) rE (F0h) rD (F0h) rC (F0h) rB (F0h) rA (F0h) r9 (F0h) r8 (F0h) r7 (F0h) r6 (F0h) r5 (F0h) r4 (F0h) r3 (F0h) r2 (F0h) r1 (F0h) r0 Register Function Stack Pointer General-purpose RAM Register Register Pointer Program Control Flag Register Interrupt Mask Register Interrupt Request Register Interrupt Priority Register Reserved Port 3 Mode Register Port 2 Mode Register Reserved Reserved T1 Prescale Register T1 Data Register T1 Mode Register Reserved Identifier SP GPR RP Flags IMR IRQ IPR P3M P2M PRE1 T1 TMR Table 12. Timer Control Registers (Group 0, Bank D, Registers 0­F) Grp/Bnk Reg (0Dh) rF (0Dh) rE (0Dh) rD (0Dh) rC (0Dh) rB (0Dh) rA (0Dh) r9 (0Dh) r8 (0Dh) r7 (0Dh) r6 (0Dh) r5 (0Dh) r4 (0Dh) r3 (0Dh) r2 (0Dh) r1 (0Dh) r0 PS003802-0901 PS003802-0901 Register Function Reserved Reserved Reserved Low-Battery Detect Flag T16 MS-Byte Capture Register T16 LS-Byte Capture Register T8 High Capture Register T8 Low Capture Register T16 MS-Byte Hold Register T16 LS-Byte Hold Register T8 High Hold Register T8 Low Hold Register T8/T16 T8/T16 Control Register B T16 Control Register T8/T16 T8/T16 Control Register A T8 Control Register P R E L I M I N A Identifier LB HI8 LO8 HI16 LO16 TC16H TC16H TC16L TC16L TC8H TC8L CTR3 CTR2 CTR1 CTR0 R Y Z86D990/Z86D991 Z86D990/Z86D991 OTP and Z86L990/Z86L991 Z86L990/Z86L991 ROM Low-Voltage Microcontrollers with ADC 54 Table 13. SMR and Port Mode Registers (Group 0, Bank F, Registers 0­F) Grp/Bnk Reg (0Fh) rF (0Fh) rE (0Fh) rD (0Fh) rC (0Fh) rB (0Fh) rA (0Fh) r9 (0Fh) r8 (0Fh) r7 (0Fh) r6 (0Fh) r5 (0Fh) r4 (0Fh) r3 (0Fh) r2 (0Fh) r1 (0Fh) r0 Register Function Reserved Reserved Reserved Reserved Stop Mode Recovery Register Reserved Reserved ADC Control Register Reserved Port 6 Mode Port 5 Stop Mode Recovery Port 5 Mode