Z90361 Z90365 PS002500-TVC1099 PWM10 Z90369ZEM Z90369 Z89C00 PORT00 PORT01 - Datasheet Archive

 

Z90365 ROM 32 KWORD TELEVISION CONTROLLER WITH OSD PRODUCT SPECIFICATION PS002500-TVC1099 ZiLOG WORLDWIDE HEADQUARTERS ·

 

Z90361 Z90361 OTP Z90365 Z90365 ROM 32 KWORD TELEVISION CONTROLLER WITH OSD PRODUCT SPECIFICATION PS002500-TVC1099 PS002500-TVC1099 ZiLOG WORLDWIDE HEADQUARTERS · 910 E. HAMILTON AVENUE · CAMPBELL, CA 95008 ZiLOG Worldwide Headquarters 910 E. Hamilton Avenue Campbell, CA 95008 Telephone: 408.558.8500 Fax: 408.558.8300 www.ZiLOG.com Document Disclaimer © 1999 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Except with the express written approval ZiLOG, use of information, devices, or technology as critical components of life support systems is not authorized. No licenses or other rights are conveyed, implicitly or otherwise, by this document under any intellectual property rights. Z90365 Z90365 ROM and Z90361 Z90361 OTP 32 KWord Television Controller with OSD Table of Contents 1 OVERVIEW . 1 1.1 1.2 Block Diagram . 3 Pin Description . 4 2 OPERATION . 6 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 CPU Descriptions . 6 Memory (ROM and RAM) . 10 Clock Circuit Description . 12 Reset Conditions . 14 Power Management . 16 I/O Port Configurations . 16 Interrupts . 18 Timers . 19 ADC . 20 Pulse Width Modulation . 21 I2C Interface . 22 On-Screen Display (OSD) . 28 Other Functions . 33 3 REGISTER GROUPS . 35 3.1 3.2 3.3 3.4 3.5 Register Description . Bank0 (I/O Ports, I2C Interface, PLL Frequency, PWM ) . Bank1 (Control Registers) . Bank2 (PWM Registers) . Bank3 (On Screen Display [OSD] registers) . 36 37 43 55 55 4 INSTRUCTION SET . 71 4.1 4.2 4.3 4.4 4.5 4.6 4.7 PS002500-TVC1099 PS002500-TVC1099 Instruction Summary . Instruction Operands . Instruction Format . Instruction Bit Codes . Instruction Format Examples . Instruction Timing . Instruction Op Codes . Preliminary 71 73 75 77 81 86 87 iii Z90365 Z90365 ROM and Z90361 Z90361 OTP 32 KWord Television Controller with OSD 5 ELECTRICAL CHARACTERISTICS . 157 5.1 5.2 5.3 5.4 5.5 Absolute Maximum and Minimum Ratings . DC Characteristics . DC Peripherals . AC Characteristics . Analog RGB . 157 158 159 160 161 6 SYSTEM DESIGN CONSIDERATIONS . 162 7 PACKAGING . 164 PS002500-TVC1099 PS002500-TVC1099 Preliminary iv Z90365 Z90365 ROM and Z90361 Z90361 OTP 32 KWord Television Controller with OSD List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Code Development Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 42-Pin SDIP Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 RAM, ROM, and Pointer Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 10 ROM Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 RAM Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Clock Switching Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 32KHz Oscillator Recommended Circuit . . . . . . . . . . . . . . . . . . . . . . . 13 Bidirectional Port Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Bidirectional Pins Multiplexed with I2C Port . . . . . . . . . . . . . . . . . . . . 17 Bidirectional Pins Multiplexed with ADC Inputs . . . . . . . . . . . . . . . . . 18 IR Capture Register Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 PWM9 and PWM10 PWM10 Output Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 OSD Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Blank and V1, V2, V3 Outputs in Digital Mode . . . . . . . . . . . . . . . . . . 29 V1, V2 and V3 Outputs in Analog (Palette) Mode . . . . . . . . . . . . . . . . 30 Character Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 IR Capture Register Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Loop Filter Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Pipeline Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Recommended Application Schematics . . . . . . . . . . . . . . . . . . . . . . 161 System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 PS002500-TVC1099 PS002500-TVC1099 Preliminary v Z90365 Z90365 ROM and Z90361 Z90361 OTP 32 KWord Television Controller with OSD PS002500-TVC1099 PS002500-TVC1099 Preliminary vi Z90365 Z90365 ROM and Z90361 Z90361 OTP 32 KWord Television Controller with OSD List of Tables Table 1 Table 2 Table 3 Table 4 Table 5 Z90365 Z90365 or Z90361 Z90361 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 RPL Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Reset Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 ADC Inputs Typical Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master I2C Bus Bit Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master I2C Bus Interface Commands . . . . . . . . . . . . . . . . . . . . . . . . . . Slave I2C Bus Interface Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . Character Expansion Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bank Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register0, R0(0) PWM9 Data Register . . . . . . . . . . . . . . . . . . . . . . . . . Register1, R1(0) PWM10 PWM10 Data Register . . . . . . . . . . . . . . . . . . . . . . . . Register2, R2(0) PLL Frequency Data Register . . . . . . . . . . . . . . . . . . Register3, R3(0) I2C Interface Register . . . . . . . . . . . . . . . . . . . . . . . . . Register4, R4(0) Port 0 Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . Register5, R5(0) Port 1 Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . Register6, R6(0) Port 0 Direction Register . . . . . . . . . . . . . . . . . . . . . . Register7, R7(0) Port 1 Direction Register . . . . . . . . . . . . . . . . . . . . . . Register0, R0(1) Clamp Position Register . . . . . . . . . . . . . . . . . . . . . . Register1, R1(1) Speed Control Register . . . . . . . . . . . . . . . . . . . . . . . Register2, R2(1) WDT/STOP (write only) and 9-bit Counter (read only) Control Register . . . . . . . . . . . . . . . . Register3, R3(1) Standard Control Register . . . . . . . . . . . . . . . . . . . . Register 4, R4(1) ADC Control Register . . . . . . . . . . . . . . . . . . . . . . . . Register5, R5(1)Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . Register6, R6(1) Clock Switch Control Register . . . . . . . . . . . . . . . . . Register7, R7(1) Interrupts/WDT/SMR Control Register . . . . . . . . . . Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register0­Register5, R0(2)­R4(2) PWM 1­5 Registers . . . . . . . . . . . . Register0­Register2 Read Operation R0(3), R2(3) Character Multiple Registers . . . . . . . . . . . . . . . . Register0­Register1 Write Operation R0(3), R1(3) Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 PS002500-TVC1099 PS002500-TVC1099 Preliminary 20 23 24 25 32 35 36 37 38 38 40 41 41 42 43 43 45 46 47 48 49 51 53 54 55 56 56 vii Z90365 Z90365 ROM and Z90361 Z90361 OTP 32 KWord Television Controller with OSD Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Table 55 Table 56 Table 57 Table 58 Table 59 Table 60 Table 61 Table 62 Table 63 Table 64 Table 65 PS002500-TVC1099 PS002500-TVC1099 Register2, R2(3) Attributes Register, Write Operation . . . . . . . . . . . . Register3 Read Operation R3(3) Attributes Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register3, R3(3) Write Operation Attribute Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Display Character Format for Attribute Data Register R3(3) OSD Mode Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Character Format, OSD Mode Write Operation Attribute Data Register R3(3) . . . . . . . . . . . . . . . . . . . . . . . . . . . Display Character Format, Attribute Data Register R3(3) Write Operation CCD Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Character Format, Attribute Data Register R3(3) CCD Mode, Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . Register4 - R4(3) OSD Control Register . . . . . . . . . . . . . . . . . . . . . . . . Register5, R5(3) Capture Register, Read Operation . . . . . . . . . . . . . . Register6, R6(3) Palette Control Register . . . . . . . . . . . . . . . . . . . . . . Register7, R7(3) Output Palette Control Register . . . . . . . . . . . . . . . . Color Palette . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . StarSight Palette Color Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Format Mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Accumulator Modification Instructions . . . . . . . . . . . . . . . . . . . . . . . . Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Load Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Program Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rotate and Shift Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Operand Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Mnemonics/Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . Condition Code Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Accumulator Modification Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flag Modification Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Pointer/ Data Pointer Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Accumulator Modification Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flag Modification Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Direct Internal Addressing Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . Short Immediate Addressing Format . . . . . . . . . . . . . . . . . . . . . . . . . . Preliminary 57 59 59 60 61 62 63 64 65 65 66 68 70 71 72 72 72 72 73 73 73 74 74 77 78 79 79 80 82 83 83 84 85 viii Z90365 Z90365 ROM and Z90361 Z90361 OTP 32 KWord Television Controller with OSD Table 66 Table 67 Table 68 Table 69 Table 70 Table 71 Table 72 Table 73 Table 74 Table 75 Table 76 PS002500-TVC1099 PS002500-TVC1099 Long Immediate Addressing Format . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Jump, Call Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Instruction Op Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Instruction Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Instruction Format Mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 V1, V2, and V3 (R,G,B) Analog Output . . . . . . . . . . . . . . . . . . . . . . . . 159 ADC0/Small Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 ADC1-ADC4/Full range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 RGB Voltage Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 RGB Time Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Preliminary ix Z90365 Z90365 ROM and Z90361 Z90361 OTP 32 KWord Television Controller with OSD PS002500-TVC1099 PS002500-TVC1099 Preliminary x Z90365 Z90365 ROM and Z90361 Z90361 OTP 32 KWord Television Controller with OSD 1 OVERVIEW The Z90365 Z90365 and Z90361 Z90361 are the ROM and OTP versions of a Television Controller with On-Screen Display (OSD) that contains 32 KWords of program memory and 640 words of RAM. · The Z90361 Z90361 is the one-time programmable (OTP) controller used to develop code and prototypes for specific television applications or initial limited production. Program ROM and Character Generation ROM (CGROM) in the Z90361 Z90361 are both programmable. The Z90361 Z90361 requires Zilog's Z90369ZEM Z90369ZEM Emulator with its proprietary Zilog Developmental Studio (ZDS) software for programing. To view code effects, the emulator uses a ZOSD board which connects directly to a television screen. Refer to Figure 1. Z90369 Z90369 In-Circuit Emulator (ICEbox) ZOSD Board Z90369 Z90369 Z90361 Z90361 Develop code on PC Download Code to Z90369 Z90369 ICE chip Converts to Video Display Review Code on TV Display Program the Z90361 Z90361 OTP Figure 1 · PS002500-TVC1099 PS002500-TVC1099 Code Development Environment The Z90365 Z90365 incorporates the ROM code developed by the customer with the Z90361 Z90361. Customer code is masked into both program ROM and CGROM. Preliminary 1 Z90365 Z90365 ROM and Z90361 Z90361 OTP 32 KWord Television Controller with OSD The Z90365 Z90365 Television Controller with OSD is based on the ZiLOG's Z89C00 Z89C00 RISC processor core. The Z89C00 Z89C00 is a second generation, 16-bit, fractional, two's complement CMOS Digital Signal Processor (DSP). Most instructions are accomplished in a single clock cycle. The processor features a 24-bit Arithmetic Logic Unit (ALU) and a 24-bit Accumulator. The processor also contains a six-level stack with three vector interrupts. (Note: The multiplier of Z89C00 Z89C00 is disabled in the Z90365 Z90365 controller.) The Z90365 Z90365 contains 32K words of program ROM and 640 words of on-chip data RAM. This device can support up to 512 characters with a16x16, 16x18 and 16x20 programmable matrix. In addition, the Z90365 Z90365 contains four external register banks with eight registers in each. The internal 24MHz/2 system clock has a Phase Lock Loop (PLL) controlled by an external 32.768KHz crystal. A five channel, 4-bit Analog to Digital Converter (ADC) supports · multiple tuner automatic frequency tuning (AFT) · analog keypad entry · audio level input · Vertical Blank Interval (VBI) data capture. Seven Pulse Width Modulator (PWM) outputs allow low cost digital to analog conversion (DAC). Five PWMs have 8-bit resolution to control video and audio attributes. Two PWM have 14-bit resolution to control an external Voltage Synthesis Tuner (VST). A Master/Slave I2C (Inter Integrated Circuit) bus interface provides serial system interconnect to common peripheral functions. Twenty programmable I/O pins provide flexibility for other digital input/output functions. An IR (InfraRed) remote capture register facilitates reliable remote data capture. On-chip Horizontal Synchronization (HSYNC) and Vertical Synchronization (VSYNC) circuits generate a video timebase (typically used for VCR and set-top applications) in the absence of an available video signal. Micro-programmable OSD generation logic provides flexibility to tailor OSD features and functions. In addition to normal OSD functions, Closed Captioning is supported in accordance with FCC Report and Order on GEN Docket No. 91-1, dated April 12, 1991. Expanded Data Service (XDS) capability can be implemented as well. The Z90365 Z90365 is packaged in a 42-pin SDIP package. Figure 2 is a block diagram of the internal structure of the chip . Figure 3 illustrates the pin locations and Table 1 describes the function of each pin. PS002500-TVC1099 PS002500-TVC1099 Preliminary 2 Z90365 Z90365 ROM and Z90361 Z90361 OTP 32 KWord Television Controller with OSD 1.1 Block Diagram PWM PWM1 PWM2 PWM3 PWM4 PWM5 IR CAPTURE IRIN COUNTER Port17 Port 00 Port 05 Port 04 ADC ADC0 ADC1 ADC2 ADC3 ADC4 PWM9 PWM10 PWM10 PORT0 PORT00 PORT00 PORT01 PORT01 PORT02 PORT02 PORT03 PORT03 PORT04 PORT04 PORT05 PORT05 PORT06 PORT06 PORT07 PORT07 PORT08 PORT08 PORT09 PORT09 PORT0F CONTROL XTAL1 XTAL2 LPF HSYNC VSYNC /RESET PORT1 PORT10 PORT10 PORT11 PORT11 PORT12 PORT12 PORT13 PORT13 PORT14 PORT14 PORT15 PORT15 PORT16 PORT16 PORT17 PORT17 PORT18 PORT18 I2C I2CMC I2CMD I2CSC I2CSD Reg Addr/Data CPU Port 11 Port 12 Port 01 Port 02 OSD V1 V2 V3 VBLANK RAM Address 640 words Data Z89C00 Z89C00 CORE ROM Addr ROM Data Figure 2 PS002500-TVC1099 PS002500-TVC1099 ROM 32K words Block Diagram Preliminary 3 Z90365 Z90365 ROM and Z90361 Z90361 OTP 32 KWord Television Controller with OSD 1.2 Pin Description PWM10 PWM10 PWM9 PWM5 PWM4 PWM3 PWM2 PWM1 Port03 Port04/ADC4 Port05/ADC3 Port00/ADC2 Port17/ADC1 GND Port10/R0 Port06/Counter Port18/G0 Port13/G1 Port14/B0 Port15/B1 Port16/SCLK Port0F 1 2 3 4 5 6 Z90365 Z90365 7 or 8 Z90361 Z90361 9 10 TOP 11 VIEW 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 Figure 3 42-Pin SDIP Pinout Table 1 Port12/I2CMD Port11/I2CMC Port02/I2CSD Port01/I2CSC Port09 Port08/R1 IRIN Port07/CSYNC VCC Reset XTAL2 XTAL1 AGND LPF CVI/ADC0 VSYNC HSYNC VBLANK V1(R) V2(G) V3(B) Z90365 Z90365 or Z90361 Z90361 Pin Description Symbol Pin # Function Direction VCC 34 +5 Volts Power GND 13, 30 0 Volts Power IRIN 36 InfraRed remote capture input Input ADC[4:0]1 9, 10, 11, 12, 28 4-Bit Analog to Digital Converter input2. Analog Input PS002500-TVC1099 PS002500-TVC1099 Preliminary 4 Z90365 Z90365 ROM and Z90361 Z90361 OTP 32 KWord Television Controller with OSD Table 1 Z90365 Z90365 or Z90361 Z90361 Pin Description Symbol Pin # Function Direction PWM10 PWM10, PWM9 1, 2 14-Bit Pulse Width Modulator Output output PWM[5:1] 3, 4, 5, 6, 7 8-Bit Pulse Width Modulator output Output PORT0[F;9-0] 21, 38, 37, 35, 15, 10, 9, 8, 40, 39, 11 Bit programmable Input/ Output ports Input/Output PORT1[8:0] 16, 12, 20, 19, Bit programmable Input/ 18, 17, 42, 41, 14 Output ports Input/Output I2CMC3 41 Master I2C Clock I/O I 2C Input/Output I2CMD4 42 Master Data I/O Input/Output I2CSC5 39 Slave I2C Clock I/O Input/Output I2CSD6 40 Slave XTAL1 31 Crystal oscillator input Analog Input XTAL2 32 Crystal oscillator output Analog Output LPF 29 LOOP FILTER Analog Input/Output HSYNC 26 H_SYNC Input/Output VSYNC 27 V_SYNC Input/Output RESET 33 Device Reset Input V3, V2, V1 22, 23, 24 OSD video output. Typically drive B, G and R outputs. Output/Analog Output VBLANK 25 OSD Blank Output Output RGB digital outputs7 37, 14, 17, 16, 19, 18 R[1:0], G[1:0] and B[1:0] outputs of the RGB matrix Output SCLK8 20 internal processor SCLK Output CSYNC9 35 Composite Sync Output Output COUNTER10 COUNTER10 15 Counter Input/Output Input/Output PS002500-TVC1099 PS002500-TVC1099 Preliminary I 2C Data I/O Input/Output 5 Z90365 Z90365 ROM and Z90361 Z90361 OTP 32 KWord Television Controller with OSD Table 1 Z90365 Z90365 or Z90361 Z90361 Pin Description Symbol 1 2 3 4 5 6 7 8 9 10 2 Pin # Function Direction ADC1 input pin is shared with Port17, ADC2 input pin is shared with Port00. ADC3 input pin is shared with Port05 and ADC4 input pin is shared with Port04. ADC0 has a lamp circuit which facilitates Composite Video input. I2CMC I/O pin is shared with Port 11 I2CMD I/O pin is shared with Port12 I2CSC I/O pin is shared with Port 01 I2CSD I/O pin is shared with Port02 Digital RGB outputs are shared with Port1 and Port0 pins Internal processor SCLK is shared with Port16 CSYNC is shared with Port07 Counter is shared with Port06 OPERATION 2.1 CPU Descriptions The Z89C00 Z89C00 core is a high-performance DSP which has a modified Harvard-type architecture with separate program and data memories. The design has been optimized for processing power and silicon space. The Z89C00 Z89C00 used in the Z90365 Z90365 device is modified. The multiplier is disabled and is not accessible. However, the X and Y registers in the multiplier are still available and can be used as a general purpose registers. See the Zilog Z89C00 Z89C00 datasheet. ALU The 24-bit ALU has two input ports, one of which is connected to the output of the 24-bit Accumulator. The other input is connected to the 24-bit P-Bus, the upper 16-bits of which are connected to the 16-bit D-Bus. Instruction Timing Several instructions are executed in one machine cycle. Long immediate instructions and Jump or Call instructions are executed in two machine cycles. When the program memory is referenced in internal RAM indirect mode, it requires three machine cycles. An additional machine cycle is required if the PC is selected as the destination of a data transfer instruction. This only occurs in the case of a register indirect branch instruction. PS002500-TVC1099 PS002500-TVC1099 Preliminary 6 Z90365 Z90365 ROM and Z90361 Z90361 OTP 32 KWord Television Controller with OSD Hardware Stack A six-level hardware stack is connected to the D-Bus to hold subroutine return addresses or data. The CALL instruction pushes PC+2 onto the stack. The RET instruction pops the contents of the stack to the PC. CPU Registers The Z90365 Z90365 has 11 physical internal registers and four external register banks with eight registers in each. In addition, it has nine virtual registers. The 11 internal registers are defined in Table 2 and the status register is defined in Table 3. Internal Registers Table 2 Internal Registers Register Register DeÞnition X X, 16-bit Y Y, 16-bit A Accumulator, 24-bit SR Status Register, 16-bit Pn:b Six RAM Address Pointers, 8-Bit each PC Program Counter, 16-Bit X and Y are 16-bit general purpose registers. A is a 24-bit Accumulator. The output of the ALU is sent to this register. When 16-bit data is transferred into this register, it goes into the 16 MSB's and the least significant eight bits are set to zero. Only the upper 16 bits are transferred to the destination register when the Accumulator is selected as a source register in transfer instruction. SR is the Status Register which contains the ALU status and the control bits listed in Table 3. The status register is always read in its entirety. S15-S12 S15-S12 are set/reset by the hardware and can only be read through software. They are set or reset by the ALU after an operation. S8-S0 can be written by software. S8, if 0 (reset), allows the hardware to overflow. If S8 is set, the hardware clamps at maximum positive or negative values instead of overflowing. S7 enables interrupts. S6 - S5 are used for "short form direct" addresses which are described below. The definitions of S2-S0 are listed in Table 4. PS002500-TVC1099 PS002500-TVC1099 Preliminary 7 Z90365 Z90365 ROM and Z90361 Z90361 OTP 32 KWord Television Controller with OSD Table 3 Status Register Bit/Field Bit Position R/W Description N 15 R ALU Negative OV 14 R ALU Overßow Z 13 R ALU Zero L 12 R Carry Reserved 11 R Reserved Reserved 10 R Reserved Reserved 9 R Reserved OP 8 R/W Overßow Protection IE 7 R/W Interrupt Enable Register Bank Selector 6,5 R/W 00 Register Bank 0 01 Register Bank 1 10 Register Bank 2 11 Register Bank 3 SFD 4,3 R/W ÒShort Form DirectÓ Bits RPL 2-0 R/W RAM Pointer Loop Size Table 4 RPL Description S2 S1 S0 Loop Size 0 0 0 256 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128 Pn:b are the pointer registers for accessing data RAM. (n= 0, 1, 2 refer to the pointer number) (b = 0, 1 refers to RAM bank 0 or 1). PS002500-TVC1099 PS002500-TVC1099 Preliminary 8 Z90365 Z90365 ROM and Z90361 Z90361 OTP 32 KWord Television Controller with OSD Pointer registers can be directly read from or written to, and can point directly to locations in data RAM or indirectly to Program Memory. PC is the Program Counter. When this register is assigned as a destination register, one NOP machine cycle is automatically added to adjust the pipeline timing. External Registers The Z90365 Z90365 module is capable of directly accessing up to eight external registers using only the three external register address signals that are normally available. In this implementation, two user bits (Status register S6-S5) are combined with the register address signals to provide the ability to address four banks of eight registers each. The registers most critical for speed are located together in Bank 3. In this specification, all external registers are referred to RX(Y) where: X is a register number within a register bank; Y is a bank number; and Z is a bit field number A register can be selected by setting bits 6 and 5 in the status register to define the bank, then specifying the address of the register on the external register address bus. External registers reside on the chip and are used to control the operation of all the peripheral modules in the device. By reading or writing to the fields in the external registers, the user can interact with the peripheral devices on the chip. Virtual Registers BUS is a read-only register which, when accessed, returns the contents of the D-Bus. It is a virtual register (physical RAM does not exist on the chip). Dn:b These eight data pointers refer to possible locations in RAM that can be used as pointers to locations in program memory. The programmer decides which location to choose two bits from in the status register and which two bits in the operand. Thus, only the lower 16 possible locations in RAM can be specified. At any one time there are eight usable pointers, four per bank, and the four pointers are in consecutive locations in RAM. For example, if S3/S4 = 01 in the status register, then D0:0/D1:0/D2:0/D3:0 refers to locations 4/5/6/7 in RAM bank 0. Note that when the data pointers are being written to, a number is actually being loaded to Data RAM, so they can be used as a limited method for writing to RAM. PS002500-TVC1099 PS002500-TVC1099 Preliminary 9 Z90365 Z90365 ROM and Z90361 Z90361 OTP 32 KWord Television Controller with OSD RAM Addressing The addresses in RAM can be specified in one of three ways. Refer to Figure 4. P0:0 RAM Pointers %FF P2:0 RAM1 256X16-BIT 256X16-BIT %37 P1:0 RAM 0 %FF RAM Pointers P0:1 256X16-BIT 256X16-BIT P1:1 P2:1 @P1:0 %37 %0321 %0321 %04 S4/S3 = 01 %00 %00 Data Pointers Internal ROM %8000 D0:0 %0321 D0:1 D1:0 @@P1:0 %0321 %1234 D2:0 D2:1 D3:0 32Kx16-Bit D1:1 D3:1 @D0:1 %0000 Figure 4 RAM, ROM, and Pointer Architecture 2.2 Memory (ROM and RAM) The Z90365 Z90365 has 32K words of Read Only Memory (ROM) and 640 words of Random Access Memory (RAM). PS002500-TVC1099 PS002500-TVC1099 Preliminary 10 Z90365 Z90365 ROM and Z90361 Z90361 OTP 32 KWord Television Controller with OSD ROM A 32K word mask ROM provides storage for both Program Memory (PROGROM) and Character Generation ROM (CGROM). The address boundary between these applications is dependent on the storage required for character graphics. The program ROM section can, in theory, be placed anywhere in the addressable ROM space; however, because CGROM usually starts at location 0000H 0000H, PROGROM resides in the higher address locations. The maximum available ROM space for program memory depends on the ROM reserved for CGROM (for an application) and the ROM size of the device selected. The size of memory used as CGROM depends on the number and resolution of characters stored in memory. An n represents the number of characters stored, ranging from 0 to 256. If characters are 16 × 18 pixels, then the upper region of memory starting at the 4K boundary is used for character storage. If not, that region can be used as program memory. 32K Int0 vector %7FFF Int1 vector %7FFE Int2 vector Reset vector Up to 5K %7FFD %7FFC %1400 CGROM - Bank 0, Scan lines 17, 18 or Bank 1, or Program ROM %1000 %10*n CGROM-Bank 0 (n Characters) Scan lines 1-16 4K %1200 Program ROM Up to 4.5K CGROM - Bank 0, Scan lines 19, 20 or Bank1 or Program ROM %0000 Up to 4K Figure 5 PS002500-TVC1099 PS002500-TVC1099 ROM Map Preliminary 11 Z90365 Z90365 ROM and Z90361 Z90361 OTP 32 KWord Television Controller with OSD RAM RAM is organized in banks of 256 words of 16 bits each. Bank 1 is always accessible. Bank0 is mapped to two banks with 256 and 128 words each. Total RAM size is 640 words. See Figure 6. 128 256 words Bank1.0 Figure 6 256 words Bank0.0 Bank0.1 RAM Allocation 2.3 Clock Circuit Description The processor is able to operate from several clock sources. · Primary Phase Lock Loop VCO source (PVCO) · Secondary Phase Lock Loop (SVCO) · 32.768-kHz oscillator clock (OSC) In addition, the processor clock can be halted temporarily to select the clock source or access ROM without disrupting normal operation of the processor. An external crystal controls the internal 32.768-kHz oscillator. The crystal is used as the clock reference for the internal Phase Locked Loop (PLL). The PLL provides the internal PVCO clock for processor operation. SCLK is generated internally by dividing the frequency of an appropriate oscillator (PVCO) by 2. The frequency of the SCLK after POR is 12.058 MHz. The SCLK signal can be sent to the Port16 output pin under software control by setting bit9 in register R3(10). The SVCO must be used as the system clock when the OSD is generated. The clock switch control register R6(1) defines the source of the SCLK for the Z90365 Z90365 core. The block diagram in Figure 7 represents the clock switch circuit. PS002500-TVC1099 PS002500-TVC1099 Preliminary 12 Z90365 Z90365 ROM and Z90361 Z90361 OTP 32 KWord Television Controller with OSD 12-MHz SVCO SVCO/PVCO 32.768-kHz oscillator 12 MHz PVCO PLL Fast/Slow No_Switch SWITCH1 SWITCH2 0 1 2 0 1 PLL Filter 0 1 SCLK 2 Divider R6(1) Figure 7 2 SWITCH3 R6(1) R1(1) Clock Switching Block Diagram Input/Drive Circuits The 32KHz oscillator circuit in Figure 8 is suggested for proper clock operations. 32.768 KHz 22 pF 10 M Z90365 Z90365 XTAL1 XTAL2 68 K 47 pF Figure 8 PS002500-TVC1099 PS002500-TVC1099 32KHz Oscillator Recommended Circuit Preliminary 13 Z90365 Z90365 ROM and Z90361 Z90361 OTP 32 KWord Television Controller with OSD 2.4 Reset Conditions Reset conditions including addresses and registers are listed in Table 5. Table 5 Reset Conditions - Reset Condition -15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Comments R0(0) PWM9 x x x x x x x x x x x x x x x x PWM9 R1(0) PWM10 PWM10 x x x x x x x x x x x x x x x x PWM10 PWM10 R2(0) pll_freq 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 PLL frequency control R3(0) I2C_int 0 0 0 0 0 1 x x x x x x x x x x I2C interface register R4(0) port0 x x x x x x x x x x x x x x x x 11-bit I/O port 0 R5(0) port1 x x x x x x x x x x x x x x x x 9-bit I/O port 1 R6(0) dir0 x x x x x 1 1 1 1 1 1 1 1 1 1 1 11-bit port 0 direction R7(0) dir1 x x x x x x x 1 1 1 1 1 1 1 1 1 9-bit port 1 direction R0(1) clamp_pos 1 0 0 0 0 0 0 0 0 x x x x x x x Position of video clamp pulse R1(1) sclk_freq 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Stop/sleep/normal mode R2(1) WDT/STOP x x x x x x x x x 0 0 0 0 0 0 0 Stop and WDT, 9-bit counter R3(1) standard_ctl 0 0 0 0 0 0 0 0 0 0 0 x x x 0 0 Output H/VSYNC/ Blink Control R4(1) ADC_ctl 0 0 0 0 0 0 0 0 0 0 0 0 x x x x A/D converter control R5(1) cap_1s_ctl x x x x 0 0 x x x x x x x x x x Counter timers control R6(1) clock_ctl 0 0 0 0 0 0 0 0 0 0 0 1 x x x x Clock control (switch VCO/DOT) R7(1) wdt_smr_ctl x x x x x x x x 0 x x x x x x x SMR and WDT control/interrupt R0(2) pwm1_data 0 0 0 0 0 0 0 0 x x x x x x x x 8-bit PWM 1 data Addr Register PS002500-TVC1099 PS002500-TVC1099 Preliminary 14 Z90365 Z90365 ROM and Z90361 Z90361 OTP 32 KWord Television Controller with OSD Table 5 Reset Conditions (Continued) R1(2) pwm2_data 0 0 0 0 0 0 0 0 x x x x x x x x 8-bit PWM 2 data R2(2) pwm3_data 0 0 0 0 0 0 0 0 x x x x x x x x 8-bit PWM 3 data R3(2) pwm4_data 0 0 0 0 0 0 0 0 x x x x x x x x 8-bit PWM 4 data R4(2) pwm5_data 0 0 0 0 0 0 0 0 x x x x x x x x 8-bit PWM 5 data R5(2) Reserved x x x x x x x x x x x x x x x x Reserved R6(2) Reserved x x x x x x x x x x x x x x x x Reserved R7(2) Reserved x x x x x x x x x x x x x x x x Reserved R0(3) hi_x2_hi_x3 x x x x x x x x x x x x x x x x Character multiple/ current data R1(3) lo_x2_mid_x3 x x x x x x x x x x x x x x x x Character multiple/ next or previous data R2(3) Ch_x1_lo_x3 x x x x x x x x x x x x x x x x Character multiple/ character graphics attribute R3(3) attr_data x x x x x x x x x x x x x x x x Character attribute/ video RAM data R4(3) osd_cntl x x x x x x x x x x x x x x x x On screen display control R5(3) cap_data x x x x x x x x x x x x x x x x Capture register data R6(3) palette_color 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Display palette color/underline color R7(3) output palette 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Output palette PS002500-TVC1099 PS002500-TVC1099 Preliminary 15 Z90365 Z90365 ROM and Z90361 Z90361 OTP 32 KWord Television Controller with OSD 2.5 Power Management There are two low power operating modes for Z90365 Z90365: SLEEP mode and STOP mode. SLEEP Mode In SLEEP mode, the controller uses the 32.768 KHz clock for the SCLK to reduce power consumption. STOP Mode In STOP mode, the processor is suspended and the power consumption is minimized. 2.6 I/O Port Configurations User control can be monitored either through the keypad scanning port or the 16-bit remote control capture register. Two input/output port blocks are available for general purpose digital I/O application. Each port bit can be programmed to be either input or output. To conserve the device pin count, some port pins are mapped to provide I/O to the ADC converter block and I2C interface block. The 20 configurable I/O pins are general purpose pins for functions such as serial data I/O, LED control, key scanning, power control and monitoring, and I2C serial data communications. Port 0 and 1 directions are defined in R6(0) and R7(0) respectively. R4(0) and R5(0) are data registers for both Ports 0 and 1. Figures 9, 10 and 11 show I/O configuration and sharing with other functional units. PS002500-TVC1099 PS002500-TVC1099 Preliminary 16 Z90365 Z90365 ROM and Z90361 Z90361 OTP 32 KWord Television Controller with OSD Direction 1 - IN 0 - OUT VCC Pad Output 20 Input Figure 9 Bidirectional Port Pins Direction 1- IN 0- OUT VCC PAD I2 C Output PORT Onput 20 Input Figure 10 Bidirectional Pins Multiplexed with I2C Port PS002500-TVC1099 PS002500-TVC1099 Preliminary 17 Z90365 Z90365 ROM and Z90361 Z90361 OTP 32 KWord Television Controller with OSD Direction 1 - IN 0 - OUT VCC PAD Output 20 Input Analog MUX Figure 11 Bidirectional Pins Multiplexed with ADC Inputs 2.7 Interrupts The Z90365 Z90365 has three external interrupt signals. There are four interrupt sources. · Horizontal sync (HSYNC) · Vertical sync (VSYNC) · Capture timer · External event (Port09). All interrupts are vectored. The capture timer and Port09 are multiplexed to the same interrupt. Interrupt priorities are programmable. Each interrupt can be masked by setting fields in the external registers. When the Z90365 Z90365 receives an interrupt request from one of the interrupt sources, it executes the interrupt service routine directly for that source. External register R7(1) controls interrupts. PS002500-TVC1099 PS002500-TVC1099 Preliminary 18 Z90365 Z90365 ROM and Z90361 Z90361 OTP 32 KWord Television Controller with OSD 2.8 Timers Watch-Dog Timer The watch-dog timer resets the CPU while it times out. External register R7(1) controls the watch-dog timer. Real Time Clock A clock timer, in real time, generates ticks every 1000, 250, 62.5 or 15.625 ms. External register R5(1) controls the real time clock. IR Capture Timer A capture timer measures time between edges of the IR signal. This timer can be programmed to measure timing from rising-to-rising, falling-to-rising, rising-to-falling, or falling-to-falling edges. IR capture timer is controlled by External register R5(1). Figure 12 is a block diagram of the IR capture register structure. CAP_Glitch CAP_Edge IR Glitch Filter Halt capture timer R5(1) Edge Detector Capture Time Capture Register Captured data R5(3) Falling edge is captured Reset R5(1) Capture Flags Prescaler CAP_speed R5(1) Raising edge is captured/ Reset R5(1) Timeout/ Reset R5(1) < Figure 12 IR Capture Register Block Diagram PS002500-TVC1099 PS002500-TVC1099 Preliminary 19 Z90365 Z90365 ROM and Z90361 Z90361 OTP 32 KWord Television Controller with OSD 2.9 ADC The Analog to Digital Converter (ADC) is a 4-bit resolution, flash A to D converter. The user program controls the five-to-one analog input multiplexor and conversion start circuits. The 4-bit conversion result can be read by the CPU after each conversion. The ADC0 input channel is dedicated to VBI (vertical blank interval) data slicing for subsequent digital signal processing. This channel has a special video clamp circuit that provides DC restoration of the composite video input signal. Typical VBI applications include Line 21 Closed Caption, Electronic Data Services, and StarSight Telecast. The range for ADC0 is from 1.5 to 2.0 V. The four remaining channels, ADC1, ADC2, ADC3, and ADC4, are general purpose ADCs which are normally used to implement tuner automatic frequency control and analog key entry. These four channels have a range from 0 to 5.0 V. The range for input signals differs according to ADC inputs. Refer to Table 6. Table 6 ADC Inputs Typical Range Input Range (V) Clamping Typical application CVI/ADC0 1.5­2.0 Yes (Ref­) CCD sampling input ADC1/P17 ADC1/P17 0­5.0 No AFC input ADC2/P00 ADC2/P00 0­5.0 No Key scanning input ADC3/P05 ADC3/P05 0­5.0 No Key scanning input ADC4/P04 ADC4/P04 0­5.0 No Key scanning input Reference voltages that have been generated internally define the maximum range of the input signal for the ADC. Nominal values are Ref+ = 2.0 V Ref­ = 1.5 V @ VCC = 5.0 V For other VCC values, the reference voltages must be prorated as Ref+ = 0.4 * VCC Ref­ = 0.3 * VCC PS002500-TVC1099 PS002500-TVC1099 Preliminary 20 Z90365 Z90365 ROM and Z90361 Z90361 OTP 32 KWord Television Controller with OSD The maximum sampling rate of the ADC converter is 3 MHz. It takes 4 SCLK cycles for valid output data from the ADC to become available. This is especially important if the application uses single shot mode. The ADC exhibits monotonous conversion characteristics with a nonlinearity of less than 0.5 LSB. ADC0. The ADC has a range of 0.5V (from 1.5V to 2.0V) and is directly multiplexed to the input of the ADC. The remaining ADC inputs (ranging from 0V to 5V) use AGND and AVCC voltage as a reference. Figure 13 is a block diagram of the ADC inner structure. Z90365 Z90365 ADC4/P04 ADC4/P04 ADC3/P05 ADC3/P05 ADC2/P00 ADC2/P00 ADC1/P17 ADC1/P17 5x1 MUX ADC Converter 4 ADC0 (CCD decoder) Clamp REF­ Figure 13 ADC Block Diagram 2.10 Pulse Width Modulation Pulse Width Modulation is used in conjunction with external low-pass filters to perform digital to analog conversion. Five 8-bit PWMs, (PWM1-PWM5) generate signals to control video and sound attributes. PWM9 and PWM10 PWM10 are 14-bit PWMs used with an external circuit to generate the control voltage for voltage synthesis tuners. When a chassis has a frequency synthesis tuner, these PWMs can also control video or sound attributes. PS002500-TVC1099 PS002500-TVC1099 Preliminary 21 Z90365 Z90365 ROM and Z90361 Z90361 OTP 32 KWord Television Controller with OSD Each PWM circuit features a data register with settings under program control. The data in the register determine the ratio of PWM High to PWM Low time. PWM data registers are NOT initialized when reset. To eliminate potential problems with PWM output, initialize PWM data registers BEFORE enabling the VCOs. External registers R0(2) to R5(2) are data registers for PWM1 to PWM4. External registers R0(0) and R1(0) are data registers for PWM9 and PWM10 PWM10. Figure 16 shows PWM circuits. VCC P PAD Output N Figure 14 PWM9 and PWM10 PWM10 Output Circuits 2.11 I2C Interface There are two hardware modules which support standard I2C bus protocol according to the I2C bus specification published by Phillips in 1992, entitled I2C Peripherals for Microcontrollers Data Handbook. The first module, the Master, can be configured for fast (400 kHz) or slow (100 kHz) bit rates and can be used in applications with a single master. The second module, the Slave, supports a 7-bit addressing format with both fast and slow bit rates. Table 7 lists the bit rates for the Master I2C Bus. PS002500-TVC1099 PS002500-TVC1099 Preliminary 22 Z90365 Z90365 ROM and Z90361 Z90361 OTP 32 KWord Television Controller with OSD Table 7 Master I2C Bus Bit Rates Mode I2C mode Bit Rate Actual Bit Rate LO/Fast Slow 0Ð100kHz 91kHz HI/Fast Fast 0Ð400kHz 334kHz To suppress possible problems on both data (SDA) and clock (SCL) lines, digital filters are implemented on all inputs of the I2C bus interface. These filters have a time constant equal to 3TSCLK = 250 ns. If the master or slave I2C interface is enabled, corresponding I/Os (Port01 and Port02 for the slave, Port11 and Port12 for the master) must be assigned as outputs. Master and Slave modules cannot be used simultaneously because of the shared register, (see the Register 3(0) data field). The software activates I2C modules by writing appropriate commands into the control register. To control the I2C bus interface, the control register R3(0) toggle bit must point to an appropriate interface (Master or Slave). M_disable or S_disable bits allow either the Master or Slave I2C interface to be disabled so not to interfere with any activity associated with the Port pins. At Power-on Reset (POR), both I2C interfaces are enabled. To use the I2C interface, the corresponding Port pin (multiplexed with the I2C Data and Clock) must be configured as an output, while M_disable or S_disable bits must be reset to 0. External register R3(0) controls the I2C. Table 8 lists the Master I2C bus interface commands. Table 9 lists the Slave I2C bus interface commands. Figures 15 and 16 are flow charts of the Master and Slave modes. PS002500-TVC1099 PS002500-TVC1099 Preliminary 23 Z90365 Z90365 ROM and Z90361 Z90361 OTP 32 KWord Television Controller with OSD Table 8 Master I2C Bus Interface Commands Command Notes/Function 000 This command sends a start bit, followed by an address byte speciÞed in the ÒdataÓ Þeld (bits ), then fetches an acknowledgment in bit . This command initializes communication, and generates 9 SCL cycles. 001 This command sends one byte of data speciÞed in the ÒdataÓ Þeld (bits ), then fetches an acknowledgment in bit . This command is used in a WRITE frame, and generates 9 SCL cycles. 010 This command sends bit as an acknowledgment (ACK = 0, NAK = 1), then receives a data byte. This command is used in a READ frame when the next data byte is expected, and generates 9 SCL cycles. Received data appears in the ÒdataÓ Þeld (bits ). 011 This command sends bit as an acknowledgment (ACK = 0, NAK = 1). This command is used in a READ frame to terminate data transfer, and generates one SCL cycle. 100 101 A NULL operation. This command must be used with a ÒRESETÓ bit and/or a ÒTOGGLEÓ bit . Using the ÒRESETÓ and/or ÒTOGGLEÓ bits with any other command, interferes with the logic of the I2C interface. 110 This command receives one data byte. It is used in a READ frame to receive the Þrst data byte after the address byte is transmitted. It generates 8 SCL cycles. 111 This command sends a stop bit, and generates one SCL cycle. PS002500-TVC1099 PS002500-TVC1099 Preliminary 24 Z90365 Z90365 ROM and Z90361 Z90361 OTP 32 KWord Television Controller with OSD Table 9 Slave I2C Bus Interface Commands Command Notes/Function 0 0 0 Reserved. Cannot be used. 0 0 1 This command sends bit as an acknowledgment (ACK = 0 only), then receives one data byte. This command is used in a WRITE frame and requires 9 SCL cycles. Received data is read as a ÒdataÓ Þeld (bits ). 0 1 0 This command sends one byte of data speciÞed in a ÒdataÓ Þeld (bits ), then fetches an acknowledgment in bit . This command is used in a READ frame and requires 9 SCL cycles. 0 1 1 Reserved. Can not be used. 1 0 0 1 0 1 A NULL operation. This command must be used with a ÒRESETÓ bit and/or ÒTOGGLEÓ bit . Using the ÒRESETÓ and/or ÒTOGGLEÓ bits with any other command, interferes with the logic of the I2C interface. 1 1 0 This command sends a bit as a not acknowledgment (NAK = 1 only) in a WRITE or READ frame. This command terminates I2C communication and requires one SCL cycle. The ÒSulfonamideÓ bit is automatically reset when a ÒbusyÓ bit goes Low. This command sends a bit as an acknowledgment (ACK = 0 only) in a READ frame and requires one SCL cycle. The Send data command (010) must be executed next. This command acknowledges an address byte in a READ frame. 1 1 1 Reserved. Cannot be used. PS002500-TVC1099 PS002500-TVC1099 Preliminary 25 Z90365 Z90365 ROM and Z90361 Z90361 OTP 32 KWord Television Controller with OSD START no yes Read R3(0) "Busy" =0? Send a start bit followed by a 7-bit Address byte Write R3(0) {0000,0xxx,Addr,R/W} no "Busy"=1 yes Read R3(0) (Read Ack bit) no (Nak) R3(0)=0? yes (Ack) Write frame More bytes to send? Read frame Write R3(0) {1100,0xxx,xxxx,xxxx} (Ask slave to send Data byte) no yes Write R3(0) {0010,0xxx,Data} (Send Data byte) yes "Busy"=1? no no "Busy"=1? Write R3(0) {0110,0xxx,0xxx,xxxx} (Ack Data byte) yes Write R3(0) {0110,0xxx,1xxx,xxxx} (Nak Data byte) Read R3(0) {xxxx,xxxx,Data} (Read Data byte) no Receive more bytes? yes yes "Busy"=1? Note: Shaded blocks are executed in software no Write R3(0) {0100,0xxx,0xxx,xxxx} (Acknowledge Data byte) Write R3(0) {1110,0xxx,xxxx,xxxx} (Send a "Stop" bit) Figure 15 Master Mode PS002500-TVC1099 PS002500-TVC1099 Preliminary 26 Z90365 Z90365 ROM and Z90361 Z90361 OTP 32 KWord Television Controller with OSD START no yes "Start" condition detected Set R3(0) Reset R3(0) yes no Address matches Reset R3(0) Set slave modeR3(0) Hold the bus Stretch clock Reset slave busyR3(0) (Nak Master) Write R3(0) {1100,0xxx,1xxx,xxxx} Ignore master Read frame R3(0)=1 Ack master (Ack Master) Write R3(0) {1100,0xxx,0xxx,xxxx} no Wait here for "send first byte" command Write frame R3(0)=0 Read R3(0) (R/W bit) Slave = 1,Busy = 0 R3(0) yes (Nak master) (Ack master) Write R3(0) Write R3(0) 1100,0xxx,1xxx,xxxx 0010,0xxx,0xxx,xxxx no Slave = 1,Busy = 0 R3(0) yes (Send data) Write R3(0) {0100,0xxx,Data} Slave = 1,Busy = 0 R3(0) no Wait for Ack from master hold the bus stretch clock (Get Data) Read R3(0) yes goto Ack Master no (Nak) Read R3(0) Ack=0? yes (Ack) hold the bus stretch clock Note: Shaded blocks are executed in software Note: If a "Stop" condition is detected at any point, the hardware resets the "Slave" bit (R3(0), and releases the I2C bus. Figure 16 Slave Mode PS002500-TVC1099 PS002500-TVC1099 Preliminary 27 Z90365 Z90365 ROM and Z90361 Z90361 OTP 32 KWord Television Controller with OSD 2.12 On-Screen Display (OSD) The Z90365 Z90365 provides sophisticated on-screen display features. On-Screen Display has two modes. · · OSD Used to generate TV control OSD CCD Used to display Closed Caption information OSD mode provides access to the full set of control attributes including latched and unlatched attributes. Unlatched attributes can be modified on a character-by-character basis. Control characters change latched attributes. The full 512-character set, formatted in two 256 character banks, can be displayed with many display attributes, including underlining, italics and blinking, eight foreground and background colors, character position offset delay, and background transparency. A 16-bit display character represents foreground color, background color, and underline attributes which can be modified character by character. A character's pixel matrx is stored as 16, 18 or 20 words in Character Generation ROM (CGROM). Additional hardware provides the capability to display characters at two and three times normal size. The smoothing logic improves the appearance of two and three times normal size characters. Fringing can be activated to improve the visibility of characters by adding a border (one pixel wide) on each side. The Z90365 Z90365 provides RGB signals and a video blank signal. RGB signals are available in two modes: digital and analog. In digital mode the output RGB signals correspond to a primary colors palette. Analog mode supports 64 different palettes which can be chosen under software control. In analog mode, each RGB signal is generated by a 2-bit digital to analog converter. The 2-bit digital inputs of the D to A converter can be switched to Port pins (P10, P13, P14, P15, P18 and P08) by setting bit9 in Register3(1) to "1". Video synchronization is normally obtained from H_FLYBACK and V_FLYBACK, but can be generated by the Z90365 Z90365 and driven to the external deflection unit via the bidirectional SYNC ports when external video synchronization signals are not present. OSD is completely software controlled. Hardware supports the optimum generation of the character based OSD, however the CPU can bypass it and generate pixels and attributes directly. The block diagram in Figure 19 shows the OSD data flow. Figures 17 through 19 show the V1, V2, V3 and Blank output circuits. PS002500-TVC1099 PS002500-TVC1099 Preliminary 28 Z90365 Z90365 ROM and Z90361 Z90361 OTP 32 KWord Television Controller with OSD P a l e t t e s R7(3) R6(3) R0(3) R1(3) R2(3) R0(3) R1(3) R2(3) Attribute R3(3) R4(3) Memory Rd Shift Register CGROM Pixels: 1x 2x 3x Full attrib R3(3) Video RAM OSD:At7Ch8 or Attr15 CCD:Char7 orAttr7 3 x D A C R G B CPU Figure 17 OSD Data Flow VCC P PAD Output N Figure 18 Blank and V1, V2, V3 Outputs in Digital Mode PS002500-TVC1099 PS002500-TVC1099 Preliminary 29 Z90365 Z90365 ROM and Z90361 Z90361 OTP 32 KWord Television Controller with OSD VCC VCC VCC I 800 mA I/2 I/4 Vx Vx PAD R3K Figure 19 V1, V2 and V3 Outputs in Analog (Palette) Mode Closed Caption Data Capture Closed-caption text can be decoded directly from the composite video signal using the processor's digital signal processing capabilities and displayed on the screen. The character representation in this mode provides simple attribute control by inserting control characters. Each word of video RAM specifies two displayed characters. The 4-bit flash A/D converter, with proper clamping, provides the ability to receive the composite video signal directly and process the closed-caption text embedded in the signal. Signal processing can be applied directly to the signal to improve decoder performance. CGROM (Character Generation ROM) The required Character Generation ROM size is dependent on the number of characters that are stored in memory. CGROM always starts at address 0000h. CGROM can be configured as two banks selectable by setting a control bit. Each bank provides up to 256 characters with 16x16, 16x18 or 16x20 pixels matrix. Absolute maximum CGROM size is 9K words (9216 words - 256x16 + 256x20). If both banks are used, the second bank starts from address 1000 hex (refer back to Figure 4). PS002500-TVC1099 PS002500-TVC1099 Preliminary 30 Z90365 Z90365 ROM and Z90361 Z90361 OTP 32 KWord Television Controller with OSD Each character pixel matrix is 16, 18 or 20 words of ROM. Each word represents 16 pixels. Scan lines 1 to 16 are mapped sequentially to ROM addresses, referenced by the character pointer and a line number offset. In 16x18 mode, scan lines 17 and 18 are offset by 1000h, referenced to scan line1. In 16 x 20 mode, scan lines 19 and 20 are offset by 1200 hex. That means that if Bank0 is in a 16 x 18 pixel matrix, it overlaps the first 32 characters of Bank1. If Bank0 is a 16 x 20 pixel matrix, it overlaps the first 64 characters of Bank1. The first character in each bank must be a space character. If an application requires Bank0 characters to be in 16 x 18, or 16 x 20, pixel matrix, the first 32 (64 for 16x20) characters of Bank1 must be sacrificed and cannot be used because lines 17 and 18 (for 16 x 18), and lines 17 through 20 (for 16 x 20) of Bank0 characters are mapped in their addresses. The first 8 (16 for 16 x 20) characters of Bank0 cannot have active pixels in lines 17 and 18 (19 and 20 for 16 x 20) to have a blank first (space) character in Bank1. If only Bank0 of CGROM is used, there is no limitation on character size. The character scan line from CGROM addressed by the character register is fetched and stored into the CGROM capture register. If a pixel is set to 1, it displays foreground color. If set to 0, it displays background color. The scan line can be stretched by the character multiplier to be two or three times normal character size by duplicating each bit in the word. Controlling Character Expansion The character size can be stretched to two or three times its size. Hardware fetches data from CGROM and stretches the data to be read from registers R0(3), R1(3), and R2(3). Figure 20 is a block diagram of the structure of the character expansion multiplexor and Table 10 lists bit functions. PS002500-TVC1099 PS002500-TVC1099 Preliminary 31 Z90365 Z90365 ROM and Z90361 Z90361 OTP 32 KWord Television Controller with OSD 16 ROM data CGROM data capture register 16 Character Expansion Multiplexor control x1, x2, x3 48 R0(3) 16 R1(3) char_mult_high 16 R2(3) char_mult_mid 16 char_mult_low Processor EXTERNAL bus Figure 20 Character Expansion Table 10 Character Expansion Register Capture Register Contents Char_mult_high x1 operation abcdefghijklmnop x2 operation aabbccddeeffgghh iijjkkllmmnnoopp x3 operation aaabbbcccdddeeef ffggghhhiiijjjkk klllmmmnnnoooppp Char_mult_mid Char_mult_low Displayed Data Formats The Z90365 Z90365 hardware supports two different data formats. · OSD mode, R4(3) = 1 supports a standard OSD with full set of features. · CCD mode, R4(3) = 0 supports reduced features which comply with the recommendations of the FCC on Closed Caption support. In CCD mode, the background color of the characters can NOT be changed and is always preset to BLACK. PS002500-TVC1099 PS002500-TVC1099 Preliminary 32 Z90365 Z90365 ROM and Z90361 Z90361 OTP 32 KWord Television Controller with OSD OSD Mode In OSD mode, each character occupies a 16-bit word in VRAM. There are two possible character formats defined: a "display" character and a "control" character. The code stored in "display" character format defines a character code and up to 7 attributes of the character. The "control" character defines latched attributes and is presented on-screen as a space character. The combination of "display" and "control" characters provides versatile OSD generation. Smoothing is supported for double-size (x2) and triple-size (x3) characters only. CCD Mode In CCD mode, each character occupies 8 bits (one byte) in VRAM. The CCD characters must be mapped into a 16-bit VRAM data field. The hardware supports compressed placement of characters in VRAM. Each word in VRAM is represented by a High byte and a Low byte. A currently active byte is selected by R4(3). The format and data representation in both bytes is exactly the same. There are two possible character formats defined: a "display" character and a "control" character. The code stored in "display" character format defines a character code. The "control" character defines five latched attributes (foreground color, italic, underline, blinking, and transparent); it is presented on screen as a space character. The combination of Display and Control characters provides the basis for a specified range of attributes defined by FCC specifications for CCD. 2.13 Other Functions Video and Sound Attribute Control Basic receiver functions such as color and volume can be controlled directly by six 6-bit pulse-width modulated ports. InfraRed Capture Function The Infrared Remote Control data capture feature uses a capture register to hold the time value from one transition of IR data to the next. Software periodically checks and reads the capture status and the value if a new capture occurs. Subsequent decoding and command passing of the received IR signal is under software control. Figure 21 illustrates the IR input circuit. PS002500-TVC1099 PS002500-TVC1099 Preliminary 33 Z90365 Z90365 ROM and Z90361 Z90361 OTP 32 KWord Television Controller with OSD 20 PAD IR Input Figure 21 IR Capture Register Input Loop Filter The Loop Filter pin configuration is represented in Figure 22. VCC VCC VCC PD "positive" out PAD PD "negative" out 20 To VCO driver Figure 22 Loop Filter Pin ConÞguration PS002500-TVC1099 PS002500-TVC1099 Preliminary 34 Z90365 Z90365 ROM and Z90361 Z90361 OTP 32 KWord Television Controller with OSD 3 REGISTER GROUPS Table 11 provides a summary of the registers in external banks. Table 11 Register Summary BANK BANK Sub Address READ Register Bank0 7 dir1 9-bit I/O port 1 direction control 6 dir0 11-bit I/O port 0 direction control 5 port1 9-bit I/O port 1 4 port0 11-bit I/O port 0 3 I2C_int I2C interface register 2 pll_freq PLL frequency control 1 PWM_data10 14-Bit PWM 10 data 0 PWM_data9 14-Bit PWM 9 data 7 wdt_smr_ctl/Interrupt SMR and WDT control and interrupt 6 clock_ctl Clock control (switch VCO/DOT) 5 cap_1s_ctl Counter timers control 4 ADC_ctl A/D converter control 3 standard_ctl Output H/VSYNC/blnk control 2 9-bit counter 1 sclk_freq Stop/sleep/normal mode 0 clamp_pos DeÞnes position of video clamp pulse 7 Reserved Reserved 6 Reserved Reserved 5 Reserved Reserved 4 pwm_data5 8-bit PWM 5 data 3 pwm_data4 8-bit PWM 4 data 2 pwm_data3 8-bit PWM 3 data 1 pwm_data2 8-bit PWM 2 data 0 pwm_data1 8-bit PWM 1 data Bank1 Bank2 PS002500-TVC1099 PS002500-TVC1099 WRITE Register STOP/WDT Preliminary Description Stop and WDT instructions, 9-bit counter 35 Z90365 Z90365 ROM and Z90361 Z90361 OTP 32 KWord Television Controller with OSD Table 11 Register Summary (Continued) BANK BANK Sub Address READ Register WRITE Register Bank3 7 output palette Output palette 6 palette_color Display palette color/underline color 5 capture_data 4 osd_control 3 attribute_data vram_data Character attribute/video RAM data 2 ch_x1_lo_x3 cg_attribute Character multiple/character graphics attribute 1 lo_x2_mid_x3 cg_nxt_prv Character multiple/next or previous data 0 hi_x2_hi_x3 cg_current Character multiple/current data Description I2C slave addr. Capture register data On screen display control 3.1 Register Description The register file in the Z90365 Z90365 is organized into four banks which can be selected by writing to bits 5 and 6 (Register Bank Selector bits) in the Status Register of the Z90365 Z90365 core. All registers are mapped into an external register space; each bank consists of 8 registers. The Status register is available to read or write at any time. The appropriate bank of registers must be selected before accessing the register. The software must keep track of which register bank is accessible at any time. Refer to Table 12 for register bank assignments. Table 12 Bank Assignments Bank Status Register Bank0 xxxx xxxx x00x xxxx b I/O ports, I2C interface, PLL frequency, 14-bit PWM Bank1 xxxx xxxx x01x xxxx b Control registers Bank2 xxxx xxxx x10x xxxx b PWM1ÐPWM5 Bank3 xxxx xxxx x11x xxxx b OSD, palette control PS002500-TVC1099 PS002500-TVC1099 Bank Functions Preliminary 36 Z90365 Z90365 ROM and Z90361 Z90361 OTP 32 KWord Television Controller with OSD 3.2 Bank0 (I/O Ports, I2C Interface, PLL Frequency, PWM ) Table 13 defines the bits for Register0, R0(0) PWM9 Data Register. Table 13 Register0, R0(0) PWM9 Data Register Bit 15 14 13 12 11 10 9 8 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset x x x x x x x x Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset x x x x x x x x Note: R = Read W = Write X = Indeterminate Reg Field Bit Position R W Value Description Port/PWM f- R W 1 0 Output port mode Output PWM mode (push-pull) Port_data -e- R W x Output data in Port mode PWM_data -dcba9876543210 R W xxx Output data in PWM mode The Port/PWM bit defines the mode of the PWM9 output. When set to 1, the PWM9 output monitors the data specified by the Port_data field. Otherwise the PWM_data field defines the waveform on the PWM9 pin. Table 14 defines the bits for Register1 - R1(0) PWM10 PWM10 Data Register. Table 15 defines the bits for Register2 - R2(0) PLL Frequency Data Register. PS002500-TVC1099 PS002500-TVC1099 Preliminary 37 Z90365 Z90365 ROM and Z90361 Z90361 OTP 32 KWord Television Controller with OSD Table 14 Register1, R1(0) PWM10 PWM10 Data Register Bit 15 14 13 12 11 10 9 8 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset x x x x x x x x Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset x x x x x x x x Note: R = Read W = Write X = Indeterminate Reg Field Bit Position R W Data Description Port/PWM f- R W 1 0 Output port mode Output PWM mode (push-pull) Port_data -e- R W x Output data in Port mode PWM_data -dcba9876543210 R W xxx Output data in PWM mode Table 15 Register2, R2(0) PLL Frequency Data Register Bit 15 14 13 12 11 10 9 8 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 1 1 1 0 0 0 0 Note: R = Read W = Write X = Indeterminate Reg Field W Data Description M_disable f- R W 1 0 I2C Master interface disabled I2C Master interface enabledÐPOR S_disable -e- R W 1 0 I2C Slave interface disabled I2C Slave interface enabledÐPOR Reserved -dcba98- R W Return 0 No Effect W xx PLL divider =256 + xx Data PS002500-TVC1099 PS002500-TVC1099 Bit Position R -76543210 R Preliminary 38 Z90365 Z90365 ROM and Z90361 Z90361 OTP 32 KWord Television Controller with OSD If the master or slave I2C interface is enabled, the corresponding I/Os (Port01 and Port02 for the slave, Port11 and Port12 for the master) must be assigned as outputs. The VCO, DOT, and SCLK frequency are defined as: FVCO = FDOT = FSCLK = XTAL * (256 + PLLDATA) Therefore, XTAL = 32.768 KHz At POR the PLL frequency data register is preset to %70, which corresponds to the VCO frequency of 12.058 MHz. The PLL_data field can be loaded with any value from %00. This value corresponds to an SCLK = 256*XTAL up to %FF, which corresponds to an SCLK = 511*XTAL. Because the SCLK frequency is proportional to the frequency of the XTAL, it is impossible to specify the maximum value that can be written into the PLL_data field. Note: It is the customer's responsibility not to exceed the SCLK frequency of 12.5 MHz. For common applications incorporating a 32.768KHz XTAL oscillator, the maximum setting of the PLL_data field in R2(0) is %7D, which corresponds to SCLK = 381*XTAL = 12.485 MHz. Tables 16 through 20 describe the bits in registers 3 through 7. PS002500-TVC1099 PS002500-TVC1099 Preliminary 39 Z90365 Z90365 ROM and Z90361 Z90361 OTP 32 KWord Television Controller with OSD Register3, R3(0) I2C Interface Register Table 16 Bit 15 14 13 12 11 10 9 8 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 1 x x Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset x x x x x x x x Note: R = Read W = Write X = Indeterminate Reg Field Bit Position R W Data Description Command fed-s R W %D Toggle -c- R Reset -b- Return 0 See full description in Tables 8 and 9. 1 0 W 1 0 Slave interface Master interfaceÐPOR condition Toggle active I2C interface No effect R W 1 0 Slave_mode -a- R Return 0 Reset Slave I2C interface if bit = 1 Reset Master I2C interface if bit = 0 No effect 1 0 Slave mode is active (POR condition) Slave mode is inactive No effect 1 0 Slave I2C interface is busy Slave I2C interface is idle No effect 1 0 W Master I2C interface is busy Master I2C interface is idle No effect xx W xx Received data Data to be sent W SlaveBusy -9- R W MasterBusy -8- Data -76543210 R R Data written to R3(0) requires 4 cycles before being applied. Consecutive writings to these bits require at least a 6-cycle delay. Received data is available for reading only when the busy bit is reset to a 0. At POR, the speed of the I2C interface is set to Low controlled by R(3)1. PS002500-TVC1099 PS002500-TVC1099 Preliminary 40 Z90365 Z90365 ROM and Z90361 Z90361 OTP 32 KWord Television Controller with OSD Table 17 Register4, R4(0) Port 0 Data Register Bit 15 14 13 12 11 10 9 8 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset x x x x x x x x Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset x x x x x x x x Note: R = Read W = Write X = Indeterminate Reg Field Bit Position Port_data R W f-9876543210 R xxxx W Table 18 Data Description If a port is configured in Input mode, enter the input data onto the port pins. xxxx If a port is configured in Output mode, then the data is written directly to the port data. Register5, R5(0) Port 1 Data Register Bit 15 14 13 12 11 10 9 8 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset x x x x x x x x Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset x x x x x x x x Note: R = Read W = Write X = Indeterminate PS002500-TVC1099 PS002500-TVC1099 Preliminary 41 Z90365 Z90365 ROM and Z90361 Z90361 OTP 32 KWord Television Controller with OSD Reg Field Bit Position R W Data Description Reserved fedcba9- R Return 0 No Effect W Port_data -876543210 R xxxx W Table 19 If a port is configured in Input mode, enter the input data onto the port pins. xxxx If a port is configured in Output mode, then the data is written directly to the port data. Register6, R6(0) Port 0 Direction Register Bit 15 14 13 12 11 10 9 8 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset x x x x x 1 1 1 Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 Note: R = Read W = Write X = Indeterminate Reg Field Bit Position R W Data Description Port_direction fedcba9876543210 R W xxxx 1: Input mode for corresponding bit 0: Output mode for corresponding bit PS002500-TVC1099 PS002500-TVC1099 Preliminary 42 Z90365 Z90365 ROM and Z90361 Z90361 OTP 32 KWord Television Controller with OSD Table 20 Register7, R7(0) Port 1 Direction Register Bit 15 14 13 12 11 10 9 8 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset x x x x x x x 1 Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 Note: R = Read W = Write X = Indeterminate Reg Field Bit Position R Reserved W Data fedcba9- R Return 0 No Effect W Port_direction -876543210 R Description xxxxx W 1: Input mode for corresponding bit 0: Output mode for corresponding bit 3.3 Bank1 (Control Registers) Tables 21 through 27 provide bit functions for Bank 1 Control registers. Table 21 Register0, R0(1) Clamp Position Register Bit 15 14 13 12 11 10 9 8 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 x x x x x x x Note: R = Read W = Write X = Indeterminate PS002500-TVC1099 PS002500-TVC1099 Preliminary 43 Z90365 Z90365 ROM and Z90361 Z90361 OTP 32 KWord Television Controller with OSD Reg Field Bit Position R Disable_clamp_1 f- R W Data Description W 1 0 Reserved -edcba987- R W Position -6543210 R W xx ADC0 Clamp generation is disabled ADC0 Clamp generation is enabled Return Ò0Ó No Effect Position of clamp pulse (from leading edge of the H-FLYBACK) At POR the disable_clamp bit is set to 1. The clamp pulse is generated if Enabled (bit ) and the SCLK frequency are switched back to PVCO. The SVCO/PVCO flag in R6(1) must be reset to 0 before the current HSYNC, regardless of whether the SVCO is enabled or disabled. The clamp position is defined by the Position field. The width of the clamp pulse cannot be modified and is set to 1us. The value that can be assigned to the "Position" field must be >%10 and