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PR3400

Catalog Datasheet MFG & Type PDF Document Tags

MIPS R3000A

Abstract: 74fct244a on the PR3400. Selects between single word and block refill during cache misses. Configurable either , conditional branch status from the coprocessors to the PR3400. Active LOW inputs: A six-bit interrupt bus used , refill. When LOW, CpCondO is configured to be an output driven by the PR3100A to the PR3400. 3.7 IStream , module contains: - PR3400 integrated CPU and FPA - PR3100A PaceWrapTM Write/Read & Parity Buffer - 64 Kbytes of data cache - 64 Kbytes of instruction cache - High speed clock generation unit PR3400 contains
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OCR Scan
MIPS R3000A 74fct244a PCBM/3400 PR3400/

PR3400

Abstract: fpa g12 FPA is connected internally. Output of PR3400. A 1-bit bus used to transfer conditional branch status , connected internally. Output of PR3400. A 6-bit bus used by the memory interface and coprocessors to signal , Clkin CPSync I o Note: CpBusy, CpCond (1) are output pins from PR3400. 4/ 1/92 1-85 , 78769-2963 (800) 225-5373 7.0 ORDERING INFORMATION PR3400- XX X X XXX X Tem perature , Flat Pack Military product compliant to MIL-STD-883C, Class B DESCRIPTION The PaceMips PR3400 is an
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OCR Scan
PR3000A fpa g12 tag 136 m2 32-BIT 256KB PR3010A IL-STD-883C
Abstract: Coprocessor busy stall initiationAermination signal. FpBusy of FPA is connected internally. Output of PR3400. , . The Co-processor 1 (FPA) condition signal FpCond is connected internally. Output of PR3400. lnt(5:0 , coprocessors for timing synchronization with the CPU. Note: CpBusy, CpCond (1) are output pins from PR3400. , Tag 14 Wr Busy 12 13 14 15 4 / 1/92 P^ceMips , PR3400- XX X X XXX X Temperature/Qualification C = Commercial Temperature Range, 0°C to -
OCR Scan
CA95112

PR3000A

Abstract: CPGA '" â'" X Now 4 Meg DRAM Order code: PR3400-xxVB004C Board N/A N/A VME board 25,33,40 â'" â'" X Now 16 Meg DRAM Order code: PR3400-xxVB016C Board N/A N/A Notes: 1. Ordering information remains the , CPGA PR3100A 20,25,33 SF 172 X X X Buffer Contact Marketing CQFP PR3400L 25,33,40 SG 145 X Now CPU/FPA 2x (Four Clock Inputs) Monolithic CPGA Yes D PR3400L 25,33 SG 145 X X Now CPU/FPA CPGA Yes D PR3400 25,33,40 SG 175 X Now CPU/FPA CPGA Yes D PR3400 25,33 SG 175 X X Now CPU/FPA CPGA
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OCR Scan
PR3000 CPGA 84 pin cpu PR2000 PR2000A PR2010A PR30001 PR30101 PR3010

PR3000A

Abstract: CPGA : PR3400-xxVB004C 16 Meg DRAM Order code: PR3400-xxVB016C N/A N/A N/A N/A N/A N/A - - Notes: 1 , PERFORMANCE SEMICONDUCTOR 50E D TObES'i? QÜÜ13Ô7 0D7 «P S C 32- and 64-bit RISC MIPS Microprocessors Part Type PR2000A1 PR2010A' PR3000' PR3000' PR3010' PR3010' PR3010' PR3000A' PR3000A PR3000A PR3000A PR3000A PR3000A PR3010A PR3010A PR3010A PR3010A PR3010A PR3010A PR3020 PR3100P PR3100A PR3100A PR3100A PR3400L PR3400L PR3400 PR3400 PR3400 PR3400 PR3400N PR4000P2 PR4000S2 PR4000M2
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OCR Scan
3400N CPU/FPA/PR3100A PCBM/3400- VB004C VB016C PR2000A-16PGC

53C700

Abstract: PR3000A the four Pacerunner/3400 VME Boards: PR340025VB004C PR340033VB004C PR340025VB016C PR340033VB016C = , $-FEATURES 33MHz and 40MHz RISC PR3400 (Integrated PR3000A CPU/PR3010A FPA) Offer 28 and 32 VAXmips respectively , nation of high performance and integration based on Performance Semiconductor's PR3400A chipset. Built on , PR3400 CPU daughter-board that provides the CPU/FPA, cache memory, write/read, and parity buffer , daughter-board are the following: PR3400 integrated CPU and FPA, 64KBytes of instruction cache, 64KBytes of data
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OCR Scan
53C700 53c70 scsi manual IEEE1014 RS232 SCC2692 53C710 82C501 IEEE802
Abstract: speeds of the ¡386 and i486, and the PR3000A/PR3400. Processor Access Time Frequency Output , PR3000A or PR3400 CPU /I Tag Bus A -ft- - f t | Data Bus D- Cache Control* P4C218(4 UnHs) Figure 4 IX86 64KByte Cache Figure 3 MIPS PR3000A or PR3400 (64KByte i- & d- Caches -
OCR Scan
R4000S 512KB R3000 PP52C GR52B PR3000A/PR3400
Abstract: i486, and the PR3000A/PR3400. Processor ¡386 ¡486 Frequency 40 MHz 33 MHz 25 MHz 50 MHz 33 MHz 33 MHz , Configurations for PR3000A and Ì386/Ì486 I- C a c h e C o ntrol* P4C218{4 U nits) Tag B us PR3400 CPU $ D- C a c h e C o n tro l* P4C218(4 Units) Figure 3 MIPS PR3000A or PR3400 (64KByte i- & d -
OCR Scan
P4C219 128KB P4C218-
Abstract: performance processor speeds of the ¡386 and ¡486, and the PR3000A/PR3400. Processor ¡386 i486 Frequency 40 , ideally suited for cache RAM applications with the MIPS PR3000A/PR3400, and Intel's 80386 and 80486 , O CACHE RAM CONFIGURATIONS FOR PR3000A AND ¡386/¡486 MIPS PR3000A or PR3400 (64KB I- & d-Caches , d re s s Bus Tag Bus Ap- An, An PR3400 C PU $ /L T i n n . C ache C ontroller -
OCR Scan
P4C214 MIL-STD-883D MIL-STD-883 P4C214- P4C214-13
Abstract: high performance processor speeds of the ¡386 and i486, and the PR3000A/PR3400. Processor , MIPS PR3000A/PR3400, and Intel's 80386 and 80486 processors. It is pin programmable into either a , ° 1° i s s i CACHE RAM CONFIGURATIONS FOR PR3000A AND ¡386/¡486 MIPS PR3000A o r PR3400 -
OCR Scan
P4C214-1

1AM7

Abstract: PR3400 are multiplexed on two separate pins (pins 95 & 97) similar to PR3000A, PR3400 and PR3400L. To use , /termination signal. FjpBusy of FPA is connected internally. Output of PR3400N. A 1-bit bus used to transfer , signal FpCond is connected internally. Output of PR3400N. A 6-bit bus used by the memory interface and , output pins from PR3400N. 2/ 16/93 4 m TQt iBST? OOOEHTE 2 4 2 PaceMips PR3400N , (800) 225-5373 6.0 ORDERING INFORMATION PR3400N- XX X X XXX X Temperature
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OCR Scan
1AM7 160-P

TAG L7

Abstract: fpu coprocessor AMT»«?*) PR3400N CPU/FPA i LATCH } T oatacacm Figure 1.0 PR3400N-Based Multiprocessing System with , , Mplnvalidate are multiplexed on two separate pins (pins 95 & 97) similar to PR3000A, PR3400 and PR3400L. To use , busy stall initiation/termination signal. FpBusy of FPA is connected internally. Output of PR3400N. , PR3400N. lnt(5:0) 1 A 6-bit bus used by the memory interface and coprocessors to signal maskable , timing synchronization with the CPU. 1705 TW 06 Note: CpBusy, CpCond (1) are output pins from PR3400N.
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OCR Scan
TAG L7 fpu coprocessor PR31 mps 1136 TAG 93
Abstract: swap Banks A & B at the output does not occur in PR3000A/PR3400 cache applications. S o t ^ is , operation is not possible in PACEMIPS PR3000A/PR3400 applications, Address Valid to End of WRITE (tA ) and -
OCR Scan
P4C215/P4C216 R3000A P4C215 P4C216 V7/82
Abstract: of 0 A , 0 £ a to swap Banks A & 8 at the output does not occur in PR3000A/PR3400 cache applications -
OCR Scan
SR52B

mip 836

Abstract: SysA034 PR3000A/PR3010A, PR3400, PIMM, and PIPER On-chip 8KBytes of Instruction cache & 8KBytes of Data cache with parity protection Fully binary compatible with PR3000A/PR3010A, PR3400, PIMM, and PIPER Memory
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OCR Scan
mip 836 SysA034 AT324 AV34 R4000MC MIP 411 PR4300SC PR4300MC PR4000MC PR4000SC/MC 447-PIN PR4000X
Abstract: n the in stru ction s used â  User m ode binary c om p atib ility w ith PR3000A/ PR3010A, PR3400 -
OCR Scan
PR4000PC 64-BIT PR4000P 179-P PR4000P-
Abstract: used â  User mode binary c om p atib ility w ith PR3000A/ PR3010A, PR3400, PIMM, and PIPER â -
OCR Scan
Abstract: internally. Output of PR3400L. A 1-bit bus used to transfer conditional branch status from the coprocessors , . Output of PR3400L. lnt(5:0) 1 A 6-bit bus used by the memory interface and coprocessors to , for timing synchronization with the CPU. Note: CpBusy, CpCond (1) are output pins from PR3400L. , PaceMipsâ"¢ PR3400L CPU 32-BIT RISC PROCESSOR WITH FLOATING POINT ACCELERATOR FEATURES , ¿A- DESCRIPTION The PaceMips PR3400L is manufactured using PACE III Technology which is -
OCR Scan

100CPGA

Abstract: 140 83 - - 1-53 DDDlHDfl ObT M Figure 4.1 PaceMips PR3400L - 145-PIn Ceramic , PaceMips PR3400N Designed for systems which have limited available board SUPPORT & EXTENDED CACHES . area, the PR3400N provides the maximum D f t r f n r m a p r p ^ _ ACTTM 2 F ie ld P , in Figures 6 and 7. 1-59 OlTHMTb 0Q01414 3b3 PaceMips PR3400N 2.0 SIGNAL
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OCR Scan
100CPGA A1225A 100PQFP 100VQFP A1240A 132CPGA

PR3000A

Abstract: connected internally. Output of PR3400L. A 6-bit bus used by the memory interface and coprocessors to signal , Note: CpBusy, CpCond (1) are output pins from PR3400L. 1-99 4/1/92 PaceMips PR3400L , PaceMipsTM PR3400L CPU 32-BIT RISC PROCESSOR WITH FLOATING POINT ACCELERATOR X r , -883C, Class B -DESCRIPTION The PaceMips PR3400L , designed for applications requiring maximum balanced performance and minimum board space. The PR3400L with
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OCR Scan