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PR3000A

Catalog Datasheet MFG & Type PDF Document Tags

PR3000A

Abstract: CPGA Now 32-bit FPA Use PR3010A for new designs CQFP Yes D PR3000A' 20,25,33 SG 145 X Now 32-bit CPU For old existing designs only CPGA Yes D PR3000A 20,25,33,40 SG 175 X Now 32-bit CPU CPGA Yes D PR3000A 20,25,28,33 SG 175 X X Now 32-bit CPU CPGA Yes D PR3000A 20,25,33 SF 172 X Now , PR2000A' 16 PGC 145 X Now 32-bit CPU Use PR3000A for new designs CPGA No U PR2010A' 16 QJC 84 X Now , PR3000A for new designs CPGA No u PR30001 20,25,33 QLC 172 X Now 32-bit CPU Use PR3000A for new designs
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PR3000 CPGA 84 pin cpu PR3400 PR2000 PR30101 PR3010 PR301 CPU/FPA/PR3100A PCBM/3400-

PR3020s

Abstract: PR3000A Clock An inverted version of the PR3000A's SysOut signal from the PR3000 processor that synchronizes , device. WbFull The Write Buffer asserts this signal to the PR3000A's WrBusy input whenever it cannot , )] are clocked into the device on the trailing edge of the Clock signal and are taken from the PR3000A's , Clock signal and are taken from the PR3000A's Tag bus. Eachdevice also has separate inputs (Addressl , the device on the leading edge of the Clock signal and are taken from the PR3000A's data bus. In
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PR3020s TMPR3020 PR3020 R2020 CA95112

PR2000

Abstract: MIPS R3000A Endian selection of the PR3000A. Should be programmed identically to the PR3000A BigEndian. Block (words , PR3000A Mode Configuration Table 4.8 summarizes the PR3000A's mode selectable features. All reserved modes , PR2000. PR3000A This allows the PIMM's CPU to operate as a PR3000A. Deassertion causes the CPU to operate , PR3000A CPU · PR3010A FPA · PR3100A Wrtte/Read and Parity Buffer · bus snooper to assist In , Bicameral latched cache RAMs 32-bit RISC Processor PR3000A contains: · thirty-two general 32-bit registers
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MIPS R3000A R2000 mips processor P4C92815 960X1560 PR301OA MIL-STD-883C

PR2000

Abstract: R2000 mips processor is identical to the Little and Big Endian selection of the PR3000A. Should be programmed Identically , Clock Cycles 8 7 6 5 4 3 2 1 PR3000A Mode Configuration Table 4.8 summarizes the PR3000A's mode , to handle stores Identical to the PR2000. PR3000A This allows the PIMM's CPU to operate as a PR3000A. , PERFORMANCE INTEGRATED MIPS MODULE PIMM" FEATURES: Single VLSI muttichip module contains: · PR3000A CPU · , ) is a single VLSI package containing the PR3000A RISC processor, the PR3010A floating point
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ha 1166 x 00D15S1 PR300QA
Abstract: â  32-BIT RISC Processor (PaceMips PR3000A) that contains thirty-two general purpose 32 , of 1.0 clo ck c ycle s per in stru ctio n â  Pin com patible w ith the PR3000A â'¢ 145-pin Ceram , with the PR3000A processor. When used with the PACEWRAP"PR3100A single-chip write, read, and parity , PR3400L provides the maximum performance achievable with the PR3000A RISC microprocessor. It contains both the PR3000A processor and its tightly coupled floating point coprocessor on a single die. 1.3 -
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256KB
Abstract: PaceMipsâ"¢ PR3000A CPU 32-BIT RISC PROCESSOR WITH INTEGRATED MEMORY MANAGEMENT FEATURES I , rate of one instruction per cycle DESCRIPTION The PaceMips PR3000A Processor is an advanced 32 , Technology. The PaceMips PR3000A approaches an execution rate of one instruction per cycle by using a LOAD , for virtual-to-physical memory mapping. The PaceMips PR3000A Processor is manufactured using PACE , environment volume production facility. The PaceMips PR3000A Processor is available in a 160-lead Metal -
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M1L-STD-883C

PR3000A

Abstract: CPGA PERFORMANCE SEMICONDUCTOR 50E D TObES'i? QÜÜ13Ô7 0D7 «P S C 32- and 64-bit RISC MIPS Microprocessors Part Type PR2000A1 PR2010A' PR3000' PR3000' PR3010' PR3010' PR3010' PR3000A' PR3000A PR3000A PR3000A PR3000A PR3000A PR3010A PR3010A PR3010A PR3010A PR3010A PR3010A PR3020 PR3100P , -bit 32-bit 32-bit 32-bit 32-bit 32-bit 32-bit CPU CPU CPU CPU CPU CPU FPA FPA FPA FPA FPA FPA Use PR3000A for new designs UsePR3010A for new designs Use PR3000A for new designs Use PR3000A for new designs Use
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PR3400N PR4000P2 PR4000S2 PR4000M2 3400N PR3400-

IRD2

Abstract: GND18 ~? m * g i m -»o - PR3000A172 Hnout 1-9 4/ 1/92 . PacaMlps PR3000A Figure 5.2 , PaceMipsTM PR3000A CPU 32-BIT RISC PROCESSOR WITH INTEGRATED MEMORY MANAGEMENT 7$ FEATURES 32 , PaceMips PR3000A Processor is an advanced 32-bit RISC processor designed for very high performance , highest performance possible from the PACE Technology. The PaceMips PR3000A approaches an execution rate , PR3000A Processor is manufactured using PACE III Technology which is Performance Advanced CMOS Engineered
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IRD2 GND18 tag 136 m2

MPS 2112

Abstract: dd1555 and Big Endian selection of the PR3000A. Should be programmed identically to the PR3000A BigEndian , 2 111 1 PR3000A Mode Configuration Table 4.8 summarizes the PR3000A's mode selectable features , operate as a PR3000A. Deassertion causes the CPU to operate as an R2000. R3000Amust be asserted forthe , contains: â'¢ PR3000A CPU â'¢ PR3010A FPA â'¢ PR3100A Write/Read and Parity Buffer â'¢ Four P4C92815 Bicameral latched cache RAMs â  32-bit RISC Processor PR3000A contains: â'¢ thirty-two general 32
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MPS 2112 dd1555 R3000A PR31 MIPS R2000 td70c 00G1574
Abstract: ) operation. An inverted version of the PR3000A's SysOut signal from the PR3000 processor that , particular Write Buffer. The Write Buffer asserts this signal to the PR3000A's WrBusy input whenever it , )] are clocked into the device on the trailing edge of the Clock signal and are taken from the PR3000A's , Clock signal and are taken from the PR3000A's Tag bus. Each Write Buffer device has nine data inputs , PR3000A's data bus. In Figure 1.2, each device captures eight bits of data and one bit of parity. Also -
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1AM7

Abstract: PR3400 in a monolithic VLSI package 32-BIT RISC Processor (PaceMips PR3000A) that contains thiity-two , with the PR3000A processor. When used with the PACEWRAP,`PR3100P single-chip write, read, and parity , board area, the PR3400N provides the maximum performance achievable with the PR3000A RISC microprocessor. It contains both the PR3000A processor and its tightly coupled floating point coprocessor on a single die. 1.2 CPU & FPA INTERCONNECTION The PR3400N contains the PR3000A and PR3010A integrated on a single
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1AM7 160-P PR3400N-

TAG L7

Abstract: fpu coprocessor   CPU and FPA in a monolithic VLSI package â  32-BIT RISC Processor (PaceMips PR3000A) that contains , software compatible with the PR3000A processor. When used with the PACEWRAP,"PR31 OOP single-chip write , available board area, the PR3400N provides the maximum performance achievable with the PR3000A RISC microprocessor. It contains both the PR3000A processor and its tightly coupled floating point coprocessor on a single die. 1.2 CPU & FPA INTERCONNECTION The PR3400N contains the PR3000A and PR3010A integrated on a
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TAG L7 fpu coprocessor mps 1136 TAG 93
Abstract: Ram Configurations for PR3000A and i386/i486 I- Cache Control* P4C218(4 Units) Address Bus PR3000A or PR3400 CPU /I Tag Bus A -ft- - f t | Data Bus D- Cache Control* P4C218(4 UnHs) Figure 4 IX86 64KByte Cache Figure 3 MIPS PR3000A or PR3400 (64KByte i- & d- Caches , speeds of the ¡386 and i486, and the PR3000A/PR3400. Processor Access Time Frequency Output -
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R4000S 512KB R3000 PP52C GR52B PR3000A/PR3400

PR3000A

Abstract: - FEATURES CPU and FPA in a monolithic VLSI package 32-BIT RISC Processor (PaceMips PR3000A) that contains , execution rate of 1.0 clock cycles per instruction Pin compatible with the PR3000A 145-pin Ceramic Pin Grid , its additional capability remains software compatible with the PR3000A processor. When used with the , provides the maximum performance achievable with the PR3000A RISC microprocessor. It contains both the PR3000A processor and its tightly coupled floating point coprocessor on a single die. By reducing printed
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Abstract: - FEATURES â  CPU and FPA in a monolithic VLSI package â  32-BIT RISC Processor (PaceMips PR3000A) that , limited available board area, the PR3400 provides the maximum performance achievable with the PR3000A RISC microprocessor. It contains both the PR3000A processor and its tightly coupled floating point , critical high-speed signals which service the cache, this packaging provides the PR3000A and PR301OA an , SRAM parameters. 1.2 CPU & FPA INTERCONNECTION The PR3400 contains the PR3000A and PR3010A -
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Abstract: Configurations for PR3000A and Ì386/Ì486 I- C a c h e C o ntrol* P4C218{4 U nits) Tag B us PR3400 CPU $ D- C a c h e C o n tro l* P4C218(4 Units) Figure 3 MIPS PR3000A or PR3400 (64KByte i- & d , i486, and the PR3000A/PR3400. Processor ¡386 ¡486 Frequency 40 MHz 33 MHz 25 MHz 50 MHz 33 MHz 33 MHz -
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P4C219 128KB P4C218-
Abstract: MIPS PR3000A/PR3400, and Intel's 80386 and 80486 processors. It is pin programmable into either a , ° 1° i s s i CACHE RAM CONFIGURATIONS FOR PR3000A AND ¡386/¡486 MIPS PR3000A o r PR3400 , high performance processor speeds of the ¡386 and i486, and the PR3000A/PR3400. Processor -
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P4C214 MIL-STD-883D MIL-STD-883 P4C214- P4C214-1
Abstract: ideally suited for cache RAM applications with the MIPS PR3000A/PR3400, and Intel's 80386 and 80486 , O CACHE RAM CONFIGURATIONS FOR PR3000A AND ¡386/¡486 MIPS PR3000A or PR3400 (64KB I- & d-Caches , performance processor speeds of the ¡386 and ¡486, and the PR3000A/PR3400. Processor ¡386 i486 Frequency 40 -
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P4C214-13

117 AJG

Abstract: MIPS R2000 of the CPU is identical to the PR3000A. The 32-bit RISC CPU has a five-stage instruction pipeline, 32 , those supported by the PR3000A. The architecture of the FPA is identical to the PR301 OA. The FPA , contains the following: - CPU (PR3000A based) - FPA (PR3010A based) - Write/Read Buffer - Instruction and Data Caches - 32-bit Counters/Timers â  Instruction set compatible with the PR3000A RISC CPU , protection. 2.0 PIPER OPERATION The execution engine of the PIPER is based on the PR3000A CPU and PR3010A
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117 AJG performance piper mips risc architecture gerry kane MIPS FPA 256KD burndy

PR3400

Abstract: fpa g12 in a monolithic VLSI package 32-BIT RISC Processor (PaceMlps PR3000A) that contains thirty-two , board area, the PR3400 provides the m axim um perform ance achievable w ith the PR3000A RISC m icroprocessor. It contains both the PR3000A processor and its tightly coupled floating point coprocessor on a , high-speed signals w hich service the cache, this packaging provides the PR3000A and PR301OA an environm ent , operation of the PR3400 is identical to the operation of the PR3000A CPU and PR3010A FPU (connected as
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fpa g12 IL-STD-883C
Abstract: Available in 160-pin PQFP package Full PR3000A block refill and streaming support X? DESCRIPTION , APPLICATION PR3000A CPU AdrLo & Tag Consol Signals Data [031:00) Ite e C m fy ene* PR 3100A , PR3000A with the correct timing to perform a block transfer of the number of words configured by IBIkSize , buffer. If CpCondO is configured as an input, it will be sampled by both the PR31 OOAandthe PR3000A , AocTyp(2:0) LATCH ICIk DCIk U LATCH PR3000A Gr3 ÃRd DATA CACHE INSTRUCTION -
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R2000A R2000A/ R2000A/R3000A
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