V292PBC - Datasheet Archive

 

PCI Bus New interface chip makes is easy! 1. Objective This application note describes a simple way to interface the PPC403Gx

 

Interface the Power PC 403Gx to the PCI Bus New interface chip makes is easy! 1. Objective This application note describes a simple way to interface the PPC403Gx processor to the PCI bus utilizing the V292PBC V292PBC PCI host bridge from V3 Semiconductor. 2. Overview Although the V292PBC V292PBC doesn't interface guilelessly to the PPC403Gx processors, the new B2 revision of the device greatly simplifies the interface when compared to other solutions. Earlier versions of the V292PBC V292PBC required the use of a prohibitively large number of external components. This is due to the requirement of the PPC403Gx that data be returned to the processor the cycle after the data "ready" indication. A new mode bit in the B2 revision of the V292PBC V292PBC causes data to be returned in the manner desired by the PPC403Gx. Without this feature, it is necessary to latch the entire data bus. 3. Interconnection Interconnection of the PPC403Gx to the V292PBC V292PBC uses only minimal glue logic as indicated in Figure 1. Figure 1: Interconnection of the V292PBC V292PBC with the PPC403Gx Processor MUX V292PBC V292PBC DRAM PPC403Gx DQ0:31 R/W# LA23:2 R/W# A8:29 AMuxCAS ID31:0 D0:31 RASn LBWE3:0 WBE0:3 PCI Bus BREQ BGNT CAS0:3 HoldReq DRAMOE HoldAck DRAMWE A0:10 RAS CAS0:3 WE0:3 OE LREQ BURST RDY PLD XREQ XACK XSize0:1 CSn READY Copyright © 1996, V3 Semiconductor Inc. V292PBC V292PBC to FIFO Interface App Note Rev 0.9x (Preliminary) 1-1 Interconnection Note that the V292PBC V292PBC bus ordering convention is the reverse of the PPC403Gx. That is, local data bit 0 (ID0) on the V292PBC V292PBC is equivalent to D31 on the PPC403Gx The V292PBC V292PBC to PPC403Gx interface must accomplish two main functions: · Allow the PPC403Gx (as a master) to access the V292PBC V292PBC (as a slave) · Allow the V292PBC V292PBC to become the local bus master and access DRAM controlled by the PPC403Gx 3.1 V292PBC V292PBC LOCAL BUS SLAVE INTERFACE Access of the V292PBC V292PBC by the processor is accomplished by using one of the chip select outputs of the processor (CSn#) to cause the LREQ# signal into the V292PBC V292PBC to be asserted. When LREQ# is sampled asserted by the V292PBC V292PBC, it will examine the address of the request to determine what address space the access is directed at (PCI access aperture 0, PCI access aperture 1, or access to the internal registers. Later, the V292PBC V292PBC will assert RDY# to indicate that the data is ready. This gets inverted into READY back to the PP403Gx. The slave interface doesn't support bursting because the PPC403Gx lacks an end of burst indicator. For optimal performance, bursting can be accomplished using the DMA controller which generates master cycles which can be bursted. 3.2 V292PBC V292PBC LOCAL BUS MASTER INTERFACE The local bus master interface is a little more complicated than the slave interface since more handshaking is required by the PPC403Gx to allow an alternate bus master to take over. 3-2 V292PBC V292PBC to FIFO Interface App Note Rev 0.9x (Preliminary) Copyright © 1996, V3 Semiconductor Inc. Performance Optimization 3.3 PLD EQUATIONS /* Master Interface */ holdreq = # b dram_dis = # xsize1 = xreq = # qlreq.d = rdy = breq holdreq & !(xack & dram_dis) & xsize gnt = holdack; !dram_dis & xsize1 & !burst & xack dram_dis & !xack; burst; lreq & !qlreq burst; lreq & !(xack and !burst) xack; 1; /* Slave Interface */ ready = rdy; lreq lreq.oe = csn; = !holdack; burst = 'h'0; burst.oe = !holdack; lbwe[3:0]= wbe[0:3]; lbwe[3:0].oe = ! holdack; 4. Performance Optimization It is important to understand the issues that determine PCI performance in a given system. The V292PBC V292PBC has been designed to maximize PCI performance with a number of unique and powerful features. These issues are discussed in the following sub-sections. 4.1 LONG BURSTS There is a relationship between burst length and bus utilization. High utilization is only achievable by supporting long bursts. Although the PPC403Gx itself doesn't support burst sizes larger than 4 words the V292PBC V292PBC as a local bus master can perform long bursts of 1KB. Also, the burst size of the PCI transactions can be controlled independently of the local bus (see the FIFO_CFG register in the V292PBC V292PBC user manual). 4.2 ELIMINATE THE WEAK LINK It is vital that all links in the chain of data flow be capable of long, zero wait bursts and not only the PCI bridge. Other parts of the system such as the PCI system memory may not be Copyright © 1996, V3 Semiconductor Inc. V292PBC V292PBC to FIFO Interface App Note Rev 0.9x (Preliminary) 4-3 Conclusion capable of sustaining zero wait long bursts and can become the bottleneck of performance. 4.3 ELIMINATE WAIT STATES Bursting alone isn't enough! It is also important to burst without wait states. A single wait state during bursts results in a loss of 1/2 of the available bus bandwidth! The zero wait state DRAM access modes of the PPC403Gx should be utilized whenever possible. 4.4 "PUSH" DON'T "PULL" The best PCI performance is obtained when data is "pushed" from the source to the destination. This involves performing write cycles and avoiding read cycles. Pushing allows data to be posted into the write posting FIFO of the bridge device. In the case of the PBC series bridges, 256 bytes can be posted in each direction (PCI-local, local-PCI) which is significantly larger than the capabilities of any other bridge device including PCI-to-PCI bridges made by DEC and IBM. Pushing is a faster approach because it avoids the latency of reading. Read latency in cumulative. In other words the total latency for the first data of a burst read is the sum of all read latencies in the path of data flow. However, writes can immediately be posted into the first element in the data flow path. The master that initiated the write will be free to do other operations while the previously posted data continues to propagate through the system to its final destination. 4.5 READ PREFETCH When a pushing data flow is not possible, then read prefetching should be used. Although most PCI bridges provide prefetch capabilities, few of them have the multiple prefetch capabilities that the PBC devices employ. With dual prefetch buffers in each direction (a total of 4) it isn't necessary to invalidate the prefetched data nearly as often. The PBC devices can keep 4 simultaneous sequential data streams supplied without scraping any data! This is particularly useful when multiple PCI masters will want to move data through the bridge. 5. Conclusion Unique features of the V292PBC V292PBC provide a low glue interface to the PPC403Gx which eliminate the need for external data latches. This, in combination with the large FIFO capacity and long bursting capabilities of the V292PBC V292PBC yield a simple yet high performance PPC403Gx PCI interfacing solution. 6. For More Information: Other complementing V292PBC V292PBC documents include: 5-4 V292PBC V292PBC to FIFO Interface App Note Rev 0.9x (Preliminary) Copyright © 1996, V3 Semiconductor Inc. For More Information: · PBC User's Manual (this document) · V292PBC V292PBC Data Sheet To obtain the most up-to-date information on this product, please contact our web site at: www.vcubed.com Or contact V3 Semiconductor at: 1.800.488.8410 (US and Canada) 1.408.988.1050 (Outside North America) E-mail: v3help@vcubed.com Copyright © 1996, V3 Semiconductor Inc. V292PBC V292PBC to FIFO Interface App Note Rev 0.9x (Preliminary) 6-5 For More Information: 6-6 V292PBC V292PBC to FIFO Interface App Note Rev 0.9x (Preliminary) Copyright © 1996, V3 Semiconductor Inc.