PM8385 PMC-2031142 PMC-2031860 PM835 PM837 PM838 RM7000 PM8368 TX100/ RX100/ - Datasheet Archive

 

Released PM8385 QuadPHYÒ RT 4-Port GE/FC Retimer Product Overview Released Issue No. 1: November, 2003 Proprietary and

 

QuadPHYÒ RT ASSP Standard Product Overview Released PM8385 PM8385 QuadPHYÒ RT 4-Port GE/FC Retimer Product Overview Released Issue No. 1: November, 2003 Proprietary and Confidential to PMC-Sierra, Inc. Document No.: PMC-2031142 PMC-2031142, Issue 1 1 QuadPHYÒ RT ASSP Standard Product Overview Released Legal Information Copyright Copyright 2003 PMC-Sierra, Inc. All rights reserved. The information in this document is proprietary and confidential to PMC-Sierra, Inc., and for its customers' internal use. In any event, no part of this document may be reproduced or redistributed in any form without the express written consent of PMC-Sierra, Inc. PMC-2031142 PMC-2031142 (r1) Disclaimer None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. Trademarks PMC-Sierra is a trademark of PMC-Sierra, Inc. Other product and company names mentioned herein may be the trademarks of their respective owners. Patents The technology discussed in this document may be protected by one or more patent grants. Proprietary and Confidential to PMC-Sierra, Inc. Document No.: PMC-2031142 PMC-2031142, Issue 1 2 QuadPHYÒ RT ASSP Standard Product Overview Released Contacting PMC-Sierra PMC-Sierra 8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: +1 (604) 415-6000 Fax: +1 (604) 415-6200 Document Information: document@pmc-sierra.com Corporate Information: info@pmc-sierra.com Technical Support: apps@pmc-sierra.com Web Site: http://www.pmc-sierra.com Proprietary and Confidential to PMC-Sierra, Inc. Document No.: PMC-2031142 PMC-2031142, Issue 1 3 QuadPHYÒ RT ASSP Standard Product Overview Released Revision History Issue No. Issue Date Details of Change 1 November 2003 Initial Release Proprietary and Confidential to PMC-Sierra, Inc. Document No.: PMC-2031142 PMC-2031142, Issue 1 4 QuadPHYÒ RT ASSP Standard Product Overview Released Table of Contents Legal Information. 2 Copyright. 2 Disclaimer . 2 Trademarks . 2 Patents 2 Contacting PMC-Sierra. 3 Revision History. 4 Table of Contents. 5 List of Figures . 6 List of Tables. 6 Preface 1 . 7 Features . 8 High Speed Interface Features . 8 Test and Control Features. 8 Packaging . 8 2 Applications. 10 3 Operational Description . 13 4 Block Diagram. 14 5 Pin Description . 15 6 Functional Description . 21 6.1 6.2 Receive Channel for SERDES Reclocker. 22 6.3 Receive Retimer and Monitor. 24 6.4 5 x 5 Cross connect . 26 6.5 TX Control . 27 6.6 Transmit Channel for SERDES / Reclocker. 27 6.7 Clock Synthesizer. 28 6.8 Management Interface . 29 6.9 7 Mode Configuration . 22 Backplane Test/Debug Features . 29 Power Information. 30 7.1 7.2 8 Power Requirements. 30 Power Supply Filtering and Decoupling . 31 Mechanical Information. 33 Proprietary and Confidential to PMC-Sierra, Inc. Document No.: PMC-2031142 PMC-2031142, Issue 1 5 QuadPHYÒ RT ASSP Standard Product Overview Released List of Figures Figure 1 QuadPHY RT as Dual Bi-directional Gigabit Ethernet Retimer . 11 Figure 2 QuadPHY RT as Dual Bi-directional Fiber Channel Retimer. 11 Figure 3 Redundant Gigabit Ethernet or Fibre Channel Architectures . 12 Figure 4 Broadcast or Multicast for Distributed Switch Fabric Architectures . 12 Figure 5 Block Diagram . 14 Figure 6 QuadPHY RT in Repeater Mode. 21 Figure 7 QuadPHY RT in Retimer Mode. 21 Figure 8 SERDES Reclocker Block Diagram . 23 Figure 9 Rx Retimer and Monitor Block Diagram. 24 Figure 10 QuadPHY RT Redundancy Configuration Example . 27 Figure 11 QuadPHY RT with Cross-Connect as 1:3 Mux . 27 Figure 12 Recommended Power Supply Decoupling . 32 Figure 13 Mechanical Drawing 196 Pin Chip Array BGA. 33 List of Tables Table 1 Gigabit Ethernet and Fibre Channel Port Pin Descriptions . 15 Table 2 Port Control and Status Pins ­ 3.3 V I/O. 15 Table 3 Management Interface Pin Descriptions ­ 3.3 V I/O . 18 Table 4 JTAG Test Pin Descriptions ­ 3.3V I/O . 19 Table 5 Clock, Control and Status Pin Descriptions ­ 3.3 V I/O excluding REFCLK . 19 Table 6 Supply and Reference Pin Descriptions. 20 Table 7 QuadPHY RT Modes of Operation. 21 Table 8 Mode Configuration through Control Pins . 22 Table 9 Programmable Receive Equalization Settings . 24 Table 10 Monitored Receive Link Error Conditions. 26 Table 11 Transmit Amplitude Swing Control . 28 Table 12 Pre-emphasis . 28 Table 13 REFCLK and PLL Clock Combinations. 28 Table 14 Pattern Generator Test Patterns . 29 Table 15 Typical Power requirements. 30 Proprietary and Confidential to PMC-Sierra, Inc. Document No.: PMC-2031142 PMC-2031142, Issue 1 6 QuadPHYÒ RT ASSP Standard Product Overview Released Preface This Product Overview describes the features and applications of PMC-Sierra's PM8385 PM8385 QuadPHYÒ RT. The Product Overview is essential reading for system architects who are evaluating the QuadPHY RT and for designers who will use the QuadPHY RT. In order to understand the information in this document, the reader should have a strong working understanding of digital design, serializer/deserializers (SERDES), high-speed serial design, Gigabit Ethernet and Fibre Channel. Related Documents In addition to this Product Overview, please consult the QuadPHY RT datasheet, PMC-2031860 PMC-2031860 for a more comprehensive description and detailed device operation. Proprietary and Confidential to PMC-Sierra, Inc. Document No.: PMC-2031142 PMC-2031142, Issue 1 7 QuadPHYÒ RT ASSP Standard Product Overview Released 1 Features · The PM8385 PM8385 QuadPHY RT is a 4-channel uni-directional or dual bi-directional repeater /retimer for backplane and line card links operating from 1.0625Gbit/s to 2.125Gbit/s · Supports repeater or retimer applications for IEEE 802.3 Gigabit Ethernet links at 1.25 Gbit/s and Fibre Channel Physical Interface (FC-PI) links at 1.0625 or 2.125 Gbit/s. · Provides non-blocking cross-bar for protection switching, broadcasting and multi-cast · High-speed Inputs and Outputs have independent, selectable terminations on a perchannel basis that provide ability to convert between mediums with different impedances (i.e. 50-ohm PCB trace to 75-ohm cable). · Each port supports FC 1G or 2G-rate detection/auto-selection. · Contains a per-link, 16 word receive FIFO for clock rate difference compensation up to ± 100 ppm from the nominal rate, by inserting and deleting idle characters or ordered sets. · Supports single-ended or differential 125 MHz reference clock REFCLK for Gigabit Ethernet or 106.25MHz reference clock for Fibre Channel applications. High Speed Interface Features · Requires no external components to interface the high-speed signals to optics, twinnax (1000 BASE-CX), or serial back planes with use of the internal coupling capacitors. This results in minimum board footprint and greatly improved signal integrity. · High-speed outputs with selectable output amplitude and programmable pre-emphasis per port to counteract dielectric losses and allow maximum reach on printed circuit boards. · Selectable receive input equalization on per-channel basis for improved signal integrity · Selectable receive input termination or source output impedance (100/150 W differential) on per-channel basis. Test and Control Features · Standalone repeater or retimer operation via pin-strap configuration · Supports optional 2-pin serial management interface using selectable Two-Wire Interface (TWI) or MDC/MDIO protocol for configuration and diagnostic access. · Digital Loss of Link (DLOLB) detected outputs can be programmed to indicate multiple error parameters or conditions for monitoring individual or multiple links. An Interrupt output is provided to flag changes in DLOLB error conditions. · Supports internal serial loop back modes for each port for testing and debugging. · Standard 5 signal IEEE 1149.1 JTAG test port for digital pin (only) boundary scan. Packaging · 0.18 m CMOS, 1.8 V and 3.3 V Supply. · Extended temperature range of ­40 °C to +85 °C for challenging system environments. Proprietary and Confidential to PMC-Sierra, Inc. Document No.: PMC-2031142 PMC-2031142, Issue 1 8 QuadPHYÒ RT ASSP Standard Product Overview Released · Small 15 mm x 15 mm footprint, 196-pin BGA with 1.0 mm ball pitch. · Ultra-low operating power of 1.3 W typical with all 4 channels active at 2.125 G. Proprietary and Confidential to PMC-Sierra, Inc. Document No.: PMC-2031142 PMC-2031142, Issue 1 9 QuadPHYÒ RT ASSP Standard Product Overview Released 2 Applications The QuadPHY RT device addresses repeater, retiming and signal conditioning for gigabit serial link extension and ensuring standards compliance and robust system operation in a variety of challenging line card and backplane system environments. Specifically, the QuadPHY RT meets and exceeds IEEE 802.3 Gigabit Ethernet and ANSI T11.2 for 1 Gigabit and 2 Gigabit Fibre channel standards. Typically the QuadPHY RT is used as a backplane driver for link extension or as a companion for higher-layer devices such as ASICs, FPGAs and switch standard products that incorporate serial I/O. In addition to providing extensive signal integrity features to improve high-speed serial performance, the QuadPHY RT has the ability to perform error monitoring on each link. The device can be used in the following applications: · High-speed backplane driver operating from 1.0625Gbit/s to 2.125Gbit/s · Distributed switch fabrics or protection switches via data bi-cast, multi-cast or broadcast to fabric elements · Allows fully redundant systems, protection switching and simplifies distributed switch fabric applications via a non-blocking cross-bar for broadcasting and multi-casting · Enterprise Ethernet or Fibre Channel Switches. · Fibre Channel Retimer · Gigabit Ethernet Retimer including 1000 BASE-CX · Industrial Control and Processing Systems Retimers Provide Optimal Solution for the Hostile Backplane Environment The backplane is a hostile environment for multi-gigabit signals that presents many design challenges to system designers. At the same time, backplane design is a critical component in determining system reliability and robust operation. Backplane design issues include a host of challenges that must be considered including system link distance, link speed, bit error rate (BER) and jitter, line card hot plug capability, connectors, vias, and ESD protection. Subtle issues such as latch-up, common mode balance, cross talk and return loss can impact reliability and system data integrity over a wide variety of operating temperatures and environments. The QuadPHY RT provides a small footprint, and low power solution to mitigate these issues, ensure standards compliance and minimize back end system qualification. More importantly, the inclusion of retimer backplane drivers can reduce the chances of in-field system failures due to system signal integrity issues that can lead to expensive and lengthy system debug, re-design and qualification. Proprietary and Confidential to PMC-Sierra, Inc. Document No.: PMC-2031142 PMC-2031142, Issue 1 10 QuadPHYÒ RT ASSP Standard Product Overview Released The QuadPHY RT can operate as a 4 port uni-directional retimer, or a 2 port bi-directional retimer depending on system requirements. Figure 1shows the QuadPHY RT can as a bidirectional 2 port Gigabit Ethernet retimer. Other Gigabit Ethernet applications include stacking port applications (ie 1000 BASE-CX) where the QuadPHY RT drives cables between boxes. Figure 2 shows how the QuadPHY RT is used in Fibre Channel applications to convert the 150 W differential impedance from the next rack's cable to match the 100 W differential impedance connections to the Host Bus Adapter (HBA) and PBC 18x2G. Figure 1 QuadPHY RT as Dual Bi-directional Gigabit Ethernet Retimer SFP Socket Copper SFP Copper SFP SFP Socket OctalPHY® 1G SFP Socket MAC/Port Controller ASIC PM835 PM835 2 SFP Socket OctalPHY® 1G PM837 PM837 3 Switch Fabric GMII/TBI Interface ½" Optical SFP SFP Socket Optical SFP SFP Socket MAC/Port Controller ASIC Copper SFP SFP Socket SFP Socket Copper SFP Copper SFP SFP Socket Serial Backplane Links up to 48" + 2 connectors Serial Links Exceed Jitter Specifications HexPHY® 1GR PM837 PM837 3 ½" HexPHY® 1GR PM837 PM837 3 Connector SFP Socket Connector Serial Backplane Links up to 48" + 2 connectors QuadPHY® RT QuadPHY® PM838 PM838 5 RT PM838 PM838 5 Switch ASIC w/ Integrated SERDES Connector Copper SFP SFP Socket Flexible Gigabit Ethernet Line Card Serial Links Exceed Jitter Specifications Backplane Optical SFP Connector Optical SFP QuadPHY® RT QuadPHY® PM838 PM838 5 RT PM838 PM838 5 5 bit RGMII/RTBI Interface SFP Socket Figure 2 QuadPHY RT as Dual Bi-directional Fiber Channel Retimer Dual Bi-directional Retimer Front Panel Card Edge Backplane Card Edge Memory HBA Optical Interface 150 ohm Cable to Next Rack FC MAC Transceiver PM8385 PM8385 QuadPHY RT Proprietary and Confidential to PMC-Sierra, Inc. Document No.: PMC-2031142 PMC-2031142, Issue 1 Disk 0 Disk 1 Disk 2 Disk 3 FC MAC RM7000 RM7000 MIPS Processor PM8368 PM8368 PBC18x2G · · · Disk 13 Disk 14 Disk 15 11 QuadPHYÒ RT ASSP Standard Product Overview Released Redundant System Architectures Supported By the QuadPHY RT The QuadPHY RT supports redundant system architectures by allowing a single input to be broadcast to multiple outputs. The ingress data stream is broadcast to both the working and protection ports while the egress uses the management interface to select whether to source data from the working or protection port. Figure 3 shows a redundant line card application that incorporates working and protection switch fabrics. Figure 4 shows a distributed switch fabric architecture where the QuadPHY RT is used to simplify the interconnect via data broadcast or multicast cross-connect capability. Figure 3 Redundant Gigabit Ethernet or Fibre Channel Architectures Redundant Gigabit Ethernet or Fibre Channel Line Card Optical Interface Optical Interface Working Backplane Link Transceiver PM8385 PM8385 QuadPHY RT ASIC or FPGA PM8385 PM8385 QuadPHY RT Protection Backplane Link Transceiver Figure 4 Broadcast or Multicast for Distributed Switch Fabric Architectures Gigabit Ethernet or Fibre Channel Line Card with Distributed Switch Fabric Architecture Optical Interface Optical Interface Distributed Fabric Element 1 Transceiver PM8385 PM8385 QuadPHY RT ASIC or FPGA PM8385 PM8385 QuadPHY PM8385 PM8385 RT QuadPHY RT Distributed Fabric Element 2 Transceiver Proprietary and Confidential to PMC-Sierra, Inc. Document No.: PMC-2031142 PMC-2031142, Issue 1 Distributed Fabric Element n 12 QuadPHYÒ RT ASSP Standard Product Overview Released 3 Operational Description The QuadPHY RT is a low power, four-channel uni-directional retimer or 2 channel bidirectional repeater or retimer suitable for applications such as high-speed serial backplanes for Gigabit Ethernet and Fibre Channel. The QuadPHY RT significantly improves system jitter to ensure system standards compliance or to extend link distances. Extensive signal integrity features, low latency, a small footprint and low power enable best practice backplane and system design for robust and standards compliant operation in a wide variety of system environments. The internal non-blocking cross-bar provides flexibility for loopbacks or data replication for the bi-cast, multi-cast or broadcast of data to working and protection fabrics, or distributed fabric elements. The QuadPHY RT provides bi-directional clock and data recovery on all ports at 1.25Gbit/s for Gigabit Etherent per IEEE 802.3-2002 or 1.0625Gbit/s or 2.125Gbit/s Fibre Channel Physical Interface (FC-PI) data streams. The PM8385 PM8385 supports rate detection and auto-selection for 1G and 2G Fibre Channel applications. As a repeater, the QuadPHY RT uses the recovered clock as the timing reference for the egress link. As a retimer, the QuadPHY RT uses the local clock for retiming as well as an elastic FIFO for rate adaptation. The PM8385 PM8385 includes extensive features to support a wide variety of applications that require high quality and standards compliant signal integrity. The PM8385 PM8385 integrates coupling capacitors and terminating resistors to minimize board footprint and improve singal integrity. Receive input and source output termination are selectable for 100W or 150W differential. In the receive direction, the PM8385 PM8385 receives serial differential data, recovers the data and converts the data back to 8-bit or 10-bit data. The high-speed differential receiver on each link has internal capacitor coupling and parallel termination to eliminate the need for external passive devices and their impact on signal integrity. Programmable receive equalization provides robust data recovery of highly degraded input signals. After recovery, the data can be repeated using a recovered clock (repeater) or retimed to the local reference clock (retimer). An elastic FIFO provides rate adaptation and can accommodate clock differences of 200ppm. Optionally, the receive data may be multi-cast or broadcast to any output ports for redundant or distributed fabric system architectures when configured in a Retimer Mode. In the transmit direction, the PM8385 PM8385 transmitter can interface directly to optics, 1000 BASECX (twinax) or serial backplanes. Selectable pre-emphasis per port is supported to counteract dielectric losses and allow maximum reach on printed circuit boards and cable. Each output has selectable output swing and includes the source termination so that external resistors are not required. External capacitors can optionally be used on transmit and receive interfaces. In redundant system applications, the data source can be selected via the managemnet interface from either working or protection port. The QuadPHY RT can be operated either standalone (via control pins) or through an optional serial management interface. The serial management interface supports both the standard TwoWire Interface (TWI) and MDIO/MDC protocols. A fully maskable interrupt output pin is provided to signal the host device on events such as link error events. The QuadPHY RT provides optional extensive link monitoring to support backplane testing and in-system diagnostics. Proprietary and Confidential to PMC-Sierra, Inc. Document No.: PMC-2031142 PMC-2031142, Issue 1 13 QuadPHYÒ RT ASSP Standard Product Overview Released 4 Block Diagram Figure 5 Block Diagram SERDES/ Reclocker 10 Tx Control 2 10 2 10 SERDES/ Reclocker 10 2 RDIP[2] RDIN[2] TDOP[2] TDON[2] RDIP[3] RDIN[3] TDOP[3] TDON[3] DLOLB PORT_DLOLB[3:0] PORT_2G_RATE[3:0] INTRB PREEMPH[1:0] RECEQUALIZE[1:0] FC_GE_RET_SEL Control Block AUTO_RATE_SEL EXTCAP Proprietary and Confidential to PMC-Sierra, Inc. Document No.: PMC-2031142 PMC-2031142, Issue 1 Two Wire Interface TWISEL Impedance Control REFCLK_N REFCLK_S REFCLK_P RPRES SERDES/ Reclocker Pattern Generator/ Comparator CDRU CLK_SEL 2 10 Rx Retimer/ Monitor Tx Control JTAG TCK TMS TDI TDO TRSTB Cross-bar Rx Retimer/ Monitor 10 2 Tx Control DLOLBYP_MASK RET_MODE HALF_RATE 2 Tx Control RESETB TDOP[0] TDON[0] 10 2 MDC_SCL MDIO_SDA RDIP[0] RDIN[0] 2 10 Rx Retimer/ Monitor DVPRTAD[4:0] TDOP[1] TDON1] SERDES/ Reclocker Rx Retimer/ Monitor TX100/ TX100/ 150[3:0] RX100/ RX100/ 150[3:0] RDIP[1] RDIN[1] 14 QuadPHYÒ RT ASSP Standard Product Overview Released 5 Pin Description Table 1 Gigabit Ethernet and Fibre Channel Port Pin Descriptions Pin Name Type Function RDIP[3] RDIN[3] Input Receive Differential Input Positive/Negative (RDIP[3:0], RDIN[3:0]) RDIP[2] RDIN[2] RDIP and RDIN are the high-speed differential inputs used for 1.25Gbit/s Gigabit Ethernet or 1.0625 Gbit/s / 2.125 Gbit/s Fibre Channel inputs. Each input pair is internally AC coupled and terminated with a selectable 100 or 150 W termination. RDIP[1] RDIN[1] These inputs are ignored during Serial Loopback. Do not use pullup/pull-down resistors on the high-speed differential inputs. These inputs can be left unconnected when this channel is disabled. RDIP[0] RDIN[0] TDOP[3] TDON[3] Output TDOP[2] TDON[2] TDOP[1] TDON[1] TDOP[0] TDON[0] Transmit Differential Output Positive/Negative (TDOP[3:0], TDON[3:0]) TDOP and TDON are the high-speed outputs used for the 1.25Gbit/s Gigabit Ethernet or 1.0625 Gbit/s / 2.125 Gbit/s Fibre Channel outputs and are internally terminated with a selectable 100 or 150 W differential termination. These outputs are pulled high through a terminating resistor when disabled via management register control. Table 2 Port Control and Status Pins ­ 3.3 V I/O Pin Name Type Function DLOLBYP_MASK Input Performance Monitor Enable When DLOLBYP_MASK is set to logic 0, Performance Monitoring is enabled. Each receive input can be fully monitored for loss of link, link errors, and link level violations. When DLOLBYP_MASK is set to logic 1 performance monitoring is disabled. Performance monitoring is only supported in Retimer Modes (not supported in Repeater Modes).This input has an internal 50 KW pull-up resistor. EXTCAP Input External Capacitor Select This pin selects the use of external capacitors for all highspeed input ports on power-up when set to logic 1. When set to logic 0, this pin selects the use of the internal coupling capacitors for all high-speed input ports on power-up. After power-up, the use of external capacitors can be programmed in the registers on a per port basis. High-speed input ports are not DC coupled internally. This input has an internal 50 KW pull-down resistor. Proprietary and Confidential to PMC-Sierra, Inc. Document No.: PMC-2031142 PMC-2031142, Issue 1 15 QuadPHYÒ RT ASSP Standard Product Overview Released Pin Name Type Function PREEMPH[1] PREEMPH[0] Input Pre-emphasis Select The PREEMPH pins select the level of pre-emphasis used on the serial transmit outputs of all ports on power-up. After power-up, the level of pre-emphasis can be programmed in the registers on a per port basis. The amount of preemphasis is dictated by the following equation: -1 a-bz , where the coefficients a and b are set : PREEMPH[1:0] A B Pre-emphasis 00 1 0 0dB (off) 01 0.875 0.125 2.5 dB 10 0.75 0.25 6.0dB 11 0.667 0.333 9.5dB PREEMPH[1:0] inputs have internal 50 KW pulldowns. NOTE: Pre-emphasis is not supported in half-rate mode. RECEQUALIZE[1] RECEQUALIZE[0] Input Receive Equalization Select The RECEQUALIZE pins select the level of equalization used on the serial receive inputs of all ports on power-up. After power-up, the level of equalization can be programmed in the registers on a per port basis. RECEQUALIZE [1:0] Equalization Description 00 Max Equalization Both stages enabled 01 Reserved Reserved 10 Moderate Equalization 11 No Equalization 1st & 2nd Stage Eq-off (default for 2.125Gbit/s) RECEQUALIZE[1] has an internal 50 KW pullup. RECEQUALIZE[0] has an internal 50 KW pulldown. RX100/150 RX100/150[3] Input RX100/150 RX100/150[2] RX100/150 RX100/150[1] RX100/150 RX100/150[0] Receive 100 or 150 W Termination Select The RX100/150 RX100/150[X] input selects the impedance of the termination between the RDIP[X] and RDIN[X] inputs. When set to logic 0, the RX100/150 RX100/150[X] forces the RDIP[X] and the RDIN[X] inputs to match a 100 W differential termination. When set to logic 1, the RX100/150 RX100/150[X] forces the RDIP[X] and the RDIN[X] inputs to match a 150 W differential termination. These inputs each have an internal 50 KW pull-down resistor. Proprietary and Confidential to PMC-Sierra, Inc. Document No.: PMC-2031142 PMC-2031142, Issue 1 16 QuadPHYÒ RT ASSP Standard Product Overview Released Pin Name Type Function TX100/150 TX100/150[3] Input Transmit 100 or 150 W Termination Select TX100/150 TX100/150[2] The TX100/150 TX100/150[X] input selects the impedance of the termination on the TDOP[X] and TDON[X] outputs. When set to logic 0, the TX100/150 TX100/150[X] forces the TDOP[X] and the TDON[X] outputs to match a 100 W termination. When set to logic 1, the TX100/150 TX100/150[X] forces the TDOP[X] and the TDON[X] outputs to match a 150 W termination. TX100/150 TX100/150[1] TX100/150 TX100/150[0] These inputs each have an internal 50 KW pull-down resistor. RET_MODE Input Retimer Mode Select The RET_MODE pin selects the retimer data path when set to logic 1 or as the repeater data path when set to logic 0. This input has an internal 50 KW pulldown resistor. FC_GE_RET_SEL Input GE FC Retimer Select The FC_GE_RET_SEL pin selects the device to operate as a Fibre Channel Retiming device when set to logic 1 or as a Gigabit Ethernet Retiming Device when set to logic 0. This input has an internal 50 KW pullup resistor. INTRB Output Interrupt Output This output signal goes to logic 0 to indicate when an interrupt condition has occurred. Interrupt condition is defined as change of status of any port due to Port_DLOLB. The interrupt output can be masked and cleared through mask interrupt registers. This output is an Open Drain and requires an external pull-up. DLOLB Output Digital Loss of Link This pin indicates the combined state of the Digital Loss of Link logic for all active receivers. Logic 0 indicates that one or more active channels has lost link. Logic 1 indicates that all active channels are receiving valid data. PORT_DLOLB[3] Output PORT_DLOLB[2] These pins indicate the state of each port's Digital Loss of Link logic for all active receivers. Logic 0 indicates that the respective channel has lost link. Logic 1 indicates that the respective channel is receiving valid data. PORT_DLOLB[1] PORT_DLOLB[0] PORT_2G_RATE[3] Port Digital Loss of Link Output PORT_2G_RATE[2] PORT_2G_RATE[1] PORT_2G_RATE[0] Proprietary and Confidential to PMC-Sierra, Inc. Document No.: PMC-2031142 PMC-2031142, Issue 1 Port Rate Detected These pins indicate the Fibre Channel rate detected of each port's receive logic for all active receivers. Logic 0 indicates that the respective channel has detected the rate to be 1.0625 Gbit/s. Logic 1 indicates that the respective channel has detected the rate to be 2.125 Gbit/s. 17 QuadPHYÒ RT ASSP Standard Product Overview Released Table 3 Management Interface Pin Descriptions ­ 3.3 V I/O Pin Name Type Function RESETB Input Device Reset This input resets the device to a known state when set to a logic 0. All registers go to default values, all state machines are reset, and all data path flip-flops are reset. RESETB should be held low for at least 100 uS. If RESETB has been asserted, the CSU requires RESETB be negated for at least 200 uS to regain lock. Note that this pin should not be asserted for very long periods of time (many minutes or more) . DVPRTAD[4] Input DVPRTAD[3] These address terminals are used to assign a unique address to each QuadPHY RT. Note that the address is assigned to the entire chip, not to individual ports within the chip. When TWISEL is set to logic 0, DVPRTAD[4:0] pins are used as the port address according to the IEEE 802.3ae Clause 45 Management Data Interface specification. When TWISEL is set logic 1, DVPRTAD[4:0] pins are used as the lower 5 bits of the slave address according to the TWI protocol; the most significant bit of the slave address is not provided and assumed to be 0. DVPRTAD[2] DVPRTAD[1] DVPRTAD[0] TWISEL Device Port Address (DVPRTAD[4:0]) Input Two-Wire Interface Select When set to logic 1, the Management Interface operates using the standard Two-Wire Interface (TWI) protocol. When set to logic 0, the Management interface operates according to the IEEE 802.3ae Clause 45 Management Data Interface specification. This input has an internal 50 KW pull-up resistor. MDIO_SDA Input Management Data Clock ­ Serial Clock with schmit trigger MDC_SCL This signal is part of the device 2-wire serial control interface. This signal is used to clock data transfer to and from the serial management interface registers. When TWISEL is logic 1, this pin operates as the serial clock for TWI transfers. When TWISEL is logic 0, this pin operates as the Management Interface Clock. I/O Management Data Input/Output ­ Serial Data This signal is part of the device 2-wire serial control interface. When TWISEL is logic 1, this pin operates as the bi-directional serial data port for TWI transfers. When TWISEL is logic 0, this pin operates as the Management Interface bi-directional serial data port. In TWI mode, the bi-directional MDIO_SDA pin operates as an open-drain when outputting, and requires an external pull-up resistor (1 KW to 10 KW). Proprietary and Confidential to PMC-Sierra, Inc. Document No.: PMC-2031142 PMC-2031142, Issue 1 18 QuadPHYÒ RT ASSP Standard Product Overview Released Table 4 JTAG Test Pin Descriptions ­ 3.3V I/O Pin Name Type Function TMS Input JTAG (IEEE 1149.1) Test Mode Select Input This input controls the test operations that can be carried out using the IEEE 1149.1 test access port. This input has an internal 50 KW pullup resistor. TCK Schmit input JTAG (IEEE 1149.1) Test Clock Input. trigger TDI This signal provides timing for test operations that can be carried out using the IEEE 1149.1 test access port. Input JTAG (IEEE 1149.1) Test Data Input When the QuadPHY RT is configured for JTAG operation, this input carries test data into the device via the IEEE 1149.1 test access port. This input has an internal 50 KW pullup resistor. TDO Output JTAG (IEEE 1149.1) Test Data Output This signal carries test data out of the QuadPHY RT via the IEEE 1149.1 test access port. TRSTB Schmit input trigger JTAG (IEEE 1149.1) Test Reset Input Provides an asynchronous reset to the 1149.1 test access port. This input has an internal 50 KW pullup resistor. Table 5 Clock, Control and Status Pin Descriptions ­ 3.3 V I/O excluding REFCLK Pin Name Type Function REFCLK_P Input Reference Clock - Differential REFCLK_N REFCLK_S This input requires a low jitter differential reference clock operating at 106.25 MHz ±100 ppm for Fibre Channel operation or 125 MHz ±100 ppm for Gigabit Ethernet Retimer operation. The Clock Synthesis PLL uses this clock to generate a phase locked internal 20x clock for serialization and deserialization. These pins are internally terminated with a 100 W and require 0.01uF external AC coupling capacitor. Input Reference Clock ­ Single-Ended This input requires a low jitter reference clock operating at 106.25 MHz ±100 ppm for Fibre Channel operation or 125 MHz ±100 ppm for Gigabit Ethernet Retimer operation. The Clock Synthesis PLL uses this clock to generate a phase locked internal 20x clock for serialization and deserialization. REFCLK_S input is tolerant of 3.3 V. CLK_SEL Input Reference Clock Select When set to logic 1, selects a single-ended reference clock, REFCLK_S, as input to the PLL. When set to logic 0, selects a differential reference clock, REFCLKP, REFCLKN, as input to the PLL. This input has an internal 50 KW pulldown resistor. Proprietary and Confidential to PMC-Sierra, Inc. Document No.: PMC-2031142 PMC-2031142, Issue 1 19 QuadPHYÒ RT ASSP Standard Product Overview Released Pin Name Type Function AUTO_RATE_SEL Input Automatic Rate Selection When set to logic 1, all ports will automatically detect the data rate of 1.0625 Gbit/s or 2.215 Gbit/s and operate at that rate. When set to logic 0, the HALF_RATE pin will select the operating rate of all ports. If the FC_GE_RET_SEL pin is set to logic 0, the AUTO_RATE_SEL pin must be set to logic 0. This input has an internal 50 KW pulldown resistor. HALF_RATE Input 1 Gbit/s Operation Select When set to logic 1 selects 1.0625/1.25 Gbit/s operation on all ports. When set to logic 0 selects 2.125 Gbit/s operation on all ports. If the FC_GE_RET_SEL pin is set to logic 0, the HALF_RATE pin must be set to logic 1. This input has an internal 50 KW pulldown resistor. Table 6 Supply and Reference Pin Descriptions Pin Name Type Function RPRES Input Terminal for a Precision Resistor A precision 10 KW 1/8 W, 1% reference resistor is connected between this terminal and ground. This resistor sets the internal reference current sources. VDD_18 Power Digital Core Power Supply 1.8 V ± 5% VDD_33 Power VDDA Power Digital quiet I/O Power Supply 3.3 V ± 5% Analog Power Supply 1.8 V ± 5% analog supply for PLL only. VSSA Ground Analog ground for PLL These pins should be tied to the same ground plane as the VSS pins. VSS Ground Ground NC No Connect No Connect. Proprietary and Confidential to PMC-Sierra, Inc. Document No.: PMC-2031142 PMC-2031142, Issue 1 20 QuadPHYÒ RT ASSP Standard Product Overview Released 6 Functional Description The following sections detail the major modes of operation and the functional description of the QuadPHY RT. The QuadPHY RT supports two main modes of operation for Gigabit Ethernet and 1/2G Fibre Channel as listed in Table 7; and is composed of five main system blocks, SERDES Reclocker, Receive Retimer/Monitor, Transmit Control, Loopback, Redundancy Control and the Packet Generator /Comparator. In addition to repeating or retiming, the nonblocking cross-connect provides significant flexibility to configure the device for redundancy, multi-cast or broadcast. Table 7 QuadPHY RT Modes of Operation QuadPHY RT Mode Description Repeater Mode Recovered serial data is retimed to recovered clock as shown in Figure 6 Retimer Mode Recovered serial data is retimed to local reference clock as shown Figure 7 Figure 6 QuadPHY RT in Repeater Mode TDOP[1] TDON[1] RDIP[1] RDIN[1] TDOP[0] TDON[0] RDIP[0] RDIN[0] Rx Retimer/ Monitor Tx Control 2 SERDES/ Reclocker Rx Retimer/ Monitor 2 Tx Control 2 SERDES/ Reclocker 2 Tx Control Cross Connect Rx Retimer/ Monitor 2 2 SERDES/ Reclocker Rx Retimer/ Monitor 2 SERDES/ Reclocker RDIP[2] RDIN[2] TDOP[2] TDON[2 RDIP[3] RDIN[3] 2 Tx Control TDOP[3] TDON[3] Pattern Generator/ Comparator Figure 7 QuadPHY RT in Retimer Mode 10 TDOP[1] TDON[1] RDIP[1] RDIN[1] 2 SERDES/ Reclocker 10 2 10 TDOP[0] TDON[0] RDIP[0] RDIN[0] 2 SERDES/ Reclocker 2 10 Rx Retimer/ Monitor Tx Control Rx Retimer/ Monitor Tx Control Rx Retimer/ Monitor Tx Control CrossConnect Rx Retimer/ Monitor Tx Control 2 10 SERDES/ Reclocker 2 RDIP[2] RDIN[2] TDOP[2] TDON[2] 10 2 10 SERDES/ Reclocker 2 RDIP[3] RDIN[3] TDOP[3] TDON[3] 10 Pattern Generator/ Comparator Proprietary and Confidential to PMC-Sierra, Inc. Document No.: PMC-2031142 PMC-2031142, Issue 1 21 QuadPHYÒ RT ASSP Standard Product Overview Released 6.1 Mode Configuration The major functional modes of the QuadPHY RT can be configured through simple pin configuration using the Port Control pins. Table 8 summarizes the configuration requirements for the various operating modes. Table 8 Mode Configuration through Control Pins Operating Mode DLOLBYP_ MASK RET_MODE AUTO_RATE_SEL HALF_RATE FC_GE_RET_SEL GigE/1G FC Repeater 1 0 0 1 X 2G FC Repeater 1 0 0 0 X GigE Retimer 0 1 0 1 0 1G FC Retimer 0 1 1/01 12 1 2G FC Retimer 0 1 1/01 02 1 1. AutoRate Detection for Fibre Channel Retimer Modes is optional. Set AUTORATE to `1' to enable AutoRate Detection. 2. When AutoRate Detection is enabled the HALF_RATE pin is ignored. 6.2 Receive Channel for SERDES Reclocker The SERDES Reclocker block provides clock and data recovery and optional serial to parallel data conversion for an incoming Gigabit Ethernet or 1/2 Gigabit Fibre Channel data stream. Two modes of operation are provided for Repeater and Retimer applications. In repeater mode, the SERDES Reclocker block is used to recover the clock and data for transmission on the associated transmit data path. In Retimer mode after the data is recovered it is converted from a serial to a parallel data stream to be sent to the upstream Retimer block. The SERDES Reclocker receive channel contains the subsystems to recover clock and data (Clock Data Recovery Unit - CDRU), perform optional receive equalization, and convert the data from serial to 10-bit parallel format (Serial In Parallel Out ­ SIPO). Proprietary and Confidential to PMC-Sierra, Inc. Document No.: PMC-2031142 PMC-2031142, Issue 1 22 QuadPHYÒ RT ASSP Standard Product Overview Released Figure 8 SERDES Reclocker Block Diagram SERDES Reclocker RX RX100/150 RX100/150 Equalization Select Rx Data Cap+100/ 150 Ohm Term Analog LOS Recovered clock & data CDRU Preemphasis Select 100/150 Ohm Term 10 Rx Parallel Data Rx Byte Clock SERIALIZER 1 Tx Data Serialin ParallelOut (SIPO) D/A Reclocker Path 0 Parallel-In/ Serial-Out (PISO) Retimer Path 10 TX100/150 TX100/150 Tx Byte Clock Tx Parallel Data Reclocker/ Retimer Sel 6.2.1 High-Speed Input Receiver The high-speed input receiver contains a pin selectable parallel 100 W or 150 W terminating resistor and AC coupling. The RX100/150 RX100/150 pins control the selection on a per port basis of the terminating resistor value. The internal AC coupling provided is limited to the common-mode range of 0 to VDD_18 volts on a 1 V peak differential signal level. For a common-mode range greater than this, external AC capacitors are required and the EXTCAP pin or registers must be set to logic 1. This receiver accepts the high-speed differential signal and amplifies it with programmable equalization to the proper signal levels inside the chip. The input signal is also monitored for analog loss of signal. 6.2.2 Repeater Receive Data Flow There are two paths for receive data to take through the block depending on whether the Repeater or Retimer mode is enabled. In Repeater mode, the receive data goes through the clock and data recovery process. The data is then re-transmitted out through the Serializer to the output buffers. The data is transmitted at the same rate as the input data is received using the recovered clock. Programmable receive equalization (Table 9) provides robust data recovery of highly degraded input signals. The Repeater path attenuates the jitter with minimum latency. 6.2.3 Retimer Receive Data Flow For the QuadPHY RT Retimer mode, the data goes through the clock and data recovery process, including optional programmable receive equalization (Table 9). The data is then converted from serial to 10-bit parallel via the SIPO block. This data is the presented to the adjacent Retiming block. The data then passes through the retiming logic back to the PISO. In this mode the data is transmitted out at the local clock rate. The difference in the clock rate is handled through the elastic buffer in the digital domain. This mode produces a high-speed output, which is fully compliant with Gigabit Ethernet or 1/2G Fibre Channel transmit jitter specifications. Proprietary and Confidential to PMC-Sierra, Inc. Document No.: PMC-2031142 PMC-2031142, Issue 1 23 QuadPHYÒ RT ASSP Standard Product Overview Released Table 9 Programmable Receive Equalization Settings Input Equalization Port [1:0] Equalization Comments 00 Both stages enabled Moderate-equalization Do Not Use. 10 Moderate Equalization Default 11 6.3 Max Equalization 01 No Equalization 1st & 2nd Stage Eq-off Receive Retimer and Monitor The receiver logic contains a Retimer function and data monitoring capabilities. The Retimer feature transfers the recovered data to the local clock to be retransmitted without the accumulated jitter from the serial inputs. The data path through the Retimer and all monitoring functions are enabled through registers. Figure 9 shows the Rx Retimer and Monitor functional blocks. Figure 9 Rx Retimer and Monitor Block Diagram WCLK_RATE RCLK_RATE RATE_DET Retimer HALF_RATE GE_MODE Word Synchronization FC Elasticity Buffer FORCE_RATE GE_MODE CONT_ALIGN NEG_COMDET Byte Alignment/ Rate Detection and Control RLD[9:0] 6.3.1 10 Word Alignment 8B/10B 8B/10B Encoder 8B/10B 8B/10B Decoder hrate_out RXDATAOUT[9:0] GE Elasticity Buffer Receive Retimer Function The Retimer Logic is comprised of a Byte Alignment/Rate Detection block, Word Alignment block and State Machine, 8B/10B 8B/10B Encoder and Decoder, and an Elastic Buffer. The Byte Alignment logic searches for the 10B encoded incoming serial stream for a sequence defined in IEEE 802.3 and FC-FS as a comma. It has a unique position within a 10-bit word of a valid 10B coded data stream to simplify the detection of the proper alignment of incoming characters. The GE byte sync or the FC word sync blocks can also control the byte alignment logic to explicitly search for a comma. For Gigabit Ethernet, byte alignment is performed by feeding the 8B10B 8B10B decode output into the GE Byte synchronization block to determine when to align to a comma character in the data stream. Data alignment is done either explicitly in the loss_of_sync state, or in a continuous mode where alignment will take place on any comma character. Proprietary and Confidential to PMC-Sierra, Inc. Document No.: PMC-2031142 PMC-2031142, Issue 1 24 QuadPHYÒ RT ASSP Standard Product Overview Released Fibre Channel data alignment occurs at both the byte and subsequent word levels. Word alignment partitions incoming 10B codes into groups of four characters that are aligned to the receive ordered set as defined in the FC-FC document. Similar to the Gigabit Ethernet mode, data alignment is done either explicitly in the loss_of_sync state, or in a continuous mode where alignment will take place on any comma character. 6.3.2 Fibre Channel 1 / 2 Gigabit Rate Detection (should not be used in GE mode) The QuadPHY RT optionally performs rate detection between 1 Gigabit and 2 Gigabit Fibre Channel. The Fibre Channel rate detection block uses the word synchronization state from the alignment logic. The process starts in full rate mode, and searches for word synchronization. If word sync is not gained before a counter threshold, half rate mode is selected and word alignment is monitored. After successful word synchronization is monitored to ensure proper rate acquisition at which point RATE_DET output is set to high to indicate that a valid rate has been detected. Subsequent loss of word synchronization for more than TFAIL bytes will restart the rate detection process. 6.3.3 Elastic Buffers for Rate Compensation Gigabit Ethernet Rate Compensation The Gigabit Ethernet Elastic Buffer achieves clock tolerance compensation by inserting or deleting 2 octet wide IDLE sequences or 4 octet wide configuration patterns as needed. The GE Elastic Buffer will only delete an IDLE sequence when more than one IDLE sequence has been recognized. When the GE Elastic Buffer inserts an IDLE sequence after and IDLE sequence has been recognized. The IDLE sequence inserted is the same as the previous IDLE sequence received. The QuadPHY RT has a sixteen (16) character deep FIFO on each receive channel. This enables the QuadPHY RT to tolerate up to +/-100ppm clock differences on 16k byte packets with a 4 byte IPG. Larger packet sizes can be accommodated with larger IPG. Fibre Channel Rate Compensation The Fibre Channel Elastic Buffer provides clock tolerance by inserting or deleting fill words comprised of specific IDLE or ARB ordered sets based on rules assigned to multiple buffer fill levels in the FC-AL-2 specification. In addition to supporting the 4 standard fill level states, an additional 5th non-standard fill level has been introduced in order to maintain data integrity under extreme conditions. There are two different scenarios when insertion or deletion will take place: between packets and during the transmission of primitive sequences for port initialization. ARB ordered sets (ARB(x), ARB(F0), and ARB(FF) are inserted when a Fibre Channel loop is trying to arbitrate for the use of shared loop media, where IDLEs are inserted when packets are not being sent. Note that in addition to ARB or IDLE deletion, it is possible to remove primitive sequences such as LIPs, LPBs and LPEs from the data stream for clock skew management Clock deviations are specified to +/-100 ppm within the FC_PH-x and FC-PI standards. The QuadPHY RT accommodates a worst-case clock rate difference is 200 ppm via a 16-byte deep FIFO. This depth is determined in part by the standard, which requires only 1 character for the insertion pending state, 1 word for the quiescent state, 1 word for the low priority deletion state and 1 word for the high priority deletion state [see FC-AL-2, Annex A]. Proprietary and Confidential to PMC-Sierra, Inc. Document No.: PMC-2031142 PMC-2031142, Issue 1 25 QuadPHYÒ RT ASSP Standard Product Overview Released 6.3.4 Extensive Receive Link Performance Monitoring Link performance monitoring is possible when operating in a Retimer Modes (performance monitoring is not supported in a Repeater Modes). Each receive input can be fully monitored for loss of link, link errors, and link level violations as shown in Table 10. Detected errors are tracked both by cumulative error counts and on-chip error rate calculators. The QuadPHY RT provides a digital loss of link (DLOLB) and per port loss of link indication. Also, interrupt is provided that can be programmed to indicate a change in device status and error conditions. Table 10 Monitored Receive Link Error Conditions Monitored Error Condition Description Analog Loss of Signal GE / FC The analog loss of signal looks for any change of signal status and is filtered to produce an error indication. 8B10B 8B10B code violation and disparity errors GE / FC 8B10B 8B10B errors are recorded in an 8-bit rate counter and a 16-bit absolute counter. Loss of synchronization GE / FC Monitors the word synchronization block (in Fibre Channel mode) or the GE byte synchronization block (in Gigabit Ethernet mode) for a loss of frame synchronization Comma density 6.4 Mode FC Monitors receive K28.5 comma density in Fibre Channel mode. 5 x 5 Cross connect The 5 x 5 Cross connect provides non-blocking connections from the retimer of each receive port and the Pattern Generator block to all the transmit output ports and the Pattern Comparator. The Pattern Generator/Comparator connects to any link through the 5th port of the cross connect. The 5 x 5 Cross connect can be used to implement multicasting, broadcasting, protection switching and loopback switching. The crossbar can be utilized when operating in GigE, 1G FC or 2G FC Retiming modes. The crossbar cannot be utilized when operating in a Reclocking mode. The routing of each input port through the crossbar is configurable through a single register access. As the crossbar is a completely non-blocking, fully broadcast and multicast capable, it is possible to create flexible and optimized configurations that suit specific needs. A potential configuration for redundancy is a single input with recovered serial data retimed to local reference clock and multi-cast to working and protection ports as shown in Figure 7. Figure 11 shows a 1:3 mux configuration that could be used for simplifying connection of distributed switch fabric elements. Proprietary and Confidential to PMC-Sierra, Inc. Document No.: PMC-2031142 PMC-2031142, Issue 1 26 QuadPHYÒ RT ASSP Standard Product Overview Released Figure 10 QuadPHY RT Redundancy Configuration Example 10 TDOP[1] TDON[1] RDIP[1] RDIN[1] 2 SERDES/ Reclocker 10 2 10 TDOP[0] TDON[0] RDIP[0] RDIN[0] 2 SERDES/ Reclocker 10 2 Rx Retimer/ Monitor Tx Control Rx Retimer/ Monitor Tx Control Tx Control Cross Connect Rx Retimer/ Monitor 2 10 2 2 10 SERDES/ Reclocker TDOP[2] TDON[2] RDIP[3] RDIN[3] 2 10 TDOP[3] TDON[3] Protection Port Pattern Generator/ Comparator Unused port can be turned off to optimize device power RDIP[2] RDIN[2] Working Port 10 Rx Retimer/ Monitor Tx Control SERDES/ Reclocker Figure 11 QuadPHY RT with Cross-Connect as 1:3 Mux 10 TDOP[1] TDON[1] RDIP[1] RDIN[1] 2 SERDES/ Reclocker 10 2 10 TDOP[0] TDON[0] RDIP[0] RDIN[0] 2 SERDES/ Reclocker 2 10 Rx Retimer/ Monitor Tx Control Rx Retimer/ Monitor Tx Control Rx Retimer/ Monitor Tx Control Cross Connect 2 10 RDIP[2] RDIN[2] TDOP[2] TDON[2] Working Port 2 10 SERDES/ Reclocker 10 Pattern Generator/ Comparator 6.5 2 10 Rx Retimer/ Monitor Tx Control SERDES/ Reclocker RDIP[0] RDIN[0] 2 TDOP[0] TDON[0] Protection Port TX Control The TX Control block transfers data from the ingress Receive Retimer/Monitor to the SERDES via the Loopback and Redundancy Control block. The Transmit FIFO allows the phase of Transmit clock to be arbitrary relative to the PLL reference clock (SYSCLK), which drives the Serializer and high-speed transmit logic. Note that the frequency of the SYSCLK and Transmit clock is the same. 6.6 Transmit Channel for SERDES / Reclocker The SERDES and Reclocker provides the parallel to serial conversion of 10B data received from the Receive Retimer and Monitor via the Loopback and Redundancy Control block. The serial data is then transmitted on to the high-speed channel via selectable termination and optional programmable pre-emphasis and programmable output swing. Proprietary and Confidential to PMC-Sierra, Inc. Document No.: PMC-2031142 PMC-2031142, Issue 1 27 QuadPHYÒ RT ASSP Standard Product Overview Released 6.6.1 High-Speed Output Driver The serial transmit outputs are internally terminated, complementary current-sourcing drivers. These high-speed differential outputs may directly drive optics, coaxial cable or PC-board interconnect. The QuadPHY RT supports per port pin selectable source output impedance of 100 W or 150 W differential and optional amplitude swing control (Table 11). Table 11 Transmit Amplitude Swing Control HC Port [1:0] Output Levels 00 Low Swing 01 Unused 10 High Swing 11 Mid Swing For back planes implemented with FR4 or similar materials, significant dielectric losses occur at high frequencies. These losses are frequency-dependent and severely limit the achievable separation between transmitter and receiver. To mitigate this problem, the QuadPHY RT supports programmable pre-emphasis on the high-speed transmit outputs. High-frequency components are accentuated to compensate for loss in the back plane material, so that the signal received at the far end is much cleaner and has a wider eye than data transmitted with simple bilevel output buffers. The amount of pre-emphasis is programmable according to the equation abz-1where the coefficients and the amount of pre-emphasis are listed Table 12. Table 12 Pre-emphasis Bits[1:0] b Pre-emphasis 00 1 0 0 dB (off) 01 0.875 0.125 2.5dB 10 0.75 0.25 6.0dB 11 6.7 a 0.667 0.333 9.5dB Clock Synthesizer The Clock Synthesizer uses a PLL to synthesize a clock from the REFCLK inputs. The frequency of the PLL clock is 20 times the frequency of REFCLK inputs. The synthesized clock is used by the SERDES/Reclocker blocks to generate recovered clocks and to provide an accurate and stable high speed transmit clock. The Clock Synthesizer also generates the internal core logic clock which is 212.5 MHz for FC and 250 MHz for GE. Table 13 REFCLK and PLL Clock Combinations REFCLK Frequency Pin Setting PLL Clock Frequency Transmit/Receive Data Rate 125.00 MHz FC_GE_RET_SEL = 0 2.50 GHz 1.250 Gbit/s 106.25 MHz FC_GE_RET_SEL = 1 2.125 GHz 1.0625 Gbit/s HALF_RATE = 1 106.25 MHz FC_GE_RET_SEL = 1 2.125 GHz Proprietary and Confidential to PMC-Sierra, Inc. Document No.: PMC-2031142 PMC-2031142, Issue 1 2.125 Gbit/s 28 QuadPHYÒ RT ASSP Standard Product Overview Released HALF_RATE = 0 6.8 Management Interface The QuadPHY RT can operate in a standalone mode (default) or through a 2-wire serial control interface. When in standalone mode, the device powers up with default settings. The 2-wire serial control interface mode supports both a generic 2-wire interface mode as well as the management interface described in IEEE 802.3ae. The MDIO implementation on the QuadPHY RT is logically compliant to the MDIO protocol as defined in the IEEE 802.3ae however the signaling levels (3.3V) are not compliant with those defined in IEEE802 IEEE802.3ae (1.2V). 6.9 Backplane Test/Debug Features 6.9.1 Pattern Generator/Comparator A Pattern Generator/Comparator is provided to allow extensive backplane signal integrity and jitter testing for both system development and testing or for enhanced system operational diagnostic and monitoring capabilities. The pattern generator allows a pre-determined fixed pattern (Table 14) to be continuously transmitted on all of the QuadPHY RT transmit links. The pattern comparator has the ability to compare a predetermined fixed pattern and report an error if the incoming pattern does not match the expected pattern. Table 14 Pattern Generator Test Patterns Pattern Type Description 0 Compliant RPAT 1 Low Transition Density Pattern 2 Compliant Jitter Tolerance Pattern 3 Half Rate and Quarter Rate Pattern 4 Low Frequency Pattern 5 Supply Noise Pattern 6 CUSTOM Pattern Proprietary and Confidential to PMC-Sierra, Inc. Document No.: PMC-2031142 PMC-2031142, Issue 1 29 QuadPHYÒ RT ASSP Standard Product Overview Released 7 Power Information 7.1 Power Requirements Table 15 Typical Power requirements Operation mode Parameter Typ Power for Thermal Calculations Max Current Units 2G Fiber Channel IDDOP VDD_18 410 - 651 mA IDDOP VDDA 39 - 83 mA (2 ports) 1 - 2.26 mA Total Power 2G Fiber Channel IDDOP VDD_33 0.81 1.03 - W IDDOP VDD_18 515 - 751 mA 2G Fiber Channel IDDOP VDDA 39 - 83 mA IDDOP VDD_33 1 - 2.26 mA Total Power (3 ports) 1.00 1.23 - W IDDOP VDD_18 614 - 844 mA IDDOP VDDA 39 - 83 mA IDDOP VDD_33 1 - 3 mA Total Power 1.18 1.4 - W GE Retimer IDDOP VDD_18 606 - 807 mA (4 ports) IDDOP VDDA 40 - 85 mA IDDOP VDD_33 1 - 2 mA Total Power 1.16 1.38 - W (4 ports) Notes: 1. Typical IDD values are calculated as the mean value of current under the following conditions: typically processed silicon, nominal supply voltage, TJ=60 °C, outputs loaded with 30 pF (if not otherwise specified), and a normal amount of traffic or signal activity. These values are suitable for evaluating typical device performance in a system 2. Max IDD values are currents guaranteed by the production test program and/or characterization over process for operating currents at the maximum operating voltage and operating temperature that yields the highest current (including outputs loaded to 30 pF, unless otherwise specified) 3. Typical power values are calculated using the formula: Power = i(VDDNomi x IDDTypi) Where i denotes all the various power supplies on the device, VDDNomi is the nominal voltage for supply i, and IDDTypi is the typical current for supply i (as defined in note 1 above). These values are suitable for evaluating typical device performance in a system Proprietary and Confidential to PMC-Sierra, Inc. Document No.: PMC-2031142 PMC-2031142, Issue 1 30 QuadPHYÒ RT ASSP Standard Product Overview Released 7.2 Power Supply Filtering and Decoupling 1. Use a single plane for both digital and analog grounds. 2. Provide separate analog and digital supplies. Otherwise connect the supply voltages together at one point close to the connector where the voltage is brought to the card. 3. Ferrite beads are not advisable in digital switching circuits because inductive spiking (di/dt noise) is introduced into the power rail. Simple RC filtering is probably the best approach provided care is taken to ensure the IR drop in the resistance does not lower the supply voltage below the recommended operating voltage. Figure 12 illustrates the scheme required for power supply conditioning. Component values may need adjustment to match the characteristics of the board in which the conditioning will be applied. The 10uF Ceramic caps are X5R (X7R) type, and not Tantalum or Y5V, for best frequency response and lowest ESR. Recommended components are Taiyo Yuden PN # LMK325BJ106MN LMK325BJ106MN or Panasonic PN # ECJ-3YB0J106K ECJ-3YB0J106K. Boards with the following criteria may use a distributed decoupling scheme, with 0.1 uF capacitors placed on a one-inch grid. · VDD and VDDQ pins are connected to large power planes with a minimum area of 20 square inches (~ 130 cm2) adjacent to a ground plane. · Board stack-up has a maximum power plane to ground plane spacing of 0.006 inches (~ 0.15 mm) A distributed decoupling capacitor placement offers significant improvements compared to grouped placement of capacitors. On boards that do not meet these criteria, one capacitor should be used for every two VDD_18 (or every two VDD_33) pins. The 0.1 uF capacitors should be placed as close as possible to each power pin and to ground layer. The traces from the capacitors to the QuadPHY RT power pins and to the ground plane should be as short as possible to limit series inductance. For further information regarding power supply filtering, please refer to the Digital Power Supply Bypass Guidelines Application Note [PMC-2012008 PMC-2012008]. In order to minimize the intrinsic jitter on the TDO outputs, RC filtering of the VDDA supply voltage is required. The values shown in Figure 12 were chosen to minimize the IR drop on the VDDA supply voltage, yet provide sufficient filtering of power supply noise at low frequencies. Proprietary and Confidential to PMC-Sierra, Inc. Document No.: PMC-2031142 PMC-2031142, Issue 1 31 QuadPHYÒ RT ASSP Standard Product Overview Released Figure 12 Recommended Power Supply Decoupling QuadPHY RT 1.8 V Use one 0.1uF capacitor for every two VDD pins VDD_18 VDD_18 10uF 0.1u 0.1u 0.1u VDD_18 1.8 V Digital Supply Pins GND GND GND 3.3V Use one 0.1uF capacitor for every two VDD_33 pins VDD_33 VDD_33 10uF 0.1u 0.1u 0.1u 1.8 V VDD_33 VDDA 0.47 ohm VDDA Proprietary and Confidential to PMC-Sierra, Inc. Document No.: PMC-2031142 PMC-2031142, Issue 1 1.8 V Analog Supply Pins GNDA + 22uF 3.3V Digital I/O Supply Pins 10uF 0.1uF GNDA 32 QuadPHYÒ RT ASSP Standard Product Overview Released 8 Mechanical Information This mechanical package diagram QuadPHY RT device's 196-pin chip array BGA Package is shown in Figure 13. After assembly, the QuadPHY RT is tested to meet or exceed a 0.15 mm (5.9 mil) co planarity specification. Figure 13 Mechanical Drawing 196 Pin Chip Array BGA D1,M aaa (4x) A1 BALL CORNER A D A1 BALL CORNER B eee C AB fff C A1 BALL ID INDICATOR E1,N E e I J b 5 e A2 A bbb C C A3 A1 ddd C SEATING PLANE NOTES: 1) 2) 3) 4) 5) 6) ALL DIMENSIONS IN MILLIMETER. DIMENSION aaa DENOTES PACKAGE BODY PROFILE. DIMENSION bbb DENOTES PARALLEL. DIMENSION ddd DENOTES COPLANARITY. SOLDER MASK OPENING 0.435 +/- 0.03 MM DIAMETER (SMD). PACKAGE COMPLIANT TO JEDEC REGISTERED OUTLINE MO-192 MO-192, VARIATION AAE-1. PACKAGE TYPE : 196 CHIP ARRAY BALL GRID ARRAY - CABGA BODY SIZE : 15 x 15 x 1.40 MM Dim. A A1 A2 A3 D D1 E E1 Min. 1.30 0.31 0.65 0.34 - - - - M,N - I J b e - - - - - - - - - 0.46 1.00 - - - - - - - 0.10 0.12 0.15 0.08 Nom. 1.40 0.36 0.70 0.34 15.00 13.00 15.00 13.00 14x14 1.00 1.00 BSC BSC BSC BSC Max. 1.50 0.41 0.75 0.34 - Proprietary and Confidential to PMC-Sierra, Inc. Document No.: PMC-2031142 PMC-2031142, Issue 1 - - - - - - BSC aaa bbb ddd eee f f f 0.10 33