PM7367 FREEDM-32P32 PMC-1991499 FREEDMTM-32P32 BUFFER67 PROCESSOR68 0X000 0X004 - Datasheet Archive

 

DATA SHEET PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER PM7367 FREEDMTM-32P32 FRAME ENGINE AND DATALINK MANAGER DATA

 

PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER PM7367 PM7367 FREEDMTM-32P32 FREEDMTM-32P32 FRAME ENGINE AND DATALINK MANAGER DATA SHEET ISSUE 2: AUGUST 2001 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS' INTERNAL USE PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER PUBLIC REVISION HISTORY Issue No. Issue 2 Issue 1 Issue Date August 2001 Nov, 1999 Details of Change Added patent information to legal footer. Data sheet created. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE i PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER CONTENTS 1 FEATURES.1 2 APPLICATIONS.3 3 REFERENCES .4 4 BLOCK DIAGRAM.5 5 DESCRIPTION .6 6 PIN DIAGRAM .8 7 PIN DESCRIPTION .9 8 FUNCTIONAL DESCRIPTION .30 8.1 HIGH-LEVEL DATA LINK CONTROL PROTOCOL.30 8.2 RECEIVE CHANNEL ASSIGNER .31 8.2.1 8.2.2 PRIORITY ENCODER .32 8.2.3 CHANNEL ASSIGNER .32 8.2.4 8.3 LINE INTERFACE.32 LOOPBACK CONTROLLER .33 RECEIVE HDLC PROCESSOR / PARTIAL PACKET BUFFER.33 8.3.1 8.3.2 8.4 HDLC PROCESSOR .33 PARTIAL PACKET BUFFER PROCESSOR .34 RECEIVE DMA CONTROLLER .36 8.4.1 DATA STRUCTURES .36 8.4.2 DMA TRANSACTION CONTROLLER.46 8.4.3 WRITE DATA PIPELINE/MUX .46 8.4.4 DESCRIPTOR INFORMATION CACHE .46 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE ii PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 ISSUE 2 8.4.5 8.5 FRAME ENGINE AND DATA LINK MANAGER FREE QUEUE CACHE .46 PCI CONTROLLER.47 8.5.1 8.5.2 MASTER LOCAL BUS INTERFACE.50 8.5.3 TARGET MACHINE .51 8.5.4 CBI BUS INTERFACE .53 8.5.5 8.6 MASTER MACHINE .48 ERROR / BUS CONTROL .53 TRANSMIT DMA CONTROLLER.53 8.6.1 8.6.2 TASK PRIORITIES .66 8.6.3 DMA TRANSACTION CONTROLLER.66 8.6.4 READ DATA PIPELINE.66 8.6.5 DESCRIPTOR INFORMATION CACHE .66 8.6.6 8.7 DATA STRUCTURES .54 FREE QUEUE CACHE .66 TRANSMIT HDLC CONTROLLER / PARTIAL PACKET BUFFER67 BUFFER67 8.7.1 8.7.2 8.8 TRANSMIT HDLC PROCESSOR.67 TRANSMIT PARTIAL PACKET BUFFER PROCESSOR68 PROCESSOR68 TRANSMIT CHANNEL ASSIGNER .70 8.8.1 LINE INTERFACE.71 8.8.2 PRIORITY ENCODER .71 8.8.3 CHANNEL ASSIGNER .72 8.9 PERFORMANCE MONITOR .72 8.10 JTAG TEST ACCESS PORT INTERFACE.72 8.11 PCI HOST INTERFACE .72 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE iii PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 9 ISSUE 2 NORMAL MODE REGISTER DESCRIPTION .78 9.1 10 PCI HOST ACCESSIBLE REGISTERS .78 PCI CONFIGURATION REGISTER DESCRIPTION .250 10.1 11 FRAME ENGINE AND DATA LINK MANAGER PCI CONFIGURATION REGISTERS.250 TEST FEATURES DESCRIPTION .261 11.1 TEST MODE REGISTERS .261 11.2 JTAG TEST PORT .262 11.2.1 11.2.2 12 IDENTIFICATION REGISTER .263 BOUNDARY SCAN REGISTER .263 OPERATIONS .277 12.1 12.2 TOCTL CONNECTIONS .277 12.3 13 EQUAD CONNECTIONS.277 JTAG SUPPORT.278 FUNCTIONAL TIMING .284 13.1 RECEIVE LINK INPUT TIMING .284 13.2 TRANSMIT LINK OUTPUT TIMING.285 13.3 PCI INTERFACE .287 13.4 BERT INTERFACE .296 14 ABSOLUTE MAXIMUM RATINGS.298 15 D.C. CHARACTERISTICS.299 16 FREEDM-32P32 FREEDM-32P32 TIMING CHARACTERISTICS.301 17 ORDERING AND THERMAL INFORMATION .307 18 MECHANICAL INFORMATION.308 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE iv PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER LIST OF REGISTERS REGISTER 0X000 0X000 : FREEDM-32P32 FREEDM-32P32 MASTER RESET .79 REGISTER 0X004 0X004 : FREEDM-32P32 FREEDM-32P32 MASTER INTERRUPT ENABLE.81 REGISTER 0X008 0X008 : FREEDM-32P32 FREEDM-32P32 MASTER INTERRUPT STATUS .86 REGISTER 0X00C 0X00C : FREEDM-32P32 FREEDM-32P32 MASTER CLOCK / BERT ACTIVITY MONITOR AND ACCUMULATION TRIGGER .90 REGISTER 0X010 0X010 : FREEDM-32P32 FREEDM-32P32 MASTER LINK ACTIVITY MONITOR .92 REGISTER 0X014 0X014 : FREEDM-32P32 FREEDM-32P32 MASTER LINE LOOPBACK #1 .96 REGISTER 0X018 0X018 : FREEDM-32P32 FREEDM-32P32 MASTER LINE LOOPBACK #2 .98 REGISTER 0X020 0X020 : FREEDM-32P32 FREEDM-32P32 MASTER BERT CONTROL .100 REGISTER 0X024 0X024 : FREEDM-32P32 FREEDM-32P32 MASTER PERFORMANCE MONITOR CONTROL .102 REGISTER 0X040 0X040 : GPIC CONTROL .106 REGISTER 0X100 0X100 : RCAS INDIRECT LINK AND TIME-SLOT SELECT.109 REGISTER 0X104 0X104 : RCAS INDIRECT CHANNEL DATA . 111 REGISTER 0X108 0X108 : RCAS FRAMING BIT THRESHOLD. 113 REGISTER 0X10C 0X10C : RCAS CHANNEL DISABLE . 115 REGISTER 0X180 0X180 : RCAS LINK #0 CONFIGURATION . 117 REGISTER 0X184 0X184 - 0X188 0X188 : RCAS LINK #1 TO #2 CONFIGURATION. 119 REGISTER 0X18C 0X18C : RCAS LINK #3 CONFIGURATION .121 REGISTER 0X190-0X1FC 0X190-0X1FC : RCAS LINK #4 TO LINK #31 CONFIGURATION123 CONFIGURATION123 REGISTER 0X200 0X200 : RHDL INDIRECT CHANNEL SELECT .125 REGISTER 0X204 0X204 : RHDL INDIRECT CHANNEL DATA REGISTER #1 .127 REGISTER 0X208 0X208 : RHDL INDIRECT CHANNEL DATA REGISTER #2 .130 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE v PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER REGISTER 0X210 0X210 : RHDL INDIRECT BLOCK SELECT .133 REGISTER 0X214 0X214 : RHDL INDIRECT BLOCK DATA .135 REGISTER 0X220 0X220 : RHDL CONFIGURATION .137 REGISTER 0X224 0X224 : RHDL MAXIMUM PACKET LENGTH .139 REGISTER 0X280 0X280 : RMAC CONTROL.141 REGISTER 0X284 0X284 : RMAC INDIRECT CHANNEL PROVISIONING .144 REGISTER 0X288 0X288 : RMAC PACKET DESCRIPTOR TABLE BASE LSW .146 REGISTER 0X28C 0X28C : RMAC PACKET DESCRIPTOR TABLE BASE MSW.147 REGISTER 0X290 0X290 : RMAC QUEUE BASE LSW .149 REGISTER 0X294 0X294 : RMAC QUEUE BASE MSW .150 REGISTER 0X298 0X298 : RMAC PACKET DESCRIPTOR REFERENCE LARGE BUFFER FREE QUEUE START.152 REGISTER 0X29C 0X29C : RMAC PACKET DESCRIPTOR REFERENCE LARGE BUFFER FREE QUEUE WRITE .154 REGISTER 0X2A0 : RMAC PACKET DESCRIPTOR REFERENCE LARGE BUFFER FREE QUEUE READ .156 REGISTER 0X2A4 : RMAC PACKET DESCRIPTOR REFERENCE LARGE BUFFER FREE QUEUE END.158 REGISTER 0X2A8 : RMAC PACKET DESCRIPTOR REFERENCE SMALL BUFFER FREE QUEUE START.160 REGISTER 0X2AC : RMAC PACKET DESCRIPTOR REFERENCE SMALL BUFFER FREE QUEUE WRITE .162 REGISTER 0X2B0 : RMAC PACKET DESCRIPTOR REFERENCE SMALL BUFFER FREE QUEUE READ .164 REGISTER 0X2B4 : RMAC PACKET DESCRIPTOR REFERENCE SMALL BUFFER FREE QUEUE END.166 REGISTER 0X2B8 : RMAC PACKET DESCRIPTOR REFERENCE READY QUEUE START .168 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE vi PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER REGISTER 0X2BC : RMAC PACKET DESCRIPTOR REFERENCE READY QUEUE WRITE .170 REGISTER 0X2C0 : RMAC PACKET DESCRIPTOR REFERENCE READY QUEUE READ .172 REGISTER 0X2C4 : RMAC PACKET DESCRIPTOR REFERENCE READY QUEUE END .174 REGISTER 0X300 0X300 : TMAC CONTROL .176 REGISTER 0X304 0X304 : TMAC INDIRECT CHANNEL PROVISIONING.179 REGISTER 0X308 0X308 : TMAC DESCRIPTOR TABLE BASE LSW.181 REGISTER 0X30C 0X30C : TMAC DESCRIPTOR TABLE BASE MSW .182 REGISTER 0X310 0X310 : TMAC QUEUE BASE LSW .184 REGISTER 0X314 0X314 : TMAC QUEUE BASE MSW .185 REGISTER 0X318 0X318 : TMAC DESCRIPTOR REFERENCE FREE QUEUE START .187 REGISTER 0X31C 0X31C TMAC DESCRIPTOR REFERENCE FREE QUEUE WRITE .189 REGISTER 0X320 0X320 : TMAC DESCRIPTOR REFERENCE FREE QUEUE READ .191 REGISTER 0X324 0X324 : TMAC DESCRIPTOR REFERENCE FREE QUEUE END .193 REGISTER 0X328 0X328 :TMAC DESCRIPTOR REFERENCE READY QUEUE START .195 REGISTER 0X32C 0X32C : TMAC DESCRIPTOR REFERENCE READY QUEUE WRITE .197 REGISTER 0X330 0X330 : TMAC DESCRIPTOR REFERENCE READY QUEUE READ199 READ199 REGISTER 0X334 0X334 : TMAC DESCRIPTOR REFERENCE READY QUEUE END .201 REGISTER 0X380 0X380 : THDL INDIRECT CHANNEL SELECT.203 REGISTER 0X384 0X384 : THDL INDIRECT CHANNEL DATA #1 .205 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE vii PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER REGISTER 0X388 0X388 : THDL INDIRECT CHANNEL DATA #2 .208 REGISTER 0X38C 0X38C : THDL INDIRECT CHANNEL DATA #3 . 211 REGISTER 0X3A0 : THDL INDIRECT BLOCK SELECT .216 REGISTER 0X3A4 : THDL INDIRECT BLOCK DATA .218 REGISTER 0X3B0 : THDL CONFIGURATION .220 REGISTER 0X400 0X400 : TCAS INDIRECT LINK AND TIME-SLOT SELECT .222 REGISTER 0X404 0X404 : TCAS INDIRECT CHANNEL DATA .224 REGISTER 0X408 0X408 : TCAS FRAMING BIT THRESHOLD .226 REGISTER 0X40C 0X40C : TCAS IDLE TIME-SLOT FILL DATA.228 REGISTER 0X410 0X410 : TCAS CHANNEL DISABLE .230 REGISTER 0X480 0X480 : TCAS LINK #0 CONFIGURATION .232 REGISTER 0X484-0X488 0X484-0X488 : TCAS LINK #1 TO LINK #2 CONFIGURATION .234 REGISTER 0X48C 0X48C : TCAS LINK #3 CONFIGURATION .236 REGISTER 0X490-0X4FC 0X490-0X4FC : TCAS LINK #4 TO LINK #31 CONFIGURATION238 CONFIGURATION238 REGISTER 0X500 0X500 : PMON STATUS .240 REGISTER 0X504 0X504 : PMON RECEIVE FIFO OVERFLOW COUNT.242 REGISTER 0X508 0X508 : PMON RECEIVE FIFO UNDERFLOW COUNT .244 REGISTER 0X50C 0X50C : PMON CONFIGURABLE COUNT #1.246 REGISTER 0X510 0X510 : PMON CONFIGURABLE COUNT #2 .248 REGISTER 0X00 : VENDOR IDENTIFICATION/DEVICE IDENTIFICATION.251 REGISTER 0X04 : COMMAND/STATUS .252 REGISTER 0X08 : REVISION IDENTIFIER/CLASS CODE.256 REGISTER 0X0C : CACHE LINE SIZE/LATENCY TIMER/HEADER TYPE .257 REGISTER 0X10 : CBI MEMORY BASE ADDRESS REGISTER.258 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE viii PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER REGISTER 0X3C : INTERRUPT LINE / INTERRUPT PIN / MIN_GNT / MAX_LAT.260 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE ix PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER LIST OF FIGURES FIGURE 1 ­ HDLC FRAME.30 FIGURE 2 ­ CRC GENERATOR.31 FIGURE 3 ­ PARTIAL PACKET BUFFER STRUCTURE .35 FIGURE 4 ­ RECEIVE PACKET DESCRIPTOR.37 FIGURE 5 ­ RECEIVE PACKET DESCRIPTOR TABLE.40 FIGURE 6 ­ RPDRF AND RPDRR QUEUES .42 FIGURE 7 ­ RPDRR QUEUE OPERATION.44 FIGURE 8 ­ RECEIVE CHANNEL DESCRIPTOR REFERENCE TABLE.45 FIGURE 9 ­ GPIC ADDRESS MAP .52 FIGURE 10 ­ TRANSMIT DESCRIPTOR .54 FIGURE 11 ­ TRANSMIT DESCRIPTOR TABLE .58 FIGURE 12 ­ TDRR AND TDRF QUEUES .60 FIGURE 13 ­ TRANSMIT CHANNEL DESCRIPTOR REFERENCE TABLE .62 FIGURE 14 ­ TD LINKING.65 FIGURE 15 ­ PARTIAL PACKET BUFFER STRUCTURE .69 FIGURE 16 ­ INPUT OBSERVATION CELL (IN_CELL) .274 FIGURE 17 ­ OUTPUT CELL (OUT_CELL) .275 FIGURE 18 ­ BI-DIRECTIONAL CELL (IO_CELL) .275 FIGURE 19 ­ LAYOUT OF OUTPUT ENABLE AND BI-DIRECTIONAL CELLS .276 FIGURE 20 ­ BOUNDARY SCAN ARCHITECTURE .278 FIGURE 21 ­ TAP CONTROLLER FINITE STATE MACHINE .280 FIGURE 22 ­ UNCHANNELISED RECEIVE LINK TIMING .284 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE x PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER FIGURE 23 ­ CHANNELISED T1 RECEIVE LINK TIMING .285 FIGURE 24 ­ CHANNELISED E1 RECEIVE LINK TIMING .285 FIGURE 25 ­ UNCHANNELISED TRANSMIT LINK TIMING.286 FIGURE 26 ­ CHANNELISED T1 TRANSMIT LINK TIMING.286 FIGURE 27 ­ CHANNELISED E1 TRANSMIT LINK TIMING .287 FIGURE 28 ­ PCI READ CYCLE .288 FIGURE 29 ­ PCI WRITE CYCLE .290 FIGURE 30 ­ PCI TARGET DISCONNECT .291 FIGURE 31 ­ PCI TARGET ABORT.291 FIGURE 32 ­ PCI BUS REQUEST CYCLE .292 FIGURE 33 ­ PCI INITIATOR ABORT TERMINATION .293 FIGURE 34 ­ PCI EXCLUSIVE LOCK CYCLE .294 FIGURE 35 ­ PCI FAST BACK TO BACK.296 FIGURE 36 ­ RECEIVE BERT PORT TIMING .296 FIGURE 37 ­ TRANSMIT BERT PORT TIMING .297 FIGURE 38 ­ RECEIVE LINK INPUT TIMING .302 FIGURE 39 ­ BERT INPUT TIMING .302 FIGURE 40 ­ TRANSMIT LINK OUTPUT TIMING.304 FIGURE 41 ­ BERT OUTPUT TIMING .304 FIGURE 42 ­ PCI INTERFACE TIMING .305 FIGURE 43 ­ JTAG PORT INTERFACE TIMING.306 FIGURE 44 ­ 272 PIN PLASTIC BALL GRID ARRAY (PBGA) .308 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE xi PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER LIST OF TABLES TABLE 1 ­ LINE SIDE INTERFACE SIGNALS (132) .9 TABLE 2 ­ PCI HOST INTERFACE SIGNALS (51) .14 TABLE 3 ­ MISCELLANEOUS INTERFACE SIGNALS (41).23 TABLE 4 ­ PRODUCTION TEST INTERFACE SIGNALS (0 - MULTIPLEXED)26 TABLE 5 ­ POWER AND GROUND SIGNALS (60) .27 TABLE 6 ­ RECEIVE PACKET DESCRIPTOR FIELDS.37 TABLE 7 ­ RPDRR QUEUE ELEMENT .43 TABLE 8 ­ RECEIVE CHANNEL DESCRIPTOR REFERENCE TABLE FIELDS .45 TABLE 9 ­ TRANSMIT DESCRIPTOR FIELDS .55 TABLE 10 ­ TRANSMIT DESCRIPTOR REFERENCE.61 TABLE 11 ­ TRANSMIT CHANNEL DESCRIPTOR REFERENCE TABLE FIELDS .63 TABLE 12 ­ NORMAL MODE PCI HOST ACCESSIBLE REGISTER MEMORY MAP .73 TABLE 13 ­ PCI CONFIGURATION REGISTER MEMORY MAP.77 TABLE 14 ­ BIG ENDIAN FORMAT.107 TABLE 15 ­ LITTLE ENDIAN FORMAT .107 TABLE 16 ­ CRC[1:0] SETTINGS.129 TABLE 17 ­ RPQ_RDYN[2:0] SETTINGS .142 TABLE 18 ­ RPQ_LFN[1:0] SETTINGS.143 TABLE 19 ­ RPQ_SFN[1:0] SETTINGS .143 TABLE 20 ­ TDQ_RDYN[2:0] SETTINGS.177 TABLE 21 ­ TDQ_FRN[1:0] SETTINGS .177 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE xii PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER TABLE 22 ­ CRC[1:0] SETTINGS.206 TABLE 23 ­ FLAG[2:0] SETTINGS .212 TABLE 24 ­ LEVEL[3:0]/TRANS SETTINGS .214 TABLE 25 ­ TEST MODE REGISTER MEMORY MAP .262 TABLE 26 ­ INSTRUCTION REGISTER .263 TABLE 27 ­ BOUNDARY SCAN CHAIN .264 TABLE 28 ­ FREEDM­EQUAD CONNECTIONS .277 TABLE 29 ­ FREEDM­TOCTAL CONNECTIONS .277 TABLE 30 ­ FREEDM-32P32 FREEDM-32P32 ABSOLUTE MAXIMUM RATINGS.298 TABLE 31 ­ FREEDM-32P32 FREEDM-32P32 D.C. CHARACTERISTICS.299 TABLE 32 ­ FREEDM-32P32 FREEDM-32P32 LINK INPUT (FIGURE 38, FIGURE 39).301 TABLE 33 ­ FREEDM-32P32 FREEDM-32P32 LINK OUTPUT (FIGURE 40, FIGURE 41).303 TABLE 34 ­ PCI INTERFACE (FIGURE 42) .304 TABLE 35 ­ JTAG PORT INTERFACE (FIGURE 43).305 TABLE 36 ­ FREEDM-32P32 FREEDM-32P32 ORDERING INFORMATION.307 TABLE 37 ­ FREEDM-32P32 FREEDM-32P32 THERMAL INFORMATION .307 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE xiii PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 1 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER FEATURES · Single-chip Peripheral Component Interconnect (PCI) Bus multi-channel HDLC controller. · Supports up to 32 bi-directional HDLC channels assigned to a maximum of 32 channelised T1 or E1 links. The number of time-slots assigned to an HDLC channel is programmable from 1 to 24 (for T1) and from 1 to 31 (for E1). · Supports up to 32 bi-directional HDLC channels each assigned to an unchannelised arbitrary rate link; subject to a maximum aggregate link clock rate of 64 MHz in each direction. Channels assigned to links 0 to 2 can have a clock rate of up to 45 MHz when SYSCLK is at or above 25 MHz and up to 52 MHz when SYSCLK is at 33 MHz. Channels assigned to links 3 to 31 can have a clock rate of up to 10 MHz. · Supports up to two bi-directional HDLC channels each assigned to an unchannelised arbitrary rate link of up to 45 MHz when SYSCLK is at or above 25 MHz and up to 52 MHz when SYSCLK is at 33 MHz. · Supports a mix of up to 32 channelised and unchannelised links; subject to the constraint of a maximum of 32 channels and a maximum aggregate link clock rate of 64 MHz in each direction. · For each channel, the HDLC receiver performs flag sequence detection, bit de-stuffing, and frame check sequence validation. The receiver supports the validation of both CRC-CCITT and CRC-32 CRC-32 frame check sequences. The receiver also checks for packet abort sequences, octet aligned packet length and for minimum and maximum packet length. · Alternatively, for each channel, the receiver supports a transparent mode where each octet is transferred transparently to host memory. For channelised links, the octets are aligned with the receive time-slots. · For each channel, time-slots are selectable to be in 56 kbits/s format or 64 kbits/s clear channel format. · For each channel, the HDLC transmitter performs flag sequence generation, bit stuffing, and, optionally, frame check sequence generation. The transmitter supports the generation of both CRC-CCITT and CRC-32 CRC-32 frame check sequences. The transmitter also aborts packets under the direction of the host or automatically when the channel underflows. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE 1 PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER · Supports two levels of non-preemptive packet priority on each transmit channel. Low priority packets will not begin transmission until all high priority packets are transmitted. · Alternatively, for each channel, the transmitter supports a transparent mode where each octet is inserted transparently from host memory. For channelised links, the octets are aligned with the transmit time-slots. · Directly supports a 32-bit, 33 MHz PCI 2.1 interface for configuration, monitoring and transfer of packet data, with an on-chip DMA controller with scatter/gather capabilities. · Provides 8 kbytes of on-chip memory for partial packet buffering in each direction. This memory can be configured to support a variety of different channel configurations from a single channel with 8 kbytes of buffering to 32 channels, each with a minimum of 48 bytes of buffering. · Supports PCI burst sizes of up to 128 bytes for transfers of packet data. · Pin compatible with PM7366-PI PM7366-PI (FREEDM-8 PBGA) device. · Provides a standard 5 signal P1149 P1149.1 JTAG test port for boundary scan board test purposes. · Supports 3.3 and 5 Volt PCI signaling environments. · Low power CMOS technology. · 272 pin Plastic ball grid array (PBGA) package (27 mm X 27 mm). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE 2 PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 2 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER APPLICATIONS · DCC Processing in SONET/SDH interfaces · Packet-based DSLAM equipment. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE 3 PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 3 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER REFERENCES 1. International Organization for Standardization, ISO Standard 3309-1993, "Information Technology - Telecommunications and information exchange between systems - High-level data link control (HDLC) procedures - Frame structure", December 1993. 2. RFC-1662 RFC-1662 - "PPP in HDLC-like Framing" Internet Engineering Task Force, July 1994. 3. PCI Special Interest Group, PCI Local Bus Specification, June 1, 1995, Version 2.1. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE 4 TCLK[31:0] RBD TD[31:0] Transmit Channel Assigner (TCAS) Transmit HDLC Processor / Partial Packet Buffer (THDL) Transmit DMA Controller (TMAC) Receive DMA Controller (RMAC) JTAG Port PCI Controller (GPIC) RSTB Performance Monitor (PMON) Receive HDLC Processor / Partial Packet Buffer (RHDL) REQB GNTB PERRB SERRB PCIINTB PCICLK PCICLKO SYSCLK AD[31:0] C/BEB[3:0] PAR FRAMEB TRDYB IRDYB STOPB DEVSELB IDSEL LOCKB PMC-1991499 PMC-1991499 RCLK[31:0] RBCLK Receive Channel Assigner (RCAS) 4 RD[31:0] PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER BLOCK DIAGRAM . PMCTEST TDO TDI TCK TMS TRSTB TBCLK TBD PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE 5 PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 5 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER DESCRIPTION The PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 Frame Engine and Datalink Manager device is a monolithic integrated circuit that implements HDLC processing, and PCI Bus memory management functions for a maximum of 32 bi-directional channels. For channelised links, the FREEDM-32P32 FREEDM-32P32 allows up to 32 bi-directional HDLC channels to be assigned to individual time-slots within a maximum of 32 independently timed T1 or E1 links. The channel assignment supports the concatenation of time-slots (N x DS0) up to a maximum of 24 concatenated timeslots for a T1 link and 31 concatenated time-slots for an E1 link. Time-slots assigned to any particular channel need not be contiguous within the T1 or E1 link. For unchannelised links, the FREEDM-32P32 FREEDM-32P32 processes up to 32 bi-directional HDLC channels within 32 independently timed links. The links can be of arbitrary frame format. When limited to two unchannelised links, each link can be rated at up to 45 MHz when SYSCLK is at 25 MHz and at up to 52 MHz when SYSCLK is at 33 MHz. For lower rate unchannelised links, the FREEDM-32P32 FREEDM-32P32 processes up to 32 links, where the aggregate clock rate of all the links is limited to 64 MHz, links 0 to 2 can have a clock rate of up to 45 MHz when SYSCLK is at or above 25 MHz and up to 52 MHz when SYSCLK is at 33 MHz and links 3 to 31 can have a clock rate of up to 10 MHz. The FREEDM-32P32 FREEDM-32P32 supports mixing of up to 32 channelised and unchannelised links. The total number of channels in each direction is limited to 32. The aggregate clock rate over all 32 possible links is limited to 64 MHz. In the receive direction, the FREEDM-32P32 FREEDM-32P32 performs channel assignment and packet extraction and validation. For each provisioned HDLC channel, the FREEDM-32P32 FREEDM-32P32 delineates the packet boundaries using flag sequence detection, and performs bit de-stuffing. Sharing of opening and closing flags, as well as, sharing of zeros between flags are supported. The resulting packet data is placed into the internal 8 kbyte partial packet buffer RAM. The partial packet buffer acts as a logical FIFO for each of the assigned channels. Partial packets are DMA'd out of the RAM, across the PCI bus and into host packet memory. The FREEDM-32P32 FREEDM-32P32 validates the frame check sequence for each packet, and verifies that the packet is an integral number of octets in length and is within a programmable minimum and maximum length. The receive packet status is updated before linking the packet into a receive ready queue. The FREEDM32P32 FREEDM32P32 alerts the PCI Host that there are packets in a receive ready queue by, optionally, asserting an interrupt on the PCI bus. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE 6 PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER Alternatively, in the receive direction, the FREEDM-32P32 FREEDM-32P32 supports a transparent operating mode. For each provisioned transparent channel, the FREEDM32P32 FREEDM32P32 directly transfers the received octets into host memory verbatim. If the transparent channel is assigned to a channelised link, then the octets are aligned to the received time-slots. In the transmit direction, the PCI Host provides packets to transmit using a transmit ready queue. For each provisioned HDLC channel, the FREEDM32P32 FREEDM32P32 DMA's partial packets across the PCI bus and into the transmit partial packet buffer. The partial packets are read out of the packet buffer by the FREEDM-32P32 FREEDM-32P32 and frame check sequence is optionally calculated and inserted at the end of each packet. Bit stuffing is performed before being assigned to a particular link. The flag sequence is automatically inserted when there is no packet data for a particular channel. Sequential packets are optionally separated by two flags (an opening flag and a closing flag) or a single flag (combined opening and closing flag). Zeros between flags are not shared. PCI bus latency may cause one or more channels to underflow, in which case, the packets are aborted, and the host is notified. For normal traffic, an abort sequence is generated, followed by inter-frame time fill characters (flags or all-ones bytes) until a new packet is sourced from the PCI host. No attempt is made to automatically re-transmit an aborted packet. Alternatively, in the transmit direction, the FREEDM-32P32 FREEDM-32P32 supports a transparent operating mode. For each provisioned transparent channel, the FREEDM-32P32 FREEDM-32P32 directly inserts the transmitted octets from host memory. If the transparent channel is assigned to a channelised link, then the octets are aligned to the transmitted time-slots. If a channel underflows due to excessive PCI bus latency, an abort sequence is generated, followed by inter-frame time fill characters (flags or all-ones bytes) to indicate idle channel. Data resumes immediately when the FREEDM-32P32 FREEDM-32P32 receives new data from the host. The FREEDM-32P32 FREEDM-32P32 is configured, controlled and monitored using the PCI bus interface. The FREEDM-32P32 FREEDM-32P32 is implemented in low power CMOS technology. It has TTL compatible inputs and outputs and is packaged in a 272 pin plastic ball grid array (PBGA) package. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE 7 PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 6 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER PIN DIAGRAM The FREEDM-32P32 FREEDM-32P32 is manufactured in a 272 pin Plastic ball grid array package. The center 16 balls are not used as signal I/Os and are thermal balls. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE 8 PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 7 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER PIN DESCRIPTION Table 1 ­ Line Side Interface Signals (132) Pin Name Type Pin No. Function RCLK[0] RCLK[1] RCLK[2] RCLK[3] RCLK[4] RCLK[5] RCLK[6] RCLK[7] RCLK[8] RCLK[9] RCLK[10] RCLK[11] RCLK[12] RCLK[13] RCLK[14] RCLK[15] RCLK[16] RCLK[17] RCLK[18] RCLK[19] RCLK[20] RCLK[21] RCLK[22] RCLK[23] RCLK[24] RCLK[25] RCLK[26] RCLK[27] RCLK[28] RCLK[29] RCLK[30] RCLK[31] Input G1 G3 F2 F3 E2 D1 D2 B4 A4 C6 A5 C7 B7 C8 A8 C9 A9 C10 A10 C11 A12 C12 A13 C13 B14 A15 D14 A16 C16 D16 W17 Y17 The receive line clock signals (RCLK[31:0]) contain the recovered line clock for the 32 independently timed links. Processing of the receive links is on a priority basis, in descending order from RCLK[0] to RCLK[31]. Therefore, the highest rate link should be connected to RCLK[0] and the lowest to RCLK[31]. RD[31:0] is sampled on the rising edge of the corresponding RCLK[31:0] clock. For channelised T1 or E1 links, RCLK[n] must be gapped during the framing bit (for T1 interfaces) or during time-slot 0 (for E1 interfaces) of the RD[n] stream. The FREEDM-32P32 FREEDM-32P32 uses the gapping information to determine the time-slot alignment in the receive stream. RCLK[31:0] is nominally a 50% duty cycle clock of 1.544 MHz for T1 links and 2.048 MHz for E1 links. For unchannelised links, RCLK[n] must be externally gapped during the bits or timeslots that are not part of the transmission format payload (i.e. not part of the HDLC packet). RCLK[2:0] is nominally a 50% duty cycle clock between 0 and 52 MHz. RCLK[31:3] is nominally a 50% duty cycle clock between 0 and 10 MHz. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE 9 PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER Pin Name Type Pin No. Function RD[0] RD[1] RD[2] RD[3] RD[4] RD[5] RD[6] RD[7] RD[8] RD[9] RD[10] RD[11] RD[12] RD[13] RD[14] RD[15] RD[16] RD[17] RD[18] RD[19] RD[20] RD[21] RD[22] RD[23] RD[24] RD[25] RD[26] RD[27] RD[28] RD[29] RD[30] RD[31] Input H3 G2 F1 G4 E1 E3 E4 D5 C5 B5 D7 B6 A6 A7 B8 D9 B9 D10 B10 A11 B11 B12 D12 B13 A14 C14 B15 C15 B16 A17 U16 V16 The receive data signals (RD[31:0]) contain the recovered line data for the 32 independently timed links in normal mode (PMCTEST set low). Processing of the receive links is on a priority basis, in descending order form RD[0] to RD[31]. Therefore, the highest rate link should be connected to RD[0] and the lowest to RD[31]. RBD Tristate Output H1 The receive BERT data signal (RBD) contains the receive bit error rate test data. RBD reports the data on the selected one of the receive data signals (RD[31:0]) and is updated on the falling edge of RBCLK. RBD may be tri-stated by setting the RBEN bit in the FREEDM-32P32 FREEDM-32P32 Master BERT Control register low. For channelised links, RD[n] contains the 24 (T1) or 31 (E1) time-slots that comprise the channelised link. RCLK[n] must be gapped during the T1 framing bit position or the E1 frame alignment signal (time-slot 0). The FREEDM-32P32 FREEDM-32P32 uses the location of the gap to determine the channel alignment on RD[n]. For unchannelised links, RD[n] contains the HDLC packet data. For certain transmission formats, RD[n] may contain place holder bits or time-slots. RCLK[n] must be externally gapped during the place holder positions in the RD[n] stream. The FREEDM-32P32 FREEDM-32P32 supports a maximum data rate of 10 Mbit/s on an individual RD[31:3] link and a maximum data rate of 52 Mbit/s on RD[2:0]. RD[31:0] is sampled on the rising edge of the corresponding RCLK[31:0] clock. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE 10 PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER Pin Name Type Pin No. Function RBCLK Tristate Output H2 The receive BERT clock signal (RBCLK) contains the receive bit error rate test clock. RBCLK is a buffered version of the selected one of the receive clock signals (RCLK[31:0]). RBCLK may be tri-stated by setting the RBEN bit in the FREEDM-32P32 FREEDM-32P32 Master BERT Control register low. TCLK[0] TCLK[1] TCLK[2] TCLK[3] TCLK[4] TCLK[5] TCLK[6] TCLK[7] TCLK[8] TCLK[9] TCLK[10] TCLK[11] TCLK[12] TCLK[13] TCLK[14] TCLK[15] TCLK[16] TCLK[17] TCLK[18] TCLK[19] TCLK[20] TCLK[21] TCLK[22] TCLK[23] TCLK[24] TCLK[25] TCLK[26] TCLK[27] TCLK[28] TCLK[29] TCLK[30] TCLK[31] Input L2 L4 M2 M4 N2 P1 R1 R2 P4 T2 T3 T4 W4 U5 V5 Y5 U7 Y6 W7 V8 Y8 V9 Y9 V10 Y11 V11 Y12 V12 Y13 V13 W14 V14 The transmit line clock signals (TCLK[31:0]) contain the transmit clocks for the 32 independently timed links. Processing of the transmit links is on a priority basis, in descending order from TCLK[0] to TCLK[31]. Therefore, the highest rate link should be connected to TCLK[0] and the lowest to TCLK[31]. TD[31:0] is updated on the falling edge of the corresponding TCLK[31:0] clock. For channelised T1 or E1 links, TCLK[n] must be gapped during the framing bit (for T1 interfaces) or during time-slot 0 (for E1 interfaces) of the TD[n] stream. The FREEDM-32P32 FREEDM-32P32 uses the gapping information to determine the time-slot alignment in the transmit stream. For unchannelised links, TCLK[n] must be externally gapped during the bits or timeslots that are not part of the transmission format payload (i.e. not part of the HDLC packet). TCLK[31:3] is nominally a 50% duty cycle clock between 0 and 10 MHz. TCLK[2:0] is nominally a 50% duty cycle clock between 0 and 52 MHz. Typical values for TCLK[31:0] include 1.544 MHz (for T1 links) and 2.048 MHz (for E1 links). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE 11 PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER Pin Name Type Pin No. Function TD[0] TD[1] TD[2] TD[3] TD[4] TD[5] TD[6] TD[7] TD[8] TD[9] TD[10] TD[11] TD[12] TD[13] TD[14] TD[15] TD[16] TD[17] TD[18] TD[19] TD[20] TD[21] TD[22] TD[23] TD[24] TD[25] TD[26] TD[27] TD[28] TD[29] TD[30] TD[31] Output L1 L3 M1 M3 N1 N3 P2 P3 T1 R3 U1 U2 U3 V4 Y4 W5 V6 W6 V7 Y7 W8 U9 W9 W10 Y10 W11 U11 W12 U12 W13 Y14 Y15 The transmit data signals (TD[31:0]) contains the transmit data for the 32 independently timed links in normal mode (PMCTEST set low). Processing of the transmit links is on a priority basis, in descending order from TD[0] to TD[31]. Therefore, the highest rate link should be connected to TD[0] and the lowest to TD[31]. TBD Input W15 The transmit BERT data signal (TBD) contains the transmit bit error rate test data. When the TBERTEN bit in the BERT Control register is set high, the data on TBD is transmitted on the selected one of the transmit data signals (TD[31:0]). TBD is sampled on the rising edge of TBCLK. For channelised links, TD[n] contains the 24 (T1) or 31 (E1) time-slots that comprise the channelised link. TCLK[n] must be gapped during the T1 framing bit position or the E1 frame alignment signal (time-slot 0). The FREEDM-32P32 FREEDM-32P32 uses the location of the gap to determine the channel alignment on TD[n]. For unchannelised links, TD[n] contains the HDLC packet data. For certain transmission formats, TD[n] may contain place holder bits or time-slots. TCLK[n] must be externally gapped during the place holder positions in the TD[n] stream. The FREEDM-32P32 FREEDM-32P32 supports a maximum data rate of 10 Mbit/s on an individual TD[31:3] link and a maximum data rate of 52 Mbit/s on TD[2:0] TD[31:0] is updated on the falling edge of the corresponding TCLK[31:0] clock. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE 12 PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER Pin Name Type Pin No. Function TBCLK Tristate Output Y16 The transmit BERT clock signal (TBCLK) contains the transmit bit error rate test clock. TBCLK is a buffered version of the selected one of the transmit clock signals (TCLK[31:0]). TBCLK may be tri-stated by setting the TBEN bit in the FREEDM-32P32 FREEDM-32P32 Master BERT Control register low. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE 13 PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER Table 2 ­ PCI Host Interface Signals (51) Pin Name Type Pin No. Function PCICLK Input B17 The PCI clock signal (PCICLK) provides timing for PCI bus accesses. PCICLK is a nominally 50% duty cycle, 0 to 33 MHz clock. PCICLKO Output C17 The PCI clock output signal (PCICLKO) is a buffered version of the PCICLK. PCICLKO may be used to drive the SYSCLK input. AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6] AD[7] AD[8] AD[9] AD[10] AD[11] AD[12] AD[13] AD[14] AD[15] AD[16] AD[17] AD[18] AD[19] AD[20] AD[21] AD[22] AD[23] AD[24] AD[25] AD[26] AD[27] AD[28] AD[29] AD[30] I/O U19 U18 T17 U20 T18 T19 T20 R18 R20 P18 P19 P20 N18 N19 N20 M17 J19 J18 J17 H20 H19 H18 G20 G19 F19 E20 G17 F18 E19 D20 E18 The PCI address and data bus (AD[31:0]) carries the PCI bus multiplexed address and data. During the first clock cycle of a transaction, AD[31:0] contains a physical byte address. During subsequent clock cycles of a transaction, AD[31:0] contains data. A transaction is defined as an address phase followed by one or more data phases. When Little-Endian byte formatting is selected, AD[31:24] contain the most significant byte of a DWORD while AD[7:0] contain the least significant byte. When Big-Endian byte formatting is selected. AD[7:0] contain the most significant byte of a DWORD while AD[31:24] contain the least significant byte. When the FREEDM-32P32 FREEDM-32P32 is the initiator, AD[31:0] is an output bus during the first (address) phase of a transaction. For write transactions, AD[31:0] remains an output bus for the data phases of the transaction. For read transactions, AD[31:0] is an input bus during the data phases. When the FREEDM-32P32 FREEDM-32P32 is the target, AD[31:0] is an input bus during the first (address) phase of a transaction. For write transactions, AD[31:0] remains an input bus during the data phases of the transaction. For read transactions, AD[31:0] is an output bus during the data phases. When the FREEDM-32P32 FREEDM-32P32 is not involved in the current transaction, AD[31:0] is tri-stated. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE 14 PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER Pin Name Type Pin No. Function AD[31] I/O D19 As an output bus, AD[31:0] is updated on the rising edge of PCICLK. As an input bus, AD[31:0] is sampled on the rising edge of PCICLK. C/BEB[0] C/BEB[1] C/BEB[2] C/BEB[3] I/O R19 M18 J20 G18 The PCI bus command and byte enable bus (C/BEB[3:0]) contains the bus command or the byte valid indications. During the first clock cycle of a transaction, C/BEB[3:0] contains the bus command code. For subsequent clock cycles, C/BEB[3:0] identifies which bytes on the AD[31:0] bus carry valid data. C/BEB[3] is associated with byte 3 (AD[31:24]) while C/BEB[0] is associated with byte 0 (AD[7:0]). When C/BEB[n] is set high, the associated byte is invalid. When C/BEB[n] is set low, the associated byte is valid. When the FREEDM-32P32 FREEDM-32P32 is the initiator, C/BEB[3:0] is an output bus. When the FREEDM-32P32 FREEDM-32P32 is the target, C/BEB[3:0] is an input bus. When the FREEDM-32P32 FREEDM-32P32 is not involved in the current transaction, C/BEB[3:0] is tri-stated. As an output bus, C/BEB[3:0] is updated on the rising edge of PCICLK. As an input bus, C/BEB[3:0] is sampled on the rising edge of PCICLK. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE 15 PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER Pin Name Type Pin No. Function PAR I/O M19 The parity signal (PAR) indicates the parity of the AD[31:0] and C/BEB[3:0] buses. Even parity is calculated over all 36 signals in the buses regardless of whether any or all the bytes on the AD[31:0] are valid. PAR always reports the parity of the previous PCICLK cycle. Parity errors detected by the FREEDM-32P32 FREEDM-32P32 are indicated on output PERRB and in the FREEDM-32P32 FREEDM-32P32 Interrupt Status register. When the FREEDM-32P32 FREEDM-32P32 is the initiator, PAR is an output for writes and an input for reads. When the FREEDM-32P32 FREEDM-32P32 is the target, PAR is an input for writes and an output for reads. When the FREEDM-32P32 FREEDM-32P32 is not involved in the current transaction, PAR is tri-stated. As an output signal, PAR is updated on the rising edge of PCICLK. As an input signal, PAR is sampled on the rising edge of PCICLK. FRAMEB I/O K17 The active low cycle frame signal (FRAMEB) identifies a transaction cycle. When FRAMEB transitions low, the start of a bus transaction is indicated. FRAMEB remains low to define the duration of the cycle. When FRAMEB transitions high, the last data phase of the current transaction is indicated. When the FREEDM-32P32 FREEDM-32P32 is the initiator, FRAMEB is an output. When the FREEDM-32P32 FREEDM-32P32 is the target, FRAMEB is an input. When the FREEDM-32P32 FREEDM-32P32 is not involved in the current transaction, FRAMEB is tri-stated. As an output signal, FRAMEB is updated on the rising edge of PCICLK. As an input signal, FRAMEB is sampled on the rising edge of PCICLK. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE 16 PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER Pin Name Type Pin No. Function TRDYB I/O K19 The active low target ready signal (TRDYB) indicates when the target is ready to start or continue with a transaction. TRDYB works in conjunction with IRDYB to complete transaction data phases. During a transaction in progress, TRDYB is set high to indicate that the target cannot complete the current data phase and to force a wait state. TRDYB is set low to indicate that the target can complete the current data phase. The data phase is completed when TRDYB is set low and the initiator ready signal (IRDYB) is also set low. When the FREEDM-32P32 FREEDM-32P32 is the initiator, TRDYB is an input. When the FREEDM-32P32 FREEDM-32P32 is the target, TRDYB is an output. During accesses to FREEDM-32P32 FREEDM-32P32 registers, TRDYB is set high to extend data phases over multiple PCICLK cycles. When the FREEDM-32P32 FREEDM-32P32 is not involved in the current transaction, TRDYB is tri-stated. As an output signal, TRDYB is updated on the rising edge of PCICLK. As an input signal, TRDYB is sampled on the rising edge of PCICLK. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE 17 PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER Pin Name Type Pin No. Function IRDYB I/O K18 The active low initiator ready (IRDYB) signal is used to indicate whether the initiator is ready to start or continue with a transaction. IRDYB works in conjunction with TRDYB to complete transaction data phases. When IRDYB is set high and a transaction is in progress, the initiator is indicating it cannot complete the current data phase and is forcing a wait state. When IRDYB is set low and a transaction is in progress, the initiator is indicating it has completed the current data phase. The data phase is completed when IRDYB is set low and the target ready signal (IRDYB) is also set low. When the FREEDM-32P32 FREEDM-32P32 is the initiator, IRDYB is an output. When the FREEDM-32P32 FREEDM-32P32 is the target, IRDYB is an input. When the FREEDM-32P32 FREEDM-32P32 is not involved in the current transaction, IRDYB is tri-stated. IRDYB is updated on the rising edge of PCICLK or sampled on the rising edge of PCICLK depending on whether it is an output or an input. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE 18 PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER Pin Name Type Pin No. Function STOPB I/O L20 The active low stop signal (STOPB) requests the initiator to stop the current bus transaction. When STOPB is set high by a target, the initiator continues with the transaction. When STOPB is set low, the initiator will stop the current transaction. When the FREEDM-32P32 FREEDM-32P32 is the initiator, STOPB is an input. When STOPB is sampled low, the FREEDM-32P32 FREEDM-32P32 will terminate the current transaction in the next PCICLK cycle. When the FREEDM-32P32 FREEDM-32P32 is the target, STOPB is an output. The FREEDM-32P32 FREEDM-32P32 only issues transaction stop requests when responding to reads and writes to configuration space (disconnecting after 1 DWORD transferred) or if an initiator introduces wait states during a transaction. When the FREEDM-32P32 FREEDM-32P32 is not involved in the current transaction, STOPB is tri-stated. STOPB is updated on the rising edge of PCICLK or sampled on the rising edge of PCICLK depending on whether it is an output or an input. IDSEL Input F20 The initialization device select signal (IDSEL) enables read and write access to the PCI configuration registers. When IDSEL is set high during the address phase of a transaction and the C/BEB[3:0] code indicates a register read or write, the FREEDM-32P32 FREEDM-32P32 performs a PCI configuration register transaction and asserts the DEVSELB signal in the next PCICLK period. IDSEL is sampled on the rising edge of PCICLK. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE 19 PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER Pin Name Type Pin No. Function DEVSELB I/O K20 The active low device select signal (DEVSELB) indicates that a target claims the current bus transaction. During the address phase of a transaction, all targets decode the address on the AD[31:0] bus. When a target, recognizes the address as its own, it sets DEVSELB low to indicate to the initiator that the address is valid. If no target claims the address in six bus clock cycles, the initiator assumes that the target does not exist or cannot respond and aborts the transaction. When the FREEDM-32P32 FREEDM-32P32 is the initiator, DEVSELB is an input. If no target responds to an address in six PCICLK cycles, the FREEDM32P32 FREEDM32P32 will abort the current transaction and alerts the PCI Host via an interrupt. When the FREEDM-32P32 FREEDM-32P32 is the target, DEVSELB is an output. DELSELB is set low when the address on AD[31:0] is recognised. When the FREEDM-32P32 FREEDM-32P32 is not involved in the current transaction, DEVSELB is tri-stated. FREEDM-32P32 FREEDM-32P32 is updated on the rising edge of PCICLK or sampled on the rising edge of PCICLK depending on whether it is an output or an input. LOCKB Input L18 The active low bus lock signal (LOCKB) locks a target device. When LOCKB and FRAME are set low, and the FREEDM-32P32 FREEDM-32P32 is the target, an initiator is locking the FREEDM-32P32 FREEDM-32P32 as an "owned" target. Under these circumstances, the FREEDM-32P32 FREEDM-32P32 will reject all transaction with other initiators. The FREEDM-32P32 FREEDM-32P32 will continue to reject other initiators until its owner releases the lock by forcing both FRAMEB and LOCKB high. As a initiator, the FREEDM32P32 FREEDM32P32 will never lock a target. LOCKB is sampled using the rising edge of PCICLK. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE 20 PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER Pin Name Type Pin No. Function REQB Output E17 The active low PCI bus request signal (REQB) requests an external arbiter for control of the PCI bus. REQB is set low when the FREEDM32P32 FREEDM32P32 desires access to the host memory. REQB is set high when access is not desired. REQB is updated on the rising edge of PCICLK. GNTB Input D18 The active low PCI bus grant signal (GNTB) indicates the granting of control over the PCI in response to a bus request via the REQB output. When GNTB is set high, the FREEDM-32P32 FREEDM-32P32 does not have control over the PCI bus. When GNTB is set low, the external arbiter has granted the FREEDM-32P32 FREEDM-32P32 control over the PCI bus. However, the FREEDM-32P32 FREEDM-32P32 will not proceed until the FRAMEB signal is sampled high, indicating no current transactions are in progress. GNTB is sampled on the rising edge of PCICLK. PCIINTB OD Output W16 The active low PCI interrupt signal (PCIINTB) is set low when a FREEDM-32P32 FREEDM-32P32 interrupt source is active, and that source is unmasked. The FREEDM-32P32 FREEDM-32P32 may be enabled to report many alarms or events via interrupts. PCIINTB returns high when the interrupt is acknowledged via an appropriate register access. PCIINTB is an open drain output and is updated on the rising edge of PCICLK. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE 21 PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER Pin Name Type Pin No. Function PERRB I/O L19 The active low parity error signal (PERRB) indicates a parity error over the AD[31:0] and C/BEB[3:0] buses. Parity error is signalled when even parity calculations do not match the PAR signal. PERRB is set low at the cycle immediately following an offending PAR cycle. PERRB is set high when no parity error is detected. PERRB is enabled by setting the PERREN bit in the Control/Status register in the PCI Configuration registers space. Regardless of the setting of PERREN, parity errors are always reported by the PERR bit in the Control/Status register in the PCI Configuration registers space. PERRB is updated on the rising edge of PCICLK. SERRB OD Output M20 The active low system error signal (SERRB) indicates an address parity error. Address parity errors are detected when the even parity calculations during the address phase do not match the PAR signal. When the FREEDM32P32 FREEDM32P32 detects a system error, SERRB is set low for one PCICLK period. SERRB is enabled by setting the SERREN bit in the Control/Status register in the PCI Configuration registers space. Regardless of the setting of SERREN, parity errors are always reported by the SERR bit in the Control/Status register in the PCI Configuration registers space. SERRB is an open drain output and is updated on the rising edge of PCICLK. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE 22 PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER Table 3 ­ Miscellaneous Interface Signals (41) Pin Name Type Pin No. Function SYSCLK Input J4 The system clock (SYSCLK) provides timing for the core logic. SYSCLK is nominally a 50% duty cycle 25 MHz to 33 MHz clock. RSTB Input U14 The active low reset signal (RSTB) signal provides an asynchronous FREEDM-32P32 FREEDM-32P32 reset. RSTB is an asynchronous input. When RSTB is set low, all FREEDM-32P32 FREEDM-32P32 registers are forced to their default states. In addition, TD[31:0] are forced high and all PCI output pins are forced tri-state and will remain high or tri-stated, respectively, until RSTB is set high. PMCTEST Input V15 The PMC production test enable signal (PMCTEST) places the FREEDM-32P32 FREEDM-32P32 is test mode. When PMCTEST is set high, production test vectors can be executed to verify manufacturing via the test mode interface signals TA[10:0], TA[11]/TRS, TRDB, TWRB and TDAT[15:0]. PMCTEST must be tied low in normal operation. TCK Input K2 The test clock signal (TCK) provides timing for test operations that can be carried out using the IEEE P1149 P1149.1 test access port. TMS and TDI are sampled on the rising edge of TCK. TDO is updated on the falling edge of TCK. TMS Input J1 The test mode select signal (TMS) controls the test operations that can be carried out using the IEEE P1149 P1149.1 test access port. TMS is sampled on the rising edge of TCK. TMS has an integral pull up resistor. TDI Input K3 The test data input signal (TDI) carries test data into the FREEDM-32P32 FREEDM-32P32 via the IEEE P1149 P1149.1 test access port. TDI is sampled on the rising edge of TCK. TDI has an integral pull up resistor. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE 23 PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 ISSUE 2 Pin No. FRAME ENGINE AND DATA LINK MANAGER Pin Name Type TDO Tristate K1 Output The test data output signal (TDO) carries test data out of the FREEDM-32P32 FREEDM-32P32 via the IEEE P1149 P1149.1 test access port. TDO is updated on the falling edge of TCK. TDO is a tri-state output which is inactive except when scanning of data is in progress. TRSTB Input The active low test reset signal (TRSTB) provides an asynchronous FREEDM-32P32 FREEDM-32P32 test access port reset via the IEEE P1149 P1149.1 test access port. TRSTB is an asynchronous input with an integral pull up resistor. J3 Function Note that when TRSTB is not being used, it must be connected to the RSTB input. VBIAS[3:1] Input J2 B19 W19 The bias signals (VBIAS[3:1]) provide 5 Volt bias to input and I/O pads to allow the FREEDM32P32 FREEDM32P32 to tolerate connections to 5 Volt devices. To avoid damage to the device, the VBIAS[3:1] signals must be connected together externally and must at all times be kept at a voltage that is equal to or higher than the VDD[28:1] power supplies. In a 3.3V operating environment, VBIAS[3:1] and VDD[28:1] may be connected together. In a 5V operating environment, VBIAS[3:1] should be powered up to 5V before VDD[28:1] are powered up to 3.3V. EN5V Input C4 The 5 Volt PCI signalling enable signal (EN5V) causes the PCI Host Interface Signals to operate in the 5V PCI signalling environment when set high and the 3.3V PCI signalling environment when set low. EN5V is an asynchronous input with an integral pull up resistor. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE 24 PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER Pin Name Type Pin No. Function NC Open A2 A3 A18 A19 B1 B2 B3 B18 B20 C1 C2 C19 C20 D3 P17 V1 V2 V17 V19 V20 W1 W2 W3 W18 W20 Y2 Y3 Y18 Y19 These pins must be left unconnected. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE 25 PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER Table 4 ­ Production Test Interface Signals (0 - Multiplexed) Pin Name Type Pin No. Function TA[0] TA[1] TA[2] TA[3] TA[4] TA[5] TA[6] TA[7] TA[8] TA[9] TA[10] Input The test mode address bus (TA[10:0]) selects specific registers during production test (PMCTEST set high) read and write accesses. TA[10:0] replace RD[20:10] when PMCTEST is set high. TA[11]/TR S Input The test register select signal (TA[11]/TRS) selects between normal and test mode register accesses during production test (PMCTEST set high). TRS is set high to select test registers and is set low to select normal registers. TA[11]/TRS replaces RD[21] when PMCTEST is set high. TRDB Input The test mode read enable signal (TRDB) is set low during FREEDM-32P32 FREEDM-32P32 register read accesses during production test (PMCTEST set high). The FREEDM-32P32 FREEDM-32P32 drives the test data bus (TDAT[15:0]) with the contents of the addressed register while TRDB is low. TRDB replaces RD[22] when PMCTEST is set high. TWRB Input The test mode write enable signal (TWRB) is set low during FREEDM-32P32 FREEDM-32P32 register write accesses during production test (PMCTEST set high). The contents of the test data bus (TDAT[15:0]) are clocked into the addressed register on the rising edge of TWRB. TWRB replaces RD[23] when PMCTEST is set high. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE 26 PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 ISSUE 2 Pin Name Type TDAT[0] TDAT[1] TDAT[2] TDAT[3] TDAT[4] TDAT[5] TDAT[6] TDAT[7] TDAT[8] TDAT[9] TDAT[10] TDAT[11] TDAT[12] TDAT[13] TDAT[14] TDAT[15] Pin No. I/O FRAME ENGINE AND DATA LINK MANAGER Function The bi-directional test mode data bus (TDAT[15:0]) carries data read from or written to FREEDM-32P32 FREEDM-32P32 registers during production test. TDAT[15:0] replace TD[31:16] when PMCTEST is set high. Table 5 ­ Power and Ground Signals (60) Pin Name Type Pin No. Function VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD10 VDD11 VDD11 VDD12 VDD12 VDD13 VDD13 VDD14 VDD14 VDD15 VDD15 VDD16 VDD16 Power C3 C18 D6 D11 D15 F4 F17 K4 L17 R4 R17 U6 U10 U15 V3 V18 The DC power pins should be connected to a well decoupled +3.3 V DC supply. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE 27 PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER Pin Name Type Pin No. Function VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS10 VSS11 VSS11 VSS12 VSS12 VSS13 VSS13 VSS14 VSS14 VSS15 VSS15 VSS16 VSS16 VSS17 VSS17 VSS18 VSS18 VSS19 VSS19 VSS20 VSS20 VSS21 VSS21 VSS22 VSS22 VSS23 VSS23 VSS24 VSS24 VSS25 VSS25 VSS26 VSS26 VSS27 VSS27 VSS28 VSS28 VSS29 VSS29 VSS30 VSS30 VSS31 VSS31 VSS32 VSS32 Ground A1 A20 D4 D8 D13 D17 H4 H17 J9 J10 J11 J12 K9 K10 K11 K12 L9 L10 L11 L12 M9 M10 M11 M12 N4 N17 U4 U8 U13 U17 Y1 Y20 The DC ground pins should be connected to ground. Notes on Pin Description: 1. All FREEDM-32P32 FREEDM-32P32 inputs and bi-directionals present minimum capacitive loading and operate at TTL compatible logic levels. PCI signals conform to the 3.3 or 5 Volt signaling environment depending on the setting of the EN5V input. 2. Most FREEDM-32P32 FREEDM-32P32 non-PCI digital outputs and bi-directionals have 4 mA drive capability, except the PCICLKO, RBCLK, TBCLK, RBD and PCIINTB PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE 28 PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER outputs which have 6 mA drive capability and the TD[0], TD[1], and TD[2] outputs which have 8 mA drive capability. 3. All FREEDM-32P32 FREEDM-32P32 non-PCI digital outputs and bi-directionals are 5 V tolerant when tristated except those with 8 mA drive capability, i.e. TD[2:0]. (TD[2:0] are never tristated in normal operation ­ only under JTAG boundary scan control.) 4. Inputs TMS, TDI, TRSTB and EN5V are Schmitt triggered and have internal pull-up resistors. 5. Inputs RD[31:0], RCLK[31:0], TCLK[31:0], SYSCLK, PCICLK, TBD, RSTB, GNTB, IDSEL, LOCKB, TCK and PMCTEST are Schmitt triggered. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE 29 PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 8 8.1 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER FUNCTIONAL DESCRIPTION High-Level Data Link Control Protocol Figure 1 shows a diagram of the synchronous HDLC protocol supported by the FREEDM-32P32 FREEDM-32P32. The incoming stream is examined for flag bytes (01111110 bit pattern) which delineate the opening and closing of the HDLC packet. The packet is bit de-stuffed which discards a "0" bit which directly follows five contiguous "1" bits. The resulting HDLC packet size must be a multiple of an octet (8 bits) and within the expected minimum and maximum packet length limits. The minimum packet length is that of a packet containing two information bytes (address and control) and FCS bytes. For packets with CRC-CCITT as FCS, the minimum packet length is four bytes while those with CRC-32 CRC-32 as FCS, the minimum length is six bytes. An HDLC packet is aborted when seven contiguous "1" bits (with no inserted "0" bits) are received. At least one flag byte must exist between HDLC packets for delineation. Contiguous flag bytes, or all ones bytes between packets are used as an "inter-frame time fill". Adjacent flag bytes may share zeros. Figure 1 ­ HDLC Frame Flag Information FCS Flag Flag HDLC Packet The CRC algorithm for the frame checking sequence (FCS) field is either a CRC-CCITT or CRC-32 CRC-32 function. Figure 2 shows a CRC encoder block diagram using the generating polynomial g(X) = 1 + g1X + g2X2 +.+ gn-1Xn-1 + Xn. The CRC-CCITT FCS is two bytes in size and has a generating polynomial g(X) = 1 + X5 + X12 + X16. The CRC-32 CRC-32 FCS is four bytes in size and has a generating polynomial g(X) = 1 + X + X2 + X4 + X5 + X7 + X8 + X10 + X11 + X12 + X16 + X22 + X23 + X26 + X32. The first FCS bit received is the residue of the highest term. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE 30 PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER Figure 2 ­ CRC Generator g1 D0 g2 D1 LSB 8.2 gn-1 D2 Parity Check Digits Message Dn-1 MSB Receive Channel Assigner The Receive Channel Assigner block (RCAS) processes up to 32 serial links. Each link is independent and has its own associated clock. For each link, the RCAS performs a serial to parallel conversion to form data bytes. The data bytes are multiplexed, in byte serial format, for delivery to the Receive HDLC Processor / Partial Packet Buffer block (RHDL) at SYSCLK rate. In the event where multiple streams have accumulated a byte of data, multiplexing is performed on a fixed priority basis with link #0 having the highest priority and link #31 the lowest. Links containing a T1 or an E1 stream may be channelised. Data at each timeslot may be independently assigned to a different channel. The RCAS performs a table lookup to associate the link and time-slot identity with a channel. T1 and E1 framing bits/bytes are identified by observing the gap in the link clock which is squelched during the framing bits/bytes. For unchannelised links, clock rates are limited to 52 MHz on link #0 to #2 and limited to 10 MHz for the remaining links. All data on each link belongs to one channel. For the case of two unchannelised links, the maximum link rate is 45 MHz for SYSCLK at 25 MHz and 52 MHz for SYSCLK at 33 MHz. For the case of more numerous unchannelised links or a mixture of channelise with unchannelised links, the total instantaneous link rate over all the links is limited to 64 MHz. The RCAS performs a table lookup using only the link number to determine the associated channel, as time-slots are non-existent in unchannelised links. The RCAS provides diagnostic loopback that is selectable on a per channel basis. When a channel is in diagnostic loopback, stream data on the received links originally destined for that channel is ignored. Transmit data of that channel is substituted in its place. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE 31 PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER 8.2.1 Line Interface There are 32 identical line interface blocks in the RCAS. Each line interface contains a bit counter, an 8-bit shift register and a holding register, that, together, perform serial to parallel conversion. Whenever the holding register is updated, a request for service is sent to the priority encoder block. When acknowledged by the priority encoder, the line interface would respond with the data residing in the holding register. To support channelised links, each line interface block contains a time-slot counter and a clock activity monitor. The time-slot counter is incremented each time the holding register is updated. The clock activity monitor is a counter that increments at the system clock (SYSCLK) rate and is cleared by a rising edge of the receive clock (RCLK[n]). A framing bit (T1) or framing byte (E1) is detected when the counter reaches a programmable threshold. In which case, the bit and time-slot counters are initialised to indicate that the next bit is the most significant bit of the first time-slot. For unchannelised links, the time-slot counter and the clock activity monitor are held reset. 8.2.2 Priority Encoder The priority encoder monitors the line interfaces for requests and synchronises them to the SYSCLK timing domain. Requests are serviced on a fixed priority scheme where highest to lowest priority is assigned from the line interface attached to RD[0] to that attached to RD[31]. Thus, simultaneous requests from RD[m] will be serviced ahead of RD[n], if m < n. When there are no pending requests, the priority encoder generates an idle cycle. In addition, once every fourth SYSCLK cycle, the priority encoder inserts a null cycle where no requests are serviced. This cycle is used by the channel assigner downstream for host microprocessor accesses to the provisioning RAMs. 8.2.3 Channel Assigner The channel assigner block determines the channel number of the data byte currently being processed. The block contains a 1024 word channel provision RAM. The address of the RAM is constructed from concatenating the link number and the time-slot number of the current data byte. The fields of each RAM word include the channel number and a time-slot enable flag. The time-slot enable flag labels the current time-slot as belonging to the channel indicted by the channel number field. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE 32 PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER 8.2.4 Loopback Controller The loopback controller block implements the channel based diagnostic loopback function. Every valid data byte belonging to a channel with diagnostic loopback enabled from the Transmit HDLC Processor / Partial Packet Buffer block (THDL) is written into a 64 word FIFO. The loopback controller monitors for an idle time-slot or a time-slot carrying a channel with diagnostic loopback enabled. If either conditions hold, the current data byte is replaced by data retrieved from the loopback data FIFO. 8.3 Receive HDLC Processor / Partial Packet Buffer The Receive HDLC Processor / Partial Packet Buffer block (RHDL) processes up to 32 synchronous transmission HDLC data streams. Each channel can be individually configured to perform flag sequence detection, bit de-stuffing and CRC-CCITT or CRC-32 CRC-32 verification. The packet data is written into the partial packet buffer. At the end of a frame, packet status including CRC error, octet alignment error and maximum length violation are also loaded into the partial packet buffer. Alternatively, a channel can be provisioned as transparent, in which case, the HDLC data stream is passed to the partial packet buffer processor verbatim. There is a natural precedence in the alarms detectable on a receive packet. Once a packet exceeds the programmable maximum packet length, no further processing is performed on it. Thus, octet alignment detection, FCS verification and abort recognition are squelched on packets with a maximum length violation. An abort indication squelches octet alignment detection, minimum packet length violations, and FCS verification. In addition, FCS verification is only performed on packets that do not have octet alignment errors, in order to allow the RHDL to perform CRC calculations on a byte-basis. The partial packet buffer is an 8 Kbyte RAM that is divided into 16-byte blocks. Each block has an associated pointer which points to another block. A logical FIFO is created for each provisioned channel by programming the block pointers to form a circular linked list. A channel FIFO can be assigned a minimum of 3 blocks (48 bytes) and a maximum of 512 blocks (8 Kbytes). The depth of the channel FIFOs are monitored in a round-robin fashion. Requests are made to the Receive DMA Controller block (RMAC) to transfer, to the PCI host memory, data in channel FIFOs with depths exceeding their associated threshold. 8.3.1 HDLC Processor The HDLC processor is a time-slice state machine which can process up to 32 independent channels. The state vector and provisioning information for each PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE 33 PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER channel is stored in a RAM. Whenever new channel data arrives, the appropriate state vector is read from the RAM, processed and written back to the RAM. The HDLC state-machine can be configured to perform flag delineation, bit de-stuffing, CRC verification and length monitoring. The resulting HDLC data and status information is passed to the partial packet buffer processor to be stored in the appropriate channel FIFO buffer. The configuration of the HDLC processor is accessed using indirect channel read and write operations. When an indirect operation is performed, the information is accessed from RAM during a null clock cycle generated by the upstream Receive Channel Assigner block (RCAS). Writing new provisioning data to a channel resets the channel's entire state vector. 8.3.2 Partial Packet Buffer Processor The partial packet buffer processor controls the 8 Kbyte partial packet RAM which is divided into 16 byte blocks. A block pointer RAM is used to chain the partial packet blocks into circular channel FIFO buffers. Thus, non-contiguous sections of the RAM can be allocated in the partial packet buffer RAM to create a channel FIFO. System software is responsible for the assignment of blocks to individual channel FIFOs. Figure 3 shows an example of three blocks (blocks 1, 3, and 200) linked together to form a 48 byte channel FIFO. The partial packet buffer processor is divided into three sections: writer, reader and roamer. The writer is a time-sliced state machine which writes the HDLC data and status information from the HDLC processor into a channel FIFO in the packet buffer RAM. The reader transfers channel FIFO data from the packet buffer RAM to the downstream Receive DMA Controller block (RMAC). The roamer is a time-sliced state machine which tracks channel FIFO buffer depths and signals the reader to service a particular channel. If a buffer over-run occurs, the writer ends the current packet from the HDLC processor in the channel FIFO with an over-run flag and ignores the rest of the packet. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE 34 PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER Figure 3 ­ Partial Packet Buffer Structure Partial Packet Buffer RAM Block Pointer RAM Block 0 16 bytes Block 0 XX Block 1 16 bytes Block 1 0x03 Block 2 16 bytes Block 2 XX Block 3 16 bytes Block 3 0xC8 Block 200 16 bytes Block 200 0x01 Block 511 16 bytes Block 511 XX The FIFO algorithm of the partial packet buffer processor is based on a programmable per-channel transfer size. Instead of tracking the number of full blocks in a channel FIFO, the processor tracks the number of transactions. Whenever the partial packet writer fills a transfer-sized number of blocks or writes an end-of-packet flag to the channel FIFO, a transaction is created. Whenever the partial packet reader transmits a transfer-size number of blocks or an end-of-packet flag to the RMAC block, a transaction is deleted. Thus, small packets less than the transfer size will be naturally transferred to the RMAC block without having to precisely track the number of full blocks in the channel FIFO. The partial packet roamer performs the transaction accounting for all channel FIFOs. The roamer increments the transaction count when the writer signals a new transaction and sets a per-channel flag to indicate a non-zero transaction count. The roamer searches the flags in a round-robin fashion to decide for which channel FIFO to request transfer by the RMAC block. The roamer informs the partial packet reader of the channel to process. The reader transfers the data to the RMAC until the channel transfer size is reached or an end of packet PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE 35 PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER is detected. The reader then informs the roamer that a transaction is consumed. The roamer updates its transaction count and clears the non-zero transaction count flag if required. The roamer then services the next channel with its transaction flag set high. The writer and reader determine empty and full FIFO conditions using flags. Each block in the partial packet buffer has an associated flag. The writer sets the flag after the block is written and the reader clears the flag after the block is read. The flags are initialized (cleared) when the block pointers are written using indirect block writes. The writer declares a channel FIFO overrun whenever the writer tries to store data to a block with a set flag. In order to support optional removal of the FCS from the packet data, the writer does not declare a block as filled (set the block flag nor increment the transaction count) until the first double word of the next block in channel FIFO is filled. If the end of a packet resides in the first double word, the writer declares both blocks as full at the same time. When the reader finishes processing a transaction, it examines the first double word of the next block for the end-of-packet flag. If the first double word of the next block contains only FCS bytes, the reader would, optionally, process next transaction (end-of-packet) and consume the block, as it contains information not transferred to the RMAC block. 8.4 Receive DMA Controller The Receive DMA Controller block (RMAC) is a DMA controller which stores received packet data in host computer memory. The RMAC is not directly connected to the host memory PCI bus. Memory accesses are serviced by a downstream PCI controller block (GPIC). The RMAC and the host exchange information using receive packet descriptors (RPDs). The descriptor contains the size and location of buffers in host memory and the packet status information associated with the data in each buffer. RPDs are transferred from the RMAC to the host and vice versa using descriptor reference queues. The RMAC maintains all the pointers for the operation of the queues. The RMAC provides two receive packet descriptor reference (RPDR) free queues to support small and large buffers. The RMAC acquires free buffers by reading RPDRs from the free queues. After a packet is received, the RMAC places the associated RPDR onto a RPDR ready queue. To minimise host bus accesses, the RMAC maintains a descriptor reference table to store current DMA information. This table contains separate DMA information entries for up to 32 receive channels. 8.4.1 Data Structures For packet data, the RMAC communicates with the host using Receive Packet Descriptors (RPD), Receive Packet Descriptor References (RPDR), the Receive PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE 36 PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER Packet Descriptor Reference Ready (RPDRR) queue and the Receive Packet Descriptor Reference Small and Large Buffer Free (RPDRF) queues. The RMAC copies packet data to data buffers in host memory. The RPD, RPDR, RPDRR queue, and Small and Large RPDRF queues are data structures which are used to transfer host memory data buffer information. All five data structures are manipulated by both the RMAC and the host computer. The RPD holds the data buffer size, data buffer address, and packet status information. The RPDR is a pointer which is used to index into a table of RPDs. The RPDRR queue and RPDRF queues allow the RMAC and the host to pass RPDRs back and forth. These data structures are described in more detail in the following sections. Receive Packet Descriptor The Receive Packet Descriptors (RPDs) pass buffer and packet information between the RMAC and the host. Both the RMAC and the host read and write information in the RPDs. The host writes RPD fields which describe the size and address of data buffers in host memory. The RMAC writes RPD fields which provide number of bytes used in each data buffer, RPD link information, and the status of the received packet. RPDs are stored in host memory in a Receive Packet Descriptor Table which is described in a later section. The Receive Packet Descriptor structure is shown in Figure 4. Figure 4 ­ Receive Packet Descriptor Bit 31 0 Data Buffer Start Address [31:0] Bytes In Buffer [15:0] Status [5:0] Reserved (18) Reserved (16) Offset[1:0] CE RCC [6:0] Next RPD Pointer [13:0] Receive Buffer Size [15:0] Table 6 ­ Receive Packet Descriptor Fields Field Data Buffer Start Address[31:0] Description The Data Buffer Start Address[31:0] bits point to the data buffer in host memory. This field is expected to be configured by the Host during initialisation. The Data Buffer Start Address field is valid in all RPDs. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE 37 PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 ISSUE 2 Field RCC[6:0] FRAME ENGINE AND DATA LINK MANAGER Description The Receive Channel Code (RCC[6:0]) bits are used by the RMAC to indicate which channel an RPD is associated with. Legal values for this field are 0 to 31. For a linked list of RPDs, all the RPDs' RCC fields are valid, i.e. all contain the same channel value. CE The Chain End (CE) bit indicates the end of a linked list of RPDs. When CE is set to logic one, the current RPD is the last RPD of a linked list of RPDs. When CE is set to logic zero, the current RPD is not the last RPD of a linked list. The CE bit is valid for all RPDs written by the RMAC to the Receive Ready Queue. When a packet requires only one RPD, the CE bit is set to logic one. The CE bit is ignored for all RPDs read by the RMAC from the Receive Free Queues, each of which is assumed to point to only one buffer, i.e. not a chain. Offset[1:0] The Offset[1:0] bits indicate the byte offset of the data packet from the start of the buffer. If this value is nonzero, there will be `dummy' (i.e. undefined) bytes at the start of the data buffer prior to the packet data proper. For a linked list of RPDs, only the first RPD's Offset field is valid. All other RPD Offset fields of the linked list are set to 0. Status [5:0] The Status[5:0] bits indicate the status of the received packet. Status[0] Status[1] Status[2] Status[3] Status[4] Status[5] Rx buffer overrun Packet exceeds max. allowed size CRC error Packet Length not an exact no. of bytes HDLC abort detected Unused (set to 0) For a linked list of RPDs, only the last RPD's Status field is valid. All other RPD Status fields of the linked list are invalid and should be ignored. When a packet requires only one RPD, the Status field is valid. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE 38 PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 ISSUE 2 Field Bytes in Buffer [15:0] FRAME ENGINE AND DATA LINK MANAGER Description The Bytes in Buffer[15:0] bits indicate the number of bytes actually used in the current RPD's data buffer to store packet data. The count excludes the 'dummy' bytes inserted as a result of a non-zero Offset field. A count greater than 32767 bytes indicates a packet that is shorter than the expected length of the FCS field. The Bytes in Buffer field is invalid when Status[0] or Status[4] is asserted . Next RPD Pointer [13:0] The Next RPD Pointer[13:0] bits store a RPDR which enables the RMAC to support linked lists of RPDs. This field, which is only valid when CE is equal to logic zero, contains the RPDR to the next RPD in a linked list. The RMAC links RPDs when more than one buffer is needed to store a packet. The Next RPD Pointer is not valid for the last RPD in a linked list (when CE=1). When a packet requires only one RPD, the Next RPD Pointer field is not valid. Receive Buffer Size The Receive Buffer Size[15:0] bits indicate the size in [15:0] bytes of the current RPD's data buffer. This field is expected to be configured by the Host during initialisation. The Receive Buffer Size must be a non-zero integer multiple of four and less than or equal to 32764. The Receive Buffer Size field is valid in all RPDs. The Receive Buffer Size and Data Buffer Start Address fields are written only by the host. The RMAC reads these fields to determine where to store packet data. All other fields are written only by the RMAC. Receive Packet Descriptor Table The Receive Packet Descriptor Table resides in host memory and stores all the RPDs. The RPD Table can contain a maximum of 16384 RPDs. The base of the RPD table is user programmable using the Rx Packet Descriptor Table Base (RPDTB) register. The table is indexed by a Receive Packet Descriptor Reference (RPDR) which is a 14-bit pointer defining the offset of a RPD from the table base. Thus, as shown in the following diagram, a RPD can be located by adding the RPDR to the Rx Packet Descriptor Table Base register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE 39 PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER Figure 5 ­ Receive Packet Descriptor Table RPDTB[31:4] = Rx Packet Descriptor Table Base register RPDR[13:0] = Receive Packet Desriptor Reference RPD_ADDR[31:0] = Receive Packet Descriptor Address Bit 31 Bit 0 RPDTB[31:4] 0000 + RPDR[13:0] 0000 = RPD_ADDR[31:0] Bit 31 RPDTB RPD 1 RPD_ADDR Bit 0 Dword 0 Dword 1 Dword 2 Dword 3 Dword 0 RPD 2 Dword 3 Dword 0 RPD 16384 Dword 3 The Receive Packet Descriptor Table resides in host memory. The Rx Packet Descriptor Table Base register resides in the RMAC; this register is initialised by the host. The RPDRs reside in host memory and are accessed using receive packet queues which are described in the next section. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE 40 PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER Receive Packet Queues Receive Packet Queues are used to transfer RPDRs between the host and the RMAC. There are three queues: a RPDR Large Buffer Free Queue (RPDRLFQ), a RPDR Small Buffer Free Queue (RPDRSFQ) and a RPDR Ready Queue (RPDRRQ). The free queues contain RPDRs referencing RPDs that define free buffers. The ready queue contains RPDRs referencing RPDs that define buffers ready for host processing. The RMAC pulls RPDRs from the free queues when it needs free data buffers. The RMAC places an RPDR onto the ready queue after it has filled the buffers with data from each complete packet. The host removes RPDRs from the ready queue to process the data buffers. The host places the RPDRs back onto the free queues after it finishes reading the data from the buffers. When starting to process a packet, the RMAC uses a small buffer RPD to store the packet data. If the packet requires more than one buffer, the RMAC uses large buffer RPDs to store the remainder of the packet. The RMAC links together all the RPDs required to store the packet and returns the RPDR associated with the first RPD onto the ready queue. All receive packet queues reside in host memory and are defined by the Rx Queue Base (RQB) register and index registers which reside in the RMAC. The Rx Queue Base is the base address for the receive packet queues. Each packet queue has four index registers which define the start and end of the queue and the read and write locations of the queue. Each index register is 16 bits in length and defines an offset from the Rx Queue Base. Thus, as shown in the Figure 6, the host address of a RPDR is calculated by adding the index register to the Rx Queue Base register. The host initialises the Rx Queue Base and all the index registers. When an entity (either the RMAC or the host) removes elements from a queue, the entity updates the read pointer for that queue. When an entity (either the RMAC or the host) places elements onto a queue, the entity updates the write pointer for that queue. The read index for each queue points to the last valid RPDR read while the write index points to where the next RPDR can be written. The start index points to the first valid location within the queue; an RPDR can be written to this location. However, the end index points to a location that is beyond a queue; an RPDR can not be written to this location. Note however, the start index of one queue can be set to the end index of another queue. A queue is empty when the read index is one less than the write index; a queue is also empty if the read index is one less than the end index and the write index equals the start index. A queue is full when the read index is equal to the write index. Figure 6 shows the RPDR reference queues. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE 41 PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER Figure 6 ­ RPDRF and RPDRR Queues Receive Packet Descriptor (RPD) Reference Queues Base Address: RQB[31:2] = Rx Queue Base register Index Registers: Large Buffer Free Queue: Small Buffer Free Queue: RPDRLFQS[15:0] = RPDRLFQW[15:0] = RPDRLFQR[15:0] = RPDRLFQE[15:0] = RPDRSFQS[15:0] RPDRSFQW[15:0] RPDRSFQR[15:0] RPDRSFQE[15:0] RPDR Large Free Queue Start register RPDR Large Free Queue Write register RPDR Large Free Queue Read register RPDR Large Free Queue End register = = = = RPDR Small Free Queue Start register RPDR Small Free Queue Write register RPDR Small Free Queue Read register RPDR Small Free Queue End register Ready Queue: RPDRRQS[15:0] RPDRRQW[15:0] RPDRRQR[15:0] RPDRRQE[15:0] = = = = RPDR Ready Queue Start register RPDR Ready Queue Write register RPDR Ready Queue Read register RPDR Ready Queue End register Base Address + Index Register -Host Address RQB[31:2] + Index[15:0] 00 00 AD[31:0] Rx Packet Descriptor Reference Queue Memory M Bit 31 RPDRRQS RPDRRQR Bit 0 Status + RPDR Status + RPDR Status + RPDR Host Memory Status + RPDR RPDRRQW Status + RPDR Status + RPDR RPDRRQE RPDRLFQS RPDRLFQR RQB RPDR RPD Reference Queues RPDR RPDR RPDRLFQW RPDRLFQE RPDRSFQS RPDRSFQR RPDR RPDR RPDR RPDR RPDR RPDR Valid RPDR RPDRSFQW RPDRSFQE RPDR RPDR RPDR PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE 42 256KB 256KB PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER Note that the maximum value to which an end pointer may be set is FFFF hex, resulting in a maximum offset from the queue base address of (4*(FFFF-1) = 3FFF8 hex. An end pointer must not be set to 0 hex in an attempt to include offset 3FFFC hex in a queue. As shown in Figure 6, the ready queue elements have a status field as well as an RPDR field. The RMAC fills in the status field to mark whether a packet was successfully received or not. The host reads the status field. The ready queue element is shown in Table 7 below along with the definition of the status bits. If the RMAC requires a buffer of a particular size (i.e. small or large) and no RPDR is available in the corresponding free queue, a RPDR from the other free queue is substituted. The host may, therefore, force the RMAC to store received data in buffers of only one size by setting one of the free queues to zero length, i.e. by setting the start and end index registers of one of the queues to equal values. If the RMAC requires a buffer and neither free queue contains RPDRs, an RPQ_ERRI interrupt is generated. Table 7 ­ RPDRR Queue Element Bit 15 Bit 0 STATUS[1:0] RPDR[13:0] Field Description STATUS[1:0] The encoding for the status field is as follows: 00 - Successful reception of packet. 01 - Unsuccessful reception of packet. 10 - Unprovisioned partial packet. 11 - Reserved. RPDR[13:0] The RPDR[13:0] field defines the offset of the first RPD in a linked chain of RPDs, each pointing to a buffer containing the received data. As described previously, the RMAC links a large buffer RPD to a small buffer RPD if more than one buffer is needed for a packet. The RMAC links additional large buffer RPDs to the end of the chain as required until the entire packet is copied to host memory (provided that the host has not disabled use of both free queues by setting one of them to length zero). After storing the packet data, the RMAC places the STATUS+RPDR for the first RPD onto the ready queue. Only the RPDR associated with the first RPD is placed onto the ready queue. All other required RPDs are linked to the first RPD as shown in Figure 7. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE 43 PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER Although a STATUS+RPDR only totals to 16 bits, each queue entry is a dword, i.e. 32 bits. When the RMAC block writes a STATUS+RPDR to the ready queue, it sets the third byte to 0 and the fourth (most significant) byte is unmodified. Figure 7 ­ RPDRR Queue Operation Rx Packet Descriptor Reference Ready Queue RPDRRQ_START_ADDR Bit 31 Bit 0 RPDRRQ_READ_ADDR buffer -packet M RPD - 16 bytes STATUS + RPDR STATUS + RPDR RPDRRQ_WRITE_ADDR STATUS + RPDR RPD - 16 bytes buffer -packet N RPD - 16 bytes buffer -start of packet O RPD - 16 bytes buffer -middle of packet O RPD - 16 bytes buffer -end of packet O RPDRRQ_END_ADDR Receive Channel Descriptor Reference Table On a per-channel basis, the RMAC caches information such as the current DMA information in a Receive Channel Descriptor Reference (RCDR) Table. The RMAC can process 32 channels and stores three dwords of information per channel. This information is cached internally in order to decrease the number of host bus accesses required to process each data packet. The structure of the RCDR table is shown in Figure 8. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE 44 PM7367 PM7367 FREEDM-32P32 FREEDM-32P32 DATA SHEET PMC-1991499 PMC-1991499 ISSUE 2 FRAME ENGINE AND