PM5356 S/UNI-622-MAX PMC-1980589 622-MAX UNI622-MAX CRSI-622 CSPI-622 - Datasheet Archive

 

PM5356 S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 ISSUE 5 SATURN USER NETWORK INTERFACE (622-MAX) PM5356 S/UNI-622-MAX

 

PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 ISSUE 5 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) S/ UNI622-MAX UNI622-MAX R DATASHEET RELEASED ISSUE 5: DECEMBER 1999 PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 ISSUE 5 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) CONTENTS 1 FEATURES.1 1.1 GENERAL .1 1.2 THE SONET RECEIVER.1 1.3 THE RECEIVE ATM PROCESSOR.2 1.4 THE SONET TRANSMITTER.2 1.5 THE TRANSMIT ATM PROCESSOR .3 2 APPLICATIONS .4 3 REFERENCES .5 4 DEFINITIONS .6 5 APPLICATION EXAMPLES .9 6 BLOCK DIAGRAM .12 7 DESCRIPTION .13 8 PIN DIAGRAM .15 9 PIN DESCRIPTION .16 9.1 9.2 PARALLEL LINE SIDE INTERFACE SIGNALS - CRU AND CSU BYPASS .18 9.3 CLOCKS AND ALARMS SIGNALS .21 9.4 ATM (UTOPIA) SYSTEM INTERFACE.23 9.5 MICROPROCESSOR INTERFACE SIGNALS .30 9.6 JTAG TEST ACCESS PORT (TAP) SIGNALS.32 9.7 ANALOG SIGNALS .33 9.8 10 SERIAL LINE SIDE INTERFACE SIGNALS .16 POWER AND GROUND.34 FUNCTIONAL DESCRIPTION.40 10.1 RECEIVE LINE INTERFACE (CRSI-622 CRSI-622).40 10.2 RECEIVE SECTION OVERHEAD PROCESSOR (RSOP) .42 10.3 RECEIVE LINE OVERHEAD PROCESSOR (RLOP).43 10.4 THE RECEIVE APS, SYNCHRONIZATION EXTRACTOR AND BIT ERROR MONITOR (RASE) .45 10.5 RECEIVE PATH OVERHEAD PROCESSOR (RPOP) .46 10.6 RECEIVE ATM CELL PROCESSOR (RXCP).50 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR IT'S CUSTOMER'S INTERNAL USE i PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 ISSUE 5 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) 10.7 TRANSMIT LINE INTERFACE (CSPI-622 CSPI-622) .54 10.8 TRANSMIT SECTION OVERHEAD PROCESSOR (TSOP) .54 10.9 TRANSMIT LINE OVERHEAD PROCESSOR (TLOP).55 10.10 TRANSMIT PATH OVERHEAD PROCESSOR (TPOP) .56 10.11 TRANSMIT ATM CELL PROCESSOR (TXCP).57 10.12 ATM UTOPIA SYSTEM INTERFACES .58 10.13 JTAG TEST ACCESS PORT .60 10.14 MICROPROCESSOR INTERFACE.60 11 NORMAL MODE REGISTER DESCRIPTION .66 12 TEST FEATURES DESCRIPTION .219 12.1 12.2 13 MASTER TEST AND TEST CONFIGURATION REGISTERS.219 JTAG TEST PORT.222 OPERATION .229 13.1 13.2 ATM CELL DATA STRUCTURE.234 13.3 BIT ERROR RATE MONITOR .235 13.4 AUTO ALARM CONTROL CONFIGURATION .236 13.5 CLOCKING OPTIONS.237 13.6 LOOPBACK OPERATION .238 13.7 1+1 APS SUPPORT .243 13.8 JTAG SUPPORT .244 13.9 BOARD DESIGN RECOMMENDATIONS .248 13.10 POWER SUPPLIES .249 13.11 INTERFACING TO ECL OR PECL DEVICES .252 13.12 CLOCK SYNTHESIS AND RECOVERY.254 13.13 14 SONET/SDH FRAME MAPPINGS AND OVERHEAD BYTE USAGE .229 SYSTEM INTERFACE DLL OPERATION .255 FUNCTIONAL TIMING.256 14.1 PARALLEL LINE INTERFACE.256 14.2 ATM UTOPIA LEVEL 2 SYSTEM INTERFACE .257 14.3 ATM UTOPIA LEVEL 3 SYSTEM INTERFACE .258 15 ABSOLUTE MAXIMUM RATINGS.260 16 D.C. CHARACTERISTICS.261 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR IT'S CUSTOMER'S INTERNAL USE ii PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 ISSUE 5 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) 17 MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS.263 18 A.C. TIMING CHARACTERISTICS.267 18.1 SYSTEM RESET TIMING .267 18.2 PARALLEL LINE INTERFACE TIMING .268 18.3 SERIAL LINE INTERFACE TIMING .270 18.4 UTOPIA LEVEL 2 SYSTEM INTERFACE TIMING .271 18.5 UTOPIA LEVEL 3 SYSTEM INTERFACE TIMING .274 18.6 JTAG TEST PORT TIMING .276 19 ORDERING AND THERMAL INFORMATION .278 20 MECHANICAL INFORMATION.279 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR IT'S CUSTOMER'S INTERNAL USE iii PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 1 1.1 ISSUE 5 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) FEATURES General · Single chip ATM over SONET/SDH Physical Layer Device operating at 622.08 Mbit/s. · Implements the ATM Forum User Network Interface Specification and the ATM physical layer for Broadband ISDN according to CCITT Recommendation I.432. · Processes duplex bit-serial 622.08 Mbit/s STS-12c/STM-4-4c data streams with on-chip clock and data recovery and clock synthesis. · Supports a duplex byte-serial 77.76 Mbyte/s STS-12c/STM-4-4c line side interface for use in applications where by-passing clock recovery, clock synthesis, and serializer-deserializer functionality is desired. · Supports a byte-serial 19.44 Mbyte/s STS-3c/STM-1 line side interface on the transmit and/or receive interface for use in applications where a 155.52 Mbit/s data rate is desired. · Supports clock recovery by-pass for use in applications where external clock recovery is desired. Meets Bellcore GR-253-CORE GR-253-CORE (1995 Issues) for jitter tolerance and intrinsic jitter criteria. · Provides UTOPIA Level 2 16-bit wide System Interface (clocked up to 50 MHz) with parity support for ATM applications. · Provides UTOPIA Level 3 compatible 8-bit wide System Interface (clocked up to 100 MHz) with parity support for ATM applications. · Provides support functions for a two chip solution for 1+1 APS operation. · Provides a standard 5 signal IEEE 1149.1 JTAG test port for boundary scan board test purposes. · Provides a generic 8-bit microprocessor bus interface for configuration, control, and status monitoring. · Low power 3.3V CMOS with TTL compatible digital inputs and CMOS/TTL digital outputs. PECL inputs and outputs are 3.3V and 5V compatible. · Industrial temperature range (-40°C to +85°C). · 304 pin Super BGA package. 1.2 · The SONET Receiver Provides a serial interface at 622.08 Mbit/s with clock and data recovery. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS' INTERNAL USE 1 PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 ISSUE 5 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) · Frames to and de-scrambles the received STS-12c/STM-4-4c stream. · Optionally frames to and de-scrambles a received STS-3c/STM-1 stream. · Interprets the received payload pointer (H1, H2) and extracts the STS-12c/STM-4-4c or STS-3c/STM1 synchronous payload envelope and path overhead. · Filters and captures the automatic protection switch channel (APS) bytes in readable registers and detects APS byte failure. · Captures and de-bounces the synchronization status (S1) nibble in a readable register. · Detects signal degrade (SD) and signal fail (SF) threshold crossing alarms based on received B2 errors. · Detects loss of signal (LOS), out of frame (OOF), loss of frame (LOF), line alarm indication signal (AIS-L), line remote defect indication (RDI-L), loss of pointer (LOP), path alarm indication signal (AISP), path remote defect indication (RDI-P), path extended remote defect indicator (extended RDI-P). · Counts received section BIP-8 (B1) errors, received line BIP-96 BIP-96 (B2) errors, line remote error indicates (REI-L), received path BIP-8 (B3) errors and path remote error indications (REI-P) for performance monitoring purposes. 1.3 The Receive ATM Processor · Extracts ATM cells from the received STS-12c/STM-4-4c or STS-3c/STM-1 payload using ATM cell delineation. · Provides ATM cell payload de-scrambling. · Performs header check sequence (HCS) error detection and correction, and idle/unassigned cell filtering. · Detects out of cell Delineation (OCD) and loss of cell delineation (LCD) alarms. · Counts number of received cells, idle cells, errored cells and dropped cells. · Provides a UTOPIA Level 2 compliant 16-bit wide datapath interface (clocked up to 50 MHz) with parity support to read extracted cells from an internal four-cell FIFO buffer. · Provides a UTOPIA Level 3 compatible 8-bit wide datapath interface (clocked up to 100 MHz) with parity support to read extracted cells from an internal four-cell FIFO buffer. 1.4 · The SONET Transmitter Synthesizes the 622.08 MHz transmit clock from a 77.76 MHz reference. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS' INTERNAL USE 2 PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 ISSUE 5 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) · Provides a differential PECL bit-serial interface at 622.08 Mbit/s. · Inserts a register programmable path signal label (C2). · Generates the transmit payload pointer (H1, H2) and inserts the path overhead. · Scrambles the transmitted STS-12c/STM-4-4c or STS-3c/STM-1 stream and inserts the framing bytes (A1, A2). · Optionally inserts register programmable APS bytes. · Provides a byte-serial transmit path data stream allowing two devices to implement 1+1 APS. · Inserts path BIP-8 codes (B3), path remote error indications (REI-P), line BIP-96 BIP-96 codes (B2), line remote error indications (REI-L), and section BIP-8 codes (B1) to allow performance monitoring at the far end. · Allows forced insertion of all-zeros data (after scrambling) and the corruption of the section, line, or path BIP-8 codes for diagnostic purposes. · Inserts ATM cells into the transmitted STS-12c/STM-4-4c or STS-3c/STM-1 payload. 1.5 The Transmit ATM Processor · Provides idle/unassigned cell insertion. · Provides HCS generation/insertion, and ATM cell payload scrambling. · Counts number of transmitted and idle cells. · Provides a UTOPIA Level 2 compliant 16-bit wide datapath interface (clocked up to 50 MHz) with parity support for writing cells into an internal four-cell FIFO. · Provides a UTOPIA Level 3 compatible 8-bit wide datapath interface (clocked up to 100 MHz) with parity support for writing cells into an internal four-cell FIFO. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS' INTERNAL USE 3 PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 2 ISSUE 5 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) APPLICATIONS · WAN and Edge ATM switches. · LAN switches and hubs. · Routers and Layer 3 Switches · Network Interface Cards and Uplinks PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS' INTERNAL USE 4 PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 3 ISSUE 5 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) REFERENCES · ATM Forum - ATM User-Network Interface Specification, V3.1, October, 1995. · ATM Forum - "UTOPIA, An ATM PHY Interface Specification, Level 2, Version 1", June, 1995. · Bell Communications Research - GR-253-CORE GR-253-CORE "SONET Transport Systems: Common Generic Criteria", Issue 2, December 1995. · Bell Communications Research - GR-436-CORE GR-436-CORE "Digital Network Synchronization Plan", Issue 1 Revision 1, June 1996. · ETS 300 417-1-1, "Generic Functional Requirements for Synchronous Digital Hierarchy (SDH) Equipment", January, 1996. · ITU-T Recommendation G.703 - "Physical/Electrical Characteristics of Hierarchical Digital Interfaces", 1991. · ITU-T Recommendation G.704 - "General Aspects of Digital Transmission Systems; Terminal Equipment - Synchronous Frame Structures Used At 1544, 6312, 2048, 8488 and 44 736 kbit/s Hierarchical Levels", July, 1995. · ITU, Recommendation G.707 - "Network Node Interface For The Synchronous Digital Hierarchy", 1996. · ITU Recommendation G781, "Structure of Recommendations on Equipment for the Synchronous Design Hierarchy (SDH)", January 1994. · ITU, Recommendation G.783 - "Characteristics of Synchronous Digital Hierarchy (SDH) Equipment Functional Blocks", 1996. · ITU Recommendation I.432, "ISDN User Network Interfaces", March 93. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS' INTERNAL USE 5 PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 4 ISSUE 5 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) DEFINITIONS The following table defines the abbreviations for the S/UNI-622-MAX S/UNI-622-MAX. AIS Alarm Indication Signal APS Automatic Protection Switching ASSP Application Specific Standard Product ATM Asynchronous Transfer Mode BER Bit Error Rate BIP Byte Interleaved Parity CBI Common Bus Interface CMOS Complementary Metal Oxide Semiconductor CRC Cyclic Redundancy Check CRSI CRU and Serial-In Parallel-Out CRU Clock Recovery Unit CSPI CSU and Parallel-In Serial-Out CSU Clock Synthesis Unit ECL Emitter Controlled Logic ERDI Enhanced Remote Defect Indication ESD Electrostatic Discharge FEBE Far-End Block Error FIFO First-In First-Out GFC Generic Flow Control HCS Header Check Sequence LAN Local Area Network LCD Loss of Cell Delineation LOF Loss of Frame LOH Line Overhead LOP Loss of Pointer LOS Loss of Signal LOT Loss of Transition NC No Connect, indicates an unused pin PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS' INTERNAL USE 6 PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 ISSUE 5 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) NDF New Data Flag NNI Network-Network Interface ODL Optical Data Link OOF Out of Frame PECL Pseudo-ECL PLL Phase-Locked Loop PSL Path Signal Label PSLM Path Signal Label Mismatch RASE Receive APS, Synchronization Extractor and Bit Error Monitor RDI Remote Defect Indication RLOP Receive Line Overhead Processor RPOP Receive Path Overhead Processor RSOP Receive Section Overhead Processor RXCP Receive ATM Cell Processor SBGA Super Ball Grid Array SD Signal Degrade (alarm), Signal Detect (pin) SDH Synchronous Digital Hierarchy SF Signal Fail SOH Section Overhead SONET Synchronous Optical Network SPE Synchronous Payload Envelope TLOP Transmit Line Overhead Processor TOH Transport Overhead TPOP Transmit Path Overhead Processor TSOP Transmit Section Overhead Processor TXCP Transmit ATM Cell Processor UI Unit Interval UNI User-Network Interface VCI Virtual Connection Indicator VPI Virtual Path Indicator PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS' INTERNAL USE 7 PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 ISSUE 5 WAN Wide Area Network XOR SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) Exclusive OR logic operator PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS' INTERNAL USE 8 PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 5 ISSUE 5 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) APPLICATION EXAMPLES The PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX is applicable to equipment implementing Asynchronous Transfer Mode (ATM) User-Network Interfaces (UNI), ATM Network-Network Interfaces (NNI). The S/UNI-622-MAX S/UNI-622-MAX may find application at either end of switch-to-switch links or switch-toterminal links, both in public network (WAN) and private network (LAN) situations. The S/UNI622-MAX S/UNI622-MAX provides a comprehensive feature set as well as full compliance to WAN synchronization requirements. The S/UNI-622-MAX S/UNI-622-MAX performs the mapping of ATM cells into the SONET/SDH STS-12c/STM-4-4c synchronous payload envelope (SPE) and processes applicable SONET/SDH section, line and path overheads. In a typical STS-12c/STM-4-4c ATM application, the S/UNI-622-MAX S/UNI-622-MAX performs clock and data recovery in the receive direction and clock synthesis in the transmit direction of the line interface. The S/UNI-622-MAX S/UNI-622-MAX can also be configured to by-pass the clock recovery, clock synthesis, and serializer/de-serializer functions. In this mode, an external clock and data recovery/serial-toparallel converter device is required in the receive direction, and an external serial-to-parallel converter/clock synthesis device is required in the transmit direction. On the system side, the S/UNI-622-MAX S/UNI-622-MAX interfaces directly with ATM layer processors and switching or adaptation functions using a UTOPIA Level 2 compliant 16-bit (clocked up to 50 MHz) or an UTOPIA Level 3 8-bit (clocked up to 100 MHz) synchronous FIFO style interface. An application with a UTOPIA Level 2 system side interface is shown in Figure 1. An application with a UTOPIA Level 3 system side is shown in Figure 2. The initial configuration and ongoing control and monitoring of the S/UNI-622-MAX S/UNI-622-MAX are normally provided via a generic microprocessor interface. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS' INTERNAL USE 9 PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 ISSUE 5 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) Figure 1: Typical STS-12c/STM-4-4c ATM (UTOPIA Level 2) Switch Port Application UTOPIA Level 2 Interface ATM Layer Device TxClk PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX TFCLK TxEnb TENB TxClav TCA TxSOC TSOC TxPrty TxData[15:0] LIFSEL 0 TPRTY TDAT[15:0] RXD+/Optical Transceiver SD RxClk RFCLK RxEnb RENB RxClav RCA RxSOC RSOC TXD+/- RxPrty RxData[15:0] SYSSEL 0 RPRTY RDAT[15:0] PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS' INTERNAL USE 10 PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 ISSUE 5 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) Figure 2: Typical STS-12c/STM-4-4c ATM (UTOPIA Level 3) Switch Port Application UTOPIA Level 3 Interface ATM Layer Device TxClk PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX TFCLK TxEnb TENB TxClav TCA TxSOC TSOC TxPrty TxData[7:0] LIFSEL 0 TPRTY TDAT[7:0] RXD+/Optical Transceiver SD RxClk RFCLK RxEnb RENB RxVal RVAL RxSOC RSOC TXD+/- RxPrty RxData[7:0] SYSSEL 1 RPRTY RDAT[7:0] PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS' INTERNAL USE 11 S/UNI-622-MAX S/UNI-622-MAX DATASHEET BLOCK DIAGRAM PMC-1980589 PMC-1980589 6 SYSSEL TDO TDI TCK TMS TRSTB TCLK TFPI TFPO LIFSEL ATP[0] PTCLK Tx Section O/H Processor Tx Line O/H Processor Tx Path O/H Processor TENB Tx ATM Cell Processor TCA TSOC POUT[7:0] FPOUT Path Trace Buffer RBYP PECLV REFCLK+/- RRCLK+/- RFCLK RENB RCA Rx Line I/F Rx Section O/H Processor Rx Line O/H Processor Rx Path O/H Processor RPRTY Rx ATM Cell Processor RVAL RDAT[15:0] PICLK Rx APS, Sync Status, BERM PIN[7:0] FPIN Microprocessor Interface 12 OOF PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX INTB RSTB RDB WRB CSB ALE A[8:0] D[7:0] APSP[4:0] RCLK RFPO RALARM SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) ATP[1] TDAT[15:0] RSOC RXD+/- SD TPRTY PMC-Sierra, Inc. Section Trace Buffer ISSUE 5 TFCLK Tx Line I/F UTOPIA ATM Level 2 UTOPIA ATM Level 3 System Interface PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS' INTERNAL USE JTAG Test Access Port TXD+/TDREF1, TDREF0 PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 7 ISSUE 5 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) DESCRIPTION The PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX SATURN User Network Interface is a monolithic integrated circuit that implements SONET/SDH processing, ATM mapping functions at the STS-12c/STM-4-4c 622.08 Mbit/s rate. The S/UNI-622-MAX S/UNI-622-MAX receives SONET/SDH streams using a bit serial interface, recovers the clock and data and processes section, line, and path overhead. The S/UNI-622-MAX S/UNI-622-MAX can also be configured for clock and data recovery and clock synthesis by-pass where it receives SONET/SDH frames via a byte-serial interface. The S/UNI-622-MAX S/UNI-622-MAX performs framing (A1, A2), de-scrambling, detects alarm conditions, and monitors section, line, and path bit interleaved parity (B1, B2, B3), accumulating error counts at each level for performance monitoring purposes. Line and path remote error indications (M1, G1) are also accumulated. The S/UNI-622-MAX S/UNI-622-MAX interprets the received payload pointers (H1, H2) and extracts the synchronous payload envelope which carries the received ATM cell payload. When used to implement an ATM UNI or NNI, the S/UNI-622-MAX S/UNI-622-MAX frames to the ATM payload using cell delineation. HCS error correction is provided. Idle/unassigned cells may be optionally dropped. Cells are also dropped upon detection of an uncorrectable header check sequence error. The ATM cell payloads are descrambled and are written to a four-cell FIFO buffer. The received cells are read from the FIFO using a 16-bit wide UTOPIA Level 2 (clocked up to 50 MHz) or an 8-bit wide UTOPIA Level 3 (clocked up to 100 MHz) datapath interface. Counts of received ATM cell headers that are errored and uncorrectable and those that are errored and correctable are accumulated independently for performance monitoring purposes. The S/UNI-622-MAX S/UNI-622-MAX transmits SONET/SDH streams using a bit serial interface. The S/UNI-622MAX S/UNI-622MAX can also be configured for clock and data recovery and clock synthesis by-pass where it transmits the SONET/SDH frames via a byte-serial interface. The S/UNI-622-MAX S/UNI-622-MAX synthesizes the transmit clock from a 77.76MHz frequency reference and performs framing pattern insertion (A1, A2), scrambling, alarm signal insertion, and creates section, line, and path bit interleaved parity codes (B1, B2, B3) as required to allow performance monitoring at the far end. Line and path remote error indications (M1, G1) are also inserted. The S/UNI-622-MAX S/UNI-622-MAX also supports the insertion of a large variety of errors into the transmit stream, such as framing pattern errors, bit interleaved parity errors, and illegal pointers, which are useful for system diagnostics and tester applications. When used to implement an ATM UNI or NNI, ATM cells are written to an internal four cell FIFO using a 16-bit wide UTOPIA Level 2 (clocked up to 50 MHz) or an 8-bit wide UTOPIA Level 3 (clocked up to 100 MHz) datapath interface. Idle/unassigned cells are automatically inserted when the internal FIFO contains less than one complete cell. The S/UNI-622-MAX S/UNI-622-MAX provides generation of the header check sequence and scrambles the payload of the ATM cells. Each of these transmit ATM cell processing functions can be enabled or bypassed. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS' INTERNAL USE 13 PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 ISSUE 5 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) No line rate clocks are required directly by the S/UNI-622-MAX S/UNI-622-MAX as it synthesizes the transmit clock and recovers the receive clock using a 77.76 MHz reference clock. The S/UNI-622-MAX S/UNI-622-MAX outputs a differential PECL line data (TXD+/-). The S/UNI-622-MAX S/UNI-622-MAX is configured, controlled and monitored via a generic 8-bit microprocessor bus interface. The S/UNI-622-MAX S/UNI-622-MAX also provides a standard 5 signal IEEE 1149.1 JTAG test port for boundary scan board test purposes. The S/UNI-622-MAX S/UNI-622-MAX is implemented in low power, +3.3 Volt, CMOS technology. It has TTL compatible digital inputs and TTL/CMOS compatible digital outputs. High speed inputs and outputs support 3.3V and 5.0V compatible pseudo-ECL (PECL). The S/UNI-622-MAX S/UNI-622-MAX is packaged in a 304 pin SBGA package. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS' INTERNAL USE 14 PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 8 ISSUE 5 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) PIN DIAGRAM The S/UNI-622-MAX S/UNI-622-MAX is available in a 304 pin SBGA package having a body size of 31 mm by 31 mm and a ball pitch of 1.27 mm. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS' INTERNAL USE 15 PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 9 9.1 ISSUE 5 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) PIN DESCRIPTION Serial Line Side Interface Signals Pin Name RBYP Type Input Pin No. E21 Function The receive bypass (RBYP) input disables clock recovery. If RBYP is high, RXD+/- is sampled on the rising edge of RRCLK+/-. If RBYP is low, the receive clock is recovered from the RXD+/- bit stream. Please refer to the Operation section for a discussion of the operating modes. PECLV Input D22 The PECL signal voltage select (PELCV) selects between 3.3V PECL signaling and 5V PECL signaling for the PECL inputs. When PECLV is low, the PECL inputs expect a 5V PECL signal. When PECLV is high, the PECL inputs expect a 3.3V PECL signal. The PECL biasing pins PBIAS should be set to the appropriate voltage to prevent latchup. Please refer to the Operation section for a discussion of PECL interfacing issues. REFCLK+ REFCLK- Differential Y2 PECL Input AA1 The differential reference clock inputs (REFCLK+/-) provides a jitter-free 77.76 MHz reference clock for both the clock recovery and the clock synthesis circuits. REFCLK+/- is not required if the clock recovery and clock synthesis features are not used. Please refer to the Operation section for a discussion of PECL interfacing issues and reference clocks. RXD+ RXD- Differential W1 PECL Input V2 The receive differential data PECL inputs (RXD+/-) contain the NRZ bit serial receive stream. The receive clock is recovered from the RXD+/- bit stream when RBYP is set low. RXD+/- is sampled on the rising edge of RRCLK+/- when RBYP is set high. Please refer to the Operation section for a discussion of PECL interfacing issues. RRCLK+ RRCLK- Differential U1 PECL Input U2 When clock recovery is bypassed (RBYP set high), RRCLK+/- is nominally a 622.08 MHz 50% duty cycle clock and provides timing for the S/UNI-622-MAX S/UNI-622-MAX receive functions. In this case, RXD+/- is sampled on the rising edge of RRCLK+/-. RRCLK+/is ignored when RBYP is set low. Please refer to the Operation section for a discussion of PECL interfacing issues. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS' INTERNAL USE 16 PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 Pin Name SD ISSUE 5 Type Pin No. PECL Input R2 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) Function The receive signal detect PECL input (SD) indicates the presence of valid receive signal power from the Optical Physical Medium Dependent Device. A PECL logic high indicates the presence of valid data. A PECL logic low indicates a loss of signal. Please refer to the Operation section for a discussion of PECL interfacing issues TXD+ TXD- Differential L2 PECL Output L1 The transmit differential data PECL outputs (TXD+/-) contain the 622.08 Mbit/s transmit stream. The TXD+/- outputs are driven using the synthesized clock from the CSU-622 CSU-622. Please refer to the Operation section for a discussion of PECL interfacing issues. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS' INTERNAL USE 17 PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 9.2 ISSUE 5 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) Parallel Line Side Interface Signals - CRU and CSU Bypass Pin Name LIFSEL Type Input Pin No. C23 Function The line interface select (LIFSEL) selects between serial and parallel line interface modes of operation. When tied high, the parallel mode is selected by-passing the clock and data recovery, clock synthesis and the serializer/deserializer functions. When tied low, serial mode is selected, enabling clock and data recovery, clock synthesis and the serializer/de-serializer functions. During this operation, the parallel interface may be used for 1+1 APS operation. See the Operation section for more discussion of 1+1 APS support. PICLK Input AC19 The parallel input clock (PICLK) provides timing for S/UNI-622MAX S/UNI-622MAX receive function operation when the device is configured for the parallel interface mode of operation. When the RSOC3 bit is set high, PICLK is a 19.44 MHz nominally 50% duty cycle clock. When the RSOC3 bit is set low, PICLK is a 77.76 MHz nominally 50% duty cycle clock. When parallel operation is not used, PICLK may be used for 1+1 APS operation. See the Operation section for more discussion of 1+1 APS. OOF Output AA18 The out of frame (OOF) signal is high while the S/UNI-622-MAX S/UNI-622-MAX is out of frame. OOF is set low while the S/UNI-622-MAX S/UNI-622-MAX is inframe. An out of frame declaration occurs when four consecutive errored framing patterns (A1 and A2 bytes) have been received. OOF is intended to enable an upstream framing pattern detector to search for the framing pattern. This alarm indication is also available via register access. OOF is an asynchronous output with a minimum period of one PICLK clock. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS' INTERNAL USE 18 PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 Pin Name FPIN ISSUE 5 Type Pin No. Input AB17 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) Function The active-high framing position input (FPIN) signal indicates the SONET/SDH frame position on the PIN[7:0] bus. In parallel interface operation, the byte on the PIN[7:0] bus indicated by FPIN is the third A2 of the SONET/SDH framing pattern. FPIN is sampled on the rising edge of PICLK. When parallel interface operation is not used, FPIN may be used for 1+1 APS operation. In this mode, FPIN marks the marks the first synchronous payload envelope byte after the J0/Z0 bytes on PIN[7:0]. See the Operation section for more discussion of 1+1 APS. PIN[0] PIN[1] PIN[2] PIN[3] PIN[4] PIN[5] PIN[6] PIN[7] Input PTCLK Input AB18 AA17 AB16 AA16 Y16 AC15 AB15 AA15 In parallel interface operation, the data input (PIN[7:0]) bus carries the byte-serial STS-12c/STM-4-4c or STS-3c/STM-1 stream. PIN[7] is the most significant bit (corresponding to bit 1 of each serial byte, the first bit received). PIN[0] is the least significant bit (corresponding to bit 8 of each serial byte, the last bit received). PIN[7:0] is sampled on the rising edge of PICLK. Y14 The parallel transmit clock (PTCLK) provides timing for S/UNI622-MAX S/UNI622-MAX transmit function operation when the device is configured for the parallel interface mode of operation. When parallel interface operation is not used, PIN[7:0] may be used for 1+1 APS operation. In this mode, PIN[7:0] carries the byte-serial STS-12c/STM-4-4c transmit path. See the Operation section for more discussion of 1+1 APS. When TOC3 is low, PTCLK should be a 77.76 MHz nominally 50% duty cycle clock free-running (non gapped) clock. When TOC3 is high, PTCLK should be a 19.44 MHz nominally 50% duty cycle clock. FPOUT Output AC14 In parallel interface operation, the parallel outgoing stream frame pulse (FPOUT) marks the frame alignment on the POUT[7:0] bus. FPOUT marks the first synchronous payload envelope byte after the J0/Z0 bytes. FPOUT is updated on the rising edge of PTCLK. When parallel interface operation is not used, FPOUT may be used for 1+1 APS operation. In this mode, FPOUT marks the first synchronous payload envelope byte after the J0/Z0 bytes. FPOUT is updated on the rising edge of TCLK. See the Operation section for more discussion of 1+1 APS. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS' INTERNAL USE 19 PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 Pin Name POUT[0] POUT[1] POUT[2] POUT[3] POUT[4] POUT[5] POUT[6] POUT[7] ISSUE 5 Type Output Pin No. AA14 AB14 AC13 AB13 AA13 Y13 AB12 AA12 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) Function In parallel interface operation, the parallel outgoing stream, (POUT[7:0]) carries the scrambled STS-12c/STM-4-4c or STS3c/STM-1 stream in byte-serial format. POUT[7] is the most significant bit (corresponding to bit 1 of each serial word, the first bit transmitted). POUT[0] is the least significant bit (corresponding to bit 8 of each serial word, the last bit transmitted). POUT[7:0] is updated on the rising edge of PTCLK. When parallel interface operation is not used, POUT[7:0] may be used for 1+1 APS operation. In this mode, POUT[7:0] carries the byte-serial STS-12c/STM-4-4c transmit path and updates on the rising edge of TCLK. See the Operation section for more discussion of 1+1 APS. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS' INTERNAL USE 20 PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 9.3 ISSUE 5 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) Clocks and Alarms Signals Pin Name Type Pin No. Function RCLK Output AC20 The receive clock (RCLK) provides a timing reference for the S/UNI-622-MAX S/UNI-622-MAX receive function outputs. RCLK is a 77.76 MHz, 50% duty cycle clock. RFPO Output AB19 The receive frame pulse output (RFPO), when the framing alignment has been found (the OOF register bit is low), is an 8 kHz signal derived from the receive clock RCLK. RFPO pulses high for one RCLK cycle every 9720 RCLK cycles (STS-12c / STM-4-4c). RFPO is updated on the rising edge of RCLK. RALRM Output AA19 The receive alarm (RALRM) output indicates the state of the receive framing. RALRM is low if no receive alarms are active. RALRM is optionally high if line AIS (LAIS), path AIS (PAIS), line RDI (LRDI), path RDI (PRDI), enhanced path RDI (PERDI), loss of signal (LOS), loss of frame (LOF), out of frame (OOF), loss of pointer (LOP), loss of pointer concatenation (LOPC/AISC), loss of cell delineation (LCD), signal fail BER (SFBER), signal degrade BER (SDBER), or path signal label mismatch (PSLM) is detected . RALRM is an asynchronous output with a minimum period of one RCLK clock. TCLK Output B19 The transmit clock (TCLK) provides timing for the S/UNI-622MAX S/UNI-622MAX transmit function operation. TCLK is a 77.76 MHz, 50% duty cycle clock. TFPO Output A20 The active-high framing position output (TFPO) signal is an 8 kHz signal derived from the transmit clock TCLK. TFPO pulses high for one TCLK cycle every 9720 RCLK cycles (STS-12c / STM-4-4c). TFPO is updated on the rising edge of TCLK. TFPI Input A21 The active high framing position (TFPI) signal is an 8 kHz timing marker for the transmitter. TFPI is used to align the SONET/SDH transport frame generated by the S/UNI-622-MAX S/UNI-622-MAX device to a system reference. TFPI should be brought high for a single TCLK period every 9720 TCLK cycles or a multiple thereof. TFPI must be tied low if such synchronization is not required. TFPI is sampled on the rising edge of TCLK. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS' INTERNAL USE 21 PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 Pin Name APS[0] APS[1] APS[2] APS[3] APS[4] ISSUE 5 Type I/O Pin No. A19 C18 B18 D17 C17 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) Function The APS Port bus (APS[4:0]) is a bi-directional control bus that can be used to implement a 1+1 APS system. When the APSPOE register bit is set low, the APS[4:0] bus is an input. Data on this bus is used by TPOP to generate the path RDI and path FEBE. When the APSPOE register bit is set high, the APS[4:0] bus is an output with data generated by RPOP. APS[0] APS[1] APS[2] APS[3] APS[4] FEBE Clock (576 kHz) FEBE Data RDI[0] (G1 bit 5) RDI[1] (G1 bit 6) RDI[2] (G1 bit 7) See the Operation section for more discussion of 1+1 APS. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS' INTERNAL USE 22 PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 9.4 ISSUE 5 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) ATM (UTOPIA) System Interface Pin Name SYSSEL Type Pin No. Input AA23 Function The system interface select (SYSSEL) pin selects between the 16-bit UTOPIA Level 2 mode and the 8-bit UTOPIA Level 3 mode of the system side interfaces for ATM. When tied low, the 16-bit Level 2 mode is enabled. When tied high, the 8-bit Level 3 mode is enabled. This pin setting affects the pin definitions of the system interface bus and may be overridden by software in the RUL3 and TUL3 registers. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS' INTERNAL USE 23 PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 Pin Name TFCLK ISSUE 5 Type Input Pin No. M22 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) Function UTOPIA transmit FIFO write clock (TFCLK) is used to write ATM cells to the four cell transmit FIFO. When in 16-bit Level 2 ATM mode, TFCLK must cycle at a 50 MHz to 40 MHz instantaneous rate, and must be a free running clock (cannot be gapped). When in 8-bit Level 3 ATM mode, TFCLK must cycle at a 100 MHz to 60 MHz instantaneous rate, and must be a free running clock (cannot be gapped). TDAT[0] TDAT[1] TDAT[2] TDAT[3] TDAT[4] TDAT[5] TDAT[6] TDAT[7] TDAT[8] TDAT[9] TDAT[10] TDAT[11] TDAT[12] TDAT[13] TDAT[14] TDAT[15] Input K22 K21 K20 J23 J22 J21 H22 H21 H20 G23 G22 G21 G20 F22 F21 E23 The UTOPIA transmit cell data (TDAT[15:0]) bus carries the ATM cell octets that are written to the transmit FIFO. In 16-bit Level 2 ATM mode, the TDAT[15:0] is considered valid only when TENB is simultaneously asserted. In 8-bit Level 3 ATM mode, the TDAT[7:0] bus is considered valid only when TENB is simultaneously asserted. TDAT[15:8] are ignored. TDAT[15:0] is sampled on the rising edge of TFCLK. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS' INTERNAL USE 24 PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 Pin Name TSOC ISSUE 5 Type Input Pin No. L21 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) Function The UTOPIA transmit start of cell (TSOC) signal marks the start of a cell structure on the TDAT bus. In 16-bit Level 2 ATM mode, the first word of the cell structure is present on the TDAT[15:0] bus when TSOC is high. It is not necessary for TSOC to be present for each cell. In 8-bit Level 3 ATM mode, the first byte of the cell structure is present on the TDAT[7:0] bus when TSOC is high. TSOC must be present for each cell. TSOC is considered valid only when TENB is simultaneously asserted. TSOC is sampled on the rising edge of TFCLK. TENB Input L22 The UTOPIA transmit write enable (TENB) signal is an active low input which is used to initiate writes to the transmit FIFO's. When TENB is sampled high, the information sampled on the TDAT, TPRTY and TSOC signals are invalid. When TENB is sampled low, the information sampled on the TDAT, TPRTY and TSOC signals are valid and are written into the transmit FIFO. TENB is sampled on the rising edge of TFCLK. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS' INTERNAL USE 25 PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 Pin Name TCA ISSUE 5 Type Output Pin No. L23 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) Function The UTOPIA transmit cell available (TCA) signal provides direct status indication of when cell space is available in the transmit FIFO. When set high, TCA indicates that the corresponding transmit FIFO is not full and a complete cell may be written. TCA is set low to either indicate that the transmit FIFO is near full or that the transmit FIFO is full. To reduce FIFO latency, the FIFO depth at which TCA indicates "full" can be set to one, two, three or four cells. Note that regardless of what fill level TCA is set to indicate "full" at, the transmit cell processor can store 4 complete cells. In 16-bit Level 2 ATM mode, TCA will transition low one TFCLK cycle after the payload word 19 or 23 (depending of the configuration in TXCP) is sampled on the TDAT[15:0] bus. In 8-bit Level 3 ATM mode, TCA will transition low on the rising edge of TFCLK before the payload byte 45 is sampled on the TDAT[7:0] bus. TCA is updated on the rising edge of TFCLK. RFCLK Input M21 The UTOPIA receive FIFO read clock (RFCLK). RFCLK is used to read ATM cells from the four cell receive FIFO. When in 16-bit Level 2 ATM mode, RFCLK must cycle at a 50 MHz to 40 MHz instantaneous rate, and must be a free running clock (cannot be gapped). When in 8-bit Level 3 ATM mode, RFCLK must cycle at a 100 MHz to 60 MHz instantaneous rate, and must be a free running clock (cannot be gapped). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS' INTERNAL USE 26 PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 Pin Name ISSUE 5 Type RDAT[0] RDAT[1] RDAT[2] RDAT[3] RDAT[4] RDAT[5] RDAT[6] RDAT[7] RDAT[8] RDAT[9] RDAT[10] RDAT[11] RDAT[12] RDAT[13] RDAT[14] RDAT[15] Output RVAL Output Pin No. SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) Function W21 W22 W23 V21 V22 U20 U21 U22 U23 T20 T21 T22 R21 R22 R23 P20 UTOPIA receive cell data (RDAT[15:0]) bus carries the ATM cell octets that are read from the receive FIFO. N21 The UTOPIA Level 3 receive data valid (RVAL) signal indicates the validity of the receive data signals. When RVAL is high, the receive signals RDAT, RSOC and RPRTY are valid. When RVAL is low, all receive signals are invalid and must be disregarded. In 16-bit Level 2 ATM mode, RDAT[15:0] is consider valid only when RENB is asserted. RDAT[15:0] is tri-stated when RENB is sampled high. In 8-bit Level 3 ATM mode, only the RDAT[7:0] signals are valid when RVAL is asserted. RDAT[15:8] contain invalid data. RDAT[15:0] is updated on the rising edge of RFCLK. In 16-bit Level 2 ATM mode, RVAL is invalid and must be ignored. In 8-bit Level 3 ATM mode, RVAL will be high when valid data is on the RDAT bus. The RVAL will transition low when the FIFO is empty. Once deasserted, RVAL will remain deasserted until a complete ATM cell is written into the receive FIFO. RVAL is updated on the rising edge of RFCLK. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS' INTERNAL USE 27 PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 Pin Name RSOC ISSUE 5 Type Output Pin No. P23 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) Function The UTOPIA receive start of cell (RSOC) signal marks the start of a cell structure on the RDAT bus. In 16-bit Level 2 ATM mode, the first word of the cell structure is present on the RDAT[15:0] bus when RSOC is high. RSOC is tri-stated when RENB is sampled high. In 8-bit Level 3 ATM mode, the first byte of the cell structure is present on the RDAT[7:0] bus when RSOC is high. RDAT[15:8] are invalid and must be ignored. RSOC is updated on the rising edge of RFCLK. RPRTY Output P21 The UTOPIA receive parity (RPRTY) signal indicates the parity of the RDAT bus. When in 16-bit Level 2 ATM mode, the RPRTY signal indicates the parity on the RDAT[15:0] bus. RPRTY is tri-stated when RENB is sampled high. Odd or even parity selection is made in the RXCP registers. When in 8-bit Level 3 ATM mode, the RPRTY signal indicates the parity on the RDAT[7:0] bus. Odd or even parity selection is made in the RUL3 registers. RPRTY is updated on the rising edge of RFCLK. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS' INTERNAL USE 28 PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 Pin Name RENB ISSUE 5 Type Input Pin No. N23 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) Function The UTOPIA receive read enable (RENB) is used to initiate reads from the receive FIFO. The system may de-assert RENB if it is unable to accept more data. In 16-bit Level 2 ATM mode, a read is not performed and RDAT[15:0], RPRTY and RSOC will tristate when RENB is sampled high. When RENB is sampled low, the word on the RDAT[15:0] bus is read from the receive FIFO and changes to the next value on the next clock cycle. In 8-bit Level 3 ATM mode, a read is not performed and RDAT[7:0] does not change when RENB is sampled high. When RENB is sampled low, the word on the RDAT[7:0] bus is read from the receive FIFO and changes to the next value on the next clock cycle. RENB is sampled on the rising edge of RFCLK. RCA Output N20 The UTOPIA receive cell available (RCA) provides direct status indication of when a cell is available in the receive FIFO. In 16-bit Level 2 mode, RCA can be configured to de-assert when either zero or four bytes remain in the FIFO. RCA will thus transition low on the rising edge of RFCLK after payload word 24 or 19 is output on the RDAT[15:0] bus depending on the RXCP registers. In 8-bit Level 3 mode, RCA is ignored as the RVAL signal identifies valid data on the RDAT[7:0] bus. RCA is updated on the rising edge of RFCLK. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS' INTERNAL USE 29 PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 9.5 ISSUE 5 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) Microprocessor Interface Signals Pin Name CSB Type Input Pin No. C11 Function The active-low chip select (CSB) signal is low during S/UNI-622MAX S/UNI-622MAX register accesses. When CSB is high, the RDB and WRB inputs are ignored. When CSB is low, the RDB and WRB are valid. CSB must be high when RSTB is low to properly reset the chip. If CSB is not required (i.e., registers accesses are controlled using the RDB and WRB signals only), CSB must be connected to an inverted version of the RSTB input. RDB Input B11 The active-low read enable (RDB) signal is low during S/UNI622-MAX S/UNI622-MAX register read accesses. The S/UNI-622-MAX S/UNI-622-MAX drives the D[7:0] bus with the contents of the addressed register while RDB and CSB are low. WRB Input A11 The active-low write strobe (WRB) signal is low during a S/UNI622-MAX S/UNI622-MAX register write accesses. The D[7:0] bus contents are clocked into the addressed register on the rising WRB edge while CSB is low. D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] I/O B17 A17 C16 B16 C15 B15 A15 D14 The bi-directional data bus D[7:0] is used during S/UNI-622MAX S/UNI-622MAX register read and write accesses. A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] Input B14 A14 D13 C13 B13 A13 C12 B12 The address bus A[7:0] selects specific registers during S/UNI622-MAX S/UNI622-MAX register accesses. A[8] Input D11 The test register select (A[8]) signal selects between normal and test mode register accesses. A[8] is high during test mode register accesses, and is low during normal mode register accesses. A[8] may be tied low. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS' INTERNAL USE 30 PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 Pin Name RSTB ISSUE 5 Type Input Pin No. B10 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) Function The active-low reset (RSTB) signal provides an asynchronous S/UNI-622-MAX S/UNI-622-MAX reset. RSTB is a Schmitt triggered input with an integral pull-up resistor. CSB must be held high when RSTB is low in order to properly reset this chip. ALE Input A10 The address latch enable (ALE) is active-high and latches the address bus A[8:0] when low. When ALE is high, the internal address latches are transparent. It allows the S/UNI-622-MAX S/UNI-622-MAX to interface to a multiplexed address/data bus. ALE has an integral pull-up resistor. INTB Output C14 The active-low interrupt (INTB) signal is set low when a S/UNI622-MAX S/UNI622-MAX interrupt source is active and that source is unmasked. The S/UNI-622-MAX S/UNI-622-MAX may be enabled to report many alarms or events via interrupts. Examples of interrupt sources are loss of signal (LOS), loss of frame (LOF), line AIS, line remote defect indication (LRDI) detect, loss of pointer (LOP), path AIS, path remote defect indication and others. INTB is tri-stated when the all enabled interrupt sources are acknowledged via an appropriate register access. INTB is an open drain output. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS' INTERNAL USE 31 PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 9.6 ISSUE 5 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) JTAG Test Access Port (TAP) Signals Pin Name Type TCK Input A9 The test clock (TCK) signal provides clock timing for test operations that are carried out using the IEEE P1149 P1149.1 test access port. TMS Input D10 The test mode select (TMS) signal controls the test operations that are carried out using the IEEE P1149 P1149.1 test access port. TMS is sampled on the rising edge of TCK. TMS has an integral pull-up resistor. TDI Input C10 The test data input (TDI) signal carries test data into the S/UNI622-MAX S/UNI622-MAX via the IEEE P1149 P1149.1 test access port. TDI is sampled on the rising edge of TCK. TDI has an integral pull-up resistor. TDO Output C9 The test data output (TDO) signal carries test data out of the S/UNI-622-MAX S/UNI-622-MAX via the IEEE P1149 P1149.1 test access port. TDO is updated on the falling edge of TCK. TDO is a tristate output which is inactive except when shifting boundary scan data is in progress. Input B9 The active-low test reset (TRSTB) signal provides an asynchronous S/UNI-622-MAX S/UNI-622-MAX test access port reset via the IEEE P1149 P1149.1 test access port. TRSTB is a Schmitt triggered input with an integral pull-up resistor. TRSTB Pin No. Function Note that when not being used, TRSTB may be tied low or connected to the RSTB input. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS' INTERNAL USE 32 PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 9.7 ISSUE 5 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) Analog Signals Pin Name Type Pin No. Function TDREF0 TDREF1 Analog K1 K2 The transmit data reference (TDREF0 and TDREF1) analog pins are provided to create calibrated currents for the PECL output transceivers TXD+/-. A 2.00K ohm resistor is connected across the TDREF0 and TDREF1 pins. ATP[0] ATP[1] Analog E2 F3 The receive and transmit analog test ports (ATP[1:0]). These pins are used for manufacturing testing only and should be tied to analog ground (AVS). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS' INTERNAL USE 33 PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 9.8 ISSUE 5 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) Power and Ground Pin Name VBIAS[0] VBIAS[1] Type Pin No. Bias Voltage W20 E20 Function Digital input biases (VBIAS). When tied to +5V, the VBIAS inputs are used to bias the wells of the digital inputs so that the pads can tolerate up to 5V on their inputs without forward biasing internal ESD protection devices. When VBIAS are tied to +3.3V, the digital inputs will only tolerate 3.3V level voltages. The system interface inputs (RFCLK, RENB, TFCLK, TENB, TDAT[15:0], TMOD, TERR, TSOC/TSOP, TEOP and TPRTY) do not use the bias voltages and are 3.3V tolerant only. PBIAS[0] PBIAS[1] PBIAS[2] PBIAS[3] Bias Voltage W2 V3 R3 M2 PECL input biases (PBIAS). When tied to +5V, the PBIAS inputs are used to bias the wells in the PECL inputs and output so that the pads can tolerate up to 5V without forward biasing internal ESD protection devices. When the PBIAS inputs are tied to +3.3V, the pads will only tolerate 3.3V level voltages. PBIAS[0] PBIAS[1] PBIAS[2] PBIAS[3] REFCLK+/- Input RXD+/- Input RRCLK+/- Input TXD+/- Output Please see the Operation section for detailed information on PECL interfacing issues. QAVD[0] QAVD[1] Analog Power E3 R1 The quiet power (QAVD) pins for the analog core. QAVD should be connected to well-decoupled analog +3.3V supply. Please see the Operation section for detailed information. QAVS[0] QAVS[1] Analog Ground D1 P4 The quiet ground (QAVS) pins for the analog core. QAVS should be connected to analog ground of the QAVD supply. Please see the Operation section for detailed information. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS' INTERNAL USE 34 PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 ISSUE 5 Pin Name Type VDD Digital Power Pin No. A1 A23 AA3 AA21 AB2 AB22 AC1 AC23 B2 B22 C3 C21 D4 D6 D9 D12 D15 D18 D20 F4 F20 J4 J20 M4 M20 R4 R20 V4 V20 Y4 Y6 Y9 Y12 Y15 Y18 Y20 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) Function The digital power (VDD) pins should be connected to a welldecoupled +3.3 V digital power supply. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS' INTERNAL USE 35 PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 Pin Name VSS ISSUE 5 Type Digital Ground Pin No. A2 A6 A8 A12 A16 A18 A22 AA2 AA22 AB1 AB3 AB21 AB23 AC2 AC6 AC8 AC12 AC16 AC18 AC22 B1 B3 B21 B23 C2 C22 F1 F23 H1 H23 M1 M23 T1 T23 V1 V23 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) Function The digital ground (VSS) pins should be connected to the digital ground of the digital power supply. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS' INTERNAL USE 36 PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 Pin Name AVD[0] AVD[1] AVD[2] AVD[3] AVD[4] AVD[5] AVD[6] AVD[7] AVD[8] AVD[9] AVD[10] AVD[11] AVD[12] AVD[13] AVD[14] AVD[15] AVD[16] AVD[17] AVD[18] AVD[19] AVD[20] AVD[21] AVD[22] AVD[23] AVD[24] AVD[25] AVD[26] AVD[27] AVD[28] AVD[29] AVD[30] AVD[31] ISSUE 5 Type Analog Power Pin No. D3 D2 F2 H3 J2 K4 K3 L3 P1 T4 U3 Y1 W3 AA4 AC3 AA5 AB5 AC5 AA7 AB7 AA8 AA9 Y10 AC9 AB10 D8 C7 B6 B5 A4 A3 C4 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) Function The analog power (AVD) pins for the analog core. The AVD pins should be connected through passive filtering networks to a welldecoupled +3.3V analog power supply. Please see the Operation section for detailed information. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS' INTERNAL USE 37 PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 Pin Name AVS[0] AVS[1] AVS[2] AVS[3] AVS[4] AVS[5] AVS[6] AVS[7] AVS[8] AVS[9] AVS[10] AVS[11] AVS[12] AVS[13] AVS[14] AVS[15] AVS[16] AVS[17] AVS[18] AVS[19] AVS[20] AVS[21] AVS[22] AVS[23] AVS[24] AVS[25] AVS[26] AVS[27] AVS[28] AVS[29] AVS[30] AVS[31] AVS[32] AVS[33] AVS[34] AVS[35] AVS[36] AVS[37] AVS[38] AVS[39] ISSUE 5 Type Analog Ground Pin No. E4 C1 G3 H4 G2 G1 H2 J3 J1 L4 M3 N1 N2 N3 N4 T2 T3 U4 W4 Y3 Y5 AB4 AC4 AA6 Y7 AB6 Y8 AC7 AB8 AB9 AA10 AC10 A7 B7 A5 D7 C6 C5 B4 D5 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) Function The analog ground (AVS) pins for the analog core. The AVS pins should be connected to the analog ground of the analog power supply. Please see the Operation section for detailed information. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS' INTERNAL USE 38 PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 ISSUE 5 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) Notes on Pin Description: 1. All S/UNI-622-MAX S/UNI-622-MAX inputs and bi-directional signals present minimum capacitive loading and operate at TTL logic levels except the inputs marked as Analog or differential pseudo-ECL (PECL). 2. The RDAT[15:0], RCA, RCLK, RFPO, RVAL, TCA, TCLK, TFPO, POUT[7:0], FPOUT and OOF outputs have a 8mA drive capability. The TDO and INTB outputs have a 2mA drive capability. All other digital outputs and bi-directional signals have 4mA drive capability. 3. The system interface inputs RFCLK, RENB, TFCLK, TENB, TDAT[15:0], and TPRTY do not use the ESD bias voltages (VBIAS and PBIAS pins) and are 3.3V tolerate only. All other digital inputs (excluding inputs marked Analog), may operate with 5V signalling with appropriate ESD biasing. 4. The differential pseudo-ECL inputs and outputs should be terminated in a passive network and interface at PECL levels as described in the Operations section. 5. It is mandatory that every digital ground pin (VSS) be connected to the printed circuit board ground plane to ensure reliable device operation. 6. It is mandatory that every digital power pin (VDD) be connected to the printed circuit board power plane to ensure reliable device operation. 7. All analog power and ground pins can be sensitive to noise. They must be isolated from the digital power and ground. Care must be taken to correctly decouple these pins. Please refer to the Operation section and the S/UNI-622-MAX S/UNI-622-MAX reference design (PMC-981070 PMC-981070) for more information. 8. Due to ESD protection structures in the pads it is necessary to exercise caution when powering a device up or down. ESD protection devices behave as diodes between power supply pins and from I/O pins to power supply pins. Under extreme conditions it is possible to damage these ESD protection devices or trigger latch up. Please adhere to the recommended power supply sequencing as described in the Operation section of this document. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS' INTERNAL USE 39 PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 10 ISSUE 5 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) FUNCTIONAL DESCRIPTION 10.1 Receive Line Interface (CRSI-622 CRSI-622) The Receive Line Interface allows direct interface of the S/UNI-622-MAX S/UNI-622-MAX to optical modules (ODLs) or other medium interfaces. This block performs clock and data recovery on the incoming 622.08 Mbit/s data stream and SONET/SDH A1/A2 pattern framing. Clock Recovery The clock recovery unit recovers the clock from the incoming bit serial data stream and is compliant with SONET and SDH jitter tolerance requirements. The clock recovery unit utilizes a low frequency reference clock to train and monitor its clock recovery PLL. Under loss of transition conditions, the clock recovery unit continues to output a line rate clock that is locked to this reference for keep alive purposes. The clock recovery unit utilizes a 77.76 MHz reference clock. The clock recovery unit provides status bits that indicate whether it is locked to data or the reference and also supports diagnostic loopback and a loss of signal input that squelches normal input data. Initially upon start-up, the PLL locks to the reference clock, REFCLK. When the frequency of the recovered clock is within 488 ppm of the reference clock, the PLL attempts to lock to the data. Once in data lock, the PLL reverts to the reference clock if no data transitions occur in 96 bit periods or if the recovered clock drifts beyond 488 ppm of the reference clock. When the transmit clock is derived from the recovered clock (loop timing), the accuracy of the transmit clock is directly related to the REFCLK reference accuracy in the case of a loss of transition condition. To meet the Bellcore GR-253-CORE GR-253-CORE SONET Network Element free-run accuracy specification, the reference must be within +/-20 ppm. For LAN applications, the REFCLK accuracy may be relaxed to +/-50 ppm. The loop filter transfer function is optimized to enable the PLL to track the jitter, yet tolerate the minimum transition density expected in a received SONET/SDH data signal. The total loop dynamics of the clock recovery PLL yield a jitter tolerance that exceeds the minimum tolerance specified for SONET/SDH equipment by GR-253-CORE GR-253-CORE. Note that for frequencies below 300Hz, the jitter tolerance is greater than 22 UIpp; 22UIpp is the maximum jitter tolerance of the test equipment. The dip in the jitter tolerance curve between 10 kHz and 30 kHz is due to the clock difference detector. The typical jitter tolerance performance of the S/UNI-622-MAX S/UNI-622-MAX is shown in Figure 3 with the GR253-CORE GR253-CORE jitter tolerance specification limits. The jitter tolerance setup used a Hewlett Packard HFBR-5208M HFBR-5208M multi-mode fiber optic transceiver with approximately -10 dBm input power. The RTYPE register bit in CRSI-622 CRSI-622 was set to logic zero. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS' INTERNAL USE 40 PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 ISSUE 5 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) Note that for frequencies below 300Hz, the jitter tolerance is greater than 22 UIpp; 22UIpp is the maximum jitter tolerance of the test equipment. The dip in the jitter tolerance curve between 10 kHz and 30 kHz is due to the clock difference detector. Figure 3: Typical STS-12c/STM-4-4c S/UNI-622-MAX S/UNI-622-MAX Jitter Tolerance 100 Jitter Tolerance [UIpp] 10 1 0.1 10 100 1000 10000 100000 1000000 10000000 Jitter Frequency [Hz] Serial to Parallel Converter The Serial to Parallel Converter (SIPO) converts the received bit serial stream to a byte serial stream. The SIPO searches for the initial SONET/SDH framing pattern in the receive stream, and performs serial to parallel conversion on octet boundaries. While out of frame, the CRSI-622 CRSI-622 block monitors the bit-serial STS-12c/STM-4-4c data stream for an occurrence of a A1 byte. The CRSI-622 CRSI-622 adjusts its byte alignment of the serial-to-parallel converter when three consecutive A1 bytes followed by three consecutive A2 bytes occur in the data stream. The CRSI informs the RSOP Framer block when this framing pattern has been detected to reinitializes the RSOP to the new frame alignment. While in frame, the CRSI-622 CRSI-622 maintains the byte alignment of the serial-to-parallel converter until RSOP declares out of frame. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS' INTERNAL USE 41 PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 ISSUE 5 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) 10.2 Receive Section Overhead Processor (RSOP) The Receive Section Overhead Processor (RSOP) provides frame synchronization, descrambling, section level alarm and performance monitoring. Framer The Framer Block determines the in-frame/out-of-frame status of the receive stream. While inframe, the framing bytes (A1, A2) in each frame are compared against the expected pattern. Outof-frame is declared when four consecutive frames containing one or more framing pattern errors have been received. While out of frame, the CRSI-622 CRSI-622 block monitors the bit-serial STS-12c/STM-4-4c data stream for an occurrence of the framing pattern (A1, A2). The CRSI-622 CRSI-622 informs the RSOP Framer block when three A1 bytes followed by three A2 bytes has been detected to reinitializes the frame byte counter to the new alignment. The Framer block declares frame alignment on the next SONET/SDH frame when either all A1 and A2 bytes are seen error-free or when only the first A1 byte and the first four bits of the last A2 byte are seen error-free depending upon the selected framing algorithm. Once in frame, the Framer block monitors the framing pattern sequence and declares out of frame (OOF) when one or more bits errors in each framing pattern are detected for four consecutive frames. Again, depending upon the algorithm either 24 framing bytes are examined for bit errors each frame, or only the first A1 byte and the first four bits of the last A2 byte are examined for bit errors each frame. When the parallel line interface PIN[7:0] is used, upstream circuitry monitors the receive stream for an occurrence of the three A1 bytes followed by three A2 bytes framing pattern while out-offrame. The upstream circuitry is expected to pulse input FPIN when the third A2 byte has been detected. RSOP monitors the receive data stream on PIN[7:0] for the framing pattern as before. Once in frame, RSOP monitors the framing pattern sequence and sets the OOF pin when one or more bit errors in each framing pattern are detected for four consecutive frames. Descramble The Descramble Block utilizes a frame synchronous descrambler to process the receive stream. The generating polynomial is x7 + x6 + 1 and the sequence length is 127. Details of the descrambling operation are provided in the references. Note that the framing bytes (A1 and A2) and the trace/growth bytes (J0/Z0) are not descrambled. A register bit is provided to disable the descrambling operation. Error Monitor The Error Monitor Block calculates the received section BIP-8 error detection code (B1) based on the scrambled data of the complete STS-12c/STM-4-4c frame. The section BIP-8 code is based on a bit interleaved parity calculation using even parity. The calculated BIP-8 code is compared PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS' INTERNAL USE 42 PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 ISSUE 5 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) with the BIP-8 code extracted from the B1 byte of the following frame. Differences indicate that a section level bit error has occurred. Up to 64000 (8 x 8000) bit errors can be detected per second. The Error Monitor Block accumulates these section level bit errors in a 16-bit saturating counter that can be read via the microprocessor interface. Circuitry is provided to latch this counter so that its value can be read while simultaneously resetting the internal counter to 0 or 1, if appropriate, so that a new period of accumulation can begin without loss of any events. It is intended that this counter be polled at least once per second so as not to miss bit error events. Loss of Signal The Loss of Signal Block monitors the scrambled data of the receive stream for the absence of 1's or 0's. When 20 ± 3 µs of all zeros patterns or all ones patterns are detected, a loss of signal (LOS) is declared. Loss of signal is cleared when two valid framing words are detected and during the intervening time, no loss of signal condition is detected. The LOS signal is optionally reported on the RALRM output pin when enabled by the LOSEN Receive Alarm Control Register bit. Loss of Frame The Loss of Frame Block monitors the in-frame / out-of-frame status of the Framer Block. A loss of frame (LOF) is declared when an out-of-frame (OOF) condition persists for 3 ms. The LOF is cleared when an in-frame condition persists for a period of 3 ms. To provide for intermittent outof-frame (or in-frame) conditions, the 3 ms timer is not reset to zero until an in-frame (or out-offrame) condition persists for 3 ms. The LOF and OOF signals are optionally reported on the RALRM output pin when enabled by the LOFEB and OOFEN Receive Alarm Control Register bits. 10.3 Receive Line Overhead Processor (RLOP) The Receive Line Overhead Processor (RLOP) provides line level alarm and performance monitoring. Line RDI Detect The Line RDI Detect Block detects the presence of Line Remote Defect Indication (LRDI) in the receive stream. Line RDI is declared when a 110 binary pattern is detected in bits 6, 7, and 8 of the K2 byte, for three or five consecutive frames. Line RDI is removed when any pattern other than 110 is detected in bits 6, 7, and 8 of the K2 byte for three or five consecutive frames. The LRDI signal is optionally reported on the RALRM output pin when enabled by the LRDIEN Receive Alarm Control Register bit. Line AIS Detect The Line AIS Block detects the presence of a Line Alarm Indication Signal (LAIS) in the receive stream. Line AIS is declared when a 111 binary pattern is detected in bits 6, 7, and 8 of the K2 byte, for three or five consecutive frames. Line AIS is removed when any pattern other than 111 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS' INTERNAL USE 43 PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 ISSUE 5 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) is detected in bits 6, 7, and 8 of the K2 byte for three or five consecutive frames. The LAIS signal is optionally reported on the RALRM output pin when enabled by the LAISEN Receive Alarm Control Register bit. Error Monitor Block The Error Monitor Block calculates the received line BIP-8 error detection codes based on the Line Overhead bytes and synchronous payload envelopes of the STS-12c/STM-4-4c stream. The line BIP-8 code is a bit interleaved parity calculation using even parity. Details are provided in the references. The calculated BIP-8 codes are compared with the BIP-8 codes extracted from the following frame. Any differences indicate that a line layer bit error has occurred. Optionally the RLOP can be configured to count a maximum of only one BIP error per frame. This block also extracts the line FEBE code from the M1 byte. The FEBE code is contained in bits 2 to 8 of the M1 byte, and represents the number of line BIP-8 errors that were detected in the last frame by the far end. The FEBE code value has 97 legal values (0 to 96) for an STS12c/STM-4-4c stream. Illegal values are interpreted a zero errors. The Error Monitor Block accumulates B2 error events and FEBE events in two 20-bit saturating counters that can be read via the CBI. The contents of these counters may be transferred to internal holding registers by writing to any one of the counter addresses, or by using the TIP register bit feature. During a transfer, the counter value is latched and the counter is reset to 0 (or 1, if there is an outstanding event). Note, these counters should be polled at least once per second to avoid saturation. The B2 error event counters optionally can be configured to accumulate only "word" errors. A B2 word error is defined as the occurrence of one or more B2 bit error events during a frame. The B2 error counter is incremented by one for each frame in which a B2 word error occurs. In addition the FEBE events counters optionally can be configured to accumulate only "word" events. A FEBE word event is defined as the occurrence of one or more FEBE bit events during a frame. The FEBE event counter is incremented by one for each frame in which a FEBE event occurs. If the extracted FEBE value is in the range 1 to 4 the FEBE event counter will be incremented for each and every FEBE bit. If the extracted FEBE value is greater then 4 the FEBE event counter will be incremented by 4. 10.4 The Receive APS, Synchronization Extractor and Bit Error Monitor (RASE) Automatic Protection Switch Control The Automatic Protection Switch (APS) control block filters and captures the receive automatic protection switch channel bytes (K1 and K2) allowing them to be read via the RASE APS K1 Register and the RASE APS K2 Register. The bytes are filtered for three frames before being written to these registers. A protection switching byte failure alarm is declared when twelve successive frames have been received, where no three consecutive frames contain identical K1 bytes. The protection switching byte failure alarm is removed upon detection of three consecutive PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS' INTERNAL USE 44 PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 ISSUE 5 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) frames containing identical K1 bytes. The detection of invalid APS codes is done in software by polling the RASE APS K1 Register and the RASE APS K2 Register. Bit Error Rate Monitor The Bit Error Monitor Block (BERM) calculates the received line BIP-96 BIP-96 error detection code (B2) based on the line overhead and synchronous payload envelope of the receive data stream. The line BIP-96 BIP-96 code is a bit interleaved parity calculation using even parity. Details are provided in the references. The calculated BIP code is compared with the BIP-96 BIP-96 code extracted from the B2 bytes of the following frame. Any differences indicate that a line layer bit error has occurred. Up to 768,000 (96 BIP/frame x 8000 frames/second) bit errors can be detected per second for STS12c/STM-4-4c rate. The BERM accumulates these line layer bit errors in a 20 bit saturating counter that can be read via the microprocessor interface. During a read, the counter value is latched and the counter is reset to 0 (or 1, if there is an outstanding event). Note, this counter should be polled at least once per second to avoid saturation that in turn may result in missed bit error events. The BERM block is able to simultaneously monitor for signal fail (SF) or signal degrade (SD) threshold crossing and provide alarms through software interrupts. The bit error rates associated with the SF or SD alarms are programmable over a range of 10-3 to 10-9. Details are provided in the Operations section. Synchronization Status Extraction The Synchronization Status Extraction (SSE) Block extracts the synchronization status (S1) byte from the line overhead. The SSE block can be configured to capture the S1 nibble after three or after eight frames with the same value (filtering turned on) or after any change in the value (filtering turned off). The S1 nibble can be read via the CBI interface. 10.5 Receive Path Overhead Processor (RPOP) The Receive Path Overhead Processor (RPOP) provides pointer interpretation, extraction of path overhead, extraction of the synchronous payload envelope, and path level alarm indication and performance monitoring. Pointer Interpreter The Pointer Interpreter interprets the incoming pointer (H1, H2) as specified in the references. The pointer value is used to determine the location of the path overhead (the J1 byte) in the incoming STS-12c/STM-4-4c stream. The algorithm can be modeled by a finite state machine. Within the pointer interpretation algorithm three states are defined as shown below: NORM_state (NORM) AIS_state (AIS) LOP_state (LOP) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS' INTERNAL USE 45 PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 ISSUE 5 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) The transition between states will be consecutive events (indications), e.g., three consecutive AIS indications to go from the NORM_state to the AIS_state. The kind and number of consecutive indications activating a transition is chosen such that the behavior is stable and insensitive to low BER. The only transition on a single event is the one from the AIS_state to the NORM_state after receiving a NDF enabled with a valid pointer value. It should be noted that, since the algorithm only contains transitions based on consecutive indications, this implies that, for example, nonconsecutively received invalid indications do not activate the transitions to the LOP_state. Figure 4: Pointer Interpretation State Diagram 3 x eq_new_point inc_ind / dec_ind NDF_enable NORM 3x eq_new_point 8x inv_point 8x NDF_enable 3x eq_new_point 3x AIS_ind NDF_enable 3 x AIS_ind LOP AIS 8 x inv_point The following table defines the events (indications) shown in the state diagram. Table 1: Pointer Interpreter Event (Indications) Description Event (Indication) Description norm_point disabled NDF + ss + offset value equal to active offset NDF_enable enabled NDF + ss + offset value in range of 0 to 782 or enabled NDF + ss, if NDFPOR bit is set (Note that the current pointer is not updated by an enabled NDF if the pointer is out of range). AIS_ind H1 = 'hFF, H2 = 'hFF inc_ind disabled NDF + ss + majority of I bits inverted + no majority of D bits PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS' INTERNAL USE 46 PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 ISSUE 5 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) inverted + previous NDF_enable, inc_ind or dec_ind more than 3 frames ago dec_ind disabled NDF + ss + majority of D bits inverted + no majority of I bits inverted + previous NDF_enable, inc_ind or dec_ind more than 3 frames ago inv_point not any of above (i.e., not norm_point, and not NDF_enable, and not AIS_ind, and not inc_ind and not dec_ind) new_point disabled_NDF + ss + offset value in range of 0 to 782 but not equal to active offset inc_req majority of I bits inverted + no majority of D bits inverted dec_req majority of D bits inverted + no majority of I bits inverted Note 1.- active offset is defined as the accepted current phase of the SPE (VC) in the NORM_state and is undefined in the other states. Note 2 - enabled NDF is defined as the following bit patterns: 1001, 0001, 1101, 1011, 1000. Note 3 - disabled NDF is defined as the following bit patterns: 0110, 1110, 0010, 0100, 0111. Note 4 - the remaining six NDF codes (0000, 0011, 0101, 1010, 1100, 1111) result in an inv_point indication. Note 5 - ss bits are unspecified in SONET and has bit pattern 10 in SDH Note 6 - the use of ss bits in definition of indications may be optionally disabled. Note 7 - the requirement for previous NDF_enable, inc_ind or dec_ind be more than 3 frames ago may be optionally disabled. Note 8 - new_point is also an inv_point. Note 9 - LOP is not declared if all the following conditions exist: · the received pointer is out of range (>782), · the received pointer is static, · the received pointer can be interpreted, according to majority voting on the I and D bits, as a positive or negative justification indication, · after making the requested justification, the received pointer continues to be interpretable as a pointer justification. When the received pointer returns to an in-range value, the S/UNI-622-MAX S/UNI-622-MAX will interpret it correctly. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS' INTERNAL USE 47 PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 Note 10 - ISSUE 5 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) LOP will exit at the third frame of a three frame sequence consisting of one frame with NDF enabled followed by two frames with NDF disabled, if all three pointers have the same legal value. The transitions indicated in the state diagram are defined in the following table. Table 2: Pointer Interpreter Transition Description Transition Description inc_ind/dec_ind offset adjustment (increment or decrement indication) 3 x eq_new_point three consecutive equal new_point indications NDF_enable single NDF_enable indication 3 x AIS_ind three consecutive AIS indications 8 x inv_point eight consecutive inv_point indications 8 x NDF_enable eight consecutive NDF_enable indications Note 1 - the transitions from NORM_state to NORM_state do not represent state changes but imply offset changes. Note 2 - 3 x new_point takes precedence over other events and if the IINVCNT bit is set resets the inv_point count. Note 3 - all three offset values received in 3 x eq_new_point must be identical. Note 4 - "consecutive event counters" are reset to zero on a change of state except for consecutive NDF count. The Pointer Interpreter detects loss of pointer (LOP) in the incoming STS-12c/STM-4-4c stream. LOP is declared on entry to the LOP_state as a result of eight consecutive invalid pointers or eight consecutive NDF enabled indications. The alarm condition is reported in the receive alarm port and is optionally returned to the source node by signaling the corresponding Transmit Path Overhead Processor in the local S/UNI-622-MAX S/UNI-622-MAX to insert a path RDI indication. The Pointer Interpreter detects path AIS in the incoming STS-12c/STM-4-4c stream. PAIS is declared on entry to the AIS_state after three consecutive AIS indications. The alarm condition reported in the receive alarm port and is optionally returned to the source node by signaling the corresponding Transmit Path Overhead Processor in the local SONET/SDH equipment to insert a path RDI indication. Invalid pointer indications (inv_point), invalid NDF codes, new pointer indications (new_point), discontinuous change of pointer alignment, and illegal pointer changes are also detected and reported by the Pointer Interpreter block via register bits. An invalid NDF code is any NDF code that does not match the NDF enabled or NDF disabled definitions. The third occurrence of equal PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS' INTERNAL USE 48 PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 ISSUE 5 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) new_point indications (3 x eq_new_point) is reported as a discontinuous change of pointer alignment event (DISCOPA) instead of a new pointer event and the active offset is updated with the receive pointer value. An illegal pointer change is defined as a inc_ind or dec_ind indication that occurs within three frames of the previous inc_ind, dec_ind or NDF_enable indications. Illegal pointer changes may be optionally disabled via register bits. The active offset value is used to extract the path overhead from the incoming stream and can be read from an internal register. SPE Timing The SPE Timing Block provides SPE timing information to the Error Monitor and the Extract blocks. The block contains a free running timeslot counter that is initialized by a J1 byte identifier (which identifies the first byte of the SPE). Control signals are provided to the Error Monitor and the Extract blocks to identify the Path Overhead bytes and to downstream circuitry to extract the ATM cell payload. Error Monitor The Error Monitor Block contains two 16-bit counters that are used to accumulate path BIP-8 errors (B3), and far end block errors (FEBEs). The contents of the two counters may be transferred to holding registers, and the counters reset under microprocessor control. Path BIP-8 errors are detected by comparing the path BIP-8 byte (B3) extracted from the current frame, to the path BIP-8 computed for the previous frame. FEBEs are detected by extracting the 4-bit FEBE field from the path status byte (G1). The legal range for the 4-bit field is between 0000 and 1000, representing zero to eight errors. Any other value is interpreted as zero errors. Path RDI alarm is detected by extracting bit 5 of the path status byte. The PRDI signal is set high when bit 5 is set high for five/ten consecutive frames. PRDI is set low when bit 5 is low for five/ten consecutive frames. Auxiliary RDI alarm is detected by extracting bit 6 of the path status byte. The Auxiliary RDI alarm is indicated when bit 6 is set high for five/ten consecutive frames. The Auxiliary RDI alarm is removed when bit 6 is low for five/ten consecutive frames. The Enhanced RDI alarm is detected when the enhanced RDI code in bits 5,6,7 of the path status byte indicates the same error codepoint for five/ten consecutive frames. The Enhanced RDI alarm is removed when the enhanced RDI code in bits 5,6,7 of the path status byte indicates the same non error codepoint for five/ten consecutive frames. The ERDII maskable interrupt is set high when bits 5, 6 & 7 of the path status byte (G1) byte are set to a new codepoint for five or ten consecutive frames. The ERDIV[2:0] signal reflects the state of the filtered ERDI value (G1 byte bits 5, 6, & 7). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS' INTERNAL USE 49 PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 ISSUE 5 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) 10.6 Receive ATM Cell Processor (RXCP) The Receive ATM Cell Processor (RXCP) performs ATM cell delineation, provides cell filtering based on idle/unassigned cell detection and HCS error detection, and performs ATM cell payload descrambling. The RXCP also provides a four-cell deep receive FIFO. This FIFO is used to separate the STS-12c/STM-4-4c line timing from the higher layer ATM system timing. Cell Delineation Cell Delineation is the process of framing to ATM cell boundaries using the header check sequence (HCS) field found in the cell header. The HCS is a CRC-8 calculation over the first 4 octets of the ATM cell header. When performing delineation, correct HCS calculations are assumed to indicate cell boundaries. Cells are assumed to be byte-aligned to the synchronous payload envelope. The cell delineation algorithm searches the 53 possible cell boundary candidates individually to determine the valid cell boundary location. While searching for the cell boundary location, the cell delineation circuit is in the HUNT state. When a correct HCS is found, the cell delineation state machine locks on the particular cell boundary, corresponding to the correct HCS, and enters the PRESYNC state. The PRESYNC state validates the cell boundary location. If the cell boundary is invalid, an incorrect HCS will be received within the next DELTA cells, at which time a transition back to the HUNT state is executed. If no HCS errors are detected in this PRESYNC period, the SYNC state is entered. While in the SYNC state, synchronization is maintained until ALPHA consecutive incorrect HCS patterns are detected. In such an event a transition is made back to the HUNT state. The state diagram of the delineation process is shown in Figure 5. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS' INTERNAL USE 50 PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 ISSUE 5 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) Figure 5: Cell Delineation State Diagram correct HCS (byte by byte) HUNT Incorrect HCS (cell by cell) PRESYNC ALPHA consecutive incorrect HCS's (cell by cell) SYNC DELTA consecutive correct HCS's (cell by cell) The values of ALPHA and DELTA determine the robustness of the delineation process. ALPHA determines the robustness against false misalignments due to bit errors. DELTA determines the robustness against false delineation in the synchronization process. ALPHA is chosen to be 7 and DELTA is chosen to be 6. These values result in an average time to delineation of 8 µs for the STS-12c/STM-4-4c rate. Descrambler The self-synchronous descrambler operates on the 48 byte cell payload only. The circuitry descrambles the information field using the x43 + 1 polynomial. The descrambler is disabled for the duration of the header and HCS fields and may optionally be disabled for the payload. Cell Filter and HCS Verification Cells are filtered (or dropped) based on HCS errors and/or a cell header pattern. Cell filtering is optional and is enabled through the RXCP registers. Cells are passed to the receive FIFO while the cell delineation state machine is in the SYNC state as described above. When both filtering and HCS checking are enabled, cells are dropped if uncorrectable HCS errors are detected, or if the corrected header contents match the pattern contained in the RXCP Match Header Pattern and RXCP Match Header Mask registers. Idle or unassigned cell filtering is accomplished by writing the appropriate cell header pattern into the RXCP Match Header Pattern and RXCP Match Header Mask registers. Idle/Unassigned cells are assumed to contain the all zeros pattern in the PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS' INTERNAL USE 51 PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 ISSUE 5 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) VCI and VPI fields. The RXCP Match Header Pattern and RXCP Match Header Mask registers allow filtering control over the contents of the GFC, PTI, and CLP fields of the header. The HCS is a CRC-8 calculation over the first 4 octets of the ATM cell header. The RXCP block verifies the received HCS using the polynomial, x8 + x2 + x + 1. The coset polynomial, x6 + x4 + x2 + 1, is added (modulo 2) to the received HCS octet before comparison with the calculated result. While the cell delineation state machine in Figure 5 is in the SYNC state, the HCS verification circuit implements the state machine shown in Figure 6. In normal operation, the HCS verification state machine remains in the 'Correction Mode' state. Incoming cells containing no HCS errors are passed to the receive FIFO. Incoming single-bit errors are corrected, and the resulting cell is passed to the FIFO. Upon detection of a single-bit error or a multi-bit error, the state machine transitions to the 'Detection Mode' state. In this state, programmable HCS error filtering is provided. The detection of any HCS error causes the corresponding cell to be dropped. The state machine transitions back to the 'Correction Mode' state when M (where M = 1, 2, 4, 8) cells are received with correct HCSs. The Mth cell is not discarded. Figure 6: HCS Verification State Diagram ATM DELINEATION SYNC STATE ALPHA consecutive incorrect HCS's (To HUNT state) Apparent Multi-Bit Error (Drop Cell) No Errors Detected (Pass Cell) CORRECTION MODE Single-Bit Error (Correct Error and Pass Cell) Errors Detected (Drop Cell) DETECTION MODE DELTA consecutive correct HCS's (From PRESYNC state) No Errors Detected In M Cells (Pass Mth Cell) No Errors Detected (Pass Cell) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS' INTERNAL USE 52 PMC-Sierra, Inc. PM5356 PM5356 S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX S/UNI-622-MAX DATASHEET PMC-1980589 PMC-1980589 ISSUE 5 SATURN USER NETWORK INTERFACE (622-MAX 622-MAX) Performance Monitor The Performance Monitor consists of two 12-bit saturating HCS error event counters and a 21-bit saturating receive cell counter. The first error counter accumulates correctable HCS errors, which are HCS single-bit errors, detected and corrected while the HCS Verification state machine is in the 'Correction Mode' state. The second error counter accumulates uncorrectable HCS errors, which are HCS bit errors detected while the HCS Verification state machine is in the 'Detection Mode' state or HCS bit errors detected but not corrected while the state machine is in the 'Correction Mode' state. The 21-bit receive cell counter counts all cells written into the receive FIFO. Filtered cells are not counted. Each counter may be read through the microprocessor interface. Circuitry is provided to latch these counters so that their values can be read while simultaneously resetting the internal counters to 0 or 1, if appropriate, so that a new period of accumulation can begin without loss of any events. It is intended that the counter be polled at least once per second so as not to miss any counted events. Receive FIFO The Receive FIFO block contains storage for 4 cells, along with management circuitry for reading and writing the FIFO. The receive FIFO provides for the separation of the physical layer timing from the system timing. Receive FIFO management functions include filling the receive FIFO, indicating when cells are available to be read from the receive FIFO, maintaining the receive FIFO read and write pointers, and detecting FIFO overrun conditions. Upon detection of an overrun, the FIFO discards the current cell and discards the incoming cells until there is room in the FIFO. FIFO overruns are indicated through a maskable interrupt and register bit and are considered a system error. 10.7 Transmit Line Interface (CSPI-622 CSPI-622) The Transmit Line Interface allows to directly interface the S/UNI-622-MAX S/UNI-622-MAX with optical modules (ODLs) or other medium interfaces. This block performs clock synthesis and performs parallel to serial conversion on the incoming outgoing 622.08 Mbit/s data stream. Clock Synthesis The transmit clock is synthesized from a 77.76. MHz reference by the clock synthesis unit (CSU). The transfer function yields a typical low pass corner of 1 MHz, above which reference jitter is attenuated at least 20 dB per octave. The design of the loop filter and PLL is optimized for minimum intrinsic jitter.