PM5316/PM5310 PMC-1991245 SPECTRA-4X155 PM5316 PM5310 STS-12 PMC-990822 - Datasheet Archive

 

PRELIMINARY REFERENCE DESIGN PMC-1991245 ISSUE 1 SPECTRA-4X155 WITH TBS REFERENCE DESIGN PM5316/PM5310 SPECTRA-4X155 WITH TBS

 

PM5316/PM5310 PM5316/PM5310 PRELIMINARY REFERENCE DESIGN PMC-1991245 PMC-1991245 ISSUE 1 SPECTRA-4X155 SPECTRA-4X155 WITH TBS REFERENCE DESIGN PM5316/PM5310 PM5316/PM5310 SPECTRA-4X155 SPECTRA-4X155 WITH TBS REFERENCE DESIGN PRELIMINARY ISSUE 1: JUNE 2000 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE PM5316/PM5310 PM5316/PM5310 PRELIMINARY REFERENCE DESIGN PMC-1991245 PMC-1991245 ISSUE 1 SPECTRA-4X155 SPECTRA-4X155 WITH TBS REFERENCE DESIGN PUBLIC REVISION HISTORY Issue No. Issue Date Details of Change 1 June 2000 Document created. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE PM5316/PM5310 PM5316/PM5310 PRELIMINARY REFERENCE DESIGN PMC-1991245 PMC-1991245 ISSUE 1 SPECTRA-4X155 SPECTRA-4X155 WITH TBS REFERENCE DESIGN CONTENTS 1 DEFINITIONS . 1 2 FEATURES . 2 3 APPLICATIONS . 3 4 REFERENCES. 4 5 APPLICATION EXAMPLES . 5 6 BLOCK DIAGRAM . 6 7 FUNCTIONAL DESCRIPTION. 7 7.1 PM5316 PM5316 SPECTRA-4X155 SPECTRA-4X155 . 7 7.2 PM5310 PM5310 TBS . 8 7.3 PLX TECHNOLOGY 9054 PCI INTERFACE. 8 7.4 CPLD. 9 7.5 CLOCKS. 10 7.6 POWER SUPPLY.11 7.6.1 VOLTAGE REGULATORS .11 7.6.2 HOT SWAP CONTROLLER .11 7.7 8 SYSTEM INTERFACE . 13 IMPLEMENTATION DESCRIPTION . 15 8.1 ROOT DRAWING, PAGE 1 . 15 8.2 OPTICS BLOCK, PAGE 2 . 15 8.3 SPECTRA-4X155 SPECTRA-4X155 BLOCK, PAGES 3,4,5,6 & 7 . 15 8.4 TBS BLOCK, PAGES 8, 9,10, & 11. 16 8.5 SYSTEM INTERFACE BLOCK, PAGE 12. 17 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE i PM5316/PM5310 PM5316/PM5310 PRELIMINARY REFERENCE DESIGN PMC-1991245 PMC-1991245 ISSUE 1 SPECTRA-4X155 SPECTRA-4X155 WITH TBS REFERENCE DESIGN 8.6 CPLD BLOCK, PAGE 13. 17 8.7 CPCI BLOCK, PAGES 14 & 15 . 18 8.8 POWER BLOCK, PAGE 16. 18 9 SCHEMATICS AND LAYOUT . 20 10 BILL OF MATERIAL . 21 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE ii PM5316/PM5310 PM5316/PM5310 PRELIMINARY REFERENCE DESIGN PMC-1991245 PMC-1991245 ISSUE 1 SPECTRA-4X155 SPECTRA-4X155 WITH TBS REFERENCE DESIGN LIST OF FIGURES FIGURE 1 - ADD/DROP MUX. . 5 FIGURE 2 - SPECTRA-4X155 SPECTRA-4X155 REFERENCE DESIGN BOARD. 6 FIGURE 3 - CPLD FUNCTIONAL BLOCK DIAGRAM. 10 FIGURE 4 - POWER SUPPLY SYSTEM BLOCK. .11 FIGURE 5 - CPCI HOT SWAP CIRCUIT. 12 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE iii PM5316/PM5310 PM5316/PM5310 PRELIMINARY REFERENCE DESIGN PMC-1991245 PMC-1991245 ISSUE 1 SPECTRA-4X155 SPECTRA-4X155 WITH TBS REFERENCE DESIGN LIST OF TABLES TABLE 1 - WORKING AND PROTECT HS3 CONNECTOR PINOUT . 13 TABLE 2 - AUXILIARY HS3 CONNECTOR PINOUT . 14 TABLE 3 - BILL OF MATERIAL. 21 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE iv PM5316/PM5310 PM5316/PM5310 PRELIMINARY REFERENCE DESIGN PMC-1991245 PMC-1991245 1 ISSUE 1 SPECTRA-4X155 SPECTRA-4X155 WITH TBS REFERENCE DESIGN DEFINITIONS LOS Loss of signal - When a SONET receiver detects and allzeros pattern for 10 microseconds or longer, this constitutes a LOS failure. It indicates that the upstream transmitter has failed. This condition is cleared when two consecutive valid frames are received. LOF Loss of frame - The absense of valid framing pattern for 3 microseconds leads to a LOF failure condition. This is cleared when two consecutive valid A1/A2 framing patterns are received. ODL Optical Data Link ESD ElectroStatic Discharge AIS Alarm indication signal - This condition can occur in response to one of the conditions above. The SONET signal format provides AISs for the line (AIS-L), STS Path (AIS-P), and VT Path (AIS-V) layers. BER Bit Error Rate CRU Clock Recovery Unit - Recovers timing information from receive data streams. CSU Clock Synthesis Unit - Generates timing signal for transmit data streams. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 1 PM5316/PM5310 PM5316/PM5310 PRELIMINARY REFERENCE DESIGN PMC-1991245 PMC-1991245 2 ISSUE 1 SPECTRA-4X155 SPECTRA-4X155 WITH TBS REFERENCE DESIGN FEATURES · 33 MHz CompactPCI (cPCI) interface. · 4 HP MT-RJ OC-3 rate line side transceivers operating at 3.3V provide 622 Mbit/s aggregate operation. · 3.3 V CMOS ADD/DROP Telecom bus interface to the TBS ADD/DROP Telecom bus interface. · Telecom bus is configured to operate in single STS-12 STS-12 (STM-4) mode at 77.76 MHz. · CPLD performs address decoding, timing source selection and signal interfacing functions. · Line interface speeds up to 155.52 Mbit/s. · Enables 4XOC-3 channelization. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 2 PM5316/PM5310 PM5316/PM5310 PRELIMINARY REFERENCE DESIGN PMC-1991245 PMC-1991245 3 ISSUE 1 SPECTRA-4X155 SPECTRA-4X155 WITH TBS REFERENCE DESIGN APPLICATIONS · SONET/SDH Multiservice ADMs · SONET/SDH Cross Connects · SONET/SDH Terminal Multiplexers PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 3 PM5316/PM5310 PM5316/PM5310 PRELIMINARY REFERENCE DESIGN PMC-1991245 PMC-1991245 4 ISSUE 1 SPECTRA-4X155 SPECTRA-4X155 WITH TBS REFERENCE DESIGN REFERENCES 1. PMC-Sierra, Inc. PMC-990822 PMC-990822, "SPECTRA-4X155 SPECTRA-4X155 Data Sheet ", March 2000, Issue 1. 2. PMC-Sierra, Inc. PMC-990522 PMC-990522, "TBS Telecombus Serializer", May 1999, Issue 1. 3. PLX Technology, Inc. , "PCI 9054 Data Book v2.0", August 1999. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 4 PM5316/PM5310 PM5316/PM5310 PRELIMINARY REFERENCE DESIGN PMC-1991245 PMC-1991245 5 ISSUE 1 SPECTRA-4X155 SPECTRA-4X155 WITH TBS REFERENCE DESIGN APPLICATION EXAMPLES The SPECTRA-4X155 SPECTRA-4X155 WITH TBS Reference Card can be implemented as a multi-service ADM in a SONET network. Four line side OC-3 channels provide considerable flexibility for implementing SONET ring architectures. Figure 1 below outlines a typical ADM application. Figure 1 - Add/Drop MUX. SPECTRA-155 SPECTRA-155 QUAD WITH TBS Line Card OC-N DROP RING RING OC-N ADD OC-M ADD/DROP Bus OC-M DROP OC-N RING RING ADD SPECTRA-155 SPECTRA-155 QUAD WITH TBS Line Card OC-N The SPECTRA-4X155 SPECTRA-4X155 WITH TBS Line Card can also be implemented as a SONET/SDH digital cross connect. Two TBS devices on two line cards can be interfaced to create a simple switch architecture. Note that the TBS can switch at STS-1 granularity only in the parallel to serial or serial to parallel directions. A more complete digital cross-connect can be implemented utilizing the TSE as the core cross-connect element. Additionally, the Line Card can be implemented as a Terminal Multiplexer, which is similar to the ADM, except that all incoming traffic to the card is dropped. This application would allow all four OC-3 streams to be terminated in a point-to-point network. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 5 PM5316/PM5310 PM5316/PM5310 PRELIMINARY REFERENCE DESIGN PMC-1991245 PMC-1991245 6 ISSUE 1 SPECTRA-4X155 SPECTRA-4X155 WITH TBS REFERENCE DESIGN BLOCK DIAGRAM Figure 2 - SPECTRA-4x155 Reference Design Board DD DC1J1V1 DPL DDP MT-RJ MT-RJ AD AC1J1V1/AFP APL ADP MT-RJ PM5316 PM5316 SPECTRA-155 SPECTRA-155 QUAD ACK MT-RJ 8 4 4 4 8 4 4 4 ID IJ0J1 IPL IDP OD PM5310 PM5310 OJ0J1 OPL ODP SYSCLK TBS TPWRK TNWRK TPPROT TNPROT RPWRK RNWRK RPPROT RNPROT RJ0FP TJ0FP RWSEL xCMP 4 4 4 4 4 4 4 4 AMP HS3 60 PIN ADDR DATA CSB 12 16 DCK SYSCLK CSB CPLD 19.44 MHz Ref Clk 77.76 MHz Osc. REFCLK ADDR DATA 14 8 SMA PLX 9054 PCI BRIDGE CPCI 32 32 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 6 PM5316/PM5310 PM5316/PM5310 PRELIMINARY REFERENCE DESIGN PMC-1991245 PMC-1991245 7 ISSUE 1 SPECTRA-4X155 SPECTRA-4X155 WITH TBS REFERENCE DESIGN FUNCTIONAL DESCRIPTION The PM5316 PM5316 SPECTRA-4X155 SPECTRA-4X155 receives 4 OC-3 SONET/SDH serial bit streams from 4 Hewlett Packard MT-RJ optical transceivers and recovers clock and data. The chip processes SONET section, line, and path overhead. The 77.76 Mbit/s Telecom ADD/DROP bus on the SPECTRA-4X155 SPECTRA-4X155 connects directly to the Telecom ADD/DROP bus on the TBS. The extracted payload from the incoming data bit stream is placed on the DROP Telecom bus and routed to the TBS in byte-serial format. The TBS receives and serializes the incoming byte-serial data stream into a bit-serial stream. The bit-serial stream is routed to the backplane via a pair of working, a pair of auxiliary, and a pair of protect 777.6 MHz LVDS serial links with 8B/10B-based encoding. The system side of the SPECTRA-4X155 SPECTRA-4X155 device is configured to operate in single DROP/ADD Telecombus mode at 77.76 MHz. In this mode, a single STS12 STS12 byte-serial stream connects to the Telecom bus interface of the TBS device and only the lower 8 bits of the TBS's 32 bit parallel Telecombus are required to pass traffic. The reference board routes signals to and from a backplane which permits further processing by other members of the CHESS chipset. For example, the S/UNI MACH48 MACH48 is used to terminate ATM or bit/byte HDLC. The system clock source is selectable between two modes. The board can provide it's own system clock via an onboard 77.76 MHz oscillator, or it can receive the clock signal through the backplane from a timing card. The SPECTRA-4X155 SPECTRA-4X155 19.44 MHz reference clock is provided by an on board oscillator. 7.1 PM5316 PM5316 SPECTRA-4X155 SPECTRA-4X155 The PM5316 PM5316 SPECTRA-4X155 SPECTRA-4X155 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER terminates the transport and path overhead of four STS-3 155 Mbit/s streams. The SPECTRA-4X155 SPECTRA-4X155 receives SONET/SDH frames via bit serial interfaces, recovers clock and data, and terminates the SONET/SDH section, line, and path. The SPECTRA-4X155 SPECTRA-4X155 performs framing (A1,A2), descrambling, detects alarm conditions, and monitors section and line bit interleaved parity (BIP) (B1, B2), accumulating error counts at each level for performance monitoring purposes. The SPECTRA-4X155 SPECTRA-4X155 interprets the received payload pointers (H1, H2) and extracts the synchronous payload envelope (virtual container). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 7 PM5316/PM5310 PM5316/PM5310 PRELIMINARY REFERENCE DESIGN PMC-1991245 PMC-1991245 ISSUE 1 SPECTRA-4X155 SPECTRA-4X155 WITH TBS REFERENCE DESIGN The SPECTRA-4X155 SPECTRA-4X155 transmits SONET/SDH frames, via bit serial interfaces. The chip performs framing pattern insertion (A1, A2), scrambling, alarm signal insertion, and creates section and line BIPs (B1, B2) as required to allow performance monitoring at the far end. In addition to its basic processing of the transmit SONET/SDH overhead, the SPECTRA-4X155 SPECTRA-4X155 provides convenient access to all overhead bytes, which are inserted serially on lower rate interfaces, allowing additional external sourcing of overhead, if desired. The SPECTRA-4X155 SPECTRA-4X155 is implemented in 3.3V, CMOS process technology. It has TTL and positive ECL (PECL) compatible inputs and outputs. The SPECTRA-4X155 SPECTRA-4X155 is configured, controlled and monitored via a generic 8-bit microprocessor bus interface and has a standard 5 signal JTAG test port for boundary scan board test purposes. The SPECTRA-4X155 SPECTRA-4X155 is available in a 520 pin SBGA package. 7.2 PM5310 PM5310 TBS The PM5310 PM5310 TBS Telecom bus serializer is a monolithic integrated circuit that implements conversions between parallel Telecom bus and the serial Telecom bus. The TBS can be used to connect SONET/SDH framer devices to ATM/POS processor devices or to cross-connect devices. The TBS can also be used to connect cross-connect devices (like the PM5372 PM5372 TSE) to SONET/SDH tributary unit processors and PDH mapper devices. The TBS connects the Parallel-Telecom Bus to three sets of four serial LVDS links called Working, Protect and Auxiliary. Transport and payload frame boundaries, pointer justification events and alarm conditions are marked with 8B/10B 8B/10B control characters. The read Working channel selection signal (RWSEL) determines which receive S-TCB port is forwarded to the outgoing P-TCB. Software control allows for mixing the data on the outgoing P-TCB from any of the three S-TCB ports. The TBS is configured, controlled and monitored via a generic 16-bit microprocessor bus interface and has a standard 5 signal JTAG test port for boundary scan board test purposes. The TBS is available in a 352 pin UBGA package. 7.3 PLX Technology 9054 PCI Interface The PLX Technology PCI9054 PCI9054 provides the interface between the system PCI signals and the local bus on the SPECTRA-4X155 SPECTRA-4X155 Reference Design board. The system PCI signals are found on connector J1_1. The PCI9054 PCI9054 bridge provides data and address information on the local bus side, and interrupt signalling to the host processor card. The PCI9054 PCI9054 device is configured via a 1K-bit serial EEPROM device. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 8 PM5316/PM5310 PM5316/PM5310 PRELIMINARY REFERENCE DESIGN PMC-1991245 PMC-1991245 7.4 ISSUE 1 SPECTRA-4X155 SPECTRA-4X155 WITH TBS REFERENCE DESIGN CPLD The CPLD is used for chip select decoding for SPECTRA and TBS devices that share the LA[31.2] and LD[31.0] buses. The LA[16] and LA[17] bits are used to select the appropriate device to access. When LA[17] =1, the CPLD will have it's internal register accessed with the data on LD[0] and LD[1]. When LA[17] is 0, the RDB and WRB signals are passed and LA[16] bit is used to decode between the chip selects of the SPECTRA-4X155 SPECTRA-4X155 and the TBS. LA[16] =0 will assert the CSB_SPECTRA signal, while LA[16] =1 asserts the CSB_TBS signal. The internal register is used to select the clock source for SYSCLK, DCK and ACK. LD[0] selects between the backplane supplied SYSCLK signal and the onboard oscillator. The CPLD is used to change the local read/write signal from the PCI controller (L_WRB) into two separate signals for the microprocessor interface signals RDB and WRB. The CPLD acts as a buffer for the non-LVDS signals that come in from the backplane and can show debugging information with 8 LEDs. Some of the overhead signals from the SPECTRA_4X155 4X155 are routed to the CPLD for debugging/overhead monitoring. Figure 3 details the functions of the CPLD. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 9 PM5316/PM5310 PM5316/PM5310 PRELIMINARY REFERENCE DESIGN PMC-1991245 PMC-1991245 Figure 3 ISSUE 1 SPECTRA-4X155 SPECTRA-4X155 WITH TBS REFERENCE DESIGN - CPLD Functional Block Diagram L_ADSB L_WRB LHOLD LHOLDA L_READYB RDB Micro Interface Control WRB LCLK LA[17] CSB_TBS CSB_SPECTRA LA[16] Registers LD[2:0] LOCAL_OSC Divide By N SYSCLK SYSCLK1 SYSCLK2 INTB_SPECTRA INTB_TBS 7.5 INTB Clocks The 77.76 MHz system clock signal for the TBS and ACK and DCK Telecom bus clocks for the SPECTRA-4X155 SPECTRA-4X155 can be configured in two ways: from an onboard 77.76 MHz oscillator or from the backplane. The SPECTRA-4X155 SPECTRA-4X155 19.44 MHz reference with a balance of ± 20 ppm is supplied by either a 19.44 MHz oscillator or optionally the reference clock can be supplied externally through a SMB connector. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 10 PM5316/PM5310 PM5316/PM5310 PRELIMINARY REFERENCE DESIGN PMC-1991245 PMC-1991245 7.6 ISSUE 1 SPECTRA-4X155 SPECTRA-4X155 WITH TBS REFERENCE DESIGN Power Supply Figure 4 - Power Supply System Block. +5V +3.3V +5V_PCI +3.3V_PCI +12V_PCI -12V_PCI GND Hot Swap Controller LT1643L LT1643L BD_SEL# HEALTHY# PCI_RST# +12V -12V +5V 1.8V Switching Regulator The Power Block provides stable voltage supplies delivered over the CompactPCI backplane from a centralized power supply. Voltage levels of +5V, +3.3V, +12V, -12V and regulated 1.8V are available from this block. 7.6.1 Voltage Regulators Linear regulators supply the 3.3V analog and 1.8V analog pins of the SPECTRA4X155 SPECTRA4X155 and TBS devices respectively. These regulators are located on the power sheets of the SPECTRA-4X155 SPECTRA-4X155 and the TBS. The 5V to 1.8V switching regulator module is used to generate the supply labelled 1.8V. Only the TBS uses this supply. 7.6.2 Hot Swap Controller The Hot Swap Controller is used to allow the board to be safely inserted or removed from a live cPCI slot. External N-channel MOSFETS control the 3.3V and 5V supplies, while the +12V and ­12V supplies are controlled with on-chip switches. The supply voltages are ramped up at a programmable rate. The hot swap controller is implemented using the Linear Technology LTC1643L LTC1643L. A typical cPCI Hot Swap circuit is shown below in Figure 2. Note that only the hot swap controller is implemented in the power block. Additional Hot Swap circuitry including the precharge circuitry for the cPCI bus is included in the CompactPCI block. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 11 PM5316/PM5310 PM5316/PM5310 PRELIMINARY REFERENCE DESIGN PMC-1991245 PMC-1991245 ISSUE 1 Figure 5 SPECTRA-4X155 SPECTRA-4X155 WITH TBS REFERENCE DESIGN - cPCI Hot Swap Circuit 0.01 +5V_PCI 0.005 +3.3V_PCI Q1 IRF7413 IRF7413 Q1 IRF7413 IRF7413 R4 R1 R3 5V 5A 3.3V 7.6A R2 10 10 100 +12V_PCI -12V_PCI BD_SELB CompactPCI Connector V(I/O) R6 1.2k R7 2k R5 3Vin 3Vsense GATE 3Vout 5Vin 5Vsense 5Vout 12Vin VEEin ON# V(I/O) VEEout LT1643L LT1643L FAULT# R8 2k 12V PWRGD# HEALTHYB 0.1uF 12V 500mA -12V 100mA 12Vout 0.1uF GND TIMER 0.01uF GND The 3.3V, 5V, +12V, and ­12V power supplies are generated from the medium length power pins on the PCI connector (+5V_PCI, +3.3V_PCI, etc). The long power pins which make the first connections are used to generate a 1V precharge voltage on the cPCI bus pins. In the circuit above, the 3.3V and 5V power supplies are controlled by the Nchannel pass transistors Q1 and Q2. Internal circuitry controls the +/-12V /-12V rails. R1 and R2 control overcurrent conditions. R5 and C1 provide current control loop compensation. R3 and R4 prevent high frequency oscillations in the pass transistors. Finally, the 12V Zener diode protects against power surges on the ­12V rail. During an insertion and power-up sequence, the BD_SEL# pin is the final pin to connect to the board. This pin is connected to the ON# pin of the Hot Swap Controller. When the ON# pin is pulled low, the pass transistors are turned on by pulling the GATE pin high, and the current in each pass transistor rises at a rate of dv/dt = 50µA/C1, until reaching the preset limit. If there is a high load capacitance, the rate of increase will be controlled by this value. Once the supply voltages stabilize the PWRGD# signal is pulled low. The sense resistors R1 and R2 in Figure 5 above set the current limit for the 5V and 3.3V supplies. The current limit is governed by the following equation: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 12 PM5316/PM5310 PM5316/PM5310 PRELIMINARY REFERENCE DESIGN PMC-1991245 PMC-1991245 ISSUE 1 SPECTRA-4X155 SPECTRA-4X155 WITH TBS REFERENCE DESIGN I lim = 53mV / R sense In the circuit of Figure 4 above, the 3.3V current limit will be 10.6A, and the 5V limit will be 5.3A. Upon removal, the /ON pin will be pulled high, and the GATE pin on the pass transistors is pulled low to prevent load currents on the 3.3V and 5V rails from instantaneously going to zero and glitching the power supply. The /PWRGD pin is pulled high if any of the supply voltages moves below its threshold. 7.7 System Interface This board is based on the cPCI 6U (233.35mm by 160mm) board size. The J1_1 connections are standard cPCI pinouts and the connector carries 32 standard cPCI signals. The other connectors implemented in this reference design are the AMP HS3 60 pin connectors. These connectors are used to connect the 777.6 Mbit/s LVDS signals and control signals to the backplane. Note that the columns of the connector are separated by ground planes. Column 10 of the HS3 connector does not have ground shielding on the outer side, therefore low speed signals are placed in this column. The pin assignments are made in the low-noise configuration as specified by AMP. The table on the following page outlines the HS3 pinout. Table 1 Column - Working and Protect HS3 Connector Pinout A B C E F GND SYSCLK1P SYSCLK1N SYSCLK2 P SYSCLK2N GND 2 GND RPPROT4 RNPROT4 TPPROT4 TNPROT4 GND 3 GND RPPROT3 RNPROT3 TPPROT 3 TNPROT3 GND 4 GND RPPROT2 RNPROT2 TPPROT2 TNPROT2 GND 5 GND RPPROT1 RNPROT1 TPPROT1 TNPROT1 GND 6 GND RPWRK4 RNWRK4 TPWRK4 TNWRK4 GND 7 GND RPWRK3 RNWRK3 TPWRK3 TNWRK3 GND 1 D PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 13 PM5316/PM5310 PM5316/PM5310 PRELIMINARY REFERENCE DESIGN PMC-1991245 PMC-1991245 ISSUE 1 SPECTRA-4X155 SPECTRA-4X155 WITH TBS REFERENCE DESIGN Column A B C D E F 8 GND RPWRK2 RNWRK2 TPWRK2 TNWRK2 GND 9 GND RPWRK1 RNWRK1 TPWRK1 TNWRK1 GND 10- GND TJ0FP_OUT RJ0FP_IN RWSEL_I N XCMP_IN GND Table 2 Column - Auxiliary HS3 Connector Pinout A B C D E F GND GND GND GND GND GND 2 GND GND GND TNAUX4 TPAUX4 GND 3 GND GND GND TNAUX3 TPAUX3 GND 4 GND GND GND TNAUX2 TPAUX2 GND 5 GND GND GND TNAUX1 TPAUX1 GND 6 GND GND GND GND GND GND 7 GND GND GND RNAUX4 RPAUX4 GND 8 GND GND GND RNAUX3 RPAUX3 GND 9 GND GND GND RNAUX2 RPAUX2 GND 10 GND GND GND RNAUX1 RPAUX1 GND 1 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 14 PM5316/PM5310 PM5316/PM5310 PRELIMINARY REFERENCE DESIGN PMC-1991245 PMC-1991245 8 ISSUE 1 SPECTRA-4X155 SPECTRA-4X155 WITH TBS REFERENCE DESIGN IMPLEMENTATION DESCRIPTION This section describes the hardware implementation of the SPECTRA-4X155 SPECTRA-4X155 WITH TBS reference design. Each section references the schematics contained in Section 9. 8.1 Root Drawing, Page 1 This page shows the interconnection between the functional blocks of the design. 8.2 Optics Block, Page 2 Page 2 shows the optical interface of the reference design. Four HP HFCT5905E HFCT5905E MT-RJ Duplex single mode transceivers are used to transmit and receiver four OC-3 optical streams. The HFCT-5905E HFCT-5905E is a 3.3 V PECL device in a 10-pin package. The PECL signals are connected to the SPECTRA-4X155 SPECTRA-4X155 receive and transmit pins through 50 ohm controlled impedance lines. The receive and transmit lines are properly terminated at the SPECTRA-4X155 SPECTRA-4X155 and transceiver devices. The 150 ohm resistors provide source terminations for the PECL outputs from the ODL and should be placed as close as possible to the ODL. The resistor and capacitor networks between the TXDP and TXDN lines provide biasing for the SPECTRA-4X155 SPECTRA-4X155 PECL TX outputs and should also be placed close to the ODL. 8.3 Spectra-4x155 Block, Pages 3,4,5,6 & 7 The SPECTRA_4x155_BLOCK shows the SPECTRA-4X155 SPECTRA-4X155 signals and power circuitry. Page 3 contains Block 1 of the SPECTRA-4X155 SPECTRA-4X155 device. Block 1 contains the line side signals of the SPECTRA-4X155 SPECTRA-4X155. The PECL receive lines have parallel termination resistors of 100 ohms. The transmit differential TTL outputs have series capacitors of 0.1 uF to remove any DC component of the output signal and the 158 ohm resistors are used to bring the signals to PECL signaling levels. 0.22 uF capacitors are used for the loop filter pins, CP and CN. The PECLV pin is pulled to ground to select 3.3 V optics. The REFCLK source must be a 19.44 MHz ±20ppm clock signal. By means of header J4, the clock source can be selected between an on-board oscillator or from an external source via a SMB connector. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 15 PM5316/PM5310 PM5316/PM5310 PRELIMINARY REFERENCE DESIGN PMC-1991245 PMC-1991245 ISSUE 1 SPECTRA-4X155 SPECTRA-4X155 WITH TBS REFERENCE DESIGN Page 4 contains Blocks 2 and 3 of the SPECTRA-4X155 SPECTRA-4X155 device. Blocks 2 and 3 of the SPECTRA-4X155 SPECTRA-4X155 contain the ADD/DROP Telecom bus signals. The DROP bus data signals DROP_DATA[7:0] contain the STS-3/3c received SONET/SDH payload data of all four channels. The DROP bus data signals DROP_DATA[31:8] are left floating because no data will be delivered via these bits. Similarly, for single ADD bus interface, the ADD bus data signals ADD_DATA[7:0] contain the STS-3/3c SONET/SDH payload data to transmit on the four channels. The ADD bus data signals ADD_DATA[31:8] are pulled low to prevent noise triggering these signals as these inputs will not receive any data. Header J9 provides access to the TPAIS, TPAISCK, TPAISFP, DPAIS, DPAISCK, and DPAISFP signals. Page 5 contains Block 4 of the SPECTRA-4X155 SPECTRA-4X155 device. Block 4 contains the microprocessor and JTAG signals. JTAG is not implemented in this design therefore the pins are pulled-up to maintain appropriate signal state. Page 6 contains Block 5 of the SPECTRA-4X155 SPECTRA-4X155 device. Block 5 of the SPECTRA-4X155 SPECTRA-4X155 device contains the transmit and receive overhead signals. All of the signals are routed to a 32X2 pin header for access. The four SALM signals are routed off-page to the CPLD for alarm indication. The transmit inputs are pulled-low to prevent noise triggering of the signals. The Ring Control signals are routed to a matched impedance connector for debugging. Page 7 contains Block 6 of the SPECTRA-4X155 SPECTRA-4X155 device. Block 6 contains the power pins for the SPECTRA-4X155 SPECTRA-4X155. 20 of the 48 digital power pins have 0.1 uF decoupling capacitors placed as close as possible to the pins as well as 10uF bulk capacitors. The receive and transmit analog power pins are filtered via RC filters to provide a clean 3.3 voltage to the pins. VBIAS pins (VBIAS) are tied to the 3.3V supply via a 1K resistor since there are no 5V devices on the board. The 3.3V regulator shown on this page is also used to supply the optics. 8.4 TBS Block, Pages 8, 9,10, & 11 The TBS_BLOCK shows the TBS signals and power circuitry. Page 8 contains Block 1 of the TBS device. Block 1 shows the system side LVDS signals of the TBS. These signals are received from and transmitted to the backplane. The LVDS are differential signals and the transmission traces must be 50 ohm controlled impedance lines. The TCMP and OCMP (connection memory page) signals are buffered by the CPLD and sourced from the backplane. The SYSCLK is sourced from either an on-board 77.77 MHz oscillator or an external 77.76 MHz clock signal. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 16 PM5316/PM5310 PM5316/PM5310 PRELIMINARY REFERENCE DESIGN PMC-1991245 PMC-1991245 ISSUE 1 SPECTRA-4X155 SPECTRA-4X155 WITH TBS REFERENCE DESIGN Page 9 contains Blocks 2 and 3 of the TBS device. Blocks 2 and 3 contain the ADD/DROP Telecom bus signals which interface the TBS to the SPECTRA4X155 SPECTRA4X155. Because the SPECTRA-4X155 SPECTRA-4X155 Telecom bus is configured to operate in single-drop mode, only OD1[7:0] and ID1[7:0] data bits are used. Outgoing (ADD) Telecom bus channels OD2 to OD4 are left unconnected as well as their respective ODP, OPL, OJ0J1, OPAIS, OTV5, OTPL, OTAIS, and OCOUT signals. The OPAIS, OTV5, OTPL, OTAIS, and OCOUT for channel one are routed to a header for access. Incoming (DROP) Telecom bus channels ID2 to ID4 are pulled low to prevent noise triggering the signals as well as their respective IDP, IPL, IJ0J1, IPAIS, ITV5, ITPL, and ITAIS signals. Signals IPAIS, ITV5, ITPL, and ITAIS for channel one are routed to a header for access. Page 10 contains Block 4 of the TBS device. Block 4 contains the microprocessor and JTAG signals. JTAG is not implemented in this design therefore the pins are pulled-up to maintain appropriate signal state. Page 11 contains Block 5 of the TBS device and a regulated 1.8V supply. Block 5 contains the power pins for the TBS. Both the 3.3 Volt and the 1.8 Volt supply rails are decoupled via 0.1 uF capacitors as well as 10uF bulk capacitors. The supply to the CSU_AVDH pin is passed through an RC filter to provide a clean voltage to the pin. The RES and RESK pins are externally attached via a 3.16K resistor. The 1.8V regulator shown on this page is used to supply the 1.8V analog pins on the TBS device. 8.5 System Interface Block, Page 12 The SYS_INTERFACE_BLOCK contains the AMP HS3 connectors for transfer of the LVDS signals between the backplane and the reference board. The transmit and receive differential pairs are grouped together on the connector. The top HS3 connector contains the LVDS working and protect differential signals. The differential SYSCLK signals generated on the TSE reference board are also sent through the top connector. The bottom connector is used strictly for the LVDS auxiliary channels. This connector is optional and can be populated depending on the application requirements. All of the LVDS signal traces and the differential SYSCLK traces are 50 ohm controlled impedance lines. 8.6 CPLD Block, Page 13 The CPLD_BLOCK shows the signal connections to and from the Xilinx XC9572XL XC9572XL CPLD. The CPLD is used for address decoding, microprocessor access control, signal conversion, signal buffering, and clock distribution. The PECL differential clock signals, SYSCLK1(P,N) and SYSCLK2(P,N), are translated into single-ended TTL signals using the Motorola MC100EPT23 MC100EPT23 device. A 77.76 MHz local oscillator signal is also input to the CPLD. Through PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 17 PM5316/PM5310 PM5316/PM5310 PRELIMINARY REFERENCE DESIGN PMC-1991245 PMC-1991245 ISSUE 1 SPECTRA-4X155 SPECTRA-4X155 WITH TBS REFERENCE DESIGN software control, the CPLD can select which of the clock sources is to be used and sends the selected signal to the Pericom 49FCT3807 49FCT3807 clock driver device. The 49FCT3807 49FCT3807 clock distributes the 77.76 MHz signal to the SYSCLK input on the TBS as well as to the DCK and ACK Telecom bus clocks on the SPECTRA4X155 SPECTRA4X155. The Maxim 811 power supply monitor device with reset provides manual reset capability with a push-button switch attached to the master reset input. The Motorola MC74HC244 MC74HC244 driver/buffer chip is used to drive the Lumex LXH5147 LXH5147 LED arrays. The LED's can be programmed to display the status of alarms from the SPECTRA-4X155 SPECTRA-4X155 device or to display information for debugging. The microprocessor interrupt lines are also routed to the LED's for device interrupt status. Header J1 provides an interface to the CPLD JTAG pins for programming the device. 8.7 cPCI Block, Pages 14 & 15 The CPCI_BLOCK shows the PLX 9054 signal and power circuitry connections. The PCI9054 PCI9054 is a 3.3V/5V compliant PCI v2.2 32-bit, 33MHz Bus Master Interface Controller, that provides flexible local bus configurations and Hot Swap capability. The 32 bit multiplexed address/data bus and associated control lines connect directly from the CPCI J1_1 connector to the PLC PCI9054 PCI9054 interface device. The bus and control lines are terminated with 10 ohm stub resistors that should be placed close to the J1_1 connector pins. The PCI 9054 operates with a 32-bit non-multiplexed bus (C-mode) on the local bus side. The lower two bits of the address lines are used for 16 or 8 bit byte access but are unused in this application. A serial EEPROM is required for device configuration after reset or at power-up. The Fairchild Semiconductor NM93CS46 NM93CS46 serial EEPROM is used to program the 9054. 8.8 Power Block, Page 16 The POWER_BLOCK shows the power signal connections, the Hot-Swap Controller, and voltage regulator connections. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 18 PM5316/PM5310 PM5316/PM5310 PRELIMINARY REFERENCE DESIGN PMC-1991245 PMC-1991245 ISSUE 1 SPECTRA-4X155 SPECTRA-4X155 WITH TBS REFERENCE DESIGN The Power Supply System Block provides stable voltage supplies delivered over the CompactPCI backplane from a centralized power supply. Voltage levels of +5V, +3.3V, +12V, -12V and a regulated 1.8V are provided. A voltage regulator is provided in the Power Supply System Block. The 1.8V switching regulator generates the core digital power supply required for the TBS device. The 3.3V SPECTRA devices are powered directly from the digital sections of the hot swap controller. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 19 PM5316/PM5310 PM5316/PM5310 PRELIMINARY REFERENCE DESIGN PMC-1991245 PMC-1991245 9 ISSUE 1 SPECTRA-4X155 SPECTRA-4X155 WITH TBS REFERENCE DESIGN SCHEMATICS AND LAYOUT PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 20 10 9 8 7 5 6 4 3 2 1 REVISIONS ZONE H PAGE 2 OPTICS_BLOCK SD1 RXD_P1 RXD_N1 TXD_P1 TXD_N1 SD2 RXD_P2 RXD_N2 TXD_P2 TXD_N2 SD2 RXD_P2 RXD_N2 TXD_P2 TXD_N2 SD3 RXD_P3 RXD_N3 TXD_P3 TXD_N3 SD3 RXD_P3 RXD_N3 TXD_P3 TXD_N3 SD3 RXD_P3 RXD_N3 TXD_P3 TXD_N3 APPR H RJ0FP DROP_DATA DPL DC1J1V1 DDP DCK RJ0FP_SPECTRA DROP_DATA DPL DC1J1V1 DDP DCK DROP_DATA DPL DC1J1V1 DDP SD4 RXD_P4 RXD_N4 TXD_P4 TXD_N4 PAGE 12 SYS_INTERFACE_BLOCK TAUX TAUX TAUX RAUX RAUX RAUX TWRK TWRK TWRK RWRK RWRK RWRK TPROT TPROT TPROT RPROT RPROT RPROT G ADD_DATA APL AC1J1V1_AFP ADP ACK ADD_DATA APL AC1J1V1_AFP ADP ACK ADD_DATA APL AC1J1V1_AFP ADP RESETB RESETB SD4 RXD_P4 RXD_N4 TXD_P4 TXD_N4 DATE PAGES 8,9,10,11 TBS_BLOCK SD1 RXD_P1 RXD_N1 TXD_P1 TXD_N1 SD2 RXD_P2 RXD_N2 TXD_P2 TXD_N2 F DESCRIPTION PAGES 3,4,5,6,7 SPECTRA_4X155 4X155_BLOCK SD1 RXD_P1 RXD_N1 TXD_P1 TXD_N1 G REV RDB SYSCLK1P WRB SD4 RXD_P4 RXD_N4 TXD_P4 TXD_N4 RDB WRB SYSCLK1N CSB_SPECTRA INTB_SPECTRA SYSCLK2P CSB_TBS INTB_TBS LD LA RJ0FP_IN TJ0FP_OUT RWSEL_IN XCMP_IN RJ0FP_TBS TJ0FP RWSEL OCMP TCMP F SYSCLK2N SYSCLK SYSCLK RJ0FP_IN TJ0FP_OUT RWSEL_IN XCMP_IN PAGES 14, 15 CPCI_BLOCK E E LD LD LD LA LA LA PAGE 13 CPLD_BLOCK SALM TCMP OCMP RWSEL TJ0FP RJ0FP_TBS RJ0FP_SPECTRA OVERHEAD INTB_TBS CSB_TBS DCK ACK WRB RDB RESETB CSB_SPECTRA INTB_SPECTRA SALM OVERHEAD D RJ0FP_IN TJ0FP_OUT RWSEL_IN XCMP_IN SYSCLK SYSCLK1P SYSCLK1N SYSCLK2P SYSCLK2N INTB_TBS CSB_TBS LD LA LD LA DCK ACK LHOLD LHOLDA L_ADSB L_READYB L_WRB L_USERI L_USERO L_RSTOB L_INTB L_CLK LHOLD LHOLDA L_ADSB L_READYB L_WRB L_USERI L_USERO L_RSTOB L_INTB L_CLK WRB RDB RESETB CSB_SPECTRA INTB_SPECTRA C D SALM OVERHEAD LHOLD LHOLDA L_ADSB L_READYB L_WRB L_USERI L_USERO L_RSTOB L_INTB L_CLK PWROK_1_8V C PWROK_1_8V PWROK_1_8V PAGE 16 POWER_BLOCK 5V_PCI 3_3V_PCI 12V_PCI VEE_PCI BD_SELB HEALTHYB VIO_PCI PWROK_1_8V B 5V_PCI 3_3V_PCI 12V_PCI VEE_PCI BD_SELB HEALTHYB VIO_PCI 5V_PCI 3_3V_PCI 12V_PCI VEE_PCI BD_SELB HEALTHYB VIO_PCI B PMC-Sierra, Inc. A DOCUMENT NUMBER: PMC-991245 PMC-991245 DOCUMENT ISSUE NUMBER: 1 TITLE: SPECTRA 4X155 4X155 REFERENCE DESIGN ROOT_DIAGRAM DRAWING: TITLE=SPECTRA_4X155 4X155_ROOT LAST_MODIFIED=Thu Jun 15 09:37:04 2000 10 9 8 7 6 5 4 ISSUE DATE: 00/06/09 REVISION NUMBER: 1 ENGINEER: 3 MB PAGE:1 2 1 OF 16 A 10 9 8 7 5 6 4 3 2 1 REVISIONS ZONE REV DESCRIPTION DATE APPR H H 3.3VA 150 0.01UF R37 220 0.1UF C64 R47 49.9 0.01UF 330 SD TDIS R43 49.9 2 6 CHASS1 CHASS2 VEET 3F8> RXD_P2\I RXD_N2\I 3E8< 3E8< 3 8 SD2\I 3E8< VEER F 3.3VA 100NH 100NH 7 VEER 220 R41 330 VEET SD TDIS TXD_N4\I 3G8> 5 4 RXD_P4\I RXD_N4\I 3F8< 3F8< 3 8 SD4\I 3F8< D R61 3F8< CHASS1 CHASS2 9 10 R53 150 SD3\I RXDP RXDN 150 3 8 11 12 TXDP TXDN HFCT5905 HFCT5905 1 3F8< 3F8< R57 150 C78 RXD_P3\I RXD_N3\I R40 0.1UF R49 R45 2 R39 C66 49.9 E 0.01UF 6 220 49.9 C74 0.01UF 0.01UF C70 10UF C4 + VEER 5 4 1 7 SD TDIS VCCT VCCR GND GND GND GND 3G8> 3.3VA R38 0.1UF C65 R48 330 CHASS1 CHASS2 U4 13 14 15 16 3F8> R60 RXDP RXDN VEET L8 TXD_N3\I R56 150 HFCT5905 HFCT5905 TXD_P4\I 100NH 100NH 9 10 R52 150 TXDP TXDN 150 VCCT VCCR GND GND GND GND L4 R44 49.9 2 C77 11 12 6 U3 13 14 15 16 0.01UF 100NH 100NH L7 3F8> 3.3VA 49.9 C73 0.01UF TXD_P3\I L3 0.01UF C69 + 10UF C1 C72 11 12 TXD_N2\I 5 4 R59 3E8< RXDP RXDN 9 10 R55 150 SD1\I TXDP TXDN HFCT5905 HFCT5905 R51 150 3 8 100NH 100NH D 0.01UF 3E8< 3E8< VCCT VCCR GND GND GND GND 150 RXD_P1\I RXD_N1\I VEER G 1 5 4 3.3VA E C68 C76 SD TDIS 3E8> 7 7 F C2 + CHASS1 CHASS2 13 14 15 16 R58 RXDP RXDN TXD_N1\I R54 150 HFCT5905 HFCT5905 U2 9 10 R50 150 TXDP TXDN VEET L6 1 11 12 100NH 100NH R35 220 0.1UF C63 R46 330 VCCT VCCR GND GND GND GND 3F8> 3.3VA R42 49.9 2 6 U1 13 14 15 16 TXD_P2\I L2 R34 C75 G 0.01UF 100NH 100NH L5 100NH 100NH 3E8> 3.3VA 49.9 C71 0.01UF + C67 10UF C5 0.01UF TXD_P1\I L1 10UF 100NH 100NH R36 3.3VA C C B B DRAWING: TITLE=OPTICS_BLOCK LAST_MODIFIED=Thu Jun 15 10:02:29 2000 PMC-Sierra, Inc. A DOCUMENT NUMBER: PMC-991245 PMC-991245 DOCUMENT ISSUE NUMBER: 1 ISSUE DATE: 00/06/09 TITLE: SPECTRA 4X155 4X155 REFERENCE DESIGN OPTICS_BLOCK REVISION NUMBER: 1 ENGINEER: 10 9 8 7 6 5 4 3 MB PAGE:2 2 1 OF 16 A 10 9 8 7 5 6 4 3 2 1 REVISIONS ZONE REV DESCRIPTION DATE APPR H H TXD_P4\I 50 OHM 158 R6 0.1UF C14 AA2 2D2< TXD_N4\I 50 OHM 158 R5 0.1UF C13 AA3 R4 100 RXD_P4\I RXD_N4\I 2D2> SD4\I 2E6< TXD_P3\I 50 OHM 50 OHM AB1 158 50 OHM TXD_N3\I 158 50 OHM F 0.1UF R8 2D6> 2D6> 2D6> TXD_P2\I 50 OHM 158 2G2< TXD_N2\I 50 OHM 158 2F2> 2F2> RXD_P2\I RXD_N2\I SD2\I 2H6< TXD_P1\I 50 OHM 158 2G6< TXD_N1\I 50 OHM 158 W3 50 OHM 50 OHM 2F2> W2 SD3\I 2H2< C15 R7 100 RXD_P3\I RXD_N3\I C16 0.1UF R9 50 OHM 50 OHM C79 0.22UF N3 N2 C85 0.22UF G2 G3 C86 0.22UF SD3 C18 L3 TXD2P ATP3 ATP2 ATP1 ATP0 C17 L2 TXD2N PECLV RXD2P RXD2N 2 F HEADER_6X2 SD2 R15 0.1UF C20 J3 TXD1P R14 0.1UF C19 J2 TXD1N K2 K3 RXD1P RXD1N K4 SD1 B4 REFCLK E R13 100 2F6> 2 4 6 8 10 12 R10 M3 RXD_P1\I RXD_N1\I 3 SMB D2 M1 M2 5 J2 V5 W1 V4 V3 R11 0.1UF GND TCLK RCLK4 RCLK3 RCLK2 RCLK1 1 3 5 7 9 11 E7 B6 D7 C7 Y3 2F6> 2F6> 1 2 3 4 5 6 C6 R12 0.1UF 100 E U3 U2 4.7K 2D6< AB3 AB2 C87 0.22UF R62 2D2> 2D2> JMP POSTION AD2 AD3 1 2E2< G J1 4 Y1 Y2 SOIC U9 SPECTRA4-155 SPECTRA4-155 PM5316 PM5316 1 OF 6 TXD4P CP4 CN4 TXD4N CP3 CN3 RXD4P RXD4N CP2 CN2 SD4 CP1 CN1 TXD3P TCLK TXD3N RCLK4 RCLK3 RXD3P RCLK2 RXD3N RCLK1 G SD1\I 50 OHM 50 OHM PGMTCLK PGMRCLK E6 D6 PGMTCLK PGMRCLK 1 OVERHEAD\I 6G2> 6G9> 13D4< 2 LINE SIDE 1 0.1UF 3V3 8 OUT GND 5 56 PLACE NEAR J15 REFCLK Y1 4 D HEADER2 J11 C109 D 2 TERMINATION RESISTORS AND CAPACITORS SHOULD BE PLACED NEAR U9 3.3 V 2 LOCALCLK J4 JUMPER 3 1 R63 HEADER3 19.44MHZ 44MHZ 20PPM 20PPM 1-2 2-3 EXT_REFCLK LOCALCLK EXT_REFCLK C 2 J3 5 C 3 1 4 SMB SUPPLY A 19.44 MHZ EXTERNAL REFERENCE CLOCK B B PMC-Sierra, Inc. A DOCUMENT NUMBER: PMC-991245 PMC-991245 DOCUMENT ISSUE NUMBER: 1 TITLE: SPECTRA 4X155 4X155 REFERENCE DESIGN SPECTRA_4X155 4X155_BLOCK DRAWING: TITLE=SPECTRA_4X155 4X155_BLOCK LAST_MODIFIED=Thu Jun 15 10:02:32 2000 10 9 8 7 6 5 4 ISSUE DATE: 00/06/09 REVISION NUMBER: 1 ENGINEER: 3 MB PAGE:3 2 1 OF 16 A 10 9 8 7 5 6 4 3 2 1 REVISIONS ZONE REV DESCRIPTION DATE APPR H H RN15 5 RN13 8 9E9> 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K AD31 AC28 AC29 AC30 AC31 AB27 AB28 AB29 V27 V28 V29 V30 V31 U27 U28 U29 M29 M30 M31 L28 L29 L30 K27 K28 G29 G30 G31 F27 F28 F29 F30 E28 7 6 5 4 3 2 1 0 ADD_DATA\I AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 AB30 U30 K29 E29 RN10 RN12 RN15 7 5 7 2 4.7K 4 4.7K 2 4.7K ADP4 ADP3 ADP2 ADP1 AD30 W31 M28 G28 RN8 RN10 RN28 8 5 7 1 4.7K 4 4.7K 2 4.7K APL4 APL3 APL2 APL1 AB31 U31 K30 E30 RN10 RN12 RN15 8 6 8 1 4.7K 1 4.7K 3 4.7K 1 4.7K G AC1J1V1_AFP\I 9F3> ADP\I 9G3> APL\I 9F3> ACK\I 13D1> E31 D26 E26 B27 ACK TPAIS TPAISCK TPAISFP F R20 6 7 5 5 8 6 5 6 6 5 8 6 7 5 8 7 5 7 8 6 5 6 5 6 R21 4.7K F 3 2 4 4 1 3 4 3 3 4 1 3 2 4 1 2 4 2 1 3 4 3 4 3 R22 4.7K RN8 RN30 RN9 RN8 RN9 RN30 RN30 RN9 RN29 RN11 RN11 RN11 RN11 RN29 RN12 RN12 RN13 RN14 RN14 RN28 RN14 RN14 RN28 RN15 U9 SPECTRA4-155 SPECTRA4-155 PM5316 PM5316 2 OF 6 AC1J1V1_4/AFP4 AC1J1V1_3/AFP3 AC1J1V1_2/AFP2 AC1J1V1_1/AFP1 4.7K G 4 4.7K ADD TELECOM BUS E 1 2 3 4 5 6 DROP_DATA\I 9B9< C RN8 RN29 RN28 9C3< DDP\I 2 1 1 7 8 8 4.7K 4.7K 4.7K 7 6 5 4 3 2 1 0 E DDP4 DDP3 DDP2 DDP1 RN30 RN29 RN13 8 7 7 1 4.7K 2 4.7K 2 4.7K AD28 W29 N31 H31 RN9 RN10 RN13 7 6 6 2 4.7K 3 4.7K 3 4.7K DC1J1V1\I 9C3< DPL\I 9C3< D DCK\I RJ0FP_SPECTRA\I 13D1> R23 AH30 AG29 C27 D27 B28 R24 4.7K AF28 AA28 R28 K31 AD27 W28 N30 H30 R25 4.7K D T T T T T T T T T T T T T T T T T T T T T T T T U9 SPECTRA4-155 SPECTRA4-155 PM5316 PM5316 3 OF 6 DD31 DC1J1V1_4 DD30 DC1J1V1_3 DD29 DC1J1V1_2 DD28 DC1J1V1_1 DD27 DD26 DPL4 DD25 DPL3 DD24 DPL2 DD23 DPL1 DD22 DD21 DCK DD20 DFP DD19 DPAIS DD18 DPAISCK DD17 DPAISFP DD16 DD15 DD14 DD13 DD12 DD11 DD10 DD9 DD8 DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0 4.7K TP6 TP3 TP15 TP4 TP16 TP5 TP17 TP7 TP18 TP19 TP8 TP10 TP21 TP20 TP9 TP22 TP11 TP23 TP24 TP12 TP13 TP25 TP26 TP14 AG31 AF29 AF30 AE27 AE28 AE29 AE30 AE31 AA29 AA30 Y27 Y28 Y29 Y30 Y31 W27 P27 P28 P29 P30 P31 N27 N28 N29 J27 J28 J29 J30 J31 H27 H28 H29 J9 P_1 P_2 P_3 P_4 P_5 P_6 C DROP TELECOM BUS B B DRAWING: TITLE=SPECTRA_4X155 4X155_BLOCK LAST_MODIFIED=Thu Jun 15 10:02:36 2000 PMC-Sierra, Inc. A DOCUMENT NUMBER: PMC-991245 PMC-991245 DOCUMENT ISSUE NUMBER: 1 ISSUE DATE: 00/06/09 TITLE: SPECTRA 4X155 4X155 REFERENCE DESIGN SPECTRA_4X155 4X155_BLOCK REVISION NUMBER: 1 ENGINEER: 10 9 8 7 6 5 4 3 MB PAGE:4 2 1 OF 16 A 10 9 8 7 5 6 4 3 2 1 REVISIONS ZONE REV DESCRIPTION DATE APPR H H G G F F U9 SPECTRA4-155 SPECTRA4-155 PM5316 PM5316 4 OF 6 3 4.7K 4.7K RN3 RN3 5 6 4 TCK TDI TDO TMS TRSTB D20 C20 B20 A20 E19 D19 C19 B19 INTB MBEB RDB/E RSTB WRB/RWB ALE CSB LD\I A19 C14 B14 E14 D14 A14 E15 7 6 5 4 3 2 1 0 10F4 13G1> 14H4 13H10 13H10< 3.3 V E INTB_SPECTRA\I 13E7< RDB\I RESETB\I WRB\I 13E1> 13B1> 13E1> CSB_SPECTRA\I 13E1> RN3 MICRO 1 3.3 V 4.7K 8 TP1 T AK4 AK5 AH6 AG6 AJ5 D7 D6 D5 D4 D3 D2 D1 D0 R65 3.3 V A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 R66 E E18 C18 D18 B18 A18 E17 D17 C17 B17 A17 A15 C15 B15 D15 15 14 13 12 11 10 9 8 7 6 5 4 3 2 4.7K LA\I 4.7K 14D4> D 7 RN3 2 D C C B B DRAWING: TITLE=SPECTRA_4X155 4X155_BLOCK LAST_MODIFIED=Thu Jun 15 10:02:38 2000 PMC-Sierra, Inc. A DOCUMENT NUMBER: PMC-991245 PMC-991245 DOCUMENT ISSUE NUMBER: 1 ISSUE DATE: 00/06/09 TITLE: SPECTRA 4X155 4X155 REFERENCE DESIGN SPECTRA_4X155 4X155_BLOCK REVISION NUMBER: 1 ENGINEER: 10 9 8 7 6 5 4 3 MB PAGE:5 2 1 OF 16 A 10 9 8 7 5 6 4 3 2 1 REVISIONS ZONE REV DESCRIPTION DATE APPR H H 18 17 16 15 13D4< 6G2> 3E3> 10 9 8 7 14 13 12 11 OVERHEAD\I 6 5 4 3 OVERHEAD\I 3E3> 6G9> 13D4< G G 4 3 2 1 SALM\I 13D10 13D10< U9 SPECTRA4-155 SPECTRA4-155 PM5316 PM5316 5 OF 6 AK13 AG12 AL9 AJ8 5 6 7 8 RTOHFP4 RTOHFP3 RTOHFP2 RTOHFP1 TTOHFP4 TTOHFP3 TTOHFP2 TTOHFP1 AH13 AJ11 AK9 AL7 9 10 11 12 AL18 AL17 AG15 AG14 RSLDCLK4 RSLDCLK3 RSLDCLK2 RSLDCLK1 TTOHEN4 TTOHEN3 TTOHEN2 TTOHEN1 AJ13 AK11 AG10 AH8 13 14 15 16 17 18 19 20 AK18 AK17 AH15 AH14 RSLD4 RSLD3 RSLD2 RSLD1 TSLDCLK4 TSLDCLK3 TSLDCLK2 TSLDCLK1 AJ18 AJ17 AJ15 AJ14 17 18 19 20 21 22 23 24 25 26 27 A27 C26 E25 B26 D23 C21 B21 RPOHCLK RPOHFP RPOH RPOHEN RAD B3E RALM TSLD4 TSLD3 TSLD2 TSLD1 AH18 AH17 AK15 AK14 21 22 23 24 28 29 30 31 D13 C13 B13 A13 SALM4 SALM3 SALM2 SALM1 TPOHCLK TPOHFP TPOH TPOHEN TPOHRDY TAD TAFP TACK D25 C25 A25 E24 B25 A24 B24 E23 25 26 27 28 29 30 31 32 1 2 3 4 B10 C11 D12 A12 LRDI4/RRCPCLK4 LRDI3/RRCPCLK3 LRDI2/RRCPCLK2 LRDI1/RRCPCLK1 C8 A8 B9 D10 13 14 15 16 A10 B11 C12 E13 RLAIS4/TRCPCLK4 RLAIS3/TRCPCLK3 RLAIS2/TRCPCLK2 RLAIS1/TRCPCLK1 5 6 7 8 LOS4/RRCPFP4 LOS3/RRCPFP3 LOS2/RRCPFP2 LOS1/RRCPFP1 D8 E9 C9 A9 17 18 19 20 9 10 11 12 C10 D11 E12 B12 LAIS4/RRCPDAT4 LAIS3/RRCPDAT3 LAIS2/RRCPDAT2 LAIS1/RRCPDAT1 A7 B8 D9 E10 21 22 23 24 C22 B22 A22 D21 LOF4 LOF3 LOF2 LOF1 5 6 7 8 E TRANSMIT_OVERHEAD D R68 RING_CONTROL 4.7K 4 3 2 1 F RN27 RN27 RN27 RN27 8 7 5 6 1 2 4 3 8 7 6 5 RN7 RN7 RN7 RN7 C 8 7 6 5 8 7 6 5 1 2 3 4 RX/TX OVERHEAD 1 2 3 4 RTCEN RTCOH RN4 RN4 RN4 RN4 D24 C24 J8 PLACE NEAR J15 RN6 RN6 RN6 RN6 1 2 3 4 5 6 P_1 P_2 P_3 P_4 P_5 P_6 TLAIS4/TRCPDAT4 TLAIS3/TRCPDAT3 TLAIS2/TRCPDAT2 TLAIS1/TRCPDAT1 1 2 3 4 RING_CONTROL RN5 RN5 RN5 RN5 D TLRDI4/TRCPFP4 TLRDI3/TRCPFP3 TLRDI2/TRCPFP2 TLRDI1/TRCPFP1 4.7K 4.7K 4.7K 4.7K RECEIVE_OVERHEAD AJ12 AJ10 AG9 AH7 13 14 15 16 E RTOH4 RTOH3 RTOH2 RTOH1 9 10 11 12 F AL12 AL10 AH9 AK7 4.7K 4.7K 4.7K 4.7K TTOH4 TTOH3 TTOH2 TTOH1 5 6 7 8 4.7K 4.7K 4.7K 4.7K 1 2 3 4 RTOHCLK4 RTOHCLK3 RTOHCLK2 RTOHCLK1 4.7K 4.7K 4.7K 4.7K AG13 AH11 AJ9 AG8 AK12 AK10 AL8 AJ7 4.7K 4.7K 4.7K 4.7K TTOHCLK4 TTOHCLK3 TTOHCLK2 TTOHCLK1 1 2 3 4 C J14 MICTOR 38 PIN B P1 P3 P5 P7 P9 P11 P13 P15 P17 P19 P21 P23 P25 P27 P29 P31 P33 P35 P37 P2 P4 P6 P8 P10 P12 P14 P16 P18 P20 P22 P24 P26 P28 P30 P32 P34 P36 P38 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 13 14 15 16 17 18 19 20 21 22 23 24 50 MIL J15 RECEIVE_OVERHEAD A B TRANSMIT_OVERHEAD B HEADER 32X2 RING_CONTROL 39 40 41 42 43 RING_CONTROL 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 1 2 3 4 5 6 7 8 9 10 11 12 PMC-Sierra, Inc. A DOCUMENT NUMBER: PMC-991245 PMC-991245 DOCUMENT ISSUE NUMBER: 1 TITLE: SPECTRA 4X155 4X155 REFERENCE DESIGN SPECTRA_4X155 4X155_BLOCK DRAWING: TITLE=SPECTRA_4X155 4X155_BLOCK ISSUE DATE: 00/06/09 REVISION NUMBER: 1 LAST_MODIFIED=Thu Jun 15 10:02:41 2000MB 2000MB ENGINEER: 10 9 8 7 6 5 4 3 PAGE:6 2 1 OF 16 A 10 9 8 7 5 6 4 3 2 1 REVISIONS ZONE REV DESCRIPTION DATE APPR H H G G U9 R3 R1 K1 H5 H4 Y5 U4 V2 47UF + C12 0.1UF C94 + + 47UF 47UF C27 C28 C80 0.1UF + 47UF C10 0.1UF C82 47UF 47UF + + C25 C26 0.1UF C81 C106 + 47UF C11 0.1UF C99 47UF 47UF + + 47UF 47UF 1 0 RAVS4_A RAVS4_B RAVS4_C + 3 2 AB5 AD4 AC3 D 5 4 Y4 U1 V1 R16 7 6 M4 N1 P4 + 9 8 L4 G4 H3 R2 C22 R4 R2 27 27 0 G5 AD5 7 5 3 1 R17 C24 0.1UF R64 C83 C23 100 RAVD4_A RAVD4_B RAVD4_C RAVS3_A RAVS3_B RAVS3_C R1 E RAVD3_A RAVD3_B RAVD3_C RAVS2_A RAVS2_B RAVS2_C 2.7 8 R18 27 2 RAVD2_A RAVD2_B RAVD2_C RAVS1_A RAVS1_B RAVS1_C AB4 AC5 AC4 + C 0.1UF 0.1UF 0.1UF C96 POWER PLACE 2 PER EDGE AROUND SPECTRA 4X155 4X155 C98 3.3VA 0.1UF + C47 10UF C33 10UF M5 N4 P5 + + C29 10UF C31 10UF + + C32 10UF + + C38 10UF C C46 10UF C30 10UF 3.3 V F 3.3VA RAVD1_A RAVD1_B RAVD1_C TAVS1_A TAVS1_B 27 4 R67 TAVD1_A TAVD1_B QAVS1 QAVS0 R19 3.3VA 1.0K PLACE 0.1UF CAPACITOR AS CLOSE TO POWER PIN AS POSSIBLE R3 C21 AE1 F2 E20 AK28 QAVD0 QAVD1 27 9 27 6 0.1UF D VBIAS0 VBIAS1 3.3VA C84 T4 AA27 AA5 AG21 AG11 AH28 AH16 AH4 AK30 AK2 3.3VA AVD C93 B30 B2 D28 D16 D4 E21 E11 L27 L5 T28 A1 A31 B2 B30 C3 C4 C16 C28 C29 D3 D4 D16 D28 D29 E5 E11 E16 E21 E27 L5 L27 T3 T4 T5 T27 T28 T29 AA5 AA27 AG5 AG11 AG16 AG21 AG27 AH3 AH4 AH16 AH28 AH29 AJ3 AJ4 AJ16 AJ28 AJ29 AK2 AK30 AL1 AL31 0.1UF C113 0.1UF C114 0.1UF C97 0.1UF 0.1UF C116 C104 0.1UF C107 0.1UF PLACE DECOUPLING CAPS CLOSE TO THE FOLLOWING PINS: 3.3 V VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD C91 E C112 C92 0.1UF C105 0.1UF 0.1UF C108 0.1UF 3.3 V SPECTRA4-155 SPECTRA4-155 PM5316 PM5316 6 OF 6 0.1UF F GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND C101 A2 A3 A4 A6 A11 A16 A21 A26 A28 A29 A30 B1 B3 B16 B29 B31 C1 C2 C30 C31 D1 D31 F1 F31 L1 L31 T1 T2 T30 T31 AA1 AA31 AF1 AF31 AH1 AH31 AJ1 AJ2 AJ30 AJ31 AK1 AK3 AK16 AK29 AK31 AL2 AL3 AL4 AL6 AL11 AL16 AL21 AL26 AL28 AL29 AL30 C103 0.1UF C100 0.1UF 0.1UF C102 0.1UF C115 0.1UF C89 0.1UF C88 C119 C118 0.1UF C95 0.1UF 0.1UF C90 0.1UF 3.3 V PLACE CAPS CLOSE TO EACH OF THE RAVD_A PINS B B 3 3.3V U7 LM1085 LM1085 INPUT OUTPUT 2 4 TAB 1 3.3V_REGULATED DRAWING: TITLE=SPECTRA_4X155 4X155_BLOCK + 10UF ADJ/GND 3.3VA LAST_MODIFIED=Thu Jun 15 10:02:46 2000 C9 + C8 10UF 5V PMC-Sierra, Inc. A DOCUMENT NUMBER: PMC-991245 PMC-991245 DOCUMENT ISSUE NUMBER: 1 ISSUE DATE: 00/06/09 TITLE: SPECTRA 4X155 4X155 REFERENCE DESIGN SPECTRA_4X155 4X155_BLOCK REVISION NUMBER: 1 ENGINEER: 10 9 8 7 6 5 4 3 MB PAGE:7 2 1 OF 16 A 10 9 8 7 5 6 4 3 2 1 REVISIONS ZONE REV DESCRIPTION DATE APPR H H G G UBGA U15 8 7 TPWRK4 TNWRK4 50 OHM 50 OHM K24 K23 TBS PM5310 PM5310 1 of 5 RPWRK[4] TPWRK[4] RNWRK[4] TNWRK[4] H25 H26 50 OHM 50 OHM RPWRK4 RNWRK4 8 7 6 5 TPWRK3 TNWRK3 50 OHM 50 OHM K26 K25 TPWRK[3] TNWRK[3] RPWRK[3] RNWRK[3] G24 G25 50 OHM 50 OHM RPWRK3 RNWRK3 6 5 4 3 TPWRK2 TNWRK2 50 OHM 50 OHM J25 J24 TPWRK[2] TNWRK[2] RPWRK[2] RNWRK[2] F23 F24 50 OHM 50 OHM RPWRK2 RNWRK2 4 3 2 1 TPWRK1 TNWRK1 50 OHM 50 OHM H24 H23 TPWRK[1] TNWRK[1] RPWRK[1] RNWRK[1] F25 F26 50 OHM 50 OHM RPWRK1 RNWRK1 2 1 8 7 TPPROT4 TNPROT4 50 OHM 50 OHM T25 T24 TPPROT[4] RPPROT[4] TNPROT[4] RNPROT[4] N25 N26 50 OHM 50 OHM RPPROT4 RNPROT4 8 7 6 5 TPPROT3 TNPROT3 50 OHM 50 OHM R26 R25 TPPROT[3] RPPROT[3] TNPROT[3] RNPROT[3] M23 M24 50 OHM 50 OHM RPPROT3 RNPROT3 6 5 4 3 TPPROT2 TNPROT2 50 OHM 50 OHM R24 R23 TPPROT[2] RPPROT[2] TNPROT[2] RNPROT[2] M25 M26 50 OHM 50 OHM RPPROT2 RNPROT2 4 3 2 1 TPPROT1 TNPROT1 50 OHM 50 OHM P26 P25 TPPROT[1] RPPROT[1] TNPROT[1] RNPROT[1] L24 L25 50 OHM 50 OHM RPPROT1 RNPROT1 2 1 8 7 TPAUX4 TNAUX4 50 OHM 50 OHM AA26 AA25 TPAUX[4] TNAUX[4] RPAUX[4] RNAUX[4] W23 W24 50 OHM 50 OHM RPAUX4 RNAUX4 8 7 6 5 TPAUX3 TNAUX3 50 OHM 50 OHM AA24 AA23 TPAUX[3] TNAUX[3] RPAUX[3] RNAUX[3] V24 V25 50 OHM 50 OHM RPAUX3 RNAUX3 6 5 4 3 TPAUX2 TNAUX2 50 OHM 50 OHM Y25 Y24 TPAUX[2] TNAUX[2] RPAUX[2] RNAUX[2] U25 U26 50 OHM 50 OHM RPAUX2 RNAUX2 4 3 2 1 TWRK\I 12F10 12F10< TPAUX1 TNAUX1 50 OHM 50 OHM W26 W25 TPAUX[1] TNAUX[1] RPAUX[1] RNAUX[1] U23 U24 50 OHM 50 OHM RPAUX1 RNAUX1 2 1 F TPROT\I 12G10 12G10< E TAUX\I 12C10 12C10< TJ0FP\I TCMP\I D AC22 C23 TJ0FP TCMP AB25 AB23 13D8< 13D8> ATB1 ATB0 SERIAL TELECOMBUS RJ0FP OCMP SYSCLK RWSEL 12F10 12F10> F RJ0FP_TBS\I OCMP\I SYSCLK\I RWSEL\I AD23 A24 AD12 C22 RWRK\I RPROT\I 12G10 12G10> RAUX\I 12A10 12A10> E 13D8> 13D8> 13D1> 13D8> D C C B B DRAWING: TITLE=TBS_BLOCK LAST_MODIFIED=Thu Jun 15 10:02:48 2000 PMC-Sierra, Inc. A DOCUMENT NUMBER: PMC-991245 PMC-991245 DOCUMENT ISSUE NUMBER: 1 ISSUE DATE: 00/06/09 TITLE: SPECTRA 4X155 4X155 REFERENCE DESIGN TBS_BLOCK REVISION NUMBER: 1 ENGINEER: 10 9 8 7 6 5 4 3 MB PAGE:8 2 1 OF 16 A 10 9 8 7 5 6 4 3 2 1 REVISIONS ZONE REV DESCRIPTION DATE APPR H H UBGA U15 G TP61 TP60 TP71 TP70 TP69 TP59 TP67 TP68 4E10< T T T T T T T T AA4 AC1 AB2 Y4 AB1 AA2 Y3 W4 TP37 TP33 TP41 TP30 TP32 TP28 TP29 TP36 ADD_DATA\I AF16 AD15 AE15 AF15 AD14 AE13 AD13 AF12 TP43 TP53 TP52 TP48 TP51 TP50 TP49 TP40 F T T T T T T T T T T T T T T T T M3 L1 M4 L2 K1 L3 K2 L4 D6 A4 B5 C6 D7 A5 C7 A6 7 6 5 4 3 2 1 0 E G TBS PM5310 PM5310 2 of 5 OD[4][7] ODP[4] OD[4][6] ODP[3] OD[4][5] ODP[2] OD[4][4] ODP[1] OD[4][3] OD[4][2] OPL[4] OD[4][1] OPL[3] OD[4][0] OPL[2] OPL[1] OD[3][7] OD[3][6] OJ0J1[4] OD[3][5] OJ0J1[3] OD[3][4] OJ0J1[2] OD[3][3] OJ0J1[1] OD[3][2] OD[3][1] OPAIS[4] OD[3][0] OPAIS[3] OPAIS[2] OD[2][7] OPAIS[1] OD[2][6] OD[2][5] OTV5[4] OD[2][4] OTV5[3] OD[2][3] OTV5[2] OD[2][2] OTV5[1] OD[2][1] OD[2][0] OTPL[4] OTPL[3] OD[1][7] OTPL[2] OD[1][6] OTPL[1] OD[1][5] OD[1][4] OTAIS[4] OD[1][3] OTAIS[3] OD[1][2] OTAIS[2] OD[1][1] OTAIS[1] OD[1][0] OCOUT[4] OCOUT[3] OCOUT[2] OCOUT[1] AF17 AB4 M1 A3 T TP74 T TP47 T TP34 ADP\I 4F2< AC12 Y2 J1 B7 T TP57 T TP44 T TP31 APL\I 4F2< AE11 W3 K3 C8 T TP58 T TP46 T TP27 AC1J1V1_AFP\I 4G2< AD16 AD4 N3 D3 T TP72 T TP55 T TP45 AD17 AD5 P3 D2 T TP63 T TP56 T TP42 AF18 AE4 P2 C1 T TP64 T TP65 T TP39 AE17 AC5 N2 E4 T TP73 T TP66 T TP38 AC15 AD1 M2 B4 T TP62 T TP54 T TP35 F 1 2 3 4 5 J12 P_1 P_2 P_3 P_4 P_5 HEADER5 E OUTGOING TELECOMBUS 8 RN20 4.7K4 8 UBGA U15 4.7K1 5 D RN19 4.7K1 D RN23 TBS PM5310 PM5310 3 of 5 PINS 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K AD21 AC20 AF22 AE21 AF21 AE20 AD19 AF20 ID[4][7] ID[4][6] ID[4][5] ID[4][4] ID[4][3] ID[4][2] ID[4][1] ID[4][0] ID[3][7] ID[3][6] ID[3][5] ID[3][4] ID[3][3] ID[3][2] ID[3][1] ID[3][0] AC10 AD9 AF7 AD8 AF6 AC8 AE6 AF5 RN18 RN18 RN18 RN32 RN17 RN32 RN17 RN32 1 3 2 3 4 1 3 2 8 6 7 6 5 8 6 7 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K U3 V1 U2 T3 T2 R4 T1 R3 7 6 5 4 3 2 1 0 G2 F1 G3 F2 E1 G4 F3 E2 B 4C10> DROP_DATA\I 1 1 4 RN25 RN22 RN18 IPL[4] IPL[3] IPL[2] IPL[1] AD18 AD6 R2 F4 4.7K 4.7K 4.7K 8 7 7 1 2 2 RN33 RN21 RN17 IJOJ1[4] IJOJ1[3] IJOJ1[2] IJOJ1[1] AF19 AF4 R1 E3 4.7K 4.7K 4.7K 7 7 8 2 2 1 RN23 RN20 RN17 IPAIS[4] IPAIS[3] IPAIS[2] ID[2][7] IPAIS[1] ID[2][6] ITV5[4] ID[2][5] ITV5[3] ID[2][4] ITV5[2] ID[2][3] ITV5[1] ID[2][2] ID[2][1] ITPL[4] ID[2][0] ITPL[3] ITPL[2] ID[1][7] ITPL[1] ID[1][6] ID[1][5] ID[1][4] ITAIS[4] ID[1][3] ITAIS[3] ID[1][2] ITAIS[2] ID[1][1] ITAIS[1] ID[1][0] AF23 AD10 W1 H2 4.7K 4.7K 4.7K 7 5 7 2 4 2 RN25 RN34 RN19 AF24 AD11 W2 H1 4.7K 4.7K 4.7K 5 5 6 4 4 3 RN25 RN22 RN19 AE23 AE10 V3 K4 4.7K 4.7K 4.7K 6 6 8 3 3 1 RN25 RN22 RN19 AC21 AF9 U4 J3 4.7K 4.7K 4.7K 5 7 5 4 2 4 RN33 RN22 RN32 DDP\I 4C10> DPL\I 4D2> DC1J1V1\I 4D2> C 1 2 3 4 J13 P_1 P_2 P_3 P_4 HEADER4 B 8 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 8 8 5 4.7K 4.7K 4.7K 4.7K 7 6 6 5 8 8 5 6 4.7K 4.7K 4.7K 7 2 3 3 4 1 1 4 3 AE22 AE9 V2 G1 6 RN34 RN34 RN21 RN21 RN21 RN34 RN20 RN20 C IDP[4] IDP[3] IDP[2] IDP[1] 5 PLACE RESISTORS CLOSE TO RN24 1 8 RN33 3 6 RN24 4 5 RN24 3 6 RN24 2 7 RN23 3 6 RN33 2 7 RN23 4 5 DRAWING: TITLE=TBS_BLOCK 1 2 3 LAST_MODIFIED=Thu Jun 15 10:02:52 2000 RN16 RN16 RN16 RN16 4 INCOMING TELECOMBUS PMC-Sierra, Inc. A DOCUMENT NUMBER: PMC-991245 PMC-991245 DOCUMENT ISSUE NUMBER: 1 ISSUE DATE: 00/06/09 TITLE: SPECTRA 4X155 4X155 REFERENCE DESIGN TBS_BLOCK REVISION NUMBER: 1 ENGINEER: 10 9 8 7 6 5 4 3 MB PAGE:9 2 1 OF 16 A 10 9 8 7 5 6 4 3 2 1 REVISIONS ZONE REV DESCRIPTION DATE APPR H H G G F F UBGA U15 INTB_TBS\I RSTB CSB WRB RDB ALE INTB TRSTB TCK TMS TDI TDO B21 C21 D20 D19 B20 14H4 13H10 13H10< 2 E T TP2 RN315 RN315 13E7< A23 D17 B19 B18 C17 A20 13G1> 4 MICRO JTAG 4.7K RESETB\I CSB_TBS\I WRB\I RDB\I 5E4 3.3 V 8 13B1> 13E1> 13E1> 13E1> LD\I 4.7K 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 3 4.7K RN31 A7 B8 C9 D10 B9 C10 A9 D11 B10 C11 B11 D12 A11 C12 B12 A12 6 TBS PM5310 PM5310 4 of 5 A[11]/TRS D[15] D[14] A[10] A[9] D[13] A[8] D[12] A[7] D[11] A[6] D[10] A[5] D[9] A[4] D[8] A[3] D[7] A[2] D[6] A[1] D[5] A[0] D[4] D[3] D[2] D[1] D[0] 4.7K RN31 3.3 V E B13 B14 A15 B15 C15 A16 D15 B16 A17 C16 B17 D16 RN31 13 12 11 10 9 8 7 6 5 4 3 2 7 LA\I 14D4> D D C C B B DRAWING: TITLE=TBS_BLOCK LAST_MODIFIED=Thu Jun 15 10:02:55 2000 PMC-Sierra, Inc. A DOCUMENT NUMBER: PMC-991245 PMC-991245 DOCUMENT ISSUE NUMBER: 1 ISSUE DATE: 00/06/09 TITLE: SPECTRA 4X155 4X155 REFERENCE DESIGN TBS_BLOCK REVISION NUMBER: 1 ENGINEER: 10 9 8 7 6 5 4 3 MB PAGE:10 2 1 OF 16 A 10 9 8 7 5 6 4 3 2 1 REVISIONS ZONE REV DESCRIPTION DATE APPR H H G G 3.3VA 3.3 V UBGA U15 3.3VA C126 C159 0.1UF 0.1UF C129 0.1UF C167 0.1UF C151 0.1UF C173 0.1UF 0.1UF C141 C136 0.1UF C128 0.1UF C155 C172 0.1UF C139 0.1UF 0.1UF C127 0.1UF 2.7 R33 AB24 AC24 D24 E24 J23 T23 Y23 G23 L23 P23 N24 P24 V23 D 1.8 VA C144 0.1UF C171 0.1UF C176 0.1UF C133 0.1UF C175 0.1UF 0.1UF C174 C142 0.1UF 1.8 V C156 0.1UF C153 C152 0.1UF C150 0.1UF 0.1UF C147 0.1UF 1.8 VA AVDH6 AVDH5 AVDH4 AVDH3 AVDH2 AVDH1 AVDH0 2 4 TAB 1 ADJ/GND 100 E + C54 + 10UF R29 E25 + 47UF N23 C56 0.1UF C148 3.3VA 3 C53 10UF 1.8 V 1.8 VA ADJ U12 LM1085 LM1085 INPUT OUTPUT R30 E 3.3 V 44.2 A18 A21 A8 AC2 AD20 AD22 AD7 AE12 AE18 AE5 AE8 B6 C13 D1 D21 H3 J2 P4 U1 Y1 + 1.8 V F 10UF C125 C170 0.1UF C122 0.1UF 0.1UF C124 C161 0.1UF 0.1UF C157 0.1UF C137 0.1UF 0.1UF C131 C169 0.1UF C135 0.1UF C130 C138 0.1UF C140 0.1UF 0.1UF C164 0.1UF 3.3 V A1 A13 A14 A2 A25 A26 AB26 AC25 AC26 AD2 AD25 AD26 AE1 AE24 AE26 AE3 AF1 AF13 AF14 AF2 AF25 AF26 B1 B24 B26 B3 C2 C25 C26 D25 D26 E26 G26 J26 L26 N1 P1 T26 V26 Y26 C48 F TBS PM5310 PM5310 5 of 5 VDDO0 VSS39 VSS39 VDDO1 VSS38 VSS38 VDDO2 VSS37 VSS37 VDDO3 VSS36 VSS36 VDDO4 VSS35 VSS35 VDDO5 VSS34 VSS34 VDDO6 VSS33 VSS33 VDDO7 VSS32 VSS32 VDDO8 VSS31 VSS31 VDDO9 VSS30 VSS30 VDDO10 VDDO10 VSS29 VSS29 VDDO11 VDDO11 VSS28 VSS28 VDDO12 VDDO12 VSS27 VSS27 VDDO13 VDDO13 VSS26 VSS26 VDDO14 VDDO14 VSS25 VSS25 VDDO15 VDDO15 VSS24 VSS24 VDDO16 VDDO16 VSS23 VSS23 VDDO17 VDDO17 VSS22 VSS22 VDDO18 VDDO18 VSS21 VSS21 VDDO19 VDDO19 VSS20 VSS20 VDDO20 VDDO20 VSS19 VSS19 VSS18 VSS18 VDDI19 VDDI19 VSS17 VSS17 VDDI18 VDDI18 VSS16 VSS16 VDDI17 VDDI17 VSS15 VSS15 VDDI16 VDDI16 VSS14 VSS14 VDDI15 VDDI15 VSS13 VSS13 VDDI14 VDDI14 VSS12 VSS12 VDDI13 VDDI13 VSS11 VSS11 VDDI12 VDDI12 VSS10 VSS10 VDDI11 VDDI11 VSS9 VDDI10 VDDI10 VSS8 VDDI9 VSS7 VDDI8 VSS6 VDDI7 VSS5 VDDI6 VSS4 VDDI5 VSS3 VDDI4 VSS2 VDDI3 VSS1 VSS0 VDDI2 VDDI1 VDDI0 RES CSU_AVDH E23 R69 V4 N4 H4 D8 D4 D23 D18 D13 C3 C24 B25 B2 AE25 AE2 AD3 AD24 AC9 AC4 AC23 AC19 AC14 3.16K C168 C162 0.1UF 0.1UF C163 0.1UF C149 C160 0.1UF 0.1UF C143 0.1UF 0.1UF C177 0.1UF C158 0.1UF C165 0.1UF C154 C145 C123 0.1UF C166 0.1UF 0.1UF C134 0.1UF 3.3 V AVDL5 AVDL4 AVDL3 AVDL2 AVDL1 AVDL0 RESK D POWER C C PLACE DECOUPLING CAPS CLOSE TO EACH POWER PIN + C52 + C42 10UF + C57 10UF + C41 10UF + + C58 10UF C62 10UF C60 10UF + + C49 10UF 1.8 V 10UF + C43 + C59 10UF + C55 10UF + 10UF C61 10UF 3.3 V B B DRAWING: TITLE=TBS_BLOCK PLACE 3 PER EDGE AROUND TBS LAST_MODIFIED=Thu Jun 15 10:02:58 2000 PMC-Sierra, Inc. A DOCUMENT NUMBER: PMC-991245 PMC-991245 DOCUMENT ISSUE NUMBER: 1 ISSUE DATE: 00/06/09 TITLE: SPECTRA 4X155 4X155 REFERENCE DESIGN TBS_BLOCK REVISION NUMBER: 1 ENGINEER: 10 9 8 7 6 5 4 3 MB PAGE:11 2 1 OF 16 A 10 9 8 7 5 6 4 3 2 1 REVISIONS ZONE REV DESCRIPTION DATE APPR H H FEMALE_RA J6 WORKING AND PROTECT LVDS LINKS 1 3 5 7 RPROT\I 1 3 5 7 8F3< 8 6 4 2 TPROT\I 8 6 4 2 8F8> AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AMP_HS3_6X10 G FEMALE_RA J6 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8 A9 B9 A10 B10 AMP_HS3_6X10 FEMALE_RA J6 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 RPPROT4 RPPROT3 RPPROT2 RPPROT1 RPWRK4 RPWRK3 RPWRK2 RPWRK1 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 OHM OHM OHM OHM OHM OHM OHM OHM RNPROT4 RNPROT3 RNPROT2 RNPROT1 RNWRK4 RNWRK3 RNWRK2 RNWRK1 OHM OHM OHM OHM OHM OHM OHM OHM C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 FEMALE_RA J6 C1 D1 C2 D2 C3 D3 C4 D4 C5 D5 C6 D6 C7 D7 C8 D8 C9 D9 C10 D10 AMP_HS3_6X10 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 TPPROT4 TPPROT3 TPPROT2 TPPROT1 TPWRK4 TPWRK3 TPWRK2 TPWRK1 50 50 50 50 50 50 50 50 OHM OHM OHM OHM OHM OHM OHM OHM 50 50 50 50 50 50 50 50 OHM OHM OHM OHM OHM OHM OHM OHM TNPROT4 TNPROT3 TNPROT2 TNPROT1 TNWRK4 TNWRK3 TNWRK2 TNWRK1 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E1 F1 E2 F2 E3 F3 E4 F4 E5 F5 E6 F6 E7 F7 E8 F8 E9 F9 E10 F10 AMP_HS3_6X10 G FEMALE_RA J6 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 CD1 CD2 CD3 CD4 CD5 CD6 CD7 CD8 CD9 CD10 CD1 CD2 CD3 CD4 CD5 CD6 CD7 CD8 CD9 CD10 AMP_HS3_6X10 F F FEMALE_RA J6 13D8> 1 3 5 7 TWRK\I 8 6 4 2 RWRK\I 8F8> EF1 EF2 EF3 EF4 EF5 EF6 EF7 EF8 EF9 EF10 1 3 5 7 8 6 4 2 8F3< TJ0FP_OUT\I 13F10 13F10< SYSCLK1P\I 50 OHM 13F10 13F10< SYSCLK1N\I 50 OHM 13D8< EF1 EF2 EF3 EF4 EF5 EF6 EF7 EF8 EF9 EF10 AMP_HS3_6X10 RJ0FP_IN\I E 13D8< RWSEL_IN\I 13F10 13F10< SYSCLK2P\I 50 OHM 13F10 13F10< SYSCLK2N\I E 50 OHM 13D8< XCMP_IN\I D D TPROT, TWRK, RWRK, RPROT, TAUX AND RAUX CONSIST OF DIFFERENTIAL LVDS PAIRS. EACH PAIR SHOULD BE ROUTED TOGETHER ON THE SAME LAYER AND HAVE THE SAME LENGTH. ALL LVDS TRACES SHOULD BE 50 OHM. FEMALE_RA J5 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AUXILLARY LVDS LINKS DO NOT POPULATE CONNECTOR IF AUXILLARY LVDS LINKS NOT REQUIRED TAUX\I FEMALE_RA J5 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 B A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8 A9 B9 A10 B10 AMP_HS3_6X10 2 4 6 8 8E8> 7 5 3 1 C FEMALE_RA J5 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 D1 C1 D2 C2 D3 C3 D4 C4 D5 C5 D6 C6 C7 D7 C8 D8 D9 C9 C10 D10 AMP_HS3_6X10 FEMALE_RA J5 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 TNAUX4 TNAUX3 TNAUX2 TNAUX1 50 50 50 50 RNAUX4 RNAUX3 RNAUX2 RNAUX1 50 OHM 50 OHM 50 OHM 50 OHM OHM OHM OHM OHM 50 OHM 50 OHM 50 OHM 50 OHM E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 TPAUX4 TPAUX3 TPAUX2 TPAUX1 RPAUX4 RPAUX3 RPAUX2 RPAUX1 50 50 50 50 OHM OHM OHM OHM E1 F1 E2 F2 E3 F3 E4 F4 E5 F5 E6 F6 E7 F7 E8 F8 E9 F9 E10 F10 AMP_HS3_6X10 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AMP_HS3_6X10 FEMALE_RA J5 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 CD1 CD2 CD3 CD4 CD5 CD6 CD7 CD8 CD9 CD10 CD1 CD2 CD3 CD4 CD5 CD6 CD7 CD8 CD9 CD10 AMP_HS3_6X10 FEMALE_RA J5 EF1 EF2 EF3 EF4 EF5 EF6 EF7 EF8 EF9 EF10 2 4 6 8 7 5 3 1 8E3< C RAUX\I A B DRAWING: TITLE=SYS_INTERFACE_BLOCK LAST_MODIFIED=Thu Jun 15 10:02:22 2000 EF1 EF2 EF3 EF4 EF5 EF6 EF7 EF8 EF9 EF10 AMP_HS3_6X10 PMC-Sierra, Inc. DOCUMENT NUMBER: PMC-991245 PMC-991245 DOCUMENT ISSUE NUMBER: 1 ISSUE DATE: 00/06/09 TITLE: SPECTRA 4X155 4X155 REFERENCE DESIGN SYSTEM_INTERFACE_BLOCK REVISION NUMBER: 1 ENGINEER: 10 9 8 7 6 5 4 3 MB PAGE:12 2 1 OF 16 A 10 9 8 7 5 6 4 3 2 1 REVISIONS ZONE A1 YA1 18 4 RN2 68 5 4 A2 YA2 16 3 RN2 68 6 LED_3 6 A3 YA3 14 2 RN2 68 7 LED_4 8 A4 YA4 12 1 RN2 68 8 LA\I PLACE NEAR LED DRIVER LYD D1 LED_5 11 B1 YA1 9 4 RN1 68 5 LED_6 13 B2 YB2 7 3 RN1 68 6 LED_7 15 B3 YB3 5 2 RN1 68 7 LED_8 G 3.3 V LED SSF-LXH5147 SSF-LXH5147 MC74AHC244ADW MC74AHC244ADW 14D4> H A1 A2 A3 A4 K1 K2 K3 K4 0.1UF 2 LED_2 LD\I 17 B4 YB4 3 1 RN1 68 8 A1 A2 A3 A4 K1 K2 K3 K4 LED SSF-LXH5147 SSF-LXH5147 G FOR DEBUGGING OEB* 19 LD\I LVPECL 1 2 TTL MC100LVELT23 MC100LVELT23 D1P D1N Q1 VCC GND SYSCLK1 R28 56 6 8 SYSCLK2 5 3.3 V 56 14F2> 14E2< R26 SALM\I SALM\I SALM\I SALM\I SALM\I 4 3 2 1 12E10 12E10> 12E10 12E10< 12E10 12E10> 12D10 12D10> 8D4< 8D7> 8D4< 8D7< 8D4< D RJ0FP_IN\I TJ0FP_OUT\I RWSEL_IN\I XCMP_IN\I RJ0FP_TBS\I TJ0FP\I RWSEL\I TCMP\I OCMP\I LHOLD\I LHOLDA\I L_READYB\I PWROK_1_8V\I 14F2> 14F2< 14F2< 16D8> 87 94 91 93 95 96 97 1 6 8 9 11 10 12 92 3 4 99 GND GND GND GND GND GND GND GND L_RSTOB\I 48 45 83 47 + C34 + C40 10UF + C45 10UF + C37 10UF C111 10UF C117 0.1UF C121 0.1UF C120 0.1UF C39 0.1UF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 TCK TDI TDO TMS 1 3 5 7 U10 3E3> 6G2> 6G9> 9 OEA 10 INA 12 OEB 11 3.3 V INB OA4 OA3 OA2 OA1 OA0 7 6 4 3 2 RN26 RN26 RN26 6 7 8 3 2 1 56 56 56 SYSCLK\I ACK\I DCK\I 8D4< 4F2< 4D2< D PI49FCT3805 PI49FCT3805 3.3 V J10 P_1 P_2 P_3 P_4 P_5 P_6 P_7 P_8 2 4 6 8 HEADER 4X2 OB4 OB3 OB2 OB1 OB0 14 15 17 18 19 MON 13 PLACE 49FCT3805 49FCT3805 CLOSE TO CPLD OUTPUT PIN 21 31 44 62 69 75 84 100 C OVERHEAD\I 41 32 49 50 35 53 54 37 42 60 52 61 63 55 56 64 58 59 20 5 1 OUT 77.76MHZ 76MHZ 100PPM 100PPM VCCB GND 3.3 V VCCA 3V3 4 E LED_1 LED_2 LED_3 LED_4 LED_5 LED_6 LED_7 LED_8 RJOFP_SPECTRA\I GNDA GNDB GNDQ TRI 8 5E4< 10E9< 5E4< 10E9< 5E4< 10E9< 14E2< 14E2< 5 16 8 10D9> 1 RDB\I WRB\I CSB_SPECTRA\I CSB_TBS\I L_USERI\I L_INTB\I 65 67 71 72 68 76 77 70 66 81 74 82 85 78 89 86 90 79 C36 14E2> IO1 IO4 IO1 IO4 IO1 IO4 IO1 IO4 IO1 IO4 IO1 IO4 IO1 IO4 IO1 IO4 IO1 IO4 IO4 IO1 IO4 IO1 IO4 IO1 IO4 IO1 IO4 IO1 IO1 IO4 IO1/GCK1 IO4 IO1/GCK2 IO4 IO1/GCK3 IO4 XC9572XL XC9572XL IO2 TQ100 TQ100 IO3 IO2 10NS IO3 IO3 IO2 IO3 IO2 IO3 IO2 IO3 IO2 IO3 IO2 IO3 IO2 IO3 IO2 IO3 IO2 IO3 IO2 IO2 IO3 IO2 IO3 IO2 IO3 IO2 IO3 IO2/GTS1 IO3 IO2/GTS2 IO3 IO3 IO2/GSR C35 0.1UF C146 0.1UF L_WRB\I L_ADSB\I L_USERO\I INTB_SPECTRA\I INTB_TBS\I SYSCLK1 SYSCLK2 LOCAL_OSC L_WRB\I L_CLK\I 14F2> 14F2> 5E4> 14E2> 16 13 18 20 14 15 25 17 28 33 36 29 39 30 40 22 23 27 TCK TDI TDO TMS LOCAL SYSCLK Y2 E 17 16 0.1UF VCCINT VCCINT VCCINT C51 0.1UF U11 3.3 V 2 1 0 6G9> F R27 5 57 98 3.3 V 56 7 Q0 D0P D0N 3 4 C110 0.1UF R32 0.1UF 100 C44 0.1UF 50 OHM SYSCLK2P\I 50 OHM SYSCLK2N\I 17 16 VCCIO VCCIO VCCIO VCCIO F 50 OHM SYSCLK1P\I 50 OHM SYSCLK1N\I 12E10 12E10> 12E10 12E10> 14D4> 2 1 0 U13 R31 26 38 51 88 12E10 12E10> 12E10 12E10> 1 2 3 4 5 5E4 10F4 14H4 13H10 13H10< LA\I J7 P_1 P_2 P_3 P_4 P_5 EXTERNAL SYSCLK 100 APPR 3.3 V LED_1 10F4 5E4 DATE LID D2 OEA* 14H4 13G1> DESCRIPTION C3 U8 1 H REV C 3.3 V 0.1UF 4 C6 U5 SW1 U6 VCC 1 MAX811T MAX811T 2 1 MR RESET GND 2 2 74HC08 74HC08 RESETB\I 3 5E4< 10E9< 1 PBNO 3 B B U6 4 5 74HC08 74HC08 6 DRAWING: TITLE=CPLD_BLOCK 3.3 V U6 LAST_MODIFIED=Thu Jun 15 10:02:25 2000 9 PLACE NEAR 74HC08 74HC08 8 C7 74HC08 74HC08 0.1UF 10 U6 PMC-Sierra, Inc. 12 13 74HC08 74HC08 11 A DOCUMENT NUMBER: PMC-991245 PMC-991245 DOCUMENT ISSUE NUMBER: 1 ISSUE DATE: 00/06/09 TITLE: SPECTRA 4X155 4X155 REFERENCE DESIGN CPLD_BLOCK REVISION NUMBER: 1 ENGINEER: 10 9 8 7 6 5 4 3 MB PAGE:13 2 1 OF 16 A 10 9 8 7 5 6 4 3 2 1 REVISIONS CPCI BRIDGE ZONE REV DESCRIPTION DATE APPR 3.3 V H H LOCKX FRAMEX TRDYX IRDYX IDSELX REQX 10 1 8 RN8_1 15B5> 15C5> 15G5< P_GNTB P_CLK P_INTAB 10 1 8 RN7_1 171 170 168 INTAX 5 U14 2 PWROK_1_8V\I B A 4 GND R14_1 4.7K 4.7K 4.7K 4.7K 4.7K 5 6 5 8 4.7K 4.7K 4.7K 4.7K 6 8 7 7 4.7K 4.7K 4.7K 4.7K 3 1 2 2 4 3 4 1 RN4_1 RN3_1 RN5_1 RN4_1 RN4_1 RN5_1 RN5_1 RN4_1 RES_ARRAY_4 2 4 1 4 RN1_1 RN3_1 RN2_1 RN1_1 ADJ U3_1 LT1117CST LT1117CST 3_3V_LONG VIO_LONG 15H7> 15H7> 2 1 B DRAWING: TITLE=CPCI_BLOCK ABBREV=CPCI_BLOCK LAST_MODIFIED=Thu Jun 15 10:02:12 2000 P_GNTB RSTX ENUMX INTAX REQX RN34_1 RN22_1 RN27_1 RN27_1 1 R8_1 100K 7 8 5 8 10K 10K 10K 10K 1 R12_1 R11_1 C4_1 24 0.1UF 6 7 3 3 2 5 4 7 5 8 1 2 4 7 8 5 6 3 2 1 4 1 8 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 6 8 6 3 VIN VOUT TAB ADJ RN24_1 RN26_1 RN30_1 RN32_1 RN30_1 RN29_1 RN29_1 RN29_1 RN29_1 RN32_1 RN28_1 RN28_1 RN28_1 RN28_1 1 150 2 4 R10_1 2 100 1 CBEX0 CBEX1 CBEX2 CBEX3 FRAMEX IRDYX TRDYX DEVSELX STOPX IDSELX LOCKX PARX PERRX SERRX 3 6 5 8 7 2 3 4 1 6 5 7 2 3 4 6 3 8 7 6 5 8 7 7 6 5 8 7 6 5 8 7 5 8 7 6 5 4 1 2 3 4 1 2 2 3 4 1 2 3 4 1 2 4 1 2 3 4 5 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 8 7 6 1 RN22_1 RN22_1 RN22_1 RN23_1 RN23_1 RN23_1 RN23_1 RN24_1 RN24_1 RN24_1 RN25_1 RN25_1 RN25_1 RN25_1 RN26_1 RN26_1 RN26_1 RN30_1 RN30_1 RN31_1 RN31_1 RN31_1 RN31_1 RN32_1 RN32_1 RN33_1 RN33_1 RN33_1 RN33_1 RN34_1 RN34_1 RN34_1 ADX0 ADX1 ADX2 ADX3 ADX4 ADX5 ADX6 ADX7 ADX8 ADX9 ADX10 ADX10 ADX11 ADX11 ADX12 ADX12 ADX13 ADX13 ADX14 ADX14 ADX15 ADX15 ADX16 ADX16 ADX17 ADX17 ADX18 ADX18 ADX19 ADX19 ADX20 ADX20 ADX21 ADX21 ADX22 ADX22 ADX23 ADX23 ADX24 ADX24 ADX25 ADX25 ADX26 ADX26 ADX27 ADX27 ADX28 ADX28 ADX29 ADX29 ADX30 ADX30 ADX31 ADX31 2 4.7K 4.7K 4.7K 4.7K R13_1 2.2K C PRECHARGE D1_1 3 13G10 13G10< PLACE AROUND U2 DL4148 DL4148 ALL 10 OHM STUBS WITHIN 0.6" ALL PCI SIGNAL TRACES < 1.5" P_CLK TRACE MUST BE 2.5" +/CPCI BUS TRACES ARE 65 OHM. 39 OHM STUB RESISTOR ON REQB 13G1< 1 2 3 4 CS SK DI DO VCC PRE PE GND 1V_PRECHG A 5E9< 10F8< U1_1 8 7 6 5 PLACE NEAR U1 NOTES: 1. 2. 3. 4. 5. 3.3 V NM93CS66LEN NM93CS66LEN R15_1 4.7K C B LA\I 3.3 V C21_1 + 10UF C20_1 0.1UF 3.3 V E D 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 3 D 7 5 8 5 176 161 140 132 115 108 88 69 61 44 27 19 VCC OUT 1 VSS12 VSS12 VSS11 VSS11 VSS10 VSS10 VSS9 VSS8 VSS7 VSS6 VSS5 VSS4 VSS3 VSS2 VSS1 4 16D8> 157 156 155 GNT* PCLK INTA* RSTX 3.3 V EEDI/O EESK EECS R16_1 MODE MODE TEST LOCK* FRAME* TRDY* IRDY* IDSEL REQ* RST* 166 165 164 39.2 24 17 21 18 7 172 169 PMC-Sierra, Inc. OF J1 EXCEPT P_CLK 0.1" DOCUMENT NUMBER: PMC-991413 PMC-991413 DOCUMENT ISSUE NUMBER: 1 ISSUE DATE: YY/MM/DD PLACED NEAR BRIDGE PIN TITLE: CPCI_BLOCK CPCI_BLOCK REVISION NUMBER: 2 ENGINEER: 10 9 + RN14_1 RN12_1 RN13_1 RN13_1 RN10_1 C25_1 8 5 7 8 7 + 1 4 2 1 2 C24_1 10UF 10 10 10 10 10 13E1> 13C10 13C10< 13E1> 13E7< C23_1 10UF P_LOCKB P_FRAMEB P_TRDYB P_IRDYB P_IDSEL P_REQB P_RSTB SERR* PERR* C22_1 0.1UF 15B5 15E5 15B5 15D5 15E5> 15G5< 15D5> 26 25 C19_1 0.1UF SERRX PERRX 0.1UF RN14_1 RN14_1 F C14_1 0.1UF 6 7 13E7> L_INTB\I L_RSTOB\I L_USERI\I L_USERO\I C13_1 3 2 L_CLK\I C15_1 0.1UF 10 10 PME* ENUM* PAR DEVSEL* STOP* 13E7< C17_1 0.1UF P_SERRB P_PERRB 167 52 29 22 23 ENUMX PARX DEVSELX STOPX 13D7> L_ADSB\I 0.1UF RN21_1 RN14_1 RN13_1 RN13_1 91 92 153 151 150 160 142 53 154 152 159 158 13E7< L_READYB\I C16_1 0.1UF 5 5 6 5 C-MODE C/BE* C/BE* C/BE* C/BE* 13D7> 13D7< L_WRB\I LBE0 LBE1 4 4 3 4 LBE2* LBE3* DMPAF/EOT* WAIT* BREQI CCS* LCLK LEDON/LEDIN LINT* LRESETO* USERI/DACK0/LLOCKI* USERO/DREQ0/LLOCKO* PCI9054 PCI9054 LHOLDA\I LHOLD\I 1 1K 2 1K 3 1K 4 1K 10 10 10 10 15F5< 15A5 E P_ENUMB P_PAR P_DEVSELB P_STOPB LW/R* BREQO READY* LSERR* ADS* 90 149 135 146 145 8 7 6 5 6 16 30 41 134 163 144 143 148 U2_1 G RN15_1 RN15_1 RN15_1 RN15_1 CBEX3 CBEX2 CBEX1 CBEX0 139 138 137 136 BTERM* BIGEND* LHOLDA LHOLD BLAST* 6 8 6 7 RN10_1 RN12_1 RN17_1 RN19_1 DP DP DP DP PART#PCI9054-AB50PI PCI9054-AB50PI 3 1 3 2 8 6 8 6 VDD15 VDD15 VDD14 VDD14 VDD13 VDD13 VDD12 VDD12 VDD11 VDD11 VDD10 VDD10 VDD9 VDD8 VDD7 VDD6 VDD5 VDD4 VDD3 VDD2 VDD1 162 147 141 133 116 109 99 89 70 62 45 35 28 20 1 RN1_1 RN5_1 RN3_1 RN3_1 1 3 1 3 AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD 3.3 V 7 6 5 8 10 10 10 10 15C5< 15C5 15F5 15C5 3.3 V 2 3 4 1 173 174 175 2 3 4 5 8 9 10 11 12 13 14 15 31 32 33 34 36 37 38 39 40 42 43 46 47 48 49 50 51 LBE0* LBE1* LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA 3 2 1 0 3.3 V RN2_1 RN2_1 RN2_1 RN1_1 ADX31 ADX31 ADX30 ADX30 ADX29 ADX29 ADX28 ADX28 ADX27 ADX27 ADX26 ADX26 ADX25 ADX25 ADX24 ADX24 ADX23 ADX23 ADX22 ADX22 ADX21 ADX21 ADX20 ADX20 ADX19 ADX19 ADX18 ADX18 ADX17 ADX17 ADX16 ADX16 ADX15 ADX15 ADX14 ADX14 ADX13 ADX13 ADX12 ADX12 ADX11 ADX11 ADX10 ADX10 ADX9 ADX8 ADX7 ADX6 ADX5 ADX4 ADX3 ADX2 ADX1 ADX0 1 1K 2 1K 3 1K 4 1K RN8_1 RN8_1 RN8_1 RN9_1 RN9_1 RN9_1 RN9_1 RN10_1 RN10_1 RN11_1 RN11_1 RN11_1 RN11_1 RN12_1 RN12_1 RN17_1 RN17_1 RN17_1 RN18_1 RN18_1 RN18_1 RN18_1 RN19_1 RN19_1 RN19_1 RN20_1 RN20_1 RN20_1 RN20_1 RN21_1 RN21_1 RN21_1 8 7 6 5 7 6 5 8 7 6 5 6 5 8 7 6 5 8 7 7 6 5 8 7 6 5 8 7 5 8 7 6 5 8 7 6 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 68 67 66 65 64 63 60 59 58 57 56 55 54 C/BE 3.3 V RN6_1 RN6_1 RN6_1 RN6_1 2 3 4 1 2 3 4 3 4 1 2 3 4 1 2 2 3 4 1 2 3 4 1 2 4 1 2 3 4 1 2 3 LBE0 94 LBE1 93 F 3.3 V 10F4 13H10 13H10< 4.7K 4.7K 4.7K 4.7K 95 96 97 98 100 101 102 103 104 105 106 107 110 111 112 113 114 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 C/BE C/BE C/BE C/BE G 15H8 AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD AD 15H8 5E4 13G1> 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 4.7K R7_1 3.3 V LD\I 8 7 6 5 4 3 PAGE:N PMC 2 1 OF M A 10 9 8 7 5 6 4 3 2 1 REVISIONS AD 14H10 14H10 C/BE 14F10 14F10 ZONE REV DESCRIPTION DATE APPR H H C B 4.7K 4.7K 4.7K 4.7K + C7_1 0.1UF C11_1 10UF + C8_1 + C9_1 10UF C5_1 0.1UF 0.1UF C12_1 10UF + C6_1 0.1UF VIO_PCI\I VIO_LONG 12V_PCI\I 21 18 10 VEE_PCI\I + 12 C2_1 C18_1 10UF + 14E9> C3_1 P_SERRB 14E9 0.1UF R? P_DEVSELB C1_1 10UF 7 F 1 VEE_PCI\I 16E8< HEALTHYB\I 16E8> P_IDSEL 14E9< 29 17 P_FRAMEB 14E9 E 15 9 4 P_RSTB P1_1 14E9< STRIP3 3 1 23 STRIP2 16 P_IRDYB 2 14E9 HOLE_SIZE= 150 MIL TP2_1 T CHASSIS MOUNTING HOLE ESD STRIP R2_1 28 10M E1 E2 E3 E4 E5 E6 AD E7 AD E8 AD E9 AD E10 AD E11 C/BE E15 E16 E17 E18 C/BE E19 AD E20 AD E21 C/BE E22 AD E23 AD E24 E25 14E9> 3 D TP1_1 T CHASSIS 10M 14 STRIP1 8 R3_1 1 CPCI ESD STRIP 3 P_ENUMB 14E9> 12V_PCI\I 16E8< P_CLK R1_1 D1 D2 D3 D4 D5 D6 D7 D8 AD D9 D10 AD D11 D15 D16 D17 D18 D19 D20 AD D21 D22 AD D23 D24 AD D25 G 14E9> P_REQB VIO_PCI\I 30 26 0.1UF C1 C2 C3 C4 C5 C6 C7 AD C8 C9 AD C10 C11 AD C15 C16 C17 C18 C19 AD C20 C21 AD C22 C23 AD C24 C25 P_INTAB 10M D B1 B2 B3 B4 B5 B6 B7 AD B8 B9 B10 B11 AD B15 B16 B17 B18 B19 AD B20 B21 AD B22 B23 AD B24 B25 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 F F1 F3 F5 F7 F9 F11 F13 F15 F17 F19 F21 F23 F25 A1 A2 A3 A4 A5 A6 A7 AD A8 AD A9 C/BE A10 AD A11 AD A15 A16 A17 A18 A19 A20 AD A21 A22 AD A23 A24 AD A25 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 F1 F3 F5 F7 F9 F11 F13 F15 F17 F19 F21 F23 F25 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 3_3V_PCI\I C10_1 10UF J1_1 PLACE DECOUPLING CAPS CLOSE TO CONNECTOR 5V_PCI\I RN16_1 8 RN16_1 7 RN16_1 6 RN16_1 5 G 3_3V_LONG CPCI J1 5V_PCI\I 3_3V_PCI\I 1 2 3 4 16F8< 14C3< 14C5< 16G8< 16F8< 3.3 V 14E9< C 25 20 BD_SELB\I P_STOPB P_PAR 16E8< 14E9 14E9 11 6 0 B P_GNTB 14E9< 31 27 24 22 19 DRAWING: TITLE=CPCI_BLOCK ABBREV=CPCI_BLOCK LAST_MODIFIED=Thu Jun 15 10:02:16 2000 2 P_TRDYB P_LOCKB P_PERRB 14E9 14E9 14E9 1 13 10 0 PMC-Sierra, Inc. 5 2 A DOCUMENT NUMBER: PMC-991245 PMC-991245 DOCUMENT ISSUE NUMBER: 1 ISSUE DATE: YY/MM/DD TITLE: SPECTRA 4X155 4X155 REFERENCE DESIGN CPCI_BLOCK ZPACK5X22A ZPACK5X22A CPCI REVISION NUMBER: 2 ENGINEER: 10 9 8 7 6 5 4 3 MB PAGE:15 2 1 OF 16 A PM5316/PM5310 PM5316/PM5310 PRELIMINARY REFERENCE DESIGN PMC-1991245 PMC-1991245 10 ISSUE 1 SPECTRA-4X155 SPECTRA-4X155 WITH TBS REFERENCE DESIGN BILL OF MATERIAL Table 3 Item - Bill of Material Ref. No Description Manufactures Part # 1 U6 IC QUAD 2 IN AND GATE SOIC14 SOIC14 NARROW BODY 2 J5, J6 Z-PACK 6 ROW HS3 BACKPLANE CONNECTOR, RIGHT ANGLE RECEPTACLE 3 C67-C78 C67-C78, C7_2 CAP CERAMIC X7R 0603 50V 0.01UF 4 C8_2 CAP CERAMIC X7R 1206 50V 0.047UF 047UF 5 C10_1, C3, C6, CAP CERAMIC X7R 0603 16V C7, C13-C20 C13-C20, C35, 0.1UF C36, C39, C44, C51, C63-C66 C63-C66, C80-C84 C80-C84, C88C119 C88C119, C11_1, C120-C129 C120-C129, C12_1, C130, C131, C133-C139 C133-C139, C13_1, C140C149 C140C149, C14_1, C150-C159 C150-C159, C15_1, C160C169 C160C169, C16_1, C170-C177 C170-C177, C17_1, C18_1, C19_1, C1_1, C21_1, C22_1, C23_1, C4_1, C5_2, C6_2, C9_1 6 C79, C85-C87 C85-C87 CAP SERAMIC X7R 0805 16V 0.22UF 7 C1, C2, C20_1, CAP TANCAPC 16V 20% 10UF C24_1, C25_1, C29, C2_1, C4, C5, C8, C9, C30C34 C30C34, C37, C38, C3_1, C40-C43 C40-C43, PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 21 MM74HC08M MM74HC08M 120673-1 ECU-V1H103KBV ECU-V1H103KBV ECU-V1H473KBW ECU-V1H473KBW ECJ-1VB1C104K ECJ-1VB1C104K ECJ-1VB1C224K ECJ-1VB1C224K ECS-H1CC106R ECS-H1CC106R PM5316/PM5310 PM5316/PM5310 PRELIMINARY REFERENCE DESIGN PMC-1991245 PMC-1991245 ISSUE 1 Item Ref. No SPECTRA-4X155 SPECTRA-4X155 WITH TBS REFERENCE DESIGN Description Manufactures Part # C45-C49 C45-C49, C52C55 C52C55, C57-C59 C57-C59, C5_1, C60-C62 C60-C62, C6_1, C7_1, C8_1 8 C2_2, C3_2 CAP TANCAPC 35V 20% 2.2UF ECS-H1VC225R ECS-H1VC225R 9 C1_2, C4_2, C9_2 CAP ELECTRO VA SMD 10V 20% ECE-V1AA221P ECE-V1AA221P 220UF 220UF 10 C10-C12 C10-C12, C21CAP C21CAP TANCAPD 10V 20% 47UF ECS-H1AD476R ECS-H1AD476R C28, C56 11 J14 38 PIN SIGNAL CONNECTOR, 2-767004-2 MATCHED IMPEDANCE, 0.025, SMD 12 P1_1 COMPACT PCI ESD STRIP, PART OF PCB CREATE ON PCB LAYOUT 13 D1_1 DIODE RECT 150MA 150MA 75V SMT DL4148MS DL4148MS MINIMELF 14 J11 CONN HEADER STRAIGHT PZC36SAAN PZC36SAAN 36POS 36POS MALE .1" SINGLE ROW 15 J4 CONN HEADER STRAIGHT PZC36SAAN PZC36SAAN 36POS 36POS MALE .1" SINGLE ROW 16 J13 CONN HEADER STRAIGHT PZC36SAAN PZC36SAAN 36POS 36POS MALE .1" SINGLE ROW 17 J7, J12 CONN HEADER STRAIGHT PZC36SAAN PZC36SAAN 36POS 36POS MALE .1" SINGLE ROW 18 J8, J9 CONN HEADER STRAIGHT PZC36SAAN PZC36SAAN 36POS 36POS MALE .1" SINGLE ROW 19 J15 50 MIL SPACING HEADER (150 SAMTEC HTMSPOS PER PART) 150-25-G-S-1 150-25-G-S-1 25 20 J10 HEADER 2X4 SMT 2MM MALE 87267-0850 21 J2 CONNECTOR HEADER 6X2 .1" PZC36DAAN PZC36DAAN 22 U1-U4 MT-RJ DUPLEX SINGLE MODE HFCT-5905E HFCT-5905E TRANSCEIVER HFCT-5905E HFCT-5905E 23 L1-L8 1.81 DIGI-KEY -PCD1172CT-ND -PCD1172CT-ND 24 Q1_2, Q2_2 IC MOSFET POWER IRF7413 IRF7413 25 U7 REGULATOR VARIABLE LM1085 LM1085 MICROPOWER LOW DROPOUT 3.3V 26 U12 REGULATOR VARIABLE LM1085IS-ADJ LM1085IS-ADJ MICROPOWER LOW DROPOUT ADJUSTABLE 27 U3_1 REGULATOR ADJUSTABLE LT1117CST LT1117CST SOT223 800MA 800MA OUTPUT PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 22 PM5316/PM5310 PM5316/PM5310 PRELIMINARY REFERENCE DESIGN PMC-1991245 PMC-1991245 ISSUE 1 Item Ref. No 28 U2_2 29 U5 30 U3_2 31 Y1 32 Y2 33 U13 34 U8 35 M1_1 36 U1_1 37 SW1 38 U2_1 39 U10 40 R14_2, R15_2, R5_2 41 R67, R70 42 R2_2 43 R6_2, R8_2 44 R10, R10_1, R4, R7, R13, R29, R31, R32, R64, R9_2 45 R16_2, R8_1 46 R1_1, R2_1, R3_1 47 R12_1 48 R10_2, R50-R61 R50-R61 49 R1_2 50 R3_2, R4_2 51 R13_1 SPECTRA-4X155 SPECTRA-4X155 WITH TBS REFERENCE DESIGN Description Manufactures Part # IC CPCI HOT SWAP CONTROLLER 4 PIN UP VOLTAGE MONITOR WITH MANUAL RESET INPUT 3.08V SOT143 IC VOLTAGE MONITOR WITH MANUAL RESET INPUT 2.63V SOT143 OSC HCMOS/TTL HALF SIZE 8 PIN 19.44MHZ 44MHZ 20PPM 20PPM OSC HCMOS/TTL HALF SIZE 8 PIN 77.76MHZ 76MHZ 100PPM 100PPM IC DUAL DIFFERENTIAL LVPECL TO TTL TRANSLATOR SOIC8 IC OCTAL 3-STATE NONINVERTING BUFFER/LINE DRIVER/LINE RECEIVER SO20WB SO20WB MOUNTING HOLE .150" DIA 4096 BIT SERIAL EEPROM W/ DATA PROTECT AND SEQ READ DIP8 VERT PCB MOUNT SPST PUSH BUTTOM IC PCI-TO-LOCAL BUS IC 3.3V 2X1:5 CMOS CLOCK DRIVER QSOP20 QSOP20 RES 2512 1W 1% 0.01 OHM RES 0603 1/16W 1/16W RES 0603 1/16W 1/16W RES 0603 1/16W 1/16W RES 0603 1/16W 1/16W LTC1643LCGN LTC1643LCGN MAX811TEUS-T MAX811TEUS-T MAX812REUS-T MAX812REUS-T MB3020H4819 MB3020H4819.44MH Z MB3100H77 MB3100H77.76MHZ 76MHZ MC100LVELT23D MC100LVELT23D MC74HC244ADW MC74HC244ADW MOUNTING HOLE NM93CS66LEN NM93CS66LEN DIGIKEY -P8009S-ND -P8009S-ND PCI9054-AB50PI PCI9054-AB50PI PI49FCT3805CQ PI49FCT3805CQ WSL2512-R01-1 WSL2512-R01-1 5% 1.0K OHM 5% 1.2K OHM 5% 10 OHM 1% 100 OHM ERJ-3GSYJ102V ERJ-3GSYJ102V ERJ-3GSYJ122V ERJ-3GSYJ122V ERJ-3GSYJ100V ERJ-3GSYJ100V ERJ-3EKF1000V ERJ-3EKF1000V RES 0603 1/16W 1/16W 5% 100K OHM RES 1206 1/8W 5% 10M OHM RES 0603 1/16W 1/16W 1% 150 OHM RES 0603 1/16W 1/16W 5% 150 OHM RES 0603 1/16W 1/16W 1% 182 OHM RES 0603 1/16W 1/16W 5% 2.0K OHM RES 0603 1/16W 1/16W 5% 2.2K OHM ERJ-3GSYJ104V ERJ-3GSYJ104V ERJ-8GEYJ106V ERJ-8GEYJ106V ERJ-3EKF1500V ERJ-3EKF1500V ERJ-3GSYJ151V ERJ-3GSYJ151V ERJ-3EKF1820V ERJ-3EKF1820V ERJ-3GSYJ202V ERJ-3GSYJ202V ERJ-3GSYJ222V ERJ-3GSYJ222V PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 23 PM5316/PM5310 PM5316/PM5310 PRELIMINARY REFERENCE DESIGN PMC-1991245 PMC-1991245 ISSUE 1 Item Ref. No 52 R1, R33 53 R35, R37, R39, R41 54 R11_1 55 R69 56 R34, R36, R38, R40 57 R16_1 58 R14_1, R20-R25 R20-R25, R62, R65, R66, R68, R7_1, R7_2 59 R42-R49 R42-R49 60 R26-R28 R26-R28, R63 61 R12_2, R13_2 62 R11_2 63 RN10_1, RN11_1, RN12_1, RN13_1, RN14_1, RN17_1, RN18_1, RN19_1, RN20_1, RN21_1, RN7_1, RN8_1, RN9_1 64 RN22_1, RN23_1, RN24_1, RN25_1, RN26_1, RN27_1, RN28_1, RN29_1, RN30_1, RN31_1, RN32_1, RN33_1, RN34_1 65 RN15_1, RN6_1 66 RN3-RN16 RN3-RN16, RN16_1, RN17RN19 RN17RN19, RN1_1, RN20-RN25 RN20-RN25, RN27-RN29 RN27-RN29, RN2_1, RN30RN34 RN30RN34, RN3_1, RN4_1, RN5_1 67 RN26 68 U1_2 SPECTRA-4X155 SPECTRA-4X155 WITH TBS REFERENCE DESIGN Description Manufactures Part # RES 0805 1/10W 1/10W 1% 2.7 OHM RES 0603 1/16W 1/16W 5% 220 OHM ERJ-6RQF2R7V ERJ-3GSYJ221V ERJ-3GSYJ221V RES 0805 1/10W 1/10W 5% 24 OHM RES 0603 1/16W 1/16W 1% 3.16K OHM RES 0603 1/16W 1/16W 5% 330 OHM ERJ-6GEYJ240V ERJ-6GEYJ240V ERJ-3EKF3161V ERJ-3EKF3161V ERJ-3GSYJ331V ERJ-3GSYJ331V RES 0603 1/16W 1/16W 1% 39.2 OHM RES 0603 1/16W 1/16W 5% 4.7K OHM ERJ-3EKF39R2V ERJ-3EKF39R2V ERJ-3GSYJ472V ERJ-3GSYJ472V RES 0603 1/16W 1/16W RES 0603 1/16W 1/16W RES 0603 1/16W 1/16W RES 0603 1/16W 1/16W ERJ-3EKF49R9V ERJ-3EKF49R9V ERJ-3GSYJ560V ERJ-3GSYJ560V ERJ-3GSYJ561V ERJ-3GSYJ561V ERJ-3EKF63R4V ERJ-3EKF63R4V PANASONIC -EXB-V8V100JV -EXB-V8V100JV 1% 49.9 OHM 5% 56 OHM 5% 560 OHM 1% 63.4 OHM PANASONIC -EXB-V8V103JV -EXB-V8V103JV PANASONIC -EXB-V8V102JV -EXB-V8V102JV PANASONIC -EXB-V8V472JV -EXB-V8V472JV PANASONIC -EXB-V8V560JV -EXB-V8V560JV IC REGULATOR 3.3V TO 1.8V 20 SIE501 SIE501.8R WATTS PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 24 PM5316/PM5310 PM5316/PM5310 PRELIMINARY REFERENCE DESIGN PMC-1991245 PMC-1991245 ISSUE 1 Item Ref. No 69 J1, J3 70 U9 71 D2_2 72 D2 73 D1 74 U15 75 TP1_1, TP2_1 76 U11 77 D1_2 78 J1_1 79 U14 SPECTRA-4X155 SPECTRA-4X155 WITH TBS REFERENCE DESIGN Description Manufactures Part # SMB VERTICAL GOLD MONOLITHIC FOUR CHANNEL SONET/SDH PAYLOAD EXTRACTOR/ALIGNER LED QUAD GREEN HORIZONTAL LED QUAD RED HORIZONTAL LED QUAD YELLOW HORIZONTAL TELECOMBUS SERIALIZER CONNECTOR HEADER STRAIGHT SINGLE .1" CPLD 3.3V 10NS ARF1244-ND ARF1244-ND PM5316 PM5316 SSF-LXH5147LGD SSF-LXH5147LGD SSF-LXH5147LID SSF-LXH5147LID SSF-LXH5147LYD SSF-LXH5147LYD PM5310 PM5310 N/A XC9572XL10TQ100I XC9572XL10TQ100I DIGI-KEY ZM4742ACT-ND ZM4742ACT-ND CONNECTOR ZPACK CPCI 2MM 352068-1 HM 110 POS. TYPE A WITH GND SHIELD IC SINGLE 2-INPUT POSITIVE SN74AHC1G08DC SN74AHC1G08DC AND GATE KR PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 25 PM5316/PM5310 PM5316/PM5310 PRELIMINARY REFERENCE DESIGN PMC-1991245 PMC-1991245 ISSUE 1 SPECTRA-4X155 SPECTRA-4X155 WITH TBS REFERENCE DESIGN NOTES PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 26 PM5316/PM5310 PM5316/PM5310 PRELIMINARY REFERENCE DESIGN PMC-1991245 PMC-1991245 ISSUE 1 SPECTRA-4X155 SPECTRA-4X155 WITH TBS REFERENCE DESIGN CONTACTING PMC-SIERRA, INC. PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: (604) 415-6000 Fax: (604) 415-6200 Document Information: Corporate Information: Application Information: Web Site: document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com (604) 415-4533 http://www.pmc-sierra.com None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. © 2000 PMC-Sierra, Inc. PMC-1991245 PMC-1991245 (P1) Issue date: March 2000 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE