PM3390 PMC-971034 ACCESSES41 8B10B 0X0400-0X047F 0X0480-0X04FF 0X1000-0X13FF - Datasheet Archive

 

PRELIMINARY DATASHEET PMC-971034 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX PM3390 8 PORT GIGABIT EXACT BUS SWITCHING MATRIX

 

PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX PM3390 PM3390 8 PORT GIGABIT EXACT BUS SWITCHING MATRIX DATASHEET PRELIMINARY ISSUE 4: JANUARY 1999 PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX CONTENTS 1 FEATURES. 1 2 APPLICATIONS. 3 3 REFERENCES. 4 4 BLOCK DIAGRAM . 5 5 DESCRIPTION. 6 6 PIN DIAGRAM. 7 7 PIN DESCRIPTION. 9 EXACT BUS INTERFACES . 9 EXPANDABILITY INTERFACE . 12 MICROPROCESSOR INTERFACE . 14 MISCELLANEOUS . 14 JTAG AND TEST PINS . 15 POWER AND GROUNDS . 16 8 FUNCTIONAL DESCRIPTION . 19 8.1 ARCHITECTURE OVERVIEW. 20 8.1.1 TIME AND SPACE SLICED DATAPATH . 20 8.1.2 OUTPUT-BASED DATA STREAMS. 23 8.1.3 EXPANDABILITY INTERFACE. 23 8.1.4 EXACT BUS PHYSICAL LAYER CODING . 23 8.1.5 EXACT BUS CLOCK MODES . 24 8.1.6 EXACT BUS MESSAGES. 26 8.1.7 MAJOR FUNCTIONAL BLOCKS . 27 i PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 ISSUE 4 8.2 8 PORT EXACT BUS SWITCHING MATRIX EXACT BUS INPUT BUFFER . 28 8.2.1 EXACT BUS INTERFACE. 28 8.2.2 EXACT MESSAGE TO CELL DECOMPOSITION . 29 8.2.3 EXACT CONTROL AND MESSAGE PROCESSING. 29 8.2.4 EXACT MESSAGE GATHERING. 29 8.2.5 DESTINATION TO PORT MAPPING . 30 8.2.6 ERROR HANDLING AND STATISTICS GATHERING. 30 8.3 PIPELINED DATA MULTIPLEXER . 32 8.4 CELL CENTRAL STORE. 33 8.5 FREE LIST MANAGER . 34 8.6 CELL LIST MANAGER . 35 8.6.1 BUILDING INPUT DATA STREAMS. 35 8.7 EXACT BUS OUTPUT BUFFER . 36 8.7.1 EXACT BUS INTERFACE. 36 8.7.2 EXACT CONTROL REGISTER AND BROADCAST MESSAGE PROCESSING . 36 8.7.3 LOOK AHEAD OPERATION . 36 8.8 CUT THROUGH OPERATION. 38 8.8.1 EXACT FLOW CONTROL . 38 8.8.2 NON-EXACT FLOW CONTROL . 39 8.9 CORE MANAGEMENT INTERFACE. 40 8.9.1 CMIF ACCESSES VIA THE EXACT BUS . 40 8.9.2 EXTERNAL MICROPROCESSOR INTERFACE AND CMIF ACCESSES . 41 8.9.3 AVOIDING CONFLICT FOR CRI REGISTER ACCESSES41 ACCESSES41 ii PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX 8.9.4 EXACT BUS CONTROL AND STATUS MESSAGE PROCESSING . 42 8.9.5 BROADCAST HOLD-OFF TIMER. 45 8.9.6 MESSAGE BOX FEATURE. 46 9 SYSTEM OPERATION . 47 9.1 CONFIGURATION AND INITIALIZATION. 50 9.1.1 CONFIGURATION . 50 9.1.2 INITIALIZATION . 52 9.2 DESTINATION LOOKUP TABLE . 53 9.2.1 DLT WRITE OPERATION VIA THE EXTERNAL MICROPROCESSOR INTERFACE . 54 9.2.2 DLT READ OPERATION VIA THE EXTERNAL MICROPROCESSOR INTERFACE . 54 9.2.3 DLT ACCESS OVER THE EXACT BUS . 55 9.2.4 AVOIDING SIMULTANEOUS DLT REGISTER ACCESS . 55 9.3 STATISTICS COUNTERS . 56 9.3.1 NON-EXACT FLOW CONTROL . 56 9.4 EXPANDABILITY INTERFACE . 58 9.5 MESSAGE BOX FEATURE . 61 9.5.1 MESSAGE BOX RECEIVE OPERATION. 61 9.5.2 TRANSMIT MESSAGE OPERATION . 64 9.6 JTAG TEST PORT . 68 9.6.1 IDENTIFICATION REGISTER. 68 9.6.2 BOUNDARY SCAN REGISTER. 69 9.7 JTAG SUPPORT. 84 iii PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 ISSUE 4 9.8 10 8 PORT EXACT BUS SWITCHING MATRIX TAP CONTROLLER. 86 NORMAL MODE REGISTER DESCRIPTION . 91 10.1 NOTES ON NORMAL MODE REGISTER BITS:. 92 10.2 CONTROL REGISTER INTERFACE ADDRESS SPACE . 94 10.2.1 GENERAL PURPOSE SOFTWARE REGISTERS . 95 10.3 CMIF REGISTERS . 98 10.4 EXACT BUS DESTINATION LOOKUP TABLE REGISTERS. 127 10.5 FREE LIST MANAGER REGISTERS. 131 10.6 CELL LIST MANAGER REGISTERS . 141 10.7 EXACT INPUT BUFFER (XIB) REGISTERS . 150 10.8 EXACT OUTPUT BUFFER REGISTERS . 165 11 ABSOLUTE MAXIMUM RATINGS . 174 12 D.C. CHARACTERISTICS . 176 13 A.C. TIMING CHARACTERISTICS. 177 13.1 MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS . 178 13.1.1 MICROPROCESSOR INTERFACE READ ACCESS . 178 13.1.2 MICROPROCESSOR INTERFACE WRITE ACCESS . 179 13.2 EXACT INTERFACE INTERFACE TIMING CHARACTERISTICS . 181 13.2.1 XREFCK INPUT TIMING . 181 13.2.2 CLEAR CHANNEL CLOCK MODE OR 8B10B 8B10B NONSERDES CLOCK MODE TIMING (LOAD = 30PF) . 182 13.2.3 SERDES MODE TIMING (XREFCK AT 125 MHZ; LOAD = 30PF) . 184 iv PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX 13.2.4 EXPANSION INTERFACE MODE TIMING (LOAD = 30PF) . 186 13.3 13.4 14 SYSCLK REFERENCED TIMING . 188 ­ JTAG PORT INTERFACE . 191 THERMAL INFORMATION. 193 MECHANICAL INFORMATION . 194 v PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX LIST OF REGISTERS CMIF REGISTER 0X00: DEVICE ID REGISTER (32 BITS).99 CMIF REGISTER 0X01: DEVICE CONTROL REGISTER (32 BITS) .101 CMIF REGISTER 0X02: DEVICE STATUS REGISTER (32 BITS) .103 CMIF REGISTER 0X03 BROADCAST PORT ADDRESS.106 CMIF REGISTER 0X04 BROADCAST HOLD-OFF TIMEOUT.107 CMIF REGISTER 0X05 BROADCAST ENABLE .108 CMIF REGISTER 0X06 EXACT TX PORT OUTPUT ENABLE .109 CMIF REGISTER 0X08: DEVICE ID REGISTER MIRROR.110 CMIF REGISTER 0X09: DEVICE CONTROL REGISTER MIRROR.111 CMIF REGISTER 0X0A: DEVICE STATUS REGISTER MIRROR.113 CMIF REGISTER 0X0B DLT CRI STATUS REGISTER.114 CMIF REGISTER 0X0C DLT CRI CONTROL REGISTER .116 CMIF REGISTER 0X0D DLT CRI WRITE REGISTER .117 CMIF REGISTER 0X10 MESSAGE BOX COMMAND REGISTER .118 CMIF REGISTER 0X11 MESSAGE BOX STATUS REGISTER.120 CMIF REGISTER 0X12 MESSAGE BOX RECEIVE BUFFER POINTER .121 CMIF REGISTER 0X13 MESSAGE BOX RECEIVE COUNTER.122 CMIF REGISTER 0X14 MESSAGE BOX ERROR COUNTER.123 CMIF REGISTER 0X0400-0X047F 0X0400-0X047F MESSAGE BOX RECEIVE BUFFER .124 CMIF REGISTER 0X0480-0X04FF 0X0480-0X04FF MESSAGE BOX TRANSMIT BUFFER.125 DLT REGISTERS 0X1000-0X13FF 0X1000-0X13FF: DESTINATION LOOKUP TABLE.128 FLM REGISTER 0X00 XOB HIGH THRESHOLD .132 vi PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX FLM REGISTER 0X01 XOB LOW THRESHOLD .133 FLM REGISTER 0X02 XOB BUSY THRESHOLD.134 FLM REGISTER 0X03 XIB DISCARD THRESHOLD .135 FLM REGISTER 0X04 WATERMARK.136 FLM REGISTER 0X05 DISCARD COUNT .137 FLM REGISTER 0X06 EMPTY.138 FLM REGISTER 0X07 SEQUENTIAL FLM ADDRESS SELECT .139 CLM REGISTER 0X00 ­ 0X07 OUTPUT CELL COUNTS 0-7 .142 CLM REGISTER 0X10 CUT-THROUGH DEPTH.143 CLM REGISTER 0X11 LOOK-AHEAD DISABLE .144 CLM REGISTER 0X12 CUT-THROUGH DISABLE.145 CLM REGISTER 0X13 IMMEDIATE FLUSH THRESHOLD.146 CLM REGISTER 0X14: FLOW CONTROL THRESHOLD.147 CLM REGISTER 0X15: EXPANSION PACKET RELEASE THRESHOLD.148 CLM REGISTER 0X16: EXPANSION CONTROL MODE .149 XIB REGISTER 0X00: HEADER ERRORS LSB .152 XIB REGISTER 0X01: HEADER ERRORS MSB .153 XIB REGISTER 0X02: MESSAGE ERRORS LSB.154 XIB REGISTER 0X03: MESSAGE ERRORS MSB.155 XIB REGISTER 0X04: BYTES RECEIVED LSB.156 XIB REGISTER 0X05: BYTES RECEIVED MSB.157 XIB REGISTER 0X06: MESSAGES RECEIVED LSB .158 XIB REGISTER 0X07: MESSAGES RECEIVED MSB .159 XIB REGISTER 0X08: TIMEOUT .160 vii PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX XIB REGISTER 0X09: SYNCH COUNT MINIMUM .161 XIB REGISTER 0X0A: SYNCHRONIZATION COUNT.163 XOB REGISTER 0X00: XOB ERRORS.167 XOB REGISTER 0X01: BYTES TRANSMITTED MSB.168 XOB REGISTER 0X02: BYTES TRANSMITTED LSB.169 XOB REGISTER 0X03: MESSAGES TRANSMITTED MSB .170 XOB REGISTER 0X04: MESSAGES TRANSMITTED LSB .171 XOB REGISTER 0X05: XOB: GENERAL PURPOSE SOFTWARE REGISTER 0 .172 XOB REGISTER 0X06: XOB: GENERAL PURPOSE SOFTWARE REGISTER 1 .173 viii PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX LIST OF FIGURES FIGURE 1 EXACT RING CONFIGURATION .1 FIGURE 2 96 + 4 NON-BLOCKING ETHERNET SWITCH .3 FIGURE 3 BITFIELD OF A DLT ENTRY .53 FIGURE 4: INTERCONNECTION OF FOUR PM3390S PM3390S FOR 16-PORT 16-PORT SWITCH .59 FIGURE 5 INPUT OBSERVATION CELL (IN_CELL).82 FIGURE 6 OUTPUT CELL (OUT_CELL).82 FIGURE 7 BI-DIRECTIONAL CELL (IO_CELL).83 FIGURE 8 LAYOUT OF OUTPUT ENABLE AND BI-DIRECTIONAL CELLS.83 FIGURE 9 BOUNDARY SCAN ARCHITECTURE .84 FIGURE 10 TAP CONTROLLER FINITE STATE MACHINE.87 FIGURE 11 352 BALL GRID ARRAY (SBGA) .194 ix PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 1 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX FEATURES System Features x Single Chip 8 port EXACT Bus switch matrix. x Provides a non-blocking connection between 8 EXACT Bus rings that support up to 16 Gbit/s aggregate system bandwidth. x Supports expansion for a non-blocking connection between sixteen EXACT Bus rings that provide up to 32 Gbit/s aggregate system bandwidth using four PM3390 PM3390 devices. x Simplifies design and manufacturing of high-density non-blocking 10/100/1000 Ethernet Switch products. x The EXACT Bus is a flexible gigabit full-duplex bus that allows simple chip-tochip, card-to-card, or box-to-box interconnection. x The EXACT Bus can operate in a point-to-point or insertion ring configuration. E XA C T P ort C on trolle r EXAC T P o rt C ontrolle r EXAC T P o rt C on trolle r EXAC T P ort C on trolle r EXAC T P ort C on trolle r FIGURE 1 x P M 33 90 8 G igabit EXAC T B u s P orts EXAC T P o rt C on trolle r EXACT RING CONFIGURATION Each PM3390 PM3390 port can support one EXACT Bus switch port controller such as the PM3370 PM3370 or PM3371 PM3371 (Octal 10/100 Ethernet Switch Port Controllers) or one PM3380 PM3380 (Gigabit Ethernet Switch Port Controller) device in a point-topoint connection. Alternatively, multiple EXACT Bus switch port controllers can be connected in a ring to the PM3390 PM3390. 1 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX x Supports non-blocking configurations up to 128 x 10/100 ports or 16 Gigabit Ethernet ports. x Utilizes Time and space division switching to ensure a non-blocking datapath from any port to any port. x Address lookup maps logical ports of an EXACT system to physical ports of the PM3390 PM3390. Address lookup map entries can be modified dynamically to change data paths through the PM3390 PM3390. x Optional cut through operation to reduce latency for small EXACT message transmission. x Optional 8B/10B 8B/10B encoding on the EXACT bus allows compatiblity with common SERDES devices to provide serial extension using coax or twinax cable. x Management interface that allows control register access from an external microcontroller or via EXACT Bus messages. x Pinstraps to easily configure clock frequency and data format for EXACT Bus outputs. x Provides a standard 5 signal P1149 P1149.1 JTAG test port for boundary scan test purposes. x Low power 0.35u CMOS technology with a single 3.3V power supply. x 352- pin ball-grid array (BGA) Package. 2 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 2 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX APPLICATIONS The PM3390 PM3390 is a non-blocking Ethernet Switching Matrix that contains connections to and between 8 EXACTTM Bus rings. The PM3390 PM3390 is intended as the backplane connection for Ethernet switching systems with up to 32 Gbit/s aggregate bandwidth requirements. However, the PM3390 PM3390 is not protocol dependent which allows the device to be used in applications other than Ethernet. x 10/100/1000 Ethernet Switches x Layer 3 Ethernet Switches x Routers A typical application where the PM3390 PM3390 can be used is shown in Figure 2. Port controllers such as the PM3380 PM3380 (1x1000 Mbit/s port controller) and the PM3370 PM3370 (8x10/100 port controller) use the EXACT Bus for interconnecting large Ethernet Switch Systems. A block diagram of a non-blocking 96 port 10/100 Mbit/s with four 1 Gbit/s uplinks is shown. FIGURE 2 96 + 4 NON-BLOCKING ETHERNET SWITCH Slave 24 x 10/100 + 1 x 1000 Stackable SERDES SERDES SERDES SERDES PM3390 PM3390 8 Port EXACT Bus Switch Matrix PM3370 PM3370 Octal 10/100 Switch Port Controller PM3370 PM3370 Octal 10/100 Switch Port Controller PM3370 PM3370 Octal 10/100 Switch Port Controller 24 x 10/100 24 x 10/100 1 x 1000 1 x 1000 24 x 10/100 PM3380 PM3380 Gigabit Switch Port Controller 1 x 1000 24 x 10/100 CPU 1 x 1000 SERDES SERDES SERDES SERDES SERDES SERDES Main CPU PM3370 PM3370 Octal 10/100 Switch Port Controller SERDES SERDES SERDES PM3390 PM3390 8 Port EXACT Bus Switch Matrix PM3390 PM3390 8 Port EXACT Bus Switch Matrix SERDES PM3390 PM3390 8 Port EXACT Bus Switch Matrix PM3390 PM3390 8 Port EXACT Bus Switch Matrix SERDES PM3370 PM3370 Octal 10/100 Switch Port Controller PM3370 PM3370 Octal 10/100 Switch Port Controller SERDES SERDES PM3380 PM3380 Gigabit Switch Port Controller SERDES Master 24 x 10/100 + 1 x 1000 Stackable 3 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 3 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX REFERENCES x PMC-970215 PMC-970215 EXACT Bus Protocol Specification x PMC-970862 PMC-970862 PM3380 PM3380 Gigabit Ethernet Switch Port Controller Datasheet x PMC-970861 PMC-970861 PM3370 PM3370 8 x 10/100 Mbit/s Ethernet Switch Port Controller Datasheet x PMC-980713 PMC-980713 EXACT Chipset Control and Management Interface Protocol Specification 4 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 8 PORT EXACT BUS SWITCHING MATRIX BLOCK DIAGRAM 8 x EXACT Input Ports XRXD[9:0] XRCLK 8 x EXACT Output Ports EXACT 8 Input Buffers Pipelined Data Mux CELL CENTRAL STORE Pipelined Data Mux EXACT 8 Output Buffers XTXD[9:0] XTCLK Per Port Signals Per Port Signals Management Interface Expansion Control 4 Port Expansion Interface XFLOWI XFLOWO XSTATI XSTATI XFRAMEI XFRAMEO EXRXD[8:0] EXRXCLK Control Interface SYSCLK XREFCK135 XREFCK135 XREFCK125 XREFCK125 RESETI INT NFLOW[3:0] JTAG Cell List Manager MI_AD[15:0] MI_ALE MI_RD MI_WR MI_CS Free List Manager TDI TDO TMS TCK TRSTB 4 ISSUE 4 5 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 5 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX DESCRIPTION The PM3390 PM3390 EXACT Bus Switching Matrix is a monolithic integrated circuit that provides non-blocking connections between 8 x 1000 Mbit/s EXACT Bus rings. The PM3390 PM3390 uses the EXACT Bus protocol for Physical and Link layer communications within a system. This allows protocol independence for the transport of data through the switch matrix. The PM3390 PM3390 is intended as the backplane connection for Ethernet switching systems with up to 32 Gbit/s bandwidth requirements using port controllers that support the EXACT Bus protocol. Devices such as the PM3370 PM3370 (8 x 10/100 switch port controller) and the PM3380 PM3380 (1 x 1000 switch port controller) can be used to create 10/100/1000 Ethernet switches. The PM3390 PM3390 implements 8 input EXACT Bus interfaces, a central store memory, address resolution and 8 output EXACT Bus interfaces. Each EXACT Bus interface can operate at 125MHz or 135 MHz. 135MHz operation may be used with the PM3380 PM3380 devices to provide more bandwidth for EXACT control messages while maintaining wire-speed data forwarding. The PM3390 PM3390 contains 8 EXACT Bus Input Buffers that each receive the data stream, slice the data into 32-byte cells, code the destination address and sends the cells to the central store memory. The central store memory used the time sliced data cells and then space slices the cells. This cell-based time and space sliced datapath is used to provide a non-blocking switching matrix with efficient memory utilization. The PM3390 PM3390 contains 8 EXACT Bus Output Buffers that retrieve and recombine data from the central store for transmission across the output EXACT Bus. An expandability interface allows a larger, 16 x16 switching matrix to be built. Four 8 x 8 PM3390 PM3390 devices may be combined to provide a nonblocking 32 Gbit/s aggregate bandwidth switch core. The PM3390 PM3390 can be configured and monitored by a microprocessor through the Management Interface or from a remote agent via the EXACT Bus. 6 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 6 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX PIN DIAGRAM 352 SBGA A B C D E F G H J K L M N 1 Vss vss NC NC rx0d3 rx0d0 tx0d9 tx0d6 tx0d4 tx0d1 NC NC vss 2 vss vdd vss rx0d9 rx0d6 rx0d2 NC NC NC NC NC tx1d9 tx1d7 3 rx1d1 vss vdd tdi rx0d8 rx0d5 NC tx0clk tx0d8 tx0d5 tx0d2 tx1clk tx1d8 4 rx1d5 rx1d2 tdo vdd rx0clk rx0d7 rx0d4 rx0d1 vdd tx0d7 tx0d3 tx0d0 vdd 5 rx1d9 rx1d6 rx1d3 rx1d0 6 rx2d2 rx1clk rx1d7 rx1d4 7 rx2d5 rx2d3 rx2d0 rx1d8 8 rx2d9 rx2d6 rx2d4 rx2d1 9 rx3d1 rx2clk rx2d7 vdd 10 rx3d5 rx3d3 rx3d0 rx2d8 11 rx3d8 rx3d6 rx3d4 rx3d2 12 rx4d0 rx3clk rx3d9 rx3d7 13 vss rx4d3 rx4d2 rx4d1 14 vss rx4d4 rx4d5 vdd 15 rx4d6 rx4d7 rx4d8 rx4clk 16 rx4d9 rx5d0 rx5d2 rx5d4 17 rx5d1 rx5d3 rx5d6 rx5d9 18 rx5d5 rx5d7 rx5clk vdd 19 rx5d8 rx6d0 rx6d2 rx6d5 20 rx6d1 rx6d3 rx6d6 rx6d9 21 rx6d4 rx6d7 rx6clk rx7d2 22 rx6d8 rx7d0 rx7d3 rx7d6 23 rx7d1 rx7d4 rx7d7 vdd rx7d9 ad14 ad10 ad7 vdd ad1 mi_rd test_se nflow2 24 rx7d5 vss vdd rx7d8 NC ad11 ad8 ad4 ad2 mi_wr sysclk 25 vss vdd vss ad15 ad12 NC ad5 NC mi_ale mi_cs test_ mode reseti 26 vss vss rx7clk ad13 ad9 ad6 ad3 ad0 NC xrefck 125 xrefck 135 vbias5_ nflow3 1 A B C D E F 7 G H J K L M nflow1 NC vss N PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 P ISSUE 4 R T V W AB AC AD vss tx1d5 tx1d3 NC tx2d9 tx2d7 NC NC tx3clk tx3d7 tx3d4 vss vss 1 NC tx1d4 tx1d1 NC tx2d8 tx2d5 tx2d3 tx2d0 tx3d8 tx3d5 vss vdd vss 2 tx1d6 NC tx1d0 NC tx2d6 tx2d4 tx2d1 NC NC tx3d2 vdd vss tx4clk 3 tx2clk NC vdd tx2d2 tx3d9 tx3d6 tx3d3 vdd tx3d1 tx4d9 tx4d6 4 tx3d0 tx4d8 tx4d5 NC 5 tx4d7 tx4d4 tx4d2 xstato 6 tx4d3 tx4d1 xframeo NC tx4d0 xstati xframei ex3rxck 8 vdd xflowo ex3rxd8 ex3rxd7 9 xflowi NC ex3rxd5 ex3rxd3 10 vbias5_ tx1d2 2 U 8 PORT EXACT BUS SWITCHING MATRIX Y AA AE AF 7 ex3rxd6 ex3rxd4 ex3rxd2 ex3rxd1 11 NC ex3rxd0 ex2rxck ex2rxd8 12 vdd ex2rxd7 ex2rxd6 vss ex2rxd4 NC ex2rxd5 vss 13 14 ex1rxck ex2rxd1 ex2rxd2 ex2rxd3 15 ex1rxd5 NC ex1rxd8 ex2rxd0 16 ex1rxd0 ex1rxd3 ex1rxd6 ex1rxd7 17 vdd ex0rxck ex1rxd2 ex1rxd4 18 ex0rxd4 ex0rxd7 NC ex1rxd1 19 NC ex0rxd3 ex0rxd6 ex0rxd8 20 tx5d8 ex0rxd0 ex0rxd2 ex0rxd5 21 tx5d4 tx5d7 tx5clk ex0rxd1 22 vdd tx7d0 tx7d4 tx7d8 vdd tx6d3 tx6d6 NC tx5d1 vdd tx5d3 tx5d6 tx5d9 23 tms NC tx7d3 tx7d6 tx7d9 tx6d0 NC tx6d7 tx6clk tx5d2 vdd vss tx5d5 24 nflow0 trstb tx7d1 NC NC NC tx6d1 tx6d4 tx6d8 tx5d0 vss vdd vss 25 vss tck int tx7d2 tx7d5 tx7d7 tx7clk tx6d2 tx6d5 tx6d9 NC vss vss 26 P R T U V W Y AA AB AC AD AE AF 8 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 7 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX PIN DESCRIPTION EXACT Bus Interfaces Name RX0D(9:0) Size Type Tolerant 10 I 3.3V Pin Numbers Description D2, E3, Receive data for EXACT ring 0 F4, E2, F3, G4, E1, F2, H4, F1 RX0CLK 1 I 3.3V E4 Receive clock for EXACT ring 0 TX0D(9:0) 10 O 3.3V G1, J3, Transmit data for EXACT ring 0 K4, H1, K3, J1, L4, L3, K1, M4 TX0CLK 1 O 3.3V H3 Transmit clock for EXACT ring 0 RX1D(9:0) 10 I 3.3V A5, D7, Receive data for EXACT ring 1 C6, B5, A4, D6, C5, B4, A3, D5 RX1CLK 1 I 3.3V B6 Receive clock for EXACT ring 1 TX1D(9:0) 10 O 3.3V M2, N3, Transmit data for EXACT ring 1 N2, P3, R1, R2, T1, R4, T2, T3 TX1CLK 1 O 3.3V M3 9 Transmit clock for EXACT ring 1 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 RX2D(9:0) ISSUE 4 10 I 8 PORT EXACT BUS SWITCHING MATRIX 3.3V A8, D10, Receive data for EXACT ring 2 C9, B8, A7, C8, B7, A6, D8, C7 RX2CLK 1 I 3.3V B9 Receive clock for EXACT ring 2 TX2D(9:0) 10 O 3.3V V1, V2, Transmit data for EXACT ring 2 W1, V3, W2, W3, Y2, W4, Y3, AA2 TX2CLK 1 O 3.3V T4 Transmit clock for EXACT ring 2 RX3D(9:0) 10 I 3.3V C12, A11, Receive data for EXACT ring 3 D12, B11, A10, C11, B10, D11, A9, C10 RX3CLK 1 I 3.3V B12 Receive clock for EXACT ring 3 TX3D(9:0) 10 O 3.3V Y4, AB2, Transmit data for EXACT ring 3 AC1, AA4, AC2, AD1, AB4, AC3, AD4, AC5, TX3CLK 1 O 3.3V AB1 Transmit clock for EXACT ring 3 RX4D(9:0) 10 I 3.3V A16, C15, Receive data for EXACT ring 4 B15, A15, C14, B14, B13, C13, D13, A12 RX4CLK 1 I 3.3V D15 10 Receive clock for EXACT ring 4 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 TX4D(9:0) ISSUE 4 10 O 8 PORT EXACT BUS SWITCHING MATRIX 3.3V AE4, AD5, Transmit data for EXACT ring 4 AC6, AF4, AE5, AD6, AC7, AE6, AD7, AC8 TX4CLK 1 O 3.3V AF3 Transmit clock for EXACT ring 4 RX5D(9:0) 10 I 3.3V D17, A19, Receive data for EXACT ring 5 B18, C17, A18, D16, B17, C16, A17, B16 RX5CLK 1 I 3.3V C18 Receive clock for EXACT ring 5 TX5D(9:0) 10 O 3.3V AF23, AC21, Transmit data for EXACT ring 5 AD22, AE23, AF24, AC22, AD23, AC24, AB23, AC25 TX5CLK 1 O 3.3V AE22 Transmit clock for EXACT ring 5 RX6D(9:0) 10 I 3.3V D20, A22, Receive data for EXACT ring 6 B21, C20, D19, A21 B20, C19, A20, B19 RX6CLK 1 I 3.3V C21 Receive clock for EXACT ring 6 TX6D(9:0) 10 O 3.3V AC26, AB25, Transmit data for EXACT ring 6 AA24, Y23, AB26, AA25, W23, AA26, Y25, W24 TX6CLK 1 O 3.3V AB24 11 Transmit clock for EXACT ring 6 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 RX7D(9:0) ISSUE 4 10 I 8 PORT EXACT BUS SWITCHING MATRIX 3.3V E23, D24, Receive data for EXACT ring 7 C23, D22, A24, B23, C22, D21 A23, B22 RX7CLK 1 I 3.3V C26 Receive clock for EXACT ring 7 TX7D(9:0) 10 O 3.3V V24, U23, Transmit data for EXACT ring 7 W26, U24, V26, T23, T24, U26, T25, R23 TX7CLK 1 O 3.3V Y26 Transmit clock for EXACT ring 7 Size Type Tolerant Pin Numbers Description XFLOWI 1 I 3.3V AC10 Input serial flow control stream from master PM3390 PM3390 to slave PM3390 PM3390. XFLOWO 1 O 3.3V AD9 Output serial flow control stream from master PM3390 PM3390 to slave PM3390 PM3390 XSTATI 1 I 3.3V AD8 Input EXACT ring status from slave PM3390 PM3390 to master PM3390 PM3390. XSTATO 1 O 3.3V AF6 Output EXACT ring status from slave PM3390 PM3390 to master PM3390 PM3390. XFRAMEI 1 I 3.3V AE8 Input framing bit for EXPIF status information from slave PM3390 PM3390 to master PM3390 PM3390. XFRAMEO 1 O 3.3V AE7 Output framing bit for EXPIF status information from slave PM3390 PM3390 to master PM3390 PM3390. EX0RXCLK 1 I 3.3V AD18 Shared transmit clock from slave PM3390 PM3390 to master PM3390 PM3390 for Expansion port 0. Expandability Interface Name 12 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 EX0RXD(8:0) ISSUE 4 9 I 8 PORT EXACT BUS SWITCHING MATRIX 3.3V AF20, AD19, AE20, AF21, Shared transmit data from slave PM3390 PM3390 to master PM3390 PM3390 for Expansion port 0. AC19, AD20, AE21, AF22, AD21 EX1RXCLK 1 I 3.3V AC15 Shared transmit clock from slave PM3390 PM3390 to master PM3390 PM3390 for Expansion port 1. EX1RXD(8:0) 9 I 3.3V AE16, AF17, Shared transmit data from slave PM3390 PM3390 to master PM3390 PM3390 for Expansion port `. AE17, AC16, AF18, AD17, AE18, AF19, AC17 EX2RXCLK 1 I 3.3V AE12 Shared transmit clock from slave PM3390 PM3390 to master PM3390 PM3390 for Expansion port 2. EX2RXD(8:0) 9 I 3.3V AF12, AD13, Shared transmit data from slave PM3390 PM3390 to master PM3390 PM3390 for Expansion port 2. AE13, AE14, AC14, AF15, AE15, AD15, AF16 EX3RXCLK 1 I 3.3V AF8 Shared transmit clock from slave PM3390 PM3390 to master PM3390 PM3390 for Expansion port 3. EX3RXD(8:0) 9 I 3.3V AE9, AF9, Shared transmit data from slave PM3390 PM3390 to master PM3390 PM3390 for Expansion port 3. AC11, AE10, AD11, AF10, AE11, AF11, AD12 13 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX Microprocessor Interface Name MI_AD (15:0) Size Type Tolerant Pin Numbers Description 16 B 5V D25, F23, Multiplexed address, data D26, E25, F24, G23, E26, G24, H23, F26, G25, H24, G26, J24, K23, H26 MI_ALE 1 I 5V J25 Address latch enable MI_RD 1 I 5V L23 Read strobe (low-true). De-assertion of MI_RD will cause the PM3390 PM3390 to tri-state the MI_AD[15:0] bus. MI_WR 1 I 5V K24 Write strobe(low-true). MI_CS 1 I 5V K25 Chip select (low-true). De-assertion of MI_CS during a read operation will cause the PM3390 PM3390 to tri-state the MI_AD[15:0] bus. Miscellaneous Name Size Type Tolerant Pin Numbers Description SYSCLK 1 I 3.3V L24 System clock; must be set to onehalf the maximum EXACT Bus TXCLK being used; (i.e. if the 135 MHz clock is being used, SYSCLK is 67.5 MHz; if only the 125 MHz clock is being used, SYSCLK could be either 62.5 MHz or 67.5 MHz). XREFCK135 XREFCK135 1 1 3.3V L25 EXACT Bus reference clock (135 Mhz) 14 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX XREFCK125 XREFCK125 1 I 3.3V K26 EXACT Bus reference clock (125 Mhz) RESETI 1 I 5V M25 Master reset in. This signal is active high. INT 1 O 3.3V T26 Interrupt out (high true, always driven). May be used by an external device to indicate occurrence of an interrupt condition. See CMIF register 0x02 for additional details. NFLOW (3:0) 4 O 3.3V M26, N23, These outputs provide flow-control information for devices supplying data to the PM3390 PM3390. These pins can be left as no-connects if th PM3390 PM3390 is used in an EXACT-based Ethernet switch system. N24, P25 JTAG and Test pins TEST_MODE 1 I 5V M24 Tie logic low: used by PMC-Sierra for test purposes. TEST_SE 1 I 5V M23 Tie logic low: used by PMC-Sierra for test purposes. TDI 1 I 5V D3 JTAG Test Input. When not in use for JTAG testing, this pin must be logic low. TDO 1 O 5V C4 JTAG Test Output. TMS 1 I 5V P24 JTAG Test Mode Select. When not in use for JTAG testing, this pin must be logic low. TCK 1 I 5V R26 JTAG Test Clock. When not in use for JTAG testing, this pin must be logic low. TRSTB 1 I 5V R25 JTAG Test Reset. When not in use for JTAG testing, this pin must be logic high. 15 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX Power and Grounds Name VDD Size Type Pin Numbers Description B2, B25, 3.3V power C3, C24, D4, D9, D14, D18, D23, J4, J23, N4, P23, V4, V23, AC4, AC9, AC13, AC18, AC23, AD3, AD24, AE2, AE25, VSS Ground A1, A2, A13, A14, A25, A26, B1, B3, B24, B26, C2, C25, N1, N26, P1, P26, AD2, AD25, AE1, AE3, AE24, AE26, AF1, AF2, AF13, AF14, AF25, AF26 16 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 ISSUE 4 VBIAS 8 PORT EXACT BUS SWITCHING MATRIX L26, P4 +5V Bias pins. The VBIAS inputs are used to implement 5V tolerance on the inputs. VBIAS pins must be connected to a well decoupled +5V rail if 5V tolerant inputs are required. If 5V tolerant inputs are not required, VBIAS pins must be connected to a well-decoupled 3.3V DC supply together with the power pins. Notes on Pin Description: 1. To avoid damage to the device, during power-up, and power-down the voltage on the VBIAS pin must be kept equal to or greater than the voltage on the pad ring and core power VDD pins. 2. No-Connect and provisional connection rules. Pins can be grouped according to the following rules: x input only pins x output only pins x bidirectional pins. Input only pins Unused input pins must be pulled either high or low through a resistor. The general rule is to pull the input to its logically deasserted state. If a group of inputs is never to be used then they can be tied together and pulled through a single resistor to their logically deasserted state. Up to 11 input pins can be pulled through a single 4.7K ohm resistor to either VDD or GND; up to 22 input pins can be pulled through a 1K ohm resistor to either VDD or GND. If an input is to be conditionally used (that is, "provisional usage"), then each input must have a dedicated resistor pulling the input to its logically deasserted state. Output only pins Output pins that are No-Connects can be left floating. Bi-directional pins Bi-directional pins that are NO CONNECTS can be left floating. 17 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX The following table provides examples for no-connect and provisional connection: Condition Connection description JTAG unused Unused EXACT RX/TX port. Example: RX/TX port 7. Provisional usage of EXACT RX/TX port. Example: RX/TX port 7. in a plug-in module. Microprocessor interface unused Tie TDI, TMS, TCK, TEST_MODE, TEST_SE to GND through 4.7K resistor. Tie TRSTB to VDD through 4.7K resistor. Tie RX7D[9:0] and RX7CLK together, connect to a single 4.7K resistor tied to GND. Place a 4.7K resistor on each of the RX7D[9:0] and RX7CLK lines to GND. The resistor must be placed as close as possible to the input pin on the SBGA package to minimize its affect on the transmission line characteristics of the EXACT bus. Tie MI_RD, MI_WR, MI_CS, and MI_ALE to VDD through a single 4.7K resistor. 18 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 8 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX FUNCTIONAL DESCRIPTION 19 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 8.1 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX Architecture Overview The PM3390 PM3390 is a non-blocking 8 x 8 EXACT Bus switching matrix that can be expanded to a non-blocking 16 x 16 matrix by using four PM3390 PM3390 devices. The important architectural features of the design are: x Time and space sliced datapath, x Output-based data streams, x Expandability interface. 8.1.1 Time and Space Sliced Datapath The PM3390 PM3390 provides connections to eight 1 Gbit/s data streams. If the input and output sections of the PM3390 PM3390 are considered independently, then to fulfill the purpose of the device, the architecture described can receive up to eight 1 Gbit/s input streams and supply up to eight 1 Gbit/s output streams without the loss on any data. There are pathological input/output patterns that focus input traffic at a particular output or require multiple output traffic streams to be sourced from a particular input. To provide a non-blocking switching matrix, a data storage mechanism is implemented within the matrix to avoid traffic loss during these cases of focused traffic. A dynamically allocated memory (a large central memory) is implemented as the data stream store, to reduce the memory requirements and to solve these problems. Alternative memory structures such as a static memory storage scheme (individual input/output FIFOs) would require more storage than is economical to implement. With a central memory resource in the data path, contention through this single resource must be resolved. Each input and each output is guaranteed a path to and from the store without blocking. This is achieved by slicing the input data streams both in time and space and recombining them before the streams exit the device. The dimensions of a switching matrix define the number of data streams that it can support. If a switching matrix can support n data streams, to take advantage of the architecture, the data store is divided into n independent storage arrays. Additionally, each data stream must be divided into n equal-sized pieces and each piece written into the n storage arrays over the course of n time units. By writing the n pieces of the n data 20 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX streams into n storage array over the course of n time units, each input data stream will have an independent and guaranteed time/space slice of the switching matrix. In the above figure, the slicing of the data and the data store is shown for n = 8. Slicing is accomplished at several points in the data path. The central store C ell 1 C ell 2 C ell 3 C ell 4 C ell 5 C ell 6 C ell 7 C ell 8 W ord 1 W ord 1 W ord 1 W o rd 1 W o rd 1 W o rd 1 W o rd 1 W ord 1 C ell 8 C ell 1 C ell 2 C ell 3 C ell 4 C ell 5 C ell 6 C ell 7 W ord 2 W ord 2 W ord 2 W o rd 2 W o rd 2 W o rd 2 W o rd 2 W ord 2 S p a ce C ell 7 C ell 8 C ell 1 C ell 2 C ell 3 C ell 4 C ell 5 C ell 6 W ord 3 W ord 3 W ord 3 W o rd 3 W o rd 3 W o rd 3 W o rd 3 W ord 3 C ell 6 C ell 7 C ell 8 C ell 1 C ell 2 C ell 3 C ell 4 C ell 5 W ord 4 W ord 4 W ord 4 W o rd 4 W o rd 4 W o rd 4 W o rd 4 W ord 4 C ell 5 C ell 6 C ell 7 C ell 8 C ell 1 C ell 2 C ell 3 C ell 4 W ord 5 W ord 5 W ord 5 W o rd 5 W o rd 5 W o rd 5 W o rd 5 W ord 5 C ell 4 C ell 5 C ell 6 C ell 7 C ell 8 C ell 1 C ell 2 C ell 3 W ord 6 W ord 6 W ord 6 W o rd 6 W o rd 6 W o rd 6 W o rd 6 W ord 6 C ell 3 C ell 4 C ell 5 C ell 6 C ell 7 C ell 8 C ell 1 C ell 2 W ord 7 W ord 7 W ord 7 W o rd 7 W o rd 7 W o rd 7 W o rd 7 W ord 7 C ell 2 C ell 3 C ell 4 C ell 5 C ell 6 C ell 7 C ell 8 C ell 1 W ord 8 W ord 8 W ord 8 W o rd 8 W o rd 8 W o rd 8 W o rd 8 W ord 8 Tim e is divided into eight separate banks (one for each input/output stream connected to the device), and the input/output data streams are separated into eight pipelined pieces (one for each memory bank). For these pipelined pieces to be the same size, the incoming stream is also divided into constant-sized pieces. At the input stage in the device, the input stream is divided into 32-byte cells and these cells are used throughout the device. Once the space (the central store) and the time (pipelined input streams) have been sliced, the only problem left to solve is how to write/read these streams to/from the central store. Both time and space are sliced into a 21 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX data stream number of pieces. So, at each time slice, a data element must be read/written into its corresponding space slice. The time to write/read a cell into the central store (hereafter referred to as a cell clock) is divided into n separate memory cycles where the above mentioned data/time slice memory transfers take place. Because all input data stream are divided into n parts that are each written into a separate bank, all cell transfers require a write/read of all n memory banks. These write/reads are coordinated such that each input/output stream is being written to /read from a separate bank of the central store on each memory clock, but that all will have written to /read from each bank at the completion of a cell clock. M e m o ry C lo c k C o u n te r 2 1 0 P G In p u t D ata S trea m 4 In p u t D ata S trea m 0 A In p u t D ata S trea m 5 In p u t D ata S trea m 1 I Q C e n tral S to re D ata 0 B J R C e n tral S to re D ata 1 In p u t D ata S trea m 6 In p u t D ata S trea m 2 C K S C e n tral S to re D ata 2 In p u t D ata S trea m 7 In p u t D ata S trea m 3 D L T C e n tral S to re D ata 3 In p u t D ata S trea m 0 In p u t D ata S trea m 4 E M U C e n tral S to re D ata 4 In p u t D ata S trea m 1 In p u t D ata S trea m 5 F N V C e n tral S to re D ata 5 In p u t D ata S trea m 2 In p u t D ata S trea m 6 G O W C e n tral S to re D ata 6 In p u t D ata S trea m 3 In p u t D ata S trea m 7 H P X C e n tral S to re D ata 7 H The mechanism used to supply the n data slices to the n-way central store is a log2n-stage barrel shifter. This scheme provides each input/output with a continuous, non-blocking path to the central store, which is the goal of the PM3390 PM3390 space-time sliced architecture. 22 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX 8.1.2 Output-based Data Streams Once the input data streams have been placed into the central store, they must be routed to the appropriate output ring. The banks of the central store are composed of cell locations. The used/unused status of these cell locations is maintained in a free list. As these locations are used to store input cells, the locations are linked together based on their destination ring. Each output ring has an associated linked list that corresponds to the cells that must be transferred onto its EXACT ring. The Cell List Manager (CLM) is responsible for maintaining these lists and supplying addresses to the central store for outbound data. By managing the lists in this fashion, efficient use of the central store is realized. 8.1.3 Expandability Interface The PM3390 PM3390 switching matrix is a building block that can be used to create larger port count and higher bandwidth systems. An Expandability Interface (EXPIF) has been added to the PM3390 PM3390 to allow these larger systems to remain non-blocking and to prevent any electrical problems that could arise from a "bus sharing" expandability solution. The standard expandability option will allow four PM3390 PM3390 devices to be configured into a 16 x 16 switching matrix. The four PM3390 PM3390 devices are split into two pairs and each of the pairs communicates via the EXPIF to provide the desired functionality. Under normal operation the eight input and eight output ports form an 8 port switching matrix. When the PM3390 PM3390 is configured for expandability, two PM3390 PM3390 are interconnected and the eight ports are grouped into two sets of four ports. The four transmit ports that are configured in Expansion Mode are connected to the four Expansion Interface receive ports on the second PM3390 PM3390 device (and vice-versa). Creation of a non-blocking 16x16 switching matrix is achieved by interconnecting the two sets each of two PM3390 PM3390 devices (so there are a total of four PM3390 PM3390 devices). 8.1.4 EXACT Bus Physical Layer Coding The PM3390 PM3390 input and output interfaces are based on the EXACT Bus Specification. Please refer to document PMC-970215 PMC-970215, section 4 (Physical Layer Coding and Flow Control) for a discussion of the physical layer coding that is used on the PM3390 PM3390. There are two types of coding that can be selected: either 8B10B 8B10B encoding or a binary-encoded method (referred 23 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX to as Clear Channel). The encoding is selectable on a per-port basis during the initialization sequence following reset assertion. For discussion purposes, assume for the remainder of this paragraph that a given receive port on the PM3390 PM3390 is configured to accept 8B10B 8B10B encoded characters. The stream of 8B10B 8B10B characters received by the PM3390 PM3390 can be classified by the receive logic into two classes: comma characters (referred to as EXACT bus delimiter characters) and noncomma characters (which are interpreted as EXACT message characters). There is no synchronization performed on the incoming character stream on a message-by-message basis. The on-chip 8B/10B 8B/10B receive logic that is part of the PM3390 PM3390 receiver uses the detection of the comma character (i.e. K28.5) in the data stream to delimit EXACT messages. A "synchronization" procedure is followed once, upon start-up, which insures that some configurable number of consecutive comma characters are seen in the incoming data stream before the PM3390 PM3390 receive logic will start forwarding incoming EXACT messages. A similar procedure is followed if the input receive logic had been configured to operate on a binary-encoded character stream (i.e. Clear Channel mode). The PM3390 PM3390 device handles EXACT bus delimiter characters as follows: 1. On the EXACT receive ports (XIBs), delimiter characters are used only to determine the beginning and end of EXACT messages. Although the EXACT bus specification states "it is mandatory for an odd number of characters to be inserted between every pair of IDLE or BUSY characters" the PM3390 PM3390 input receive port will process messages that do not follow this requirement. However, failure to conform to this requirement can lead to an internal overflow condition on the receive ports if the condition is sustained. 2. Internal to the PM3390 PM3390 device, the delimiter characters are stripped. 3. On the PM3390 PM3390 EXACT transmit ports the delimiter characters are reinserted. The insertion logic guarantees that the EXACT bus specification is met: there will be an odd number of characters inserted between every pair of IDLE or BUSY characters. 8.1.5 EXACT Bus Clock Modes The EXACT bus supports two modes of clock operation: SERDES and non-SERDES. 24 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX 8.1.5.1 SERDES mode clocking SERDES is an acronym for Serializer/de-serializer mode. Typically this mode is used to interface to a high-speed Serializer/de-serializer transceiver. Data is encoded using the 8B10B 8B10B linecode. Receive data (RXD[9:0]) is clocked into the receive port of the PM3390 PM3390 from the SERDES device on both the rising edge and falling edge of the RXCLK signal. Transmit data (TXD[9:0]) from the PM3390 PM3390 is valid on the rising edge only of the PM3390 PM3390 TXCLK signal. So for a 1 Gbit SERDES device, the RXCLK frequency will be 62.5 MHz while the TXCLK frequency will be 125 MHz. Alternatively, the RXCLK can be 67.5 MHz for a TXCLK clock of 135 MHz. Many SERDES devices include complementary receive clocks. Either clock can be connected to the RXCLK input of the PM3390 PM3390 device as long as the clock and data relationship meet the AC timing requirements given in the AC section of this data sheet. Either of the complementary receive clocks on the SERDES device can be connected to the RXCLK input because the on-chip 8B/10B 8B/10B receive logic that is part of the EXACT interface logic only uses the detection of the comma character (i.e. K28.5) in the data stream to delimit EXACT messages. For reference purposes, the PM3575 PM3575 24x10/100 + 2x1000 Ethernet switch reference design (uses the PM3390 PM3390, PM3370 PM3370, and PM3380 PM3380 devices) connects the RBC0 clock from the HP SERDES device (part number HDMP 1636) to the RXCLK input of the PM3390 PM3390. 8.1.5.2 non-SERDES mode clocking Receive data (RXD[9:0]) is clocked into the receive port of the PM3390 PM3390 from the upstream device on both the rising edge and falling edge of the RXCLK signal. Transmit data (TXD[9:0]) from the PM3390 PM3390 is valid on both the rising edge and falling edge of the PM3390 PM3390 TXCLK signal. So for 1 Gbit bit-rate transfer, the RXCLK frequency will be 62.5 MHz while the TXCLK frequency will also be 62.5 MHz. Alternatively, the RXCLK can be 67.5 MHz for a TXCLK clock of 135 MHz. 8.1.5.3 CLOCK and ENCODING modes The PM3390 PM3390 supports a total of four clock and data encoding modes: 1. SERDES mode 25 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX Data is 8B10B 8B10B encoded, TXCLK at twice the rate of RXCLK. Both RX and TX busses of a given port are configured to be in the same mode. 2. 8B10B 8B10B non-SERDES mode Data is 8B10B 8B10B encoded, TXCLK at same rate as RXCLK. Both RX and TX busses of a given port are configured to be in the same mode. 3. Clear Channel mode Data is binary-encoded as per EXACT Bus specification, TXCLK at same rate as RXCLK. Both RX and TX busses of a given port are configured to be in the same mode. 4. Expansion mode This is a variation of Clear Channel mode and is used only between the Transmit output port of one PM3390 PM3390 device and the Expansion Receive Data port of a different PM3390 PM3390 device. On both devices the Expansion mode interface configuration bit must be set. The Data is binary-encoded. TXCLK at same rate as RXCLK. Only the TX bus of a given port is configured to be in this mode. The RX bus of the port can be independently configured to be in either SERDES, 8B10B 8B10B non-SERDES, or Clear Channel modes. This mode of operation for a Transmit port is selected by having the Expansion Interface Mode bit set for that port (see CMIF register 0x01 for additional details). Refer to the configuration section of this document on how to select the clock and data encoding mode on a per-port basis. 8.1.6 EXACT Bus Messages The PM3390 PM3390 supports 8 input and 8 output EXACT Bus ports. The EXACT Bus is a gigabit bus that is used to connect ports controllers (PM3380 PM3380, 1x1000 and PM3370/PM3371 PM3370/PM3371, 8x10/100) and the PM3390 PM3390 switch matrix in an Ethernet switch. Please refer to the EXACT Bus Protocol Specification document for more details. The EXACT protocol partitions Ethernet frames into multiple 240 byte messages within the port controllers. This document refers to these messages, including system control messages as EXACT Messages. These EXACT messages are then transmitted out on the EXACT Bus ring for distribution to other port controllers as required. 26 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX 8.1.7 Major Functional Blocks The PM3390 PM3390 is partitioned into the following major functional blocks. The operation of each block is described in more detail in subsequent sections. Block Function XIB PDX CCS FLM CLM XOB CMIF EXACT Bus Input Buffering Pipelined Data Multiplexer Cell Central Store Free List Manager Cell List Manager EXACT Bus Output Buffering Core Management Interface 27 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 8.2 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX EXACT Bus Input Buffer The EXACT Bus Input Buffer (XIB) receives a stream of 1 Gbit/s EXACT messages from an EXACT ring. The XIB must: 1. Decode the incoming EXACT data in either 8B/10B 8B/10B encoded or in Clear Channel format. 2. Strip the destination address from incoming messages and send it to the Core Management Interface (CMIF) for destination lookup. 3a. For messages not destined to the PM3390 PM3390, gather incoming EXACT Bus messages into as much of a 32-byte cell as is possible given traffic patterns, and deliver the 32-byte cells to the Pipelined Data Multiplexer to be written into the Cell Central Store. 3b. For messages destined to the PM3390 PM3390 (EXACT Control messages or EXACT Broadcast messages), deliver the message data to the Core Management Interface (CMIF) for processing. There is one XIB for each of the eight EXACT rings that the PM3390 PM3390 supports. 8.2.1 EXACT Bus Interface Data enters the PM3390 PM3390 through the EXACT Bus receive port (XIB). The incoming data is encoded according to the EXACT Bus Protocol Specification Document. The XIB must sample the incoming data in either 8B/10B 8B/10B format or in Clear Channel format. The incoming data is received at 62.5 MHz or 67.5 MHz and is sampled on both the rising and falling edges of the receive clock. Once the data has been sampled, the XIB must strip the destination address from the incoming header and send it to the Core Management Interface (CMIF) where the destination is decoded. If the message is destined for the PM3390 PM3390, the message data is routed to the CMIF, else the data proceeds through the XIB datapath. Unlike other EXACT devices, the PM3390 PM3390 does not modify the EXACT message in any way. By not modifying the data, the PM3390 PM3390 can be programmed to work in systems that do not implement the EXACT Bus protocol. 28 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX The XIB follows a protocol to access the EXACT Bus, this protocol is described in detail in EXACT Bus Specification Document. 8.2.2 EXACT Message to Cell Decomposition The internal switching architecture of the PM3390 PM3390 is based on the notion of decomposing EXACT messages into 32-byte cells in the XIB for internal use and then re-assembling the 32-byte cells into complete EXACT messages in the XOB. The internal data path is 32-bits wide; therefore, a cell is composed of eight internal data words. The XIB stages the data it receives from the EXACT Bus in a FIFO. At each cell clock, if the XIB has a complete cell for transfer it sends the data to the PDX, otherwise it holds this data for the next cell clock where its status will be re-evaluated. A complete cell can be either a full 32-byte data cell, a fraction of a 32-byte cell that represents the last block of a data message, or a number of queue messages (up to three) destined for a given output ring. 8.2.3 EXACT Control and Message Processing The PM3390 PM3390 has a bank of control registers and these can be written or read via the EXACT bus protocol using control messages. The XIB strips the destination from the incoming message and route it to the Core Management Interface (CMIF) for destination lookup. If the destination of the message is to the PM3390 PM3390 Base Address or to the EXACT Broadcast Address, the CMIF will signal the XIB to route the message data to the CMIF for processing. 8.2.4 EXACT Message Gathering The internal architecture is based on transferring EXACT messages as 32byte cells; therefore the transfer quanta to and from the CCS is an entire 32-byte cell. Queue messages are significantly smaller than a cell. So, when a 6-byte queue message is written into the CCS there are wasted memory cycles. For optimal PM3390 PM3390 performance, some method for increasing efficiency on queue messages is needed. The method implemented in the XIB is an accumulator for EXACT message streams. By accumulating EXACT messages over a number of cell clocks, all messages can be more efficiently stored in the CCS. The XIB contains an EXACT Message Accumulator (EMA) that can store up to three queue messages for each possible output port. When data 29 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX enters the XIB, the contents of the message are stored in the section of the EMA that corresponds to the output port encoded in the DEST[9:0] field (see EXACT Bus Specification Document). EXACT messages for each output port are accumulated over a programmable period (the default is a period of eight cell clocks). If during the period, the CLM signals that it has nothing queued for the output port (i.e. the output port is not fully utilized), the messages that have been accumulated will be sent to the CCS for storage and later forwarding to the output port. 8.2.5 Destination to Port Mapping When an EXACT message enters the XIB, the DEST[9:0] field must be decoded into a destination EXACT ring number. The PM3390 PM3390 contains a Destination Lookup Table that is initialized by the system microcontroller or master port controller. The CPU maps the possible 1024 system destinations to one of eight EXACT rings (or sixteen EXACT rings in the four chip 16 x 16 configuration) to which the PM3390 PM3390 is connected. This table can be loaded dynamically to support topology changes in the network. While the cell is being staged in the XIB, the DEST[9:0] field is sent to the lookup table and a four bit value is returned. It contains PORT[2:0] which is the destination port, and DISCARD which is used to determine whether the device will drop the incoming packet because it does not support a connection to the destination EXACT ring at this time. This functionality is needed in the four-chip 16 x 16 configuration when each PM3390 PM3390 device will receive EXACT messages destined for EXACT rings that it does not drive. The lookup table will power up with all DISCARD bits set which will keep any EXACT traffic from being generated / propagated until the master CPU has initialized the PM3390 PM3390 to do so. Additionally, the DISCARD signal will be set when the message is of a type that is processed by the CMIF; these types are EXACT Broadcast and EXACT Control messages. 8.2.6 Error Handling and Statistics Gathering Line coding errors are detected on the EXACT Bus receive port (these can be 8B/10B 8B/10B encoded line coding errors or parity errors in Clear Channel format). If an XIB detects an error of this class and the error is within the header of the message, the PM3390 PM3390 will drop the message and increment a statistics counter in the control registers section of the device. If an error occurs beyond the header of the message, the PM3390 PM3390 will insert the 30 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX Error Propagation Character (See the EXACT Bus Protocol Specification) at the location of the error and truncate the rest of the message. In both cases, the XIB will increment statistics counters that tally the number of header and non-header errors received on a per EXACT port basis. When messages are received by an XIB, statistics counters tallying the number of messages and bytes received will be incremented. 31 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 8.3 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX Pipelined Data Multiplexer The Pipelined Data Multiplexer (PDX) stages both cell data and cell addresses to the Cell Central Store (CCS). The PDX arbitrates access to the CCS by the input and output ring buffers. Arbitration is crucial to provide non-blocking access for each input and output port to the central store. In addition, optimal arbitration directly affects the memory required for the central store. To prevent input overflow or output starvation, the memory architecture allows each input and each output a path to the CCS on each memory clock. 32 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 8.4 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX Cell Central Store The Cell Central Store (CCS) is composed of eight dual-port memory banks that store all of the EXACT message data streams. The data streams are converted into 32-byte cells in the XIB/XOB. These 32-byte cells are pipelined through the Write/Read PDX to the CCS. The FLM supplies the write addresses to the CCS and the CLM supplies the read addresses to the CCS. 33 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 8.5 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX Free List Manager The Free List Manager (FLM) is responsible for providing CCS write addresses used by the Write PDX. A bitmap is maintained which represents the used status of each cell location in the CCS. When the destination XOB places the cell onto the EXACT ring, the CLM sends control information to the FLM, which signals to clear the used status information in the bitmap for the address corresponding to the cell. 34 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 8.6 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX Cell List Manager The Cell List Manager (CLM) manages the EXACT messages that are stored in the CCS. As input data streams enter the chip, the FLM provides write addresses to the CCS. The CLM uses these write addresses and the destination ring and cell type information from the XIB to track the data streams per EXACT output. The CLM orders the data streams in memory for the XOB and provides a read address to the CCS per memory clock so that the XOB can read the data. 8.6.1 Building Input Data Streams The XIB decomposes EXACT messages into cells and forwards the data through the PDX to be stored in the CCS. The data is stored at an address provided by the FLM. This address, as well as status information about the cell from the XIB, is provided to the CLM. The XIB and FLM stage the address and status information so that they are aligned upon arrival at the CLM. After the CLM links the cells associated with a single message together it sends the cells to the CCS and alerts the destination output port. 35 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 8.7 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX EXACT Bus Output Buffer The EXACT Bus Output Buffer (XOB) is responsible for routing the data bound for an EXACT Bus output port from the Read PDX. Each XOB receives a data stream from the Read PDX and from the Expandability Interface (EXPIF). Based on control information from the CLM, the XOB determines which data stream will be sent to the EXACT Bus. 8.7.1 EXACT Bus Interface The XOB prepends a message with a linecode delimiter and then transmits the message as is with no modifications. The data that is transmitted onto the EXACT bus is encoded in 8B-10B 8B-10B linecode or in Clear Channel mode. Transmit data is output to the bus through the EXACT transmit port which contains a 10-bit data bus clocked by a locally provided 125/135 MHz transmit clock. The output frequency and data formats are controllable by pin straps. The XOB follows a protocol to access the EXACT bus, this protocol is described in detail in EXACT Bus Specification Document. 8.7.2 EXACT Control Register and Broadcast Message Processing The XOB has a 32-bit data port to the CMIF. When a control register message or an EXACT broadcast is intended for an EXACT ring, the CMIF sends a signal telling the XOB that it has a message pending. The XOB will finish processing the current EXACT message and upon completion send status to the CMIF indicating that it is ready to receive the control or broadcast message. After a successful status from the XOB, the CMIF will forward the message to the XOB. While the XOB is waiting for the CMIF to forward the message, it will process no other EXACT traffic. 8.7.3 Look Ahead Operation The PM3390 PM3390 incorporates a look ahead function to increase the efficiency of the EXACT Bus output ports. The look ahead function reduces the number of IDLE messages transmitted by an output port when small EXACT Bus messages are to be sent. The XOB contains two FIFOs that are used for look ahead operation. When small EXACT messages (either queue messages or the data block fragments at the end of an EXACT message) are sent, the path from 36 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX memory is used inefficiently. If the XOB did not use any form of look ahead these small messages would cause the EXACT ring to be temporarily starved. However the path from the CCS which fills these FIFOs operates at twice the bandwidth that the XOB can place data onto the EXACT Bus. Because the additional bandwidth exists, if the CLM has additional cells destined for an output, it will forward these to the XOB and set a look ahead bit. The two FIFOs in the XOB are sized so that each may store an outbound EXACT message. When the look ahead bit is set, the XOB will allow writes to the FIFO not currently sourcing data to the EXACT Bus. When the XOB encounters the end of a message in the current FIFO, it will switch FIFOs. If the message is a short message (either a queue message or the final cell fragment of a data block), the "dead time" on the EXACT Bus will be removed and the latency for the message following the short message will be decreased. The overall effect of this is to smooth the traffic flow onto the EXACT Bus. Because the XOB will switch FIFOs on EXACT message boundaries, there is no concern about message ordering. Look ahead operation will reduce latency in sparse traffic focusing conditions. In these traffic situations, the XOB would always read entire cells of data even when the cells were not full of valid data. This occurs on accumulated queue messages as well as in the final data block of EXACT messages. On average these blocks are only half full and the XOB would add one half a cell time of latency to the messages. Additionally, the XOB could not begin transmission until the entire cell had been placed in its output buffers. This would introduce another half cell time of latency. So, the overall latency penalty for not implementing the look ahead operation between the CLM and the XOB would add an additional cell time to the EXACT messages in these traffic situations. 37 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 8.8 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX Cut Through Operation The PM3390 PM3390 supports a cut through mode that allows a direct path to be created between input and output EXACT Bus ports. The cut through mode is used to increase output port transmission efficiency when there is a gap between EXACT messages. The CLM can perform cut through when a message is bound for an output that is idle. If the destination port is busy, the entire message is stored in the CCS before it is forwarded. However, if an incoming EXACT Bus Message is destined for an output that is idle, the CLM initiates cut through after receiving the first 2 ­ 3 32 byte cells of the message. Once the first 23 cells are received, the remainder of the message is streamed through the PM3390 PM3390 to the output. Reception of the first 2 cells is required in an EXACT Bus system to ensure that the output is not starved once the message transmission begins. In systems that do not implement the EXACT Bus link protocol, it is recommended that the cut through be set to start after the first 3 32 byte cells of a message. 8.8.1 EXACT Flow Control The EXACT flow control mechanism is designed to allow a system without a central resource to function fairly. Once a PM3390 PM3390 device is added to the system, the position of a device on the EXACT ring in relationship to the PM3390 PM3390 will greatly effect its ability to issue / receive traffic. The PM3390 PM3390 does not support "Ring Flow Control" that is described in the EXACT Bus protocol specification (PMC-970215 PMC-970215 Section 4.3). The PM3390 PM3390 receiver logic handles the IDLE, BUSY, FILLN, and FILLP characters (in 8B/10B 8B/10B mode these are K28.5, K28.1, K28.6, and K28.7 characters respectively of either positive or negative disparity) as valid non-EXACT characters. Hence, an EXACT message received with a BUSY character delimiter will be treated no differently than one received with an IDLE character delimiter. There is no interaction between the receipt of a given EXACT message on a port with a BUSY character delimiter to the delimiter character selected when the given message is sent out one of the eight TX ports of the PM3390 PM3390. The transmit port of the PM3390 PM3390 is capable of outputting EXACT messages delimited by either a IDLE or a BUSY characters but the message delimiter selected is based solely on the setting of the FLM XOB 38 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX Busy Threshold and the number of Cell Central Store messages that are queued internal to the device (this is a configurable parameter: see NonEXACT flow control description). 8.8.2 Non-EXACT Flow Control In non-EXACT systems, it may be necessary to flow control devices that source traffic through a PM3390 PM3390. There are two methods for implementing flow control for the PM3390 PM3390. The first method is used to prevent overflow in the CCS, when a threshold is reached, EXACT BUSY characters are transmitted instead of EXACT IDLE characters. This is a global flow control and does not address individual ports. The second method uses status signals that provide flow control information per port in the PM3390 PM3390. The traffic sourcing devices in non-EXACT systems can use this information to implement flow control. See the systems operation section for additional details on non-EXACT flow control. 39 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 8.9 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX Core Management Interface The PM3390 PM3390 provides a Core Management Interface (CMIF) to support low speed external management tasks and for diagnostic purposes. The CMIF supports read and write access of any on-chip register by a remote agent. These register accesses can be initiated either over the EXACT Bus or over a 16-bit asynchronous microprocessor port. The internal bus used for accessing these registers is called the Control Register Interface, or "CRI" bus (this terminology is used elsewhere in this document). 8.9.1 CMIF accesses via the EXACT bus The EXACT bus input buffer datapath will route EXACT bus messages to the CMIF if the 10-bit Destination Address field in the EXACT bus message matches the 10-bit DeviceAddress field of CMIF register 0x00. If the address match fails, then the received EXACT message is routed as a normal EXACT message. There is a special case if the 10-bit Destination Address field of the EXACT message is exactly equal to EXACT broadcast address (this address is configurable- see CMIF register 0x03- and defaults to the EXACT Bus broadcast address value of 10'h3FF). EXACT bus messages that have a Destination Address field that matches the DeviceAddress in CMIF register 0x00 or is equal to the EXACT bus broadcast address will be removed from the normal traffic datapath and routed to the CMIF logic block, where it will go to a 256 byte FIFO. The data in this FIFO is read and processed by a state machine according to the following rules: x If the EXACT bus message meets the criteria specified for a Control Register read/write, then the register access will be performed x Else, the received message will be written to the Message Box Receive Buffer. The Message Box feature provides a low bandwidth interface between the EXACT bus and the PM3390 PM3390's external microprocessor interface. The EXACT Control message interface allows 32 bit register reads and writes. However, only the first three registers in the PM3390 PM3390 (CMIF registers 0x00, 0x01, and 0x02) are 32-bit registers: reads and writes to registers outside of these three registers only treat 16-bits as valid. For 16 40 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX bit register reads, the upper 16 bits of the EXACT data field are returned zero. 8.9.2 External Microprocessor Interface and CMIF accesses The External Microprocessor Interface consists of 16 multiplexed address and data lines, an ALE line and active low read and write lines. The interface conforms to the Intel 80186 bus protocol timing specification. Access to all PM3390 PM3390 CRI registers is provided through the interface. In addition, the interface provides a limited interface to the EXACT bus through the Message Box feature. To read and write registers using the interface, the 16 bit register address is first placed on the AD lines and the ALE is strobed high. For a read access, the MI_RD line is brought low to enable output of the register data. For a write access, the 16 bit write data is placed on AD lines and the MI_WR line is strobed low. See the External Microprocessor timing diagram in the Functional Timing section. Most CRI registers are directly accessible through the interface by using the register address. The only exception is reading and writing of the Destination Lookup Table (DLT) registers. The DLT is accessed using the DLT CRI Control Register, DLT CRI Status Register and DLT CRI Write Register. 8.9.3 Avoiding conflict for CRI register accesses The external microprocessor is given priority use of the CRI bus. If an EXACT control message and the external microprocessor simultaneously attempt a CRI operation, the EXACT control operation will be lost. Remote agents must synchronize their accesses to avoid register access conflicts. The internal logic does not arbitrate between the two possible consumers during CRI bus accesses (external CPU versus EXACT bus message receive over the XIB input buffer) and indeterminate results will occur if two consumers are attempting a CRI bus access. The restriction on not allowing simultaneous access of internal device registers extends to the eight EXACT Bus receive ports. For example, if EXACT Control register read messages are received on the same cycle on all eight ports, only the message received on one of the eight ports will be accepted and processed as a register read; the messages from the other seven ports will be discarded by the EXACT bus input buffer (this discard allows traffic to continue to be received on all ports so that there is not 41 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX traffic blocking). The selection between receive ports is based strictly by port number, with port 0 having the highest priority and port 7 the lowest. To summarize: 1. CRI register access conflict must be avoided for proper PM3390 PM3390 device operation 2. It is up to the system's engineer to externally restrict simultaneous accesses of internal device registers. 8.9.4 EXACT Bus Control and Status Message Processing The CMIF responds to EXACT register read and write control messages (Ref. PMC-970215 PMC-970215). The PM3390 PM3390 only accepts as valid Control messages a subset of the Control Message type specified in the EXACT bus specification: i Valid EXACT Control message accepted by the PM3390 PM3390 if and only if (1) the 4 bit EXACT control message type is 4'b 1000; (2) the REG bit field is a 1. If the above condition for a valid Control message is not met (for example, if the REG bit field is a 0, which would indicate a memory control read/write) the message will be directed to the Message Box receive FIFO. Read control messages are issued to cause the target device (in this case the PM3390 PM3390) to read the specified data from its internal registers or local memory (and return the results using a single status message), and are formatted as follows: 7 6 5 4 3 2 1 0 Delimiter (8) HOPCOUNT (8) TYPE (4) CTRL (2) DEST (2) DEST (8) READSIZE (6) SRC (2) SRC (8) ADDRESS[0] (8) ADDRESS[1] (8) ADDRESS[2] (8) Note that all three of the address bytes are required, as per the EXACT bus specification, even though the least significant byte (ADDRESS[2]) is not used. 42 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX Write control messages, are issued by external EXACT devices to cause the PM3390 PM3390 to update the contents of internal registers. Three of these bytes must be used as the address of the register accessed (in the same manner as a read). Write control messages are formatted as: 7 6 5 4 3 2 1 0 Delimiter (8) HOPCOUNT (8) TYPE (4) CTRL (2) DEST (2) DEST (8) Reserved (6) SRC (2) SRC (8) ADDRESS[0] (8) ADDRESS[1] (8) ADDRESS[2] (8) DATA[0] (8) DATA[1] (8) DATA[2] (8) DATA[3] (8) The HOPCOUNT field controls message lifetime: the PM3390 PM3390 does not process this field. The 4-bit TYPE field contains 1000 binary, while the 2bit CTRL field is divided up as follows: 1 0 REG R/W The EXACT bus specification states: "The REG bit indicates, if set, that the least-significant 16 bits of the ADDRESS field of the message should be interpreted as the index of an on-chip register; otherwise, all 24 bits of the ADDRESS field should be taken as containing a 24-bit local memory address instead". As noted earlier, the PM3390 PM3390 will only accept Control Register messages so if the REG bit is a 0 the message will be sent to the Message Box receive FIFO. If set, the R/W bit signifies that a read operation is being performed (i.e., this is a read control message), and a write operation otherwise. The 10-bit DEST field identifies the EXACT-ES or EXACT-IS device (and possibly the port) at which the message is aimed, while the SRC field gives the index of the entity issuing the control message. Note that in the case of a read control message the SRC field will be used to determine where the data being read will be sent. Since the PM3390 PM3390 only accepts a Control Write Register message the number of DATA bytes that are part of the message is fixed to be 4. For accesses to the three CMIF registers that are defined to be 32-bit quantities (CMIF register addresses 0x00-0x02), the 32-bit value write 43 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX data is: write_data[31:0] = {DATA3, DATA2, DATA1,DATA0}. For all other register accesses, DATA[3] and DATA[2] are not used and the 16-bit write data is: write_data[15:0] = {DATA1,DATA0}. From the above discussion, it can be seen that EXACT Control Register messages as received by the PM3390 PM3390 will be 8 bytes in length for a read and 12 bytes in length for a write (with the Delimiter character not included in this length computation). EXACT Control Message Register Reads The CMIF creates an EXACT Status message in response to receiving a Control Register Read message. 7 BYTE 0 BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 BYTE 7 BYTE 8 BYTE 9 BYTE 10 BYTE 11 6 5 4 3 2 1 0 HOPCOUNT (8) 4'b1001 2'b11 DEST (2) DEST (8) Reserved (6) SRC (2) SRC (8) ADDRESS[0] (8) ADDRESS[1] (8) ADDRESS[2] (8) REGISTER VALUE [7:0] REGISTER VALUE[15:8] REGISTER VALUE [23:16] (all zeros for 16 bit registers) REGISTER VALUE [31:24] (all zeros for 16 bit registers) Table 1. Status Response message The HOPCOUNT byte is always set to 255 for Status Response messages. The 10 bit DEST field contains the address of the device which originated the register read control message. The 10 bit SRC field contains the PM3390 PM3390 DeviceAddress. This Control Read status EXACT message is returned on the Transmit port corresponding to the port it was received on (the only exception is for broadcast messages). EXACT bus Control Read messages can be generated at a higher rate than the PM3390 PM3390 can provide Status response messages. The CMIF has a 256 byte input FIFO to hold messages that have been received via any of the eight EXACT bus receive ports. The approximate rate at which 44 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX Control Read messages can be processed by the PM3390 PM3390 before the CMIF input FIFO fills is 25% of the available EXACT bus bandwidth (25% utilization could be the 8-byte Control register Read message followed by 24-bytes of either IDLES or normal traffic). If the CMIF input FIFO should fill, any messages that would normally be written to it would be discarded and there will be no external visibility that this condition occurred. In all cases, the EXACT bus receive ports will continue processing EXACT messages. 8.9.4.2 EXACT Control Message Register Writes EXACT bus Control Write messages can be generated at a higher rate than the PM3390 PM3390 can process the message. The approximate rate at which Control Write messages can be processed by the PM3390 PM3390 before the CMIF input FIFO fills is 25% of the available EXACT bus bandwidth (25% utilization could be the 12-byte Control register Write message followed by 20-bytes of either IDLES or normal traffic). If the CMIF input FIFO should fill, any messages that would normally be written to it would be discarded and there will be no external visibility that this condition occurred. In all cases, the EXACT bus receive ports will continue processing EXACT messages. 8.9.4.3 EXACT Broadcast Message Processing EXACT messages that have a 10-bit EXACT bus Destination Address that is equal to the configurable 10-bit BroadcastPortAddress (CRI register 0x0003) are interpreted as a broadcast message. The format of the EXACT Control message is independent of whether it is a broadcast or not and must adhere to the message format outlined above. A Control Register Read or Write message may also be a broadcast message. In this case, the control message is executed and then written to the Transmit FIFO to be processed like any other broadcast message. Broadcast messages are sent to all of the eight possible transmit ports that have the corresponding enable bit set in CMIF register 0x05. 8.9.5 Broadcast Hold-off Timer The CMIF contains a programmable timer that begins to decrement when a broadcast message transmission begins. While the timer value is greater than zero, reception of broadcasts on the XIB rings is disabled. 45 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX This feature provides a mechanism for preventing broadcast feedback loops on the network. To program the desired timeout period, the BCTIMEOUT register is written with the desired value. The timeout time period is equal to (SYSCLK period * BCTIMEOUT). 8.9.6 Message Box Feature As mentioned earlier, EXACT bus traffic that has a destination address of the PM3390 PM3390 DeviceAddress value and which does not meet the criteria specified for the PM3390 PM3390 EXACT bus Control Register message will be written to the Message Box Receive buffer. The Message Box feature provides a low bandwidth interface between the EXACT bus and the PM3390 PM3390's external microprocessor interface. If the Message Box receive buffer should fill, a message that would normally be written to that buffer would be dropped. This condition is externally visible to the user via CMIF register 0x11 (Message Box status register). Under no condition is the EXACT bus receive port blocked. 46 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 9 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX SYSTEM OPERATION 47 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX This section provides a description of the PM3390 PM3390 system operation. 48 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX 49 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 9.1 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX Configuration and Initialization 9.1.1 Configuration Several control registers within the device must be configured at reset for the device to operate properly. These are configured via pin-straps on the EXPIF data ports. On reset, the internal drivers of these ports will be tristated allowing the values from the pins to propagate to the control registers. There are 36 data pins that can be used to program various registers. One must be used to configure the device for 16 x 16 versus 8 x 8 mode. Another eight pins will be used to select the output frequency for each of the XOBs. The other 35 can be used to program the device index and any other mode registers. See the EXACT Bus Protocol Specification for more system details on device discovery and initialization. Pins used for pinstrap Internal Signal Description EX1RX[0],EX0RX[8:0] PM3390 PM3390 EXACT Base Address for the PM3390 PM3390 device; Base Address PM3390 PM3390 will respond to EXACT messages to this address. EX1RX[2:1] EXACT Ring 0 Clockmode Selects the output mode for the PM3390 PM3390 TX port. Choices are 00-SERDES 00-SERDES, 01- 8B/10B 8B/10B Encoded Mode; 10- Clear Channel Mode; 11Reserved: do not use. EX1RX[4:3] EXACT Ring 1 Clockmode Selects the output mode for the PM3390 PM3390 TX port. Choices are 00-SERDES 00-SERDES, 01- 8B/10B 8B/10B Encoded Mode; 10- Clear Channel Mode; 11Reserved: do not use. EX1RX[6:5] EXACT Ring 2 Clockmode Selects the output mode for the PM3390 PM3390 TX port. Choices are 00-SERDES 00-SERDES, 01- 8B/10B 8B/10B Encoded Mode; 10- Clear Channel Mode; 11Reserved: do not use. EX1RX[8:7] EXACT Ring 3 Clockmode Selects the output mode for the PM3390 PM3390 TX port. Choices are 00-SERDES 00-SERDES, 01- 8B/10B 8B/10B Encoded Mode; 10- Clear Channel Mode; 11Reserved: do not use. 50 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX EX2RX[1:0] EXACT Ring 4 Clockmode Selects the output mode for the PM3390 PM3390 TX port. Choices are 00-SERDES 00-SERDES, 01- 8B/10B 8B/10B Encoded Mode; 10- Clear Channel Mode; 11Reserved: do not use. EX2RX[3:2] EXACT Ring 5 Clockmode Selects the output mode for the PM3390 PM3390 TX port. Choices are 00-SERDES 00-SERDES, 01- 8B/10B 8B/10B Encoded Mode; 10- Clear Channel Mode; 11Reserved: do not use. EX2RX[5:4] EXACT Ring 6 Clockmode Selects the output mode for the PM3390 PM3390 TX port. Choices are 00-SERDES 00-SERDES, 01- 8B/10B 8B/10B Encoded Mode; 10- Clear Channel Mode; 11Reserved: do not use. EX2RX[7:6] EXACT Ring 7 Clockmode Selects the output mode for the PM3390 PM3390 TX port. Choices are 00-SERDES 00-SERDES, 01- 8B/10B 8B/10B Encoded Mode; 10- Clear Channel Mode; 11Reserved: do not use. EX3RX[6:0], EX2RX[8] EXACT TX Clk Frequency Selects the output clock multiplexer setting used by a given TX port. 0- select XREFCK125 XREFCK125 input as clock reference, 1- select XREFCK135 XREFCK135 as the clock reference. Pin strap EX2RX[8] TX port 0 EX3RX[0] TX port 1 EX3RX[1] TX port 2 EX3RX[2] TX port 3 EX3RX[3] TX port 4 EX3RX[4] TX port 5 EX3RX[5] 51 TX port clock select TX port 6 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX EX3RX[6] TX port 7 EX3RX[7] Expansion Mode Select Enables the PM3390 PM3390 Expansion Interface (EXPIF). 1-on, 0-off. See also CMIF register 0x01, Device Control Register, Expansion Interface Mode bits. EX3RX[8] Device Subtype This bit must be initialized to a logic 0 for proper device operation. 9.1.2 Initialization After de-assertion of the RESETI input, the following will occur: 1. Logic internal to the device goes through an initialization sequence that takes 1024 SYSCLK cycles to complete. One result of the initialization is that all 1024 DLT table entries will have the value of 4'b1000: that is, the DISCARD bit will be set on each entry of the table. 2. Each of the eight EXACT bus input receivers must synchronize. The process followed for synchronization is described in the register description for the SYNCH_CNT_MIN register (XIB register 0x09). 52 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 9.2 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX Destination Lookup Table The Destination Lookup Table (DLT) is used to map the logical ports of an EXACT system to the physical ports of the PM3390 PM3390. The DLT is accessed in one of two ways: (1) over the external microprocessor interface by accessing the DLT CRI Control Register, DLT CRI Status Register, and the DLT CRI Write Register; (2) over the EXACT bus by doing Control Register reads/writes to addresses in the range 0x1000 to 0x13FF. The DLT table supports 1024 entries: this is one entry per allowable EXACT logical port address (or port index). Each entry in the table has the following format: Bit 0 Bit 3 Bit 2 Bit 1 DISCARD TX_PortNum FIGURE 3 Bitfield of a DLT Entry DISCARD is set to logic 0 for addresses which are mapped within the system. The lower 3 bits of the 4 bit DLT entry indicate the TX port number to which all non-broadcast traffic will be sent. The assignment of Destination Addresses is a higher-level system implementation detail and is outside the scope of this document. The DLT is a logically a simple look-up table with the DEST[9:0] field of the EXACT message used as the address of the look-up table. The DISCARD bit is set to logic 1 for system addresses that are unmapped. When an EXACT receive port on the PM3390 PM3390 (XIB) receives a message with an unmapped address, the DLT entry is returned with DISCARD = 1 and the XIB will discard (that is, filter) the entire message. The DLT lookup is not used for these two exceptional cases of the destination address as has been previously discussed: 1. EXACT messages addressed to the EXACT system broadcast address (which is 0x3FF). 2. The destination address of the message is exactly equal to the DeviceAddress[9:0] in CRI register 0x0000. All EXACT messages that bypass the DLT lookup are forwarded to the CMIF logic. 53 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX 9.2.1 DLT Write Operation via the External Microprocessor Interface Access to the DLT through the external microprocessor interface uses the following three CRI registers: CRI register address Register Description 0x000B DLT CRI Status 0x000C DLT CRI Control 0x000D DLT CRI Write The following sequence is used to perform a DLT write operation using the external microprocessor interface: 1. Prior to performing DLT Writes, read the DLT Status Register to verify that bits 15:14 (Write:Read Done) are both set, indicating that any previous DLT writes and reads have completed. 2. Write the 4 bit value to bits [3:0] of the DLT CRI Write Register. 3. Write the 10 bit table address to bits [9:0] of the DLT CRI Control Register with bit 15 cleared. The following example in psuedo-code shows how to write a value of 4'h6 to DLT address 10'h239: 1. If (Cpu_read(0x000B) & 0xC000), go to step 2. 2. Cpu_write(0x000D, 0x0006) 3. Cpu_write(0x000C, 0x0239) Where the operators are: cpu_read(cri_register_address[15:0]), cpu_write(cri_register_address[15:0], data[15:0]). 9.2.2 DLT Read Operation via the External Microprocessor Interface The following sequence is used to perform a DLT read operation using the external microprocessor interface: 1. Prior to performing DLT Writes, read the DLT Status Register to verify that bits 15:14 (Write:Read Done) are both set, indicating that any previous DLT writes and reads have completed. 2. Write the 10 bit EXACT Port Address to bits [9:0] of the DLT CRI Control Register with bit 15 set. 54 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX 3. Poll the DLT CRI Status Register by reading until bit 14 (Read Done) is set, indicating that the read data in bits [3:0] of the register is valid. The following example in psuedo-code shows how to read a value from DLT address 10'h1C7: 1. If (Cpu_read(0x000B) & 0xC000), go to step 2. 2. Cpu_write(0x000C, 0x81C7) 3. If (Cpu_read(0x000B) & 0x4000), then DLT read is valid and the table entry was returned on bits [3:0] of the read. Where the operators are: cpu_read(cri_register_address[15:0]) cpu_write(cri_register_address[15:0], write_data[15:0]). 9.2.3 DLT access over the EXACT bus A different mechanism is used for allowing access to the Destination Lookup Table over any of the eight EXACT system ports. The DLT table is directly mapped to the CRI register space, with 0x1000 being the base address of the table and 0x13FF being the last address in the table. Standard EXACT message Control Register reads and writes are issued by the external EXACT-compatible device to setup and maintain the DLT table. 9.2.4 Avoiding simultaneous DLT register access As previously stated, to ensure reliable access to PM3390 PM3390 internal registers from the various EXACT bus input ports (0 through 7) simultaneous accesses must be avoided. One simple means of doing this is to allow only one of the possible nine consumers that can read/write the DLT table access to it: for example, only allow register access to the DLT through the external microprocessor interface and not in-band over the EXACT receive ports 0-7. A second example would be to allow access to the DLT solely through EXACT receive port 0 and not through ports 1-7 or the external microprocessor interface. 55 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 9.3 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX Statistics Counters The XIB and XOB contain counters that are readable either in-band (that is through the EXACT bus interface via Control Register reads) or by an external microprocessor. These counters maintain the number of EXACT messages and bytes that have been sent and received, the number of erred messages received, and the capacity of the Free List Manager. Refer to the normal mode register description for details on these registers. 9.3.1 Non-EXACT Flow Control There are two methods for implementing flow control in non-EXACT systems that source traffic through a PM3390 PM3390. The EXACT protocol is a fully reserved protocol that "pulls" packets from the egress to the ingress. Storage within the PM3390 PM3390 is guaranteed when using the EXACT link protocol. It is possible for systems, which use proprietary protocols to "push" packets through the PM3390 PM3390, to oversubscribe the storage and may require flow control to be implemented to prevent overflow. x Global CCS storage threshold to prevent overflow x PM3390 PM3390 per port status to provide flow control information for external non-EXACT systems Global CCS storage threshold to prevent overflow With the first method, the XOB receives a signal from the Free List Manager (FLM) indicating if the Cell Central Store capacity has reached a programmable threshold. Once this threshold has been reached, the XOB will send out BUSY characters instead of IDLE characters between messages. This mechanism can be used to prevent overflow of the CCS memory in systems that do not issue traffic according to the EXACT Bus Protocol specification. The global CCS storage threshold based flow control mechanism is very coarse grained and can only be used to prevent CCS overflow. In nonEXACT systems a finer grained flow control mechanism can be used to provide per port flow control information. The device register to set the global CCS storage threshold is FLM register 0x02, XOB Busy Threshold. 56 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX PM3390 PM3390 per port status to provide flow control for non-EXACT systems Per port flow control can be implemented by a non-EXACT system by using status information from the PM3390 PM3390. During normal operation, the four NFLOW pins of the PM3390 PM3390 cycle through an eight clock sequence that can be sampled to provide flow control information to traffic sourcing devices in non-EXACT systems. The following table shows that eight clock sequence: Clock Data Sampled Description On NFLOW[3:0] 1 0000 Synchronization Pattern 0 2 0000 Synchronization Pattern 1 3 0000 Synchronization Pattern 2 4 0000 Synchronization Pattern 3 5 0000 Synchronization Pattern 4 6 FLOW[7:4] Flow control information for sourcing devices on EXACT Rings [7:4]; this signal is active low: 0-Device BUSY, 1- Device IDLE 7 FLOW[3:0] Flow control information for sourcing devices on EXACT Rings [3:0]; this signal is active low: 0-Device BUSY, 1- Device IDLE 8 1111 Framing Pattern 1 It is the CLM register 0x14, Flow Control Threshold, that is used to set the threshold reported as FLOW[7:0] and which is output from the PM3390 PM3390 on the NFLOW[3:0] device pins. The CLM register 0x14 bits [9:0] are "FCDEPTH[9:0]". The FLOW[N] output is logically equal to: FLOW[N] = !(number of cells queued for output port N > FCDEPTH) 57 PM3390 PM3390 PRELIMINARY DATASHEET PMC-971034 PMC-971034 9.4 ISSUE 4 8 PORT EXACT BUS SWITCHING MATRIX Expandability Interface The Expandability Interface (EXPIF) provides th