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Part : PPLX-9VB-2AA Supplier : Pactec Enclosures Manufacturer : Newark element14 Stock : - Best Price : $10.81 Price Each : $12.25
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PLX9054

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: EEPROM PLX9054 PCI to local bus interface Local bus control JTAG header Address and data bus , includes a CPLD for configuring ISP1760 control signals and has three host ports. PLX9054 PCI to , Production-quality host stack · Programming guide, user manual, schematics Evaluation board PLX9054 PCI to , PLX9054 PCI to local bus interface Local bus control JTAG header PCI bus (on PC) Address and , board EEPROM PLX9054 PCI to local bus interface Local bus control JTAG header Address and ST-Ericsson
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ISP1763 PEX8111 pc motherboard schematics plx9054 vhdl code pci schematics isp1763a ISP110 ISP111 ISP1110 HBCC16 ISP1302 HVQFN24
Abstract: PC) reference board address/data EEPROM PLX9054 PCI to local bus interface local bus , Production-quality host, address/data control peripheral, OTG stacks EEPROM PLX9054 PCI to local bus interface , EEPROM PLX9054 PCI to local bus interface printer applications - DOS-based OTGC stack address & , controller operation. PLX9054 PCI to local bus interface USB (host) address/ data ISP1761 , ISP1761 PCI/Linux reference kit PLX9054 PCI to local bus interface USB (host) address/ data Philips Semiconductors
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CP2147 ISP1161A rs232 card isa slot scheme ide to usb converter circuit diagram D12Test printer circuit usb board diagram ISP1504 ISP1505 ISP1506 ISP1301 ISP1362 ISP1520
Abstract: board address/data EEPROM PLX9054 PCI to local bus interface local bus control JTAG header , Class driver unnecessary). PCI bus (on PC) evaluation board address/data EEPROM PLX9054 PCI , control PLX9054 PCI to local bus interface local bus control JTAG header handhelds PCI bus , board PLX9054 PCI to local bus interface PCI bus ISP1761 PCI/Linux OTG evaluation kit , Programming guide, user manual, schematics PLX9054 PCI to local bus interface USB (host) data NXP Semiconductors
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ISP1703 ISP1702 ISP1161A1 ISA DOS evaluation kit isa bus schematics PDIUSBD12 Mass Kit isp1160 ISP10 ISP102 ISP101 ISP12 ISP11 ISP1109
Abstract: Physical description UM0865 The 93LC56C EEPROM is required for the correct initialization of PLX9054. , 3.4.2 PLX9054 and 93LC56C EEPROM 16 3.4.3 Xilinx XC3S500E 17 4 Schematics 18 , PLX9054 EEPROM PCI CONNECTOR Figure 1 Block diagram of the ISP1763A PCI evaluation board Key , is only for using the logic analyzer. Probe debug signals between FPGA and PLX9054 communication , Specification Ver. 2.2. All PCI signals are connected to PLX9054 PCI-to-local bus I/O accelerator chip ST-Ericsson
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gigabyte ga-945gzm-s2 circuit diagram transistor ld12 SMD transistor LD3 GA-945GZM-S2 GIGABYTE 945GZM-S2 smd LD9 CD00257207 74LVT244BPW 20-TSSOP SPXO018044 TFM-135-32-S-D-A TFM135-32-S-D-A
Abstract: Lint# ISP1161x Address and Data Bus PLX9054 PCI IC Configuration Signals Local Bus , *-* The PLX9054 project is a design which implements glue logic between PLX9054 and ISP1161 *- , *-library ieee; use ieee.std_logic_1164.all; entity plx9054 is port ( -* PLX9054 clk reset_n ads_n , data data_tmp -* ISP1161 cs_n rd_n wr_n dack1_n dack2_n eot_n a_sel int ); end plx9054 , command port for accessing data port interrupt architecture rtl of plx9054 is signal a0_delay Philips Semiconductors
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UM10006 ISP1161A1 ld25 cv PC19054 NFM40P HC-49 crystal R58 B48
Abstract: Evaluation Board Block Diagram Loacal Bus Interrupt Lint# ISP1362 Address and Data Bus PLX9054 , *-* The PLX9054 project is a design which implements glue logic between PLX9054 *-* and ISP1362 , *-library ieee; use ieee.std_logic_1164.all; entity plx9054 is port ( -* PLX9054 interface clk : in , ); -int : in std_logic_vector(2 downto 1) -); end plx9054; system clock system reset PLX address , data port interrupt architecture rtl of plx9054 is - synchronous PLX interface signal signal Philips Semiconductors
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pci9054-ab50pi 4U7F 25V philips ISP1362 SMD transistor code wrn 74hct00d smd diode S5 UM10009-02 M93C56BN6 LM1117DT33 PCI9054AB50PI EPM7064AETC100-10 MAX6306UK30D2
Abstract: # ISP1161 Address and Data Bus PLX9054 PCI IC Configuration Signals Local Bus Control Signals , *-* The PLX9054 project is a design which implements glue logic between PLX9054 and ISP1161 *- , *-library ieee; use ieee.std_logic_1164.all; entity plx9054 is port ( -* PLX9054 interface clk : in , (2 downto 1) - ISP1161 interrupt ); end plx9054; architecture rtl of plx9054 is - synchronous , PCI_GNT_L PCI_RST_L PCI_INTA_L HEADER 1 1 JP12 PLX9054 with PCI Connector PCI_AD0 Philips Semiconductors
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PCI9054-PQFP176 B34 SMD Transistor 742-08-3-103-J-XX B49 diode smd ISP1611 smd transistor 2x5 UM10006-01 EPM7064AE-4 MAX6306UK30D1-T
Abstract: Data Bus PLX9054 PCI IC Configuration Signals Local Bus Control Signals ADS#, BLAST#, LW/R , *-* The PLX9054 project is a design which implements glue logic between PLX9054 and ISP1362 *- , *-library ieee; use ieee.std_logic_1164.all; entity plx9054 is port ( -* PLX9054 interface clk : in , int : in std_logic_vector(2 downto 1) - ISP1362 interrupt ); end plx9054; architecture rtl of plx9054 is signal signal signal signal signal signal a0_delay a1_delay disable_PCI_int Philips Semiconductors
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smd code book a56 transistor X2 diode zener smd code book a7 transistor LA2 DS2 smd transistor b35 ip4058 UM10009
Abstract: Evaluation Board Block Diagram Loacal Bus Interrupt Lint# ISP1362 Address and Data Bus PLX9054 , *-* The PLX9054 project is a design which implements glue logic between PLX9054 *-* and ISP1362 , *-library ieee; use ieee.std_logic_1164.all; entity plx9054 is port ( -* PLX9054 interface clk : in , ); -int : in std_logic_vector(2 downto 1) -); end plx9054; system clock system reset PLX address , data port interrupt architecture rtl of plx9054 is - synchronous PLX interface signal signal Philips Semiconductors
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TRANSISTOR SMD a43 B56 smd transistor SmD TRANSISTOR a45 SmD TRANSISTOR a42 smd transistor guide book SmD TRANSISTOR a41 F/16V ZVP2106/TO FDS9431A
Abstract: (BADDR2+0x4001004) in FPGA to "1". Set bit11 and bit8 of ISTCSR register (BADDR0+0x68) in PLX9054 to "1". The interrupt status are seen by the below registers. - Bit15 of INTCSR register in PLX9054. If , of PLX9054 Reserved Daughter Board and FPGA Area Reserved The memory map of BADDR2 is the below Fujitsu
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MB8629XEB01 MB8629X 93CS56L AVD7120 0x4001004 vpo5 av9173-01 V832
Abstract: , PLX9054 PCI-to-local bus bridge, SRAM, and serial EEPROM on board. The PC1 Mass Storage kit can connect , converts the PLX9054 local bus to the ISP1582 generic processor bus. The PLX9054 converts PCI access to , The Xilinx XCS30XL translates the PLX9054 PCI bridge local bus to the ISP1582 generic processor bus Philips Semiconductors
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PCI9054 plx 9054 fpga dma vhdl header 17x2 Xilinx Spartan 6 Eval Kit pci9054 fpga plx9054 ieee.std_logic_1164.all JTAG header 14 UM10040
Abstract: on PCI. On these boards are the ISP1582, Xilinx® XCS30XL, Xilinx XC17S30XL serial PROM, PLX9054 , converts the PLX9054 local bus to the ISP1582 generic processor bus. The PLX9054 converts PCI access to , SPARTAN XCS30XL The Xilinx XCS30XL translates the PLX9054 PCI bridge local bus to the ISP1582 generic Philips Semiconductors
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CONN PCB 17x2 LD11 plx 9054 isp1583 plx9054 spartan ISP1561 UM10036 ISP1582/83
Abstract: PLX9054 with PCI Connector Number Revision A2 Date: File: 1 2 3 4 5 6 7 15 Philips Semiconductors
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PHP109 A143 crystal PCICONUNV PCI-AD14 PCI-AD12 LA15
Abstract: interfaced to PCI bridge PLX9054. In the Windows CE software, macro PLX9054 is defined in file ST-Ericsson
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an10054 ISP176x usb analyzer card circuit AN10055 Suspend and wake-up LQFP128 AN10054 ISP1760/1 ISP176 CD00222786
Abstract: ISP176x host controller PCI card, the ISP176x host controller is interfaced to PCI bridge PLX9054. In the Windows CE software, the macro PLX9054 is defined in file ISP1761HCDConfig.h. By defining this macro, the NXP Semiconductors
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40328 isp1761 an10055 IP4359 an100
Abstract: ISP176x Host Controller PCI card, the ISP176x Host Controller is interfaced to PCI bridge PLX9054. In Windows CE software, macro PLX9054 is defined in file ISP1761HCDConfig.h. By defining this macro, the NXP Semiconductors
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AN10053
Abstract: xc9572xl-tq100- PAD60CIR36D XC9572XL-TQ100 1 198mW SSF-LXH5174 3.3 80mA 2 528mW PLX9054 3.3 200mA 660mW 2109mA PMC-Sierra
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plx vhdl code transistor smd bc rn 100LVEL14 PCI9054-AA50PI xc9572xl pin configuration SMD TN12 PM5372 PMC-1991247 PMC-991247 PMC-990713
Abstract: R56-R61 c2237 96F8740 1410G6 xc95216pq160 PHY_SEL[1.0] IFCLK OFCLK SSRAM 128Kx36 PLX9054 I/O ACCELERATOR UL2/PL2 BUS SLAVE PCI PMC-Sierra
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PM5351 PLX9050 C143 ESP C144 ESP smd code STPA 3F6 smd rn90 S/UNI-155-TETRA PMC-1991709 S/UNI-155 PMC-1971240
Abstract: 12B2 Zener zener 11B1 ZENER Diode 12B2 12a2 zener diode 12B1 ZENER zener 11a2 zener 10B2 zener 12B2 zener 12a2 zener 9A2 1.8V REG & HOT SWAP CONTROLLER RWSEL PECLTTL Converter SYSCLK1 SYSCLK2 PLX9054 I/O PMC-Sierra
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5B2 bridge rectifier ic 10b2 zener diode zener 10B1 5b1 bridge rectifier ic 93cs66l MUX2-b PM7390 MACH48 PMC-2000207 S/UNI-MACH48 PMC-1990823
Abstract: through the PLX9054 bridge. If porting to other hardware platforms, add interrupt number MemBase and Philips Semiconductors
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0x0060h p1761hcd AN10052
Abstract: # ISP1161 Address and Data Bus PLX9054 PCI IC Configuration Signals Local Bus Control Signals , *-* The PLX9054 project is a design which implements glue logic between PLX9054 and ISP1161 *- , *-library ieee; use ieee.std_logic_1164.all; entity plx9054 is port ( -* PLX9054 interface clk : in , (2 downto 1) - ISP1161 interrupt ); end plx9054; architecture rtl of plx9054 is - synchronous , PCI_GNT_L PCI_RST_L PCI_INTA_L HEADER 1 1 JP12 PLX9054 with PCI Connector PCI_AD0 -
OCR Scan
optocoupler substitute book hcpl3700 HCPL-3700-300 HCPL-3700 VMICPCI-1120 800-240-SRVC
Abstract: Evaluation Board Block Diagram Loacal Bus Interrupt Lint# ISP1362 Address and Data Bus PLX9054 , *-* The PLX9054 project is a design which implements glue logic between PLX9054 *-* and ISP1362 , *-library ieee; use ieee.std_logic_1164.all; entity plx9054 is port ( -* PLX9054 interface clk : in , ); -int : in std_logic_vector(2 downto 1) -); end plx9054; system clock system reset PLX address , data port interrupt architecture rtl of plx9054 is - synchronous PLX interface signal signal -
OCR Scan
logo PLC cables pin diagram siemens 10B5 triac burst control ic PLC siemens LOGO pi controller siemens logo manual fuses fast VMICPCI-2140
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