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Part Manufacturer Description PDF Type Ordering
PLL502-37 PhaseLink 750kHz - 800MHz Low Phase Noise Multiplier VCXO
ri

9 pages,
251.67 Kb

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PLL502-37OC PhaseLink 750kHz - 800MHz Low Phase Noise Multiplier VCXO
ri

9 pages,
253.22 Kb

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PLL502-37OCL PhaseLink 750kHz - 800MHz Low Phase Noise Multiplier VCXO
ri

9 pages,
253.22 Kb

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PLL502-37OCL-R PhaseLink 750kHz - 800MHz Low Phase Noise Multiplier VCXO
ri

9 pages,
253.22 Kb

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PLL502-37OC-R PhaseLink 750kHz - 800MHz Low Phase Noise Multiplier VCXO
ri

9 pages,
253.22 Kb

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PLL502-37QC PhaseLink 750kHz - 800MHz Low Phase Noise Multiplier VCXO
ri

9 pages,
253.22 Kb

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PLL502-37QCL PhaseLink 750kHz - 800MHz Low Phase Noise Multiplier VCXO
ri

9 pages,
253.22 Kb

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PLL502-37QCL-R PhaseLink 750kHz - 800MHz Low Phase Noise Multiplier VCXO
ri

9 pages,
253.22 Kb

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PLL502-37QC-R PhaseLink 750kHz - 800MHz Low Phase Noise Multiplier VCXO
ri

9 pages,
253.22 Kb

Original Buy
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Catalog Search Results

Catalog Datasheet Results Type PDF Document Tags
Abstract: is VDD, pin 11 is GND. However, PLL502-37/-39 have SEL0 (pin 10), and pin11 is VDD. See pin , PLL502-35 PLL502-35 (PECL with inverted OE), PLL502-37 (CMOS), PLL502-38 PLL502-38 (PECL), and PLL502-39 PLL502-39 (LVDS) are high , 155.52MHz, 110dBc/Hz for 622.08MHz). CMOS (PLL502-37), PECL (PLL502-35 PLL502-35 and PLL502-38 PLL502-38) or LVDS (PLL502-39 PLL502-39 , by-pass PLL502-3x OUTPUT ENABLE LOGICAL LEVELS Part # PLL502-38 PLL502-38 PLL502-35 PLL502-35 PLL502-37 PLL502-39 PLL502-39 , levels for PLL502-37/-39 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510 ... Original
datasheet

9 pages,
197.15 Kb

PLL502-39 PLL502-38 PLL502-37 PLL502-35 155.52MHZ vcxo PLL502-35/-37/-38/-39 PLL502-35/-37/-38/-39 abstract
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Abstract: ) PLL502-37OC PLL502-37OC-R PLL502-37QC-R PLL502-37OCL PLL502-37OCL-R PLL502-37QCL-R P502-37OC P502-37OC , VCON XOUT VDD 5 CLKT GND The PLL502-35 PLL502-35 (LVPECL with inverted OE), PLL50237 (LVCMOS , 155.52MHz, -115dBc/Hz for 622.08MHz). LVCMOS (PLL502-37), LVPECL (PLL502-35 PLL502-35 and PLL502-38 PLL502-38) or LVDS , , PLL502-35/-38 PLL502-35/-38 do not have SEL0 available: Pin 10 is VDD, pin 11 is GND. However, PLL502-37/-39 have SEL0 , Part # PLL502-38 PLL502-38 PLL by-pass PLL502-3x PLL502-35 PLL502-35 PLL502-37 PLL502-39 PLL502-39 OE 0 (Default ... Original
datasheet

9 pages,
350.98 Kb

QFN-16L PLL502-39 PLL502-38 PLL502-37 PLL502-35 PLL502-37 abstract
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Abstract: ) TSSOP (Tape and Reel) 3x3 QFN (Tube) 3x3 QFN (Tape and Reel) PLL502-37OC PLL502-37OC-R PLL502-37QC PLL502-37QC-R PLL502-37OCL PLL502-37OCL-R PLL502-37QCL PLL502-37QCL-R P502-37OC P502-37OC P502-37OC P502-37OC , SEL0 available: Pin 10 is VDD, pin 11 is GND. However, PLL502-37/-39 have SEL0 (pin 10), and pin11 is , DIAGRAM 13 VCON XOUT GND The PLL502-35 PLL502-35 (PECL with inverted OE), PLL502-37 (CMOS , , -125dBc/Hz for 155.52MHz, -115dBc/Hz for 622.08MHz). CMOS (PLL502-37), PECL (PLL502-35 PLL502-35 and PLL502-38 PLL502-38 ... Original
datasheet

9 pages,
253.21 Kb

PLL502-39 PLL502-38 PLL502-37 PLL502-35QC PLL502-35OC-R PLL502-35OC PLL502-35 PLL502-35/-37/-38/-39 PLL502-35/-37/-38/-39 abstract
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Abstract: Video Input/Output Daughter Card User Guide UG235 UG235 (v1.2.1) October 31, 2007 R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recordin ... Original
datasheet

68 pages,
10496.11 Kb

rca TO VGA ic schematic diagram vga to rca cable ECJ-0EB1E102K vga to rca video pinout schematic diagram vga to composite vga to rca schematic schematic diagram vga to svideo schematic diagram video out vga how to wire vga to rca jacks rca TO VGA pinout VGA TO HDMI PINOUT UG235 UG235 abstract
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