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Part : PLL-11-Y2-2.5 Supplier : Panduit Manufacturer : Avnet Stock : - Best Price : - Price Each : -
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PLL11 Datasheet

Part Manufacturer Description PDF Type
PLL1100A Z-Communications PHASE LOCKED LOOP Original
PLL-11-Y2-2.5 Panduit Labels, Labeling, Computers, Office - Components, Accessories, LABEL LSR POLY WHITE 1 X.75" Original

PLL11

Catalog Datasheet MFG & Type PDF Document Tags

AK8140A

Abstract: PLL11 frequency Output State PLL1_0 or PLL1_1 PLL1_0 or PLL1_1 PLL1_0 or PLL1_1 PLL1_0 or PLL1_1 PLL1_0 or PLL1_1 PLL1_0 or PLL1_1 PLL1_0 or PLL1_1 PLL1_0 or PLL1_1 20h CLK2 Output State CLK3 Output State , ] 0 MDIVP1 [0] 0 PLL1_1 MDIV1 Setting PLL1_1 NDIV1 Integral Part Setting PLL1_1 NDIV1 Fractional Part , . Please set PLL parameter according to . PLL1 has two Frequency mode predefined as PLL1_0 or PLL1_1 and , frequency of PLL is chosen from two setups PLL1_0 and PLL1_1. FS1_x 0 1 PLL1 Frequency PLL1_0 Predefined by
Asahi Kasei Microdevices
Original
AK8140A PLL11 CLK30 230MH 16M-60MH 4M-100MH 160MH

FIN212AC

Abstract: FIN212ACGFX bit clock. MODES (1,2,3); PLL1=1,PLL0=0 (Divide-by-2) or PLL1=1,PLL0=1 (Divide-by-3) For some , (PLL1=1, PLL0=0) Multiplier x 3.5 Deserializer Configuration: Edge Rate Mode: SLOW MODE 1 (S1=1, S0 , =1 100 PLL1=1, PLL0=0 50 PLL1=1, PLL0=1 fSTRB MHz 331/3 % of fCKREF tCPWH
Fairchild Semiconductor
Original
FIN212AC FIN212ACGFX FIN212ACMLX MO-195 MO-220 13M-pixel 8/10-B

AN-5058

Abstract: AN-5061 bit clock. MODES (1,2,3); PLL1=1,PLL0=0 (Divide-by-2) or PLL1=1,PLL0=1 (Divide-by-3) For some , : MODE 1 (S1=0, S0=1) CKREF=26MHz STROBE Frequency = 10 MHz PLL Divide Mode: Divide-by 2 (PLL1=1, PLL0 , fSTRB PLL1=0, PLL0=1 100 PLL1=1, PLL0=0 50 PLL1=1, PLL0=1 fSTRB 100 33 /3 %
Fairchild Semiconductor
Original
AN-5058 AN-5061 DP10 FIN212ACBFX 337 BGA footprint 5M cmos camera
Abstract: ,3); PLL1=1,PLL0=0 (Divide-by-2) or PLL1=1,PLL0=1 (Divide-by-3) For some microcontroller applications , PLL Divide Mode: Divide-by 2 (PLL1=1, PLL0=0) Multiplier x 3.5 Deserializer Configuration: Edge , =0 fSTRB Strobe Frequency Relative to CKREF Frequency fCKREF fSTRB PLL1=0, PLL0=1 PLL1=1, PLL0=0 PLL1=1 Fairchild Semiconductor
Original

35x45mm

Abstract: 6X6 mlp ,3); PLL1=1,PLL0=0 (Divide-by-2) or PLL1=1,PLL0=1 (Divide-by-3) For some microcontroller applications , Frequency = 10 MHz PLL Divide Mode: Divide-by 2 (PLL1=1, PLL0=0) Multiplier x 3.5 Deserializer , =0 fSTRB Strobe Frequency Relative to CKREF Frequency fCKREF fSTRB PLL1=0, PLL0=1 PLL1=1, PLL0=0 PLL1=1
Fairchild Semiconductor
Original
35x45mm 6X6 mlp
Abstract: ,3); PLL1=1,PLL0=0 (Divide-by-2) or PLL1=1,PLL0=1 (Divide-by-3) For some microcontroller applications , =1) CKREF=26MHz STROBE Frequency = 10 MHz PLL Divide Mode: Divide-by 2 (PLL1=1, PLL0=0) Multiplier x 3.5 , =0 fSTRB Strobe Frequency Relative to CKREF Frequency fCKREF fSTRB PLL1=0, PLL0=1 PLL1=1, PLL0=0 PLL1=1 Fairchild Semiconductor
Original
Abstract: ,3); PLL1=1,PLL0=0 (Divide-by-2) or PLL1=1,PLL0=1 (Divide-by-3) For some microcontroller applications , PLL Divide Mode: Divide-by 2 (PLL1=1, PLL0=0) Multiplier x 3.5 Deserializer Configuration: Edge , fCKREF fSTRB PLL1=0, PLL0=1 PLL1=1, PLL0=0 PLL1=1, PLL0=1 tCPWH tCPWL tCLKT tSPWH/L tSTC tHTC CKREF DC Fairchild Semiconductor
Original

337 BGA footprint

Abstract: AN-5058 STROBE CLKCKREF 10MHzCLK70MHz 140Mbps (1,2,3)PLL1=1PLL0=02 PLL1=1PLL0=13 STROBE 2 , (S1=0, S0=1) CKREF=26MHz STROBE =10 MHz PLL 2 (PLL1=1, PLL0=0) x 3.5 MODE 1 (S1=1, S0=0) 13 , =1 fCKREF 18 10 28 MHz PLL1=0, PLL0=0 CKREF tCPWH tSPWH/L tSTC tHTC PLL1=1 , tCLKT 100 T=1/fCKREF CKREF DC tCPWL fCKREF fSTRB PLL1=0, PLL0=1 PLL1=1, PLL0
Fairchild Semiconductor
Original
32MLPJEDEC MO-2205 MO1953 FIN212AC1

PHKI

Abstract: PEÃ1E nPOME}KyTOHHblEflByxn03HL4l40HHblE PR-&: Pfl-9, Pll-11, PF1-12 O Bilí M E CÃEflEHHil Peíií npgnfleÃ"Ly-rc'HHbie flgyxnciJHmiPHHUç Tunçp Pfl-S. PII-II npçflH^SHâ-HÇHbi flna BKmoHSHUp p ueniíi nooTOHHHoro TOtía pene TtinciB PrVá¡ pn-12- e nenn nepewEHHnrci rana yacroTpw 50 n.nn GCH~u e ^ewecTee BcnownrgTenbHorn pene h cxeiwa* 3(3iuMTbi sMeprnc^CT&i'i Psne nweKji nQBbiLueHHyio ytfoSNmoriïk u ^exaHHHecunw snsaeñctb m n m li he n swehnun no n pm^hlki Koi-rrairrOfl n pu chwt^h hi* l- n n mc-ibïihcieiiÃ
-
OCR Scan
PHKI 03HL4 OB03HAHEHM

hand calculator

Abstract: HC210 Two PLL Outputs Source Register Source Clock CLK5 PLL11 Destination Register INBUF
Altera
Original
hand calculator HC210 HC220 HC230 HC240 calculator on chip UG-01015-1 PLL10
Abstract: â'" 8ns output edge rates (S1=1, S0=0) CKREF is twice as fast STROBE (PLL1=1; PLL0=0) ~50% CKP , 30 PLL1=0, PLL0=0 Strobe Frequency Relative to CKREF Frequency PLL1=0, PLL0=1 100 PLL1=1, PLL0=0 fCKREF ≠ fSTRB 94.7 50 PLL1=1, PLL0=1 fSTRB MHz 331/3 % of fCKREF Fairchild Semiconductor
Original
FIN210AC FIN210ACMLX FIN210ACGFX

13M-pixel

Abstract: 202 ball bga =0) CKREF is twice as fast STROBE (PLL1=1; PLL0=0) ~50% CKP PW,(PWS1=PWS0=0) CKREF=26MHz & STROBE , 28 PLL1=0, PLL0=0 Strobe Frequency Relative to CKREF Frequency PLL1=0, PLL0=1 100 PLL1=1, PLL0=0 fCKREF fSTRB 100 50 PLL1=1, PLL0=1 fSTRB MHz 331/3 % of fCKREF tCPWH
Fairchild Semiconductor
Original
202 ball bga dsi LCD driver DP1211 30 pin flex cable lcd ipc-SM-782 mobile camera interface microcontroller

AE31

Abstract: pll-11 VCCA_PLL11 VCCD_PLL11 VCC_PLL11_OUT IO CLK14p IO CLK14n IO CLK15p IO CLK15n IO PLL11_OUT0p IO PLL11_OUT0n IO PLL11_OUT1p IO PLL11_OUT1n IO PLL11_FBp/OUT2p IO PLL11_FBn/OUT2n IO IO IO IO , Power External clock output VCCIO power for PLL11 clock outputs PLL11_OUT[1.0]p, PLL11_OUT[1.0]n, PLL11_FBp/OUT2p, and PLL11_FBn/OUT2n. This pin should be connected to the voltage level of the target device which PLL11 in bank 11 is driving. Refer to the data sheet for absolute maximum voltage rating on
Altera
Original
AE31 pll-11 PT-EP1AGX90E-1 EP1AGX90 EP1AGX90E EP1AGX90EF1152 PLL12

EP1AGX20CF484

Abstract: PLL11 PLL11_OUT[1.0]p, PLL11_OUT[1.0]n, PLL11_FBp/OUT2p, and PLL11_FBn/OUT2n. Connection Guidelines This , PLL11). When these pins are not used, they may be left floating PLL11_OUT[1,0]n (Note 4, 6) Output Optional negative external clock outputs [1,0] from enhanced PLL11. If the clock outputs are single ended, then each pair of pins (i.e., PLL11_OUT0p and PLL11_OUT0n are considered one pair) can be , PLL11_OUT[1,0]p (Note 4, 6) Output Optional positive external clock outputs [1,0] from enhanced PLL
Atmel
Original
EP1AGX20CF484 PCG-01002-1 EP1AGX60DF780 EP1AGX50DF1152 EP1AGX60EF1152

EP1AGX20CF484

Abstract: PLL11 clock outputs PLL11_OUT[1.0]p, PLL11_OUT[1.0]n, PLL11_FBp/OUT2p, and PLL11_FBn/OUT2n. This pin , negative external clock outputs [1,0] from enhanced PLL11. If the clock outputs are single-ended, then each pair of pins (i.e., PLL11_OUT0p and PLL11_OUT0n are considered one pair) can be either in-phase or , ° out-ofphase. Output Optional positive external clock outputs [1,0] from enhanced PLL11. These pins can be , ]p PLL6_OUT[1,0]n PLL11_OUT[1,0]p PLL11_OUT[1,0]n PLL12_OUT[1,0]p PLL12_OUT[1,0]n
Altera
Original
PT-EP1AGX20C-1 X16/X18 EP1AGX20CF780 EP1AGX20C

pll-11

Abstract: outputs PLL11_OUT[1.0]p, PLL11_OUT[1.0]n, PLL11_FBp/OUT2p, and PLL11_FBn/OUT2n. This pin should be , enhanced PLL11. If the clock outputs are single-ended, then each pair of pins (i.e., PLL11_OUT0p and PLL11_OUT0n are considered one pair) can be either in-phase or 180° out-of-phase. Output Optional positive , external clock outputs [1,0] from enhanced PLL11. These pins can be differential (two output pin pairs) or , IO, Input Pin Name PLL5_OUT[1,0]n PLL6_OUT[1,0]p PLL6_OUT[1,0]n PLL11_OUT[1,0]p PLL11_OUT
Altera
Original
PT-EP1AGX35C/D-1 EP1AGX35CF484 EP1AGX35DF780 EP1AGX35C/D

FIN210AC

Abstract: 13M-pixel ­ 8ns output edge rates (S1=1, S0=0) CKREF is twice as fast STROBE (PLL1=1; PLL0=0) ~50% CKP , CKREF Frequency PLL1=0, PLL0=1 100 PLL1=1, PLL0=0 fCKREF fSTRB 94.7 50 PLL1=1, PLL0
Fairchild Semiconductor
Original
DSO20 FIN210 JESD22-A114 Dp 104 ckp5e PWS1.1

DP1211

Abstract: 337 BGA footprint is twice as fast STROBE (PLL1=1; PLL0=0) CKREF=26MHz & STROBE Frequency=10 MHz © 2008 Fairchild , Frequency fCKREF fSTRB PLL1=0, PLL0=1 PLL1=1, PLL0=0 PLL1=1, PLL0=1 tCPWH tCPWL tCLKT tSPWH/L CKREF DC
Fairchild Semiconductor
Original

577ns

Abstract: Range (S1=0, S0=1) CKREF is twice as fast STROBE (PLL1=1; PLL0=0) CKREF=26MHz & STROBE Frequency=10 MHz , Frequency Relative to CKREF Frequency fCKREF fSTRB PLL1=0, PLL0=1 PLL1=1, PLL0=0 PLL1=1, PLL0=1 tCPWH tCPWL
Fairchild Semiconductor
Original
577ns

emi line filter 48MHz

Abstract: FIN210AC =1, S0=0) CKREF is twice as fast STROBE (PLL1=1; PLL0=0) ~50% CKP PW,(PWS1=PWS0=0) CKREF=26MHz & , Frequency Relative to CKREF Frequency PLL1=0, PLL0=1 100 PLL1=1, PLL0=0 fCKREF fSTRB 94.7 50 PLL1=1, PLL0=1 fSTRB MHz 331/3 % of fCKREF tCPWH CKREF DC T=1/fCKREF
Fairchild Semiconductor
Original
emi line filter 48MHz

DS70143

Abstract: DS70030 frequency Output State PLL1_0 or PLL1_1 PLL1_0 or PLL1_1 PLL1_0 or PLL1_1 PLL1_0 or PLL1_1 PLL1_0 or PLL1_1 PLL1_0 or PLL1_1 PLL1_0 or PLL1_1 PLL1_0 or PLL1_1 20h CLK2 Output State CLK3 Output State , ] 0 MDIVP1 [0] 0 PLL1_1 MDIV1 Setting PLL1_1 NDIV1 Integral Part Setting PLL1_1 NDIV1 Fractional Part , . Please set PLL parameter according to . PLL1 has two Frequency mode predefined as PLL1_0 or PLL1_1 and , frequency of PLL is chosen from two setups PLL1_0 and PLL1_1. FS1_x 0 1 PLL1 Frequency PLL1_0 Predefined by
Microchip Technology
Original
DS70030 DS70143 DS70046 ecio PLL clock microchip PIC30F6011A/ PIC30F6011A/6012A/6013A/6014A PIC30F6011A PIC30F6012A PIC30F6013A PIC30F6014A

DSPIC30F6014A pwm

Abstract: DS70046 Two PLL Outputs Source Register Source Clock CLK5 PLL11 Destination Register INBUF
Microchip Technology
Original
DS70157 DSPIC30F6014A pwm PIC30F/33F PIC30F PIC30F601XA DS80242C-
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