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PLL10 Datasheet

Part Manufacturer Description PDF Type
PLL1000A Z-Communications PHASE LOCKED LOOP Original
PLL1000A-LF Z-Communications IC PLL SNGL 988 TO 1028MHZ 5V Original
PLL102-01TC PhaseLink Low Voltage PLL Clock Drivers Original
PLL102-01TI PhaseLink Low Voltage PLL Clock Drivers Original
PLL102-01TM PhaseLink Low Voltage PLL Clock Drivers Original
PLL102-03 PhaseLink Low Skew Output Buffer Original
PLL102-03SC PhaseLink Low Skew Output Buffer Original
PLL102-03SCL PhaseLink Low Skew Output Buffer Original
PLL102-03SCL-R PhaseLink Low Skew Output Buffer Original
PLL102-03SC-R PhaseLink Low Skew Output Buffer Original
PLL102-04 PhaseLink Low Skew Output Buffer Original
PLL102-04SC PhaseLink Low Skew Output Buffer Original
PLL102-04SCL PhaseLink Low Skew Output Buffer Original
PLL102-04SCL-R PhaseLink Low Skew Output Buffer Original
PLL102-04SC-R PhaseLink Low Skew Output Buffer Original
PLL102-05 PhaseLink Low Skew Output Buffer Original
PLL102-05SC PhaseLink Low Skew Output Buffer Original
PLL102-05SCL PhaseLink Low Skew Output Buffer Original
PLL102-05SCL-R PhaseLink Low Skew Output Buffer Original
PLL102-05SC-R PhaseLink Low Skew Output Buffer Original
Showing first 20 results.

PLL10

Catalog Datasheet MFG & Type PDF Document Tags

I1023

Abstract: WD2-0 SZ1-0 INV DBO AVG SCTRL HOLD STDBY CE RESET CPINS PLL1-0 2 3 2 16 16 11 2 2 CLK L7710 BLOCK , Output Buffer Held Soft Standby Hard Standby TABLE 3. PLL1-0 00 01 10 11 PLL MODE Bus Options x1 , High-Speed FFT Processor TABLE 8. VALID COMBINATIONS OF OVERLAP MODES (OVC1-0) AND PLL MODES (PLL1-0) FOR , OVC1-0 00 01 10 11 OVC1-0 00 01 10 11 PLL1-0 Mode x1 (100 MHz) OVC1-0 Valid Operation Valid Operation Valid Operation Valid Operation PLL1-0 Mode x2 (50 MHz) Data Starvation Data Starvation Valid Operation
Logic Devices
Original
I1023 DIN15 DIN14 DIN13 DIN12 DIN11 DIN10

R1023

Abstract: LF7710 PLL mode (PLL1-0) and the overlap mode (OVC1-0). For example, if the PLL mode is x2 (PLL1-0=01 , HOLD SCL5-0 STDBY CE OCLK RESET CPINS 2 PLL1-0 ACOP CLK Logic Products 1 , Input RAM 1 0 Soft Standby 11 Output RAM 1 1 Hard Stanby TABLE 3. PLL1-0 , TABLE 8. VALID COMBINATIONS OF OVERLAP MODES (OVC1-0) AND PLL MODES (PLL1-0) FOR CTM=1 Full Complex Transform Real Transform Imaginary Transform OVC1-0 PLL1-0 Mode x1 OVC1-0 PLL1-0 Mode x1 OVC1
Logic Devices
Original
LF7710 R1023 a1024 DOUT15 DOUT14 DOUT13 DOUT12 DOUT11
Abstract: the PLL mode (PLL1-0) and the overlap mode (OVC1-0). For example, if the PLL mode is x2 (PLL1-0=01 , AVG SCTRL HOLD STDBY CE RESET CPINS PLL1-0 2 ACOP OCLK 6 SCL5-0 OVF * CLK Logic Products 1 , 0 1 0 1 Operation Normal Operation Output Buffer Held Soft Standby Hard Stanby TABLE 3. PLL1-0 , -0) AND PLL MODES (PLL1-0) FOR CTM=1 Full Complex Transform Real Transform Imaginary Transform OVC1-0 00 01 10 11 OVC1-0 00 01 10 11 OVC1-0 00 01 10 11 OVC1-0 00 01 10 11 PLL1-0 Mode x1 Valid Operation Logic Devices
Original

13M-pixel

Abstract: 202 ball bga Frequency Range (S1=S0=1) ~4 ­ 5ns output edge rates (S1=S0=1) Normal Mode (PLL1=0; PLL0=1) ~50 , =0, S0=1) ~50% CKP PW,(PWS1=PWS0=0) Normal Mode (PLL1=0, PLL0=1) © 2008 Fairchild Semiconductor , (S1=0, S0=1) ~2 ­ 3ns output edge rates (S1=0, S0=1) Normal Mode (PLL1=0; PLL0=1) ~50% CKP PW , 9 mA S1=H S0=H IDD_DES1 fCKREF=fSTRB, PLL1=0,PLL0=1; CTL_ADJ=0; CL=0pF mA S1=L , fCKREF=fSTRB, PLL1=0,PLL0=1; CTL_ADJ=0; CL=0pF 0.1 20MHz 8MHz 9 mA 28MHz 12 mA Pin
Fairchild Semiconductor
Original
FIN212AC FIN212ACMLX FIN212ACGFX 13M-pixel 202 ball bga dsi LCD driver DP1211 30 pin flex cable lcd 5M cmos camera MO-195

AK8140A

Abstract: PLL11 frequency Output State PLL1_0 or PLL1_1 PLL1_0 or PLL1_1 PLL1_0 or PLL1_1 PLL1_0 or PLL1_1 PLL1_0 or PLL1_1 PLL1_0 or PLL1_1 PLL1_0 or PLL1_1 PLL1_0 or PLL1_1 20h CLK2 Output State CLK3 Output State , Setting PLL1_0 MDIV1 Setting PLL1_0 NDIV1 Integral Part Setting PLL1_0 NDIV1 Fractional Part Setting PLL1 , . Please set PLL parameter according to . PLL1 has two Frequency mode predefined as PLL1_0 or PLL1_1 and , frequency of PLL is chosen from two setups PLL1_0 and PLL1_1. FS1_x 0 1 PLL1 Frequency PLL1_0 Predefined by
Asahi Kasei Microdevices
Original
AK8140A PLL11 CLK30 230MH 16M-60MH 4M-100MH 160MH

DP1211

Abstract: 337 BGA footprint 42-Pin Package) Serializer Configuration: 8MHz to 28MHz Frequency Range (S1=S0=1) Normal Mode (PLL1=0 , Serializer Configuration: 20MHz to 40MHz Frequency Range (S1=0, S0=1) Normal Mode (PLL1=0, PLL0 , (S1=0, S0=1) Normal Mode (PLL1=0; PLL0=1) Master clock bypass mode. FIN212AC Serializer VDDP1 D3 E4 , Inputs at GND or VDD S1=L S0=H IDD_SER1 Dynamic Serializer Power Supply Current fCKREF=fSTRB, PLL1=0,PLL0 , fCKREF=fSTRB, PLL1=0,PLL0=1; CTL_ADJ=0; CL=0pF S1=H S0=L S1=H S0=H 20MHz 40MHz 5MHz 14MHz 8MHz 28MHz 20MHz
Fairchild Semiconductor
Original
337 BGA footprint

emi line filter 48MHz

Abstract: FIN210AC 5ns output edge rates (S1=S0=1) Normal Mode (PLL1=0; PLL0=1) ~50% CKP PW,(PWS1=PWS0 , % CKP PW,(PWS1=PWS0=0) Normal Mode (PLL1=0, PLL0=1) © 2009 Fairchild Semiconductor Corporation , (S1=0, S0=1) ~2 ­ 3ns output edge rates (S1=0, S0=1) Normal Mode (PLL1=0; PLL0=1) ~50% CKP PW , fCKREF=fSTRB, PLL1=0,PLL0=1; S1=H CTL_ADJ=0; CL=0pF S0=L S1=H S0=H IDD_SER1 8MHz 9 mA 28MHz 12 mA fCKREF=fSTRB, PLL1=0,PLL0=1; CTL_ADJ=0; CL=0pF © 2009 Fairchild Semiconductor
Fairchild Semiconductor
Original
FIN210AC FIN210ACMLX FIN210ACGFX emi line filter 48MHz Dp 104 DSO20 FIN210

L7710

Abstract: XYMODE WD2-0 SZ1-0 INV DBO AVG SCTRL HOLD STDBY CE RESET CPINS PLL1-0 2 3 2 16 16 11 2 2 CLK L7710 , Loading Location TABLE 3. PLL MODE PLL1-0 00 01 10 11 Bus Options x1 x2 x3 x4 10 11 IM CACC1 , High-Speed FFT Processor TABLE 9. VALID COMBINATIONS OF OVERLAP MODES (OVC1-0) AND PLL MODES (PLL1-0) FOR , 11 PLL1-0 Mode x1 (100 MHz) Valid Operation Valid Operation Valid Operation Valid Operation PLL1-0 Mode x2 (50 MHz) Data Starvation Data Starvation Valid Operation Valid Operation PLL1-0 Mode x3 (33 MHz
Logic Devices
Original
AIN10 L7710QC10 L7710QI10 MIL-STD-883 L7710FMB12 ADOUT10
Abstract: Frequency Range (S1=S0=1) ~4 â'" 5ns output edge rates (S1=S0=1) Normal Mode (PLL1=0; PLL0=1) ~50 , =0, S0=1) ~50% CKP PW,(PWS1=PWS0=0) Normal Mode (PLL1=0, PLL0=1) © 2009 Fairchild Semiconductor , 48MHz Frequency Range (S1=0, S0=1) ~2 â'" 3ns output edge rates (S1=0, S0=1) Normal Mode (PLL1=0 , Current mA 48MHz 15.5 mA fCKREF=fSTRB, PLL1=0,PLL0=1; S1=H CTL_ADJ=0; CL=0pF; S0=L CKSI , 30 PLL1=0, PLL0=0 Strobe Frequency Relative to CKREF Frequency PLL1=0, PLL0=1 100 PLL1 Fairchild Semiconductor
Original

FIN212AC

Abstract: FIN212ACGFX the following modes, refer to Table 1. MODE 1,2,3; PLL1=0, PLL0=1; CKREF Equals STROBE This mode , ; PLL1=0, PLL0=1; CKREF Does Not Equal STROBE For microcontroller interfaces, a reference clock at the , Range PLL Divide Mode: Standard Not Over-Clocked (PLL1=0, PLL0=1) Multiplier 7x Master Clock Bypass , Current IDD_PD= IDDA + IDDS + IDDP Test Conditions IDD_SER1 fCKREF = fSTRB, PLL1=0,PLL0 , Supply Current IDD_DES1= IDDA+IDDS+IDDP fCKREF = fSTRB, PLL1=0,PLL0=1; CTL_ADJ=0; CL = 0pF S1=H
Fairchild Semiconductor
Original
MO-220 AN-5058 AN-5061 8/10-B
Abstract: =1) Normal Mode (PLL1=0; PLL0=1) ~50% CKP PW,(PWS1=PWS0=0) FIN212AC Deserializer VDDP1 Baseband , (PLL1=0, PLL0=1) © 2008 Fairchild Semiconductor Corporation FIN212AC â'¢ Rev. 1.1.0 , =0, S0=1) ~2 â'" 3ns output edge rates (S1=0, S0=1) Normal Mode (PLL1=0; PLL0=1) ~50% CKP PW , Current fCKREF=fSTRB, PLL1=0,PLL0=1; CTL_ADJ=0; CL=0pF mA 40MHz 19 mA S1=H S0=L , fCKREF=fSTRB, PLL1=0,PLL0=1; CTL_ADJ=0; CL=0pF 0.1 20MHz 20MHz 10 mA 40MHz 14 mA Fairchild Semiconductor
Original

FIN210AC

Abstract: 13M-pixel Range (S1=S0=1) ~4 ­ 5ns output edge rates (S1=S0=1) Normal Mode (PLL1=0; PLL0=1) ~50% CKP PW , =0, S0=1) ~50% CKP PW,(PWS1=PWS0=0) Normal Mode (PLL1=0, PLL0=1) © 2009 Fairchild Semiconductor , 48MHz Frequency Range (S1=0, S0=1) ~2 ­ 3ns output edge rates (S1=0, S0=1) Normal Mode (PLL1=0 , 15.5 mA fCKREF=fSTRB, PLL1=0,PLL0=1; S1=H CTL_ADJ=0; CL=0pF; S0=L CKSI+/CKSI- Not Connected , =1 CKREF Clock Frequency (5MHz - 48MHz); 10 30 PLL1=0, PLL0=0 Strobe Frequency Relative to
Fairchild Semiconductor
Original
JESD22-A114 ckp5e PWS1.1 577ns

337 BGA footprint

Abstract: AN-5058 1.3MPixel CMOSBGA 42 PLL MODE 3 (S1=S0=1) 10-30MHz PLL (PLL1=0, PLL0=1) 7x CKSI CKP"" MODE 1 , IDD_PD=IDDA + IDDS + IDDP IDD_SER1=IDDA+IDDS+IDDP fCKREF=fSTRB, PLL1=0,PLL0=1; CTL_ADJ=0; CL=0pF S1=H S0=L S1=H S0=H S1=L S0=H IDD_DES1 IDD_DES1=IDDA+IDDS+IDDP fCKREF=fSTRB, PLL1=0 , =1 fCKREF 18 10 28 MHz PLL1=0, PLL0=0 CKREF tCPWH tSPWH/L tSTC tHTC PLL1 , tCLKT 100 T=1/fCKREF CKREF DC tCPWL fCKREF fSTRB PLL1=0, PLL0=1 PLL1=1, PLL0
Fairchild Semiconductor
Original
FIN212ACBFX DP10 32MLPJEDEC MO-2205 MO1953 FIN212AC1

577ns

Abstract: =1) Normal Mode (PLL1=0; PLL0=1) FIN212AC Deserializer VDDP1 D3 E4 F4 Deserializer Configuration: ~4 ­ , Mode (PLL1=0, PLL0=1) www.fairchildsemi.com µSerDesTM FIN212AC - 12-Bit Serializer / Deserializer , Configuration: 20MHz to 40MHz Frequency Range (S1=0, S0=1) Normal Mode (PLL1=0; PLL0=1) Master clock bypass mode , Supply Current fCKREF=fSTRB, PLL1=0,PLL0=1; CTL_ADJ=0; CL=0pF S1=H S0=L S1=H S0=H S1=L S0=H IDD_DES1 Dynamic Deserializer Power Supply Current fCKREF=fSTRB, PLL1=0,PLL0=1; CTL_ADJ=0; CL=0pF S1=H S0=L S1=H
Fairchild Semiconductor
Original

Dp 104

Abstract: DSO20 Range (S1=S0=1) ~4 ­ 5ns output edge rates (S1=S0=1) Normal Mode (PLL1=0; PLL0=1) ~50% CKP PW , =0, S0=1) ~50% CKP PW,(PWS1=PWS0=0) Normal Mode (PLL1=0, PLL0=1) © 2009 Fairchild Semiconductor , 48MHz Frequency Range (S1=0, S0=1) ~2 ­ 3ns output edge rates (S1=0, S0=1) Normal Mode (PLL1=0 , 15.5 mA fCKREF=fSTRB, PLL1=0,PLL0=1; S1=H CTL_ADJ=0; CL=0pF; S0=L CKSI+/CKSI- Not Connected , =1 CKREF Clock Frequency (5MHz - 48MHz); 10 30 PLL1=0, PLL0=0 Strobe Frequency Relative to
Fairchild Semiconductor
Original
mobile camera interface microcontroller

AN-5058

Abstract: AN-5061 the following modes, refer to Table 1. MODE 1,2,3; PLL1=0, PLL0=1; CKREF Equals STROBE This mode , ; PLL1=0, PLL0=1; CKREF Does Not Equal STROBE For microcontroller interfaces, a reference clock at the , : MODE 3 (S1=S0=1) 10-30MHz Frequency Range PLL Divide Mode: Standard Not Over-Clocked (PLL1=0, PLL0 , fCKREF = fSTRB, PLL1=0,PLL0=1; CTL_ADJ=0; CL = 0pF 40MHz 19.0 mA S1=H S0=L 5MHz 9.5 , mA S1=L S0=H fCKREF = fSTRB, PLL1=0,PLL0=1; CTL_ADJ=0; CL = 0pF 13.0 S1=H S0=H
Fairchild Semiconductor
Original

35x45mm

Abstract: 6X6 mlp 1,2,3; PLL1=0, PLL0=1; CKREF Equals STROBE This mode is typically used when sending pixel data at a , synchronized and sent source synchronously with a bit clock. MODE 1,2,3; PLL1=0, PLL0=1; CKREF Does Not Equal , (S1=S0=1) 10-30MHz Frequency Range PLL Divide Mode: Standard Not Over-Clocked (PLL1=0, PLL0 , = IDDA+IDDS+IDDP fCKREF = fSTRB, PLL1=0,PLL0=1; CTL_ADJ=0; CL = 0pF S1=H S0=L S1=H S0=H S1=L S0=H IDD_DES1 Dynamic Deserializer Power Supply Current IDD_DES1= IDDA+IDDS+IDDP fCKREF = fSTRB, PLL1=0,PLL0=1; CTL_ADJ=0; CL = 0pF
Fairchild Semiconductor
Original
35x45mm 6X6 mlp
Abstract: 1,2,3; PLL1=0, PLL0=1; CKREF Equals STROBE This mode is typically used when sending pixel data at a , synchronized and sent source synchronously with a bit clock. MODE 1,2,3; PLL1=0, PLL0=1; CKREF Does Not Equal , : Standard Not Over-Clocked (PLL1=0, PLL0=1) Multiplier 7x Master Clock Bypass Mode: (clock passes from CKSI , = IDDA+IDDS+IDDP fCKREF = fSTRB, PLL1=0,PLL0=1; CTL_ADJ=0; CL = 0pF S1=H S0=L S1=H S0=H S1=L S0=H IDD_DES1 Dynamic Deserializer Power Supply Current IDD_DES1= IDDA+IDDS+IDDP fCKREF = fSTRB, PLL1=0,PLL0=1; CTL_ADJ=0; CL = 0pF Fairchild Semiconductor
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Abstract: ; PLL1=0, PLL0=1; CKREF Equals STROBE This mode is typically used when sending pixel data at a constant , synchronized and sent source synchronously with a bit clock. MODE 1,2,3; PLL1=0, PLL0=1; CKREF Does Not Equal , Divide Mode: Standard Not Over-Clocked (PLL1=0, PLL0=1) Multiplier 7x Master Clock Bypass Mode: (clock , Serializer Power Supply Current IDD_SER1= IDDA+IDDS+IDDP fCKREF = fSTRB, PLL1=0,PLL0=1; CTL_ADJ=0; CL = 0pF , = IDDA+IDDS+IDDP fCKREF = fSTRB, PLL1=0,PLL0=1; CTL_ADJ=0; CL = 0pF S1=H S0=L S1=H S0=H 20MHz 40MHz 5MHz 14MHz 8MHz Fairchild Semiconductor
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Abstract: ; PLL1=0, PLL0=1; CKREF Equals STROBE This mode is typically used when sending pixel data at a constant , synchronized and sent source synchronously with a bit clock. MODE 1,2,3; PLL1=0, PLL0=1; CKREF Does Not Equal , Divide Mode: Standard Not Over-Clocked (PLL1=0, PLL0=1) Multiplier 7x Master Clock Bypass Mode: (clock , = IDDA+IDDS+IDDP fCKREF = fSTRB, PLL1=0,PLL0=1; CTL_ADJ=0; CL = 0pF S1=H S0=L S1=H S0=H S1=L S0=H IDD_DES1 Dynamic Deserializer Power Supply Current IDD_DES1= IDDA+IDDS+IDDP fCKREF = fSTRB, PLL1=0,PLL0=1; CTL_ADJ=0; CL = 0pF Fairchild Semiconductor
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70F3612

Abstract: 70F3613 WD2-0 SZ1-0 INV DBO AVG SCTRL HOLD STDBY CE RESET CPINS PLL1-0 2 3 2 16 16 11 2 2 CLK L7710 BLOCK , Output Buffer Held Soft Standby Hard Standby TABLE 3. PLL1-0 00 01 10 11 PLL MODE Bus Options x1 , High-Speed FFT Processor TABLE 8. VALID COMBINATIONS OF OVERLAP MODES (OVC1-0) AND PLL MODES (PLL1-0) FOR , OVC1-0 00 01 10 11 OVC1-0 00 01 10 11 PLL1-0 Mode x1 (100 MHz) OVC1-0 Valid Operation Valid Operation Valid Operation Valid Operation PLL1-0 Mode x2 (50 MHz) Data Starvation Data Starvation Valid Operation
NEC
Original
PD70F3610 70F3611 70F3612 70F3613 V850ES PD70F3610 datasheet PD70F3612M2GBA2-GAH-AX 70F3614 V850ES/FE3-L

70f3617

Abstract: PD70F3615 HOLD SCL5-0 STDBY CE OCLK RESET CPINS 2 PLL1-0 ACOP CLK Logic Products 1 , Input RAM 1 0 Soft Standby 11 Output RAM 1 1 Hard Stanby TABLE 3. PLL1-0 , TABLE 8. VALID COMBINATIONS OF OVERLAP MODES (OVC1-0) AND PLL MODES (PLL1-0) FOR CTM=1 Full Complex Transform Real Transform Imaginary Transform OVC1-0 PLL1-0 Mode x1 OVC1-0 PLL1-0 Mode x1 OVC1-0 PLL1-0 Mode x1 00 Valid Operation 00 Valid Operation 00 Valid Operation 01
NEC
Original
PD70F3615 70F3616 70F3618 70F3619 70f3617 70F36 PD70F3618 70F3617 V850ES/FF3-L

70f3612

Abstract: PD70F3610 AVG SCTRL HOLD STDBY CE RESET CPINS PLL1-0 2 ACOP OCLK 6 SCL5-0 OVF * CLK Logic Products 1 , 0 1 0 1 Operation Normal Operation Output Buffer Held Soft Standby Hard Stanby TABLE 3. PLL1-0 , -0) AND PLL MODES (PLL1-0) FOR CTM=1 Full Complex Transform Real Transform Imaginary Transform OVC1-0 00 01 10 11 OVC1-0 00 01 10 11 OVC1-0 00 01 10 11 OVC1-0 00 01 10 11 PLL1-0 Mode x1 Valid Operation Valid Operation Valid Operation Valid Operation PLL1-0 Mode x2 Data Starvation Data Starvation Valid
NEC
Original
PD70F3612 witl 86 64LQFP-1010 50pFti TAA0-TAA41 PD70F3612m1 V850ES/FG3-L U18743J U15943J RAM6/8/12/16 U18666JJ2V0DS00 XX/16

70f3617

Abstract: 70f36 =1) Normal Mode (PLL1=0; PLL0=1) ~50% CKP PW,(PWS1=PWS0=0) FIN212AC Deserializer VDDP1 Baseband , (PLL1=0, PLL0=1) © 2008 Fairchild Semiconductor Corporation FIN212AC â'¢ Rev. 1.1.0 , =0, S0=1) ~2 â'" 3ns output edge rates (S1=0, S0=1) Normal Mode (PLL1=0; PLL0=1) ~50% CKP PW , Current fCKREF=fSTRB, PLL1=0,PLL0=1; CTL_ADJ=0; CL=0pF mA 40MHz 19 mA S1=H S0=L , fCKREF=fSTRB, PLL1=0,PLL0=1; CTL_ADJ=0; CL=0pF 0.1 20MHz 20MHz 10 mA 40MHz 14 mA
NEC
Original
P70-P711 4xt1 PD70F3619 P9640 U18667JJ2V0DS00 XX/32 U18667JJ2V0DS PD70F3615M1GKA-GAK-AX PD70F3615M1GKA1-GAK-AX PD70F3615M1GKA2-GAK-AX

P70-P715

Abstract: PD70F362 XYMODE WD2-0 SZ1-0 INV DBO AVG SCTRL HOLD STDBY CE RESET CPINS PLL1-0 2 3 2 16 16 11 2 2 CLK L7710 , Loading Location TABLE 3. PLL MODE PLL1-0 00 01 10 11 Bus Options x1 x2 x3 x4 10 11 IM CACC1 , High-Speed FFT Processor TABLE 9. VALID COMBINATIONS OF OVERLAP MODES (OVC1-0) AND PLL MODES (PLL1-0) FOR , 11 PLL1-0 Mode x1 (100 MHz) Valid Operation Valid Operation Valid Operation Valid Operation PLL1-0 Mode x2 (50 MHz) Data Starvation Data Starvation Valid Operation Valid Operation PLL1-0 Mode x3 (33 MHz
NEC
Original
P70-P715 PD70F362 uPD70F3620 PD70F3620 70F3621 70F3622 RAM8/12/16 U18668JJ2V0DS00 U18668JJ2V0DS

8609 396 81 15 765

Abstract: CV 7599 diode 1.3MPixel CMOSBGA 42 PLL MODE 3 (S1=S0=1) 10-30MHz PLL (PLL1=0, PLL0=1) 7x CKSI CKP"" MODE 1 , IDD_PD=IDDA + IDDS + IDDP IDD_SER1=IDDA+IDDS+IDDP fCKREF=fSTRB, PLL1=0,PLL0=1; CTL_ADJ=0; CL=0pF S1=H S0=L S1=H S0=H S1=L S0=H IDD_DES1 IDD_DES1=IDDA+IDDS+IDDP fCKREF=fSTRB, PLL1=0 , =1 fCKREF 18 10 28 MHz PLL1=0, PLL0=0 CKREF tCPWH tSPWH/L tSTC tHTC PLL1 , tCLKT 100 T=1/fCKREF CKREF DC tCPWL fCKREF fSTRB PLL1=0, PLL0=1 PLL1=1, PLL0
Altera
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8609 396 81 15 765 CV 7599 diode EP3C25 pin diagram EP3C16 PCI 6602 A 3120 0532 8 pin CIII52001-1

3841 9904

Abstract: DR 6236 078 42-Pin Package) Serializer Configuration: 8MHz to 28MHz Frequency Range (S1=S0=1) Normal Mode (PLL1=0 , Serializer Configuration: 20MHz to 40MHz Frequency Range (S1=0, S0=1) Normal Mode (PLL1=0, PLL0 , (S1=0, S0=1) Normal Mode (PLL1=0; PLL0=1) Master clock bypass mode. FIN212AC Serializer VDDP1 D3 E4 , Inputs at GND or VDD S1=L S0=H IDD_SER1 Dynamic Serializer Power Supply Current fCKREF=fSTRB, PLL1=0,PLL0 , fCKREF=fSTRB, PLL1=0,PLL0=1; CTL_ADJ=0; CL=0pF S1=H S0=L S1=H S0=H 20MHz 40MHz 5MHz 14MHz 8MHz 28MHz 20MHz
Altera
Original
3841 9904 DR 6236 078 5053 resistor NCE 7190 CIII52001-2

4046 PLL Designers Guide

Abstract: 8135 diode the following modes, refer to Table 1. MODE 1,2,3; PLL1=0, PLL0=1; CKREF Equals STROBE This mode , ; PLL1=0, PLL0=1; CKREF Does Not Equal STROBE For microcontroller interfaces, a reference clock at the , Range PLL Divide Mode: Standard Not Over-Clocked (PLL1=0, PLL0=1) Multiplier 7x Master Clock Bypass , Current IDD_PD= IDDA + IDDS + IDDP Test Conditions IDD_SER1 fCKREF = fSTRB, PLL1=0,PLL0 , Supply Current IDD_DES1= IDDA+IDDS+IDDP fCKREF = fSTRB, PLL1=0,PLL0=1; CTL_ADJ=0; CL = 0pF S1=H
Altera
Original
4046 PLL Designers Guide 8135 diode

PD70F3620

Abstract: 70f3622 Frequency Range (S1=S0=1) ~4 ­ 5ns output edge rates (S1=S0=1) Normal Mode (PLL1=0; PLL0=1) ~50 , =0, S0=1) ~50% CKP PW,(PWS1=PWS0=0) Normal Mode (PLL1=0, PLL0=1) © 2008 Fairchild Semiconductor , (S1=0, S0=1) ~2 ­ 3ns output edge rates (S1=0, S0=1) Normal Mode (PLL1=0; PLL0=1) ~50% CKP PW , 9 mA S1=H S0=H IDD_DES1 fCKREF=fSTRB, PLL1=0,PLL0=1; CTL_ADJ=0; CL=0pF mA S1=L , fCKREF=fSTRB, PLL1=0,PLL0=1; CTL_ADJ=0; CL=0pF 0.1 20MHz 8MHz 9 mA 28MHz 12 mA Pin
NEC
Original
v850es/fg3 70F362 PD70F3620M1GCA-UEU-AX PD70F3620M1GCA1-UEU-AX PD70F3620M1GCA2-UEU-AX PD70F3620M2GCA-UEU-AX PD70F3620M2GCA1-UEU-AX PD70F3620M2GCA2-UEU-AX
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