Datasheet Search Results			1 - 1 of about 1 for PLE40
	PLE40	Altera Corporation	User Configurable Logic Data Book	516.3 Kb,  8 Pages.

Fulltext Datasheet Results		1 - 4 of about 4 for PLE40
	First line: EP320DC* EP1800* PLE40 EP600DC EP320DC PROGRAMMABLE LOGIC DEVELOPMENT YTEM UPREME PLCAD-UPREME PLCAD-UPREME CONTENT Complete PLD2 ystem. PLE40, chematic Capture oftware. PLLIB-TTL, MacroFunction Library. PLME, tate Machine Entry oftware. PLFIM, Functional imulation oftware. PLED600, EP600/EP610 Adap Abstract: .. PLE40, Log  ¡Caps Schematic Capture Software. PLSLIB-TTL, TTL MacroFunction Library. PLSME, State Machine Entry Software. PLFSIM, Functional Simulation Software. PLED600 PLED600 , EP600 EP600 /EP610 EP610 ..  Tags: EP320DC EP600DC PLE40 EP1800* EP320DC*   datasheet abstract..	307.33 Kb	1 Pages	OCR Scan
	First line: schematic diagram vga LOGICAPS SCHEMATIC CAPTURE SOFTWARE PLE40 PLE40 CONTENTS SOFTWARE LogiCaps Schematic Capture. Printer/Plotter Interface. Standard Symbol Library. PLE40 FEATURES Graphical Entry Logic {Schematics. Runs PC-AT compatible) PS/2 computers. Abstract: .. LOGICAPS SCHEMATIC CAPTURE SOFTWARE PLE40 PLE40 CONTENTS SOFTWARE • LogiCaps Schematic Capture. • Printer/Plotter Interface. • Standard Symbol Library. PLE40 FEATURES Graphical Entry of ..  Tags: schematic diagram vga   datasheet abstract..	534.88 Kb	8 Pages	OCR Scan
	First line: Software support Altera General-Purpose EP-Series EPLDs. Software support EPB1400 (BUSTER). Boolean Equation Design Entry. Automatic assignments. SALSA Logic Minimization. Device fitter optimizes device resources. Support user-defined MacroFunctions. Optional Schematic Design Entry interfaces. Optio Abstract: .. For a more detailed description see the PLE40 LogiCaps data sheet. LogiCaps is a high performance schematic capture package that has been optimized for entering designs destined for Altera ..  Tags:   datasheet abstract..	974.77 Kb	6 Pages	OCR Scan
	First line: Erasable, User-Configurable circuit capable implementing 2100 equivalent gates conventional custom logic. Speed equivalent 74LS with clock rates. "Zero Power" (typically standby). Active power MHz. Forty-eight Macrocells with configurable architecture allowing inputs outputs. Programmable Abstract: .. See PLE40 data sheet. Basic gates provided are AND, OR, NAND, NOR, Exclusive OR and NOR, and NOT functions. De-Morgan's inversion bubble input of each gate is also included. These logic gates ..  Tags:   datasheet abstract..	701.76 Kb	10 Pages	OCR Scan

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