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Part Manufacturer Description Datasheet BUY
HC55184ECMZ96 Intersil Corporation SLIC 1-CH 45dB 45mA 5V/-28V 28-Pin PLCC T/R visit Intersil
TLV1543CFNG3 Texas Instruments 10-Bit 200 kSPS ADC Ser. Out, Built-In Self-Test Modes, Inherent S&H, Pin Compat. w/TLC1543, 11 Ch. 20-PLCC visit Texas Instruments
TLV1543CFN Texas Instruments 10-Bit 200 kSPS ADC Ser. Out, Built-In Self-Test Modes, Inherent S&H, Pin Compat. w/TLC1543, 11 Ch. 20-PLCC visit Texas Instruments
ISL95520HRZ-T Intersil Corporation SMBus Interface Hybrid Power Boost (HPB) and Narrow VDC (NVDC) Configurations Combo Battery Charger; QFN32; Temp Range: See Datasheet visit Intersil Buy
ISL95520HRZ Intersil Corporation SMBus Interface Hybrid Power Boost (HPB) and Narrow VDC (NVDC) Configurations Combo Battery Charger; QFN32; Temp Range: See Datasheet visit Intersil Buy
ISL95521HRZ-T Intersil Corporation Hybrid Power Boost and Narrow VDC Configurations Combination Battery Charger with SMBus Interface; QFN32; Temp Range: -40° to 85°C visit Intersil

PLCC pin configuration

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PLCC pin configuration

Abstract: AN-809 national PINOUTS The NM27LV010 is available in three packages a 32-pin LCC (leadless chip carrier with erase window) a 32-pin PLCC (plastic leaded chip carrier) and a 32-pin TSOP (thin small outline package) The LCC and PLCC pin configuration is shown in Figure 1 and the TSOP pin configuration is shown in Figure 2 The pin configuration of the LCC and PLCC packages conform to the JEDEC standard for conventional , 11368 ­ 2 FIGURE 2 TSOP Pin Configuration TL D 11368 ­ 1 FIGURE 1 LCC and PLCC Pin
National Semiconductor
Original
PLCC pin configuration AN-809 national C1995 NM27C010 BIOS 32 Pin PLCC D-82256

tda 1113

Abstract: .£ L Q .£ Î!S £ ^ a .a -*ï*ï X X Figure 4 .44-Pln PLCC Pin Configuration Standard Mode Table , ,44-Pin PLCC Pin Configuration EPROM Programming Mode Table 5. 44-Pin PLCC Pin Configuration EPROM Programming Mode Pin# 1-2 3-5 6-10 11-13 14-16 17-22 23-24 25-27 28 Table 5. 44-Pin PLCC Pin Configuration , . Standard Mode 28-Pln DIP/SOIC Pin Configuration Figure 10. Standard Mode 28-Pln PLCC Pin Configuration , J> Figure 12. EPROM Programming Mode 28-Pin PLCC Pin Configuration DS97Z8X1500 PRELIMINARY
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tda 1113 Z86E33/733/E34 Z86E43/743/E44 Z86E33 Z86733 Z86E34 Z86E43
Abstract: S 4 .0 8 4 pin PLCC Pin Configuration v o)co r> to i n ^ - c o * - _ ! < < < < < < < ,. -
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DD01S4 CAS21 CAS31
Abstract: FEATURES PIN CONFIGURATION* â¡ 5.0/2.5 M bit data rates â¡ 100% compatible with CQM9026 (in slow , ] D1 ] DO â¡ RAM buffer test capability PACKAGE: 48-pin D.I.P. â'¢Available in PLCC Pin configuration subject to change, contact factory for details. GENERAL DESCRIPTION The ELANC is , for self test â¡ On board oscillator â¡ Low power CMOS technology â¡ 48 pin D.I.P. plastic package or PLCC â¡ Single + 5 v Supply â¡ Compatible with HYC9058, HYC9068, HYC9078 C 1 C 2 -
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COM90C56

P04-P06

Abstract: P34-P35 P23 P24 /DS NC R//W P25 P26 P27 P04 Figure 3. 44-Pin PLCC Pin Configuration Standard Mode , PLCC Pin Configuration Table 4. 28-Pin DIP/SOIC/PLCC Pin Identification Pin # Symbol , to 5.5V) s 28-Pin DIP/SOIC/PLCC Packages (E33/733/E34) 40-Pin DIP Package (E43/743/E44) 44-Pin , GND P02 P11 P10 P01 P00 P30 P36 P37 P35 /RESET Figure 2. 40-Pin DIP Pin Configuration , In/Output In/Output In/Output Output Notes: Pin Configuration and Identification identical on
ZiLOG
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Z86743 Z86E44 P04-P06 P34-P35 diode p25 p03 transistor 3 pin CP97DZ83300 Z86E33/733/E34/E43/743/E44
Abstract: and One-Time Programmable EPROM (OTP). 290414-1 Figure 1. DIP Pin Configuration 290414-2 Figure 2. PLCC Pin Configuration Figure 3. QFP Pin Configuration The complete document fo r this , Packages (See Packaging Spec., Order #240800, Package Type P, N, and S) Pin, Software and , fabricated on Intel's CHMOS lll-E process. The UPI-C42 is pin, software, and architecturally compatible with -
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UPI-C42/UPI-L42 UPI-41 UPI-42 UPIL42 UPI-L42
Abstract: Figure 1. DIP Pin Configuration a a ft_ O. n_ (V y a s a as 2 1 0 3 9 3 -3 Figure 2. PLCC Pin Configuration The complete document for this product is available on Intel's "Data-on-Demand" , UPI-41AH/42AH UNIVERSAL PERIPHERAL INTERFACE 8-BIT SLAVE MICROCONTROLLER UPI-41: 6 MHz; UPI-42: 12.5 MHz Pin, Software and Architecturally Compatible with all UPI-41 and UPI-42 Products 8-Bit CPU , EPROM (OTP). All UPI-41 AH and UPI-42AH devices are fully pin compatible for easy transition from -
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p17c

Abstract: 3P19 23 2« 27 28 290414-2 Figure 2. PLCC Pin Configuration i1 á- , ¡ PI0 290414-1 Figure 1. DIP Pin Configuration ¡8 a Ji i « nnnnnnnnnnn I i 4 3 2 1 44 43 42 , . "iiii'ua"! â â  ' i? 290414-3 Figure 3. QFP Pin Configuration 5-112 September 1991 Order , UNIVERSAL PERIPHERAL INTERFACE CHMOS 8-BIT SLAVE MICROCONTROLLER Pin, Software and Architecturally , -42 family. It Is fabricated on Intel's CHMOS lll-E process. The UPI-C42 is pin, software, and
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p17c 3P19 3P2T 290414-001 0BF8 UPITM-C42 UP1-C42 P24/OBFE

64k DRAM

Abstract: COM90C56 8 C 9 C 10 C 11 C 12 PACKAGE: 24-pin D.I.P. * Also available 28-pin PLCC Pin configuration , Simplifies the interface of COM90C56 to lower cost DRAM Single + 5 v supply PIN CONFIGURATION ' VJ7 24
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64k DRAM COM90C57 90C57 LS244 LS374

240800

Abstract: UPI-42 290414-2 Figure 2. PLCC Pin Configuration ¡fiiTi i1 , Figure 1. DIP Pin Configuration a Jll* 3 4 3 2 1 44 , 3EA a is s -s g s s g 3 a jt: H S IB. 290414-3 Figure 3. QFP Pin Configuration 5-112 , UPITM-C42 UNIVERSAL PERIPHERAL INTERFACE CHMOS 8-BIT SLAVE MICROCONTROLLER Pin, Software and , UPI-C42 is pin, software, and architecturally compatible with the NMOS UPI family The UPI-C42 has all of
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240800 P10C P27/0ACK P24/OBFC

12C-MOS

Abstract: Z90611 3 P36 P37 3 P35 a /RESET 3 R//RL 3 /AS 3 P34 3 P33 3 P32 3 P31 Figure 2. 44-Pin PLCC Pin Configuration Table 1. 44-Pin PLCC Pin Identification Pin # 1 2 3-4 5 6-10 11 12 13 14-16 17-19 20-21 22 23 , ) 236 236 VO Lines 32 32 Package 44-Pin PLCC 44-Pin PLCC Vectored, Prioritized , PRELIMINARY 3 Z90611/12 CMOS Z8 8K OTP/ROM I/O Decoder (ROM) Zllog Table 1. 44-Pin PLCC Pin , 0.0.0.0.(900.0.0.0.0. n n n n n n n n n n n X 6 4 1 42 40 * 3 9 C 7 8 38 c 9 37 c 36 C 10 c c PLCC 33 C ¡3
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Z90611 12C-MOS Z90612
Abstract: c C C C C 17 18 u u lo o CL Figure 3 . 44-Pin PLCC Pin Configuration Standard Mode , Figure 5. Standard Mode 28-Pin DIP/SOIC Pin Configuration Table 4. 28-Pin DIP/SOIC/PLCC Pin , Configuration identical on DIP and Cerdip W indow Lid style packages. Figure 6. Standard Mode 28-Pin PLCC Pin , Temperature (Vc c = 3.5V to 5.5V) Extended Temperature (Vc c = 4.5V to 5.5V) 28-Pin DIP/SOIC/PLCC Packages (E33/733/E34) 40-Pin DIP Package (E43/743/E44) 44-Pin PLCC/QFP Packages (E43/743/E44) Software Enabled -
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CPS95C00125 MIL-STD-883C
Abstract: Configuration Standard Mode Table 2. 44-Pin PLCC Pin Identification P in # Symbol Function , . Standard Mode 28-Pin DIP/SOIC Pin Configuration Figure 6. Standard Mode 28-Pin PLCC Pin Configuration , 8-Bit Counter/Timers Each with a 6Bit Programmable Prescaler 28-Pin DIP/SOIC/PLCC Packages (E33/733/E34) 40-Pin DIP Package (E43/743/E44) 44-Pin PLCC/QFP Packages (E43/743/E44) Six Vectored , Pin Configuration Standard Mode 19 GND Ground 32-33 34 35-39 40 Pin 4 Output -
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Abstract: pletely static operation â'¢ IN P U T/O U TP U T T TL com patible (three state output) â'¢ 28-pin DIP â'¢ 32-lead PLCC PIN CONFIGURATION (TOP VIEW) FUNCTIONAL BLOCK DIAGRAM eg cl â , 256H ZB is m anufactured by the CM O S double silicon gate technology and is contained in 28-pin DIP or 32-lead PLCC package. (OKI can provide program m ing service as per custom er's request.) FEATURES â'¢ +5V single pow er supply â'¢ 32,768-w ord x 8-bit configuration â'¢ A ccess tim e: M AX 70 -
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MSM27C256HZB 768-W AX525 AX184 MSM27C256

Z8614

Abstract: PLCC pin configuration Z8614 DIP Z8614 PLCC Note: Pins 8 and 9 actually are connected to the chip, although used only for testing. These pins must be used as floaters by the customer. 44-Lead PLCC Pin Configuration 40-Lead DIP Pin Configuration 3 Z8614 CPS DC-4038-03 DC CHARACTERISTICS VCC = 4.75 V to , with 4 Kbytes of ROM. The Z8614 KBC is housed in 40-lead DIP and 44-lead PLCC packages, and is
ZiLOG
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P12P06

C1996

Abstract: NM27LV210 EPROM November 1994 PLCC Pin Configuration TQFP Pin Configuration PLCC Pin Configuration , options 44-Pin PLCC 44 Pin TQFP Block Diagram TL D 11376 ­ 1 TRI-STATE is a registered , foreseen this need and provides windowed LCC for prototyping and software development PLCC for , NM27LV210 V F 250 250 NM27LV210 VE FE 250 250 Note Surface mount PLCC package available for commercial and extended temperature ranges only Package Types NM27LV210 V F V e PLCC package F e TQFP
National Semiconductor
Original
C1996 V44A VEJ44A 576-B RRD-B30M17
Abstract: '- 1 - 1 - - Figure 3. 44-Pin PLCC Pin Configuration Table 2. 44-Pin PLCC Pin , Figure 5. 44-Pin PLCC Pin Configuration (EPROM Mode) Table 4. 44-Pin PLCC Pin Identification P in # 1 , 8K OTP FEATURES 40-Pin DIP or 44-Pin PLCC Package 4.5V to 5.5V Operating Range Low P ow e r C , Pin Configuration DS97KEY1800 3 ZlLOG Z 86E 23 K e ybo a r d C o ntro ller PIN , Pin Configuration (EPROM Mode) 5 ZlLOG Z 86E 23 K e ybo a r d C o ntro ller PIN -
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Z86E23 Z8602 P33-P30 P37P34

NM27LV210

Abstract: QQbTTQfi 555 H RRO-B20M114/Pnnted in U S A This Material Copyrighted By Its Respective Manufacturer PLCC Pin Configuration PLCC Pin Configuration TQFP Pin Configuration cT K °I2 | be: 6 5 4 3 2 1J 44 , 3.3V â'" 50 mW active power @ 3.3V â  Surface mount package options â'" 44-Pin PLCC â'" 44 Pin , prototyping and software development, PLCC for production runs, TQFP for PC board sensitive users. The , VE, FE, 150 150 NM27LV210 VE, FE, 200 200 NM27LV210 VE, FE, 250 250 Pin Names A0-A15 Addresses
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TL/D/11376-1

NM27LV210

Abstract: /D/11376 b5D112b OGbTTDfi B55 RR0-B20M114/Pnnted m U S A PLCC Pin Configuration PLCC Pin Configuration TQFP Pin Configuration o o lu x °i2 | ri] e 5 4 3 2 tl*4 43 42 41 40:iï >13 °12 44 43 42 4 1 , 3.3V â'" 50 mW active power @ 3.3V â  Surface mount package options _ 44-Pin PLCC â'" 44 Pin TQFP , prototyping and software development, PLCC for production runs, TQFP for PC board sensitive users. The , NM27LV210V, F, 250 250 Pin Names A0-A15 Addresses CE Chip Enable OÃ' Output Enable 00-015 Outputs P5M
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MAX184

Abstract: MAX525 Completely static operation INPUT/OUTPUT TTL compatible (three state output) 28-pin DIP 32-lead PLCC PIN CONFIGURATION (TOP VIEW) A6 [5 A5 [6 A4 [7 A3 [J A2 [J A1 fà AO [à NC [fi? 00 [¡3 ^ 5! 8: o 81? 2 < < > z , technology and is contained in 28-pin DIP or 32-tead PLCG package. (OKI can provide programming service as per customer's request.) FEATURES +5V single power supply 32,768-word x 8-bit configuration Access
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MAX525 MAX184 242M0 724E40 D013337 0G133MD
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