NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Part | Manufacturer | Description | Samples | Ordering |
| HLMP-K401-E0000 | Avago Technologies | Visible LED, T-1 SINGLE COLOR LED, ORANGE, 3 mm, PLASTIC PACKAGE-2 | 
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| HLMP-K401-EF000 | Avago Technologies | Visible LED, T-1 SINGLE COLOR LED, ORANGE, 3 mm, PLASTIC PACKAGE-2 |
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| HLMP-K401-E0002 | Avago Technologies | Visible LED, T-1 SINGLE COLOR LED, ORANGE, 3 mm, PLASTIC PACKAGE-2 |
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| HLMP-K401-FGD00 | Avago Technologies | Visible LED, T-1 SINGLE COLOR LED, ORANGE, 3 mm, PLASTIC PACKAGE-2 |
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| HLMP-K401 | Avago Technologies | Visible LED, T-1 SINGLE COLOR LED, ORANGE, 3 mm, PLASTIC PACKAGE-2 |
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| Catalog Datasheet Results | Type | Document Tags |
| Abstract: 1156 Ball Flip-Chip BGA (FF1156/FFG1156 FF1156/FFG1156) Package for Virtex-6 FPGAs PK401 (v1.0) January 7, 2010 X-Ref Target - Figure 1 pk401_01_121009 © 2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. PK401 (v1.0 , FPGAs Revision History The following table shows the revision history for this document. PK401 ... | Original |
2 pages, |
FFG1156 FF1156/FFG1156 PK401 FF1156/FFG1156 abstract |
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| Abstract: MOTOROLA Order this document by MRF1035MB/D MRF1035MB/D SEMICONDUCTOR TECHNICAL DATA The RF Line Microwave Pulse Power Transistors MRF1035MB MRF1035MB Designed for Class B and C common base amplifier applications in short and long pulse TACAN, IFF, DME, and radar transmitters. · Guaranteed Performance @ 1090 MHz, 50 Vdc Output Power = 35 Watts Peak Minimum Gain = 10 dB 35 W (PEAK), 960 1215 MHz MICROWAVE POWER TRANSISTORS NPN SILICON · 100% Tested for Load Mismatch at All Phase Angl ... | Original |
4 pages, |
MRF1035MB MRF1035MB/D MRF1035MB/D abstract |
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| Abstract: MOTOROLA Order this document by MRF1035MA/D MRF1035MA/D SEMICONDUCTOR TECHNICAL DATA The RF Line Microwave Pulse Power Transistors MRF1035MA MRF1035MA MRF1035MB MRF1035MB . . . designed for Class B and C common base amplifier applications in short and long pulse TACAN, IFF, DME, and radar transmitters. · Guaranteed Performance @ 1090 MHz, 50 Vdc Output Power = 35 Watts Peak Minimum Gain = 10 dB 35 W (PEAK), 960 1215 MHz MICROWAVE POWER TRANSISTORS NPN SILICON · 100% Tested for Load Mismatch ... | Original |
4 pages, |
MRF1035MB MRF1035MA MRF1035MA/D MRF1035MA/D abstract |
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| Abstract: The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. 32 SH7262 SH7262 Group, SH7264 SH7264 Group User's Manual: Hardware Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 SH7260 Series SH7262 SH7262 R5S72620 R5S72620 R5S72621 R5S72621 R5S72622 R5S72622 R5S72623 R5S72623 R5S72624 R5S72624 R5S72625 R5S72625 R5S72626 R5S72626 R5S72627 R5S72627 SH7264 SH7264 R5S72640 R5S72640 R5S72641 R5S72641 R5S72642 R5S72642 R5S72643 R5S72643 R5S72644 R5S72644 R5S72645 R5S72645 R5S72646 R5S72646 R5S ... | Original |
2162 pages, |
schematic diagram mac audio mpx 4000 SH7264 bosch edc 16 bosch edc 17 R5S72645 SH7262 SH7260 SH7262 abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
| Over 1.1 million files (1986-2013): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer. |
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| begin 755 psplit M 0,!"P ! , " @ "\$" T .@0)(#H$25 M*B "E *@!)0"0 H7 !(U"+@ , C" &(@) 0* 0! 0 "@$ M ! !1[ 0 $ Q6 www.datasheetarchive.com/download/86338383-960526ZC/psplit.uu |
Xilinx | 05/09/1996 | 154.34 Kb | UU | psplit.uu |
| ;: ftopa.lca (4005EPG156-3 4005EPG156-3 4005EPG156-3 4005EPG156-3), xdelay 5.0.24, Wed Oct 4 14:04:49 1995 Version 2 Design 4005EPG156 4005EPG156 4005EPG156 4005EPG156 4 0 Speed -3 Addnet CLK bufgs_bl.O KD.K LD.K Netdelay CLK KD.K 1.3 LD.K 1.3 Program CLK {160G251 160G251 160G251 160G251} {160G295 160G295 160G295 160G295} {160G377 160G377 160G377 160G377} NProgram CLK col.D.long.9:LD.K col.D.long.9:KD.K col.D.long.9:bufgs_bl.O Addnet CLKP i_bufgs_bl.I bufgs_bl.I Netdelay CLKP bufgs_bl.I 3.9 Program CLKP {27G28 27G28 27G28 27G28} NProgram CLKP i_bufgs_bl.I:bufgs_bl.I Addnet DI0 PAD101 PAD101 PAD101 PAD101.I1 HB.F4 Netdelay DI0 HB.F4 1.2 Program DI0 {80G409 80G409 80G409 80G409} {35G409 35G409 35G409 35G409 www.datasheetarchive.com/files/xilinx/pci/xc4000e/ftopa.lca |
Xilinx | 12/10/1995 | 67.09 Kb | LCA | ftopa.lca |
| ;: res_no_share.lca (4005PC84-5 4005PC84-5 4005PC84-5 4005PC84-5), xdelay Beta-5.2.0b, Fri Jun 2 17:02:48 1995 Version 2 Design 4005PC84 4005PC84 4005PC84 4005PC84 4 0 Speed -5 Addnet add_17/n27 GB.X HB.F4 Netdelay add_17/n27 HB.F4 1.2 Program add_17/n27 {79G418 79G418 79G418 79G418} {72G418 72G418 72G418 72G418} NProgram add_17/n27 row.H.local.2:HB.F4 row.H.local.2:GB.X Addnet add_17/n28 GB.Y LD.F1 MD.F1 Netdelay add_17/n28 LD.F1 3.2 MD.F1 3.2 Program add_17/n28 {137G204 137G204 137G204 137G204} {137G248 137G248 137G248 137G248} {137G358 137G358 137G358 137G358} {107G358 107G358 107G358 107G358} {100G365 100G365 100G365 100G365} {100G409 100G409 100G409 100G409} {100G420 100G420 100G420 100G420} {100G442 100G442 100G442 100G442} NProgram add_17/n28 col.D.long.1:MD.F1 col.D.l www.datasheetarchive.com/files/xilinx/bbs/swhlp/synopsys/verilog/res_shar/res_no_s.lca |
Xilinx | 02/06/1995 | 27.48 Kb | LCA | res_no_s.lca |
| ;: gate_red_dw.lca (4005PC84-5 4005PC84-5 4005PC84-5 4005PC84-5), ppr Xilinx:ppr:beta-5.2.0a:95/05/24, 1995/05/31 09:34:57 Version 2 Design 4005PC84 4005PC84 4005PC84 4005PC84 Speed -5 Addnet n95 NC.G1 PC.F4 OC.X NProgram n95 NC.G1:col.C.local.7 OC.40.1.6 OC.40.1.23 OC.X:col.C.local.7 PC.F4:row.P.local.2 OC.X:row.P.local.2 Addnet n14_2 PAD83 PAD83 PAD83 PAD83.I2 KB.F3 OC.C1 NProgram n14_2 KB.F3:col.C.long.2 OC.C1:col.C.long.2 PAD83 PAD83 PAD83 PAD83.I2:col.C.long.2 Addnet n14_1 PAD83 PAD83 PAD83 PAD83.I1 NC.F1 NC.G2 PC.F1 NProgram n14_1 NC.F1:col.C.local.0 OC.40.1.0 OC.40.1.29 NC.G2:row.O.local.10 OC.40.1. www.datasheetarchive.com/files/xilinx/bbs/swhlp/synopsys/vhdl/gate_red/gate_re0.odf |
Xilinx | 31/05/1995 | 44.63 Kb | ODF | gate_re0.odf |
| ;: gate_red_dw.lca (4005PC84-5 4005PC84-5 4005PC84-5 4005PC84-5), xdelay Pre-5.2.0h, Wed May 31 09:35:29 1995 Version 2 Design 4005PC84 4005PC84 4005PC84 4005PC84 4 0 Speed -5 Addnet _cell_381/DATA1 381/DATA1 381/DATA1 381/DATA1_0 HH.Y HH.C3 Netdelay _cell_381/DATA1 381/DATA1 381/DATA1 381/DATA1_0 HH.C3 1.3 Program _cell_381/DATA1 381/DATA1 381/DATA1 381/DATA1_0 {369G395 369G395 369G395 369G395} {369G398 369G398 369G398 369G398} NProgram _cell_381/DATA1 381/DATA1 381/DATA1 381/DATA1_0 col.J.local.4:HH.C3 col.J.local.4:HH.Y Addnet _cell_383/DATA1 383/DATA1 383/DATA1 383/DATA1_0 JH.X JH.G2 Netdelay _cell_383/DATA1 383/DATA1 383/DATA1 383/DATA1_0 JH.G2 1.2 Program _cell_383/DATA1 383/DATA1 383/DATA1 383/DATA1_0 {346G319 346G319 346G319 346G319} {336G319 336G319 336G319 336G319} NProgram _cell_383/DATA1 383/DATA1 383/DATA1 383/DATA1_0 row.K.local.2:JH.G2 row.K.local.2:JH.X Addnet www.datasheetarchive.com/files/xilinx/bbs/swhlp/synopsys/vhdl/gate_red/gate_re0.lca |
Xilinx | 31/05/1995 | 63.48 Kb | LCA | gate_re0.lca |
| ;: res_xblox_share.lca (4005PC84-5 4005PC84-5 4005PC84-5 4005PC84-5), xdelay Beta-5.2.0b, Fri Jun 2 18:39:13 1995 Version 2 Design 4005PC84 4005PC84 4005PC84 4005PC84 4 0 Speed -5 Addnet _CELL_135/Z 135/Z 135/Z 135/Z_0 GC.X OC.F2 Netdelay _CELL_135/Z 135/Z 135/Z 135/Z_0 OC.F2 4.6 Program _CELL_135/Z 135/Z 135/Z 135/Z_0 {122G93 122G93 122G93 122G93} {135G93 135G93 135G93 135G93} {135G357 135G357 135G357 135G357} {107G357 107G357 107G357 107G357} {99G365 99G365 99G365 99G365} {99G409 99G409 99G409 99G409} {99G420 99G420 99G420 99G420} {99G433 99G433 99G433 99G433} NProgram _CELL_135/Z 135/Z 135/Z 135/Z_0 row.P.local.8:OC.F2 col.D.long.0:row.P.local.8-l col.D.long.0:row.J.local.8-s JC.40.1.17 JC.40.1.2 HC.40.1.27 HC.40.1.2 col.C.local.3:GC.X Addnet _CELL_135/Z 135/Z 135/Z 135/Z_1 OD.X OC.G1 Netdelay _CELL_135/ www.datasheetarchive.com/files/xilinx/bbs/swhlp/synopsys/verilog/res_shar/res_xbl1.lca |
Xilinx | 02/06/1995 | 23.7 Kb | LCA | res_xbl1.lca |
| ;: res_xblox_share.lca (4005PC84-5 4005PC84-5 4005PC84-5 4005PC84-5), ppr Xilinx:ppr:Beta-5.2.0a:95/05/30, 1995/06/02 18:38:59 Version 2 Design 4005PC84 4005PC84 4005PC84 4005PC84 Speed -5 Addnet R52/U8/S0 R52/U8/S0 R52/U8/S0 R52/U8/S0_1/CO_0 PC.COUT OC.CIN NProgram R52/U8/S0 R52/U8/S0 R52/U8/S0 R52/U8/S0_1/CO_0 OC.CIN:PC.COUT Addnet R52/U8/S0 R52/U8/S0 R52/U8/S0 R52/U8/S0_1/CO_2 OC.COUT NC.CIN NProgram R52/U8/S0 R52/U8/S0 R52/U8/S0 R52/U8/S0_1/CO_2 NC.CIN:OC.COUT Addnet _CELL_136/Z 136/Z 136/Z 136/Z_0 OC.F1 OK.X NProgram _CELL_136/Z 136/Z 136/Z 136/Z_0 OC.F1:col.C.local.3 col.C.local.3:row.O.long.5-S row.O.long.5:col.I.local.1 col.K.local.3:row.O.long.5-L OK.X:col.K.local.3 Addnet _CELL_135/Z 135/Z 135/Z 135/Z_0 OC.F2 GC.X www.datasheetarchive.com/files/xilinx/bbs/swhlp/synopsys/verilog/res_shar/res_xbl1.odf |
Xilinx | 02/06/1995 | 17.55 Kb | ODF | res_xbl1.odf |
| ;: res_no_share.lca (4005PC84-5 4005PC84-5 4005PC84-5 4005PC84-5), ppr Xilinx:ppr:Beta-5.2.0a:95/05/30, 1995/06/02 17:02:12 Version 2 Design 4005PC84 4005PC84 4005PC84 4005PC84 Speed -5 Addnet n164 PAD10 PAD10 PAD10 PAD10.I2 HC.F3 EC.F3 HD.F3 GD.F3 OG.F1 OH.F2 NK.F2 JL.F1 NProgram n164 HC.F3:col.D.long.5 EC.F3:col.D.long.5 row.B.local.3:col.D.long.5-L BE.40.1.12 BE.40.1.37 HD.F3:col.E.long.5 GD.F3:col.E.long.5 NProgram n164 row.B.local.3:col.E.long.5-L BF.40.1.12 BF.40.1.37 PAD10 PAD10 PAD10 PAD10.I2:row.B.local.3 OG.F1:col.G.long.0 OH.F2:row.P.local.8 NK.F2:row.O.local.8 NProgram n164 ro www.datasheetarchive.com/files/xilinx/bbs/swhlp/synopsys/verilog/res_shar/res_no_s.odf |
Xilinx | 02/06/1995 | 20.25 Kb | ODF | res_no_s.odf |
| ;: plgply.lca (4005PQ160-6 4005PQ160-6 4005PQ160-6 4005PQ160-6), xdelay 5.1.0, Fri May 19 13:26:54 1995 Version 2 Design 4005PQ160 4005PQ160 4005PQ160 4005PQ160 4 0 Speed -6 Addnet $1N199 1N199 1N199 1N199 EH.X TBUF.BK.1.T TBUF.BK.2.T TBUF.CK.2.T TBUF.CK.1.T TBUF.DK.2.T TBUF.DK.1.T TBUF.EK.2.T TBUF.EK.1.T DH.F1 Netdelay $1N199 1N199 1N199 1N199 TBUF.BK.1.T 4.3 TBUF.BK.2.T 4.3 TBUF.CK.2.T 4.3 TBUF.CK.1.T 4.3 TBUF.DK.2.T 4.3 TBUF.DK.1.T 4.3 TBUF.EK.2.T 4.3 TBUF.EK.1.T 4.3 DH.F1 2.8 Program $1N199 1N199 1N199 1N199 {404G667 404G667 404G667 404G667} {404G649 404G649 404G649 404G649} {404G623 404G623 404G623 404G623} {404G605 404G605 404G605 404G605} {404G579 404G579 404G579 404G579} {404G561 404G561 404G561 404G561} {404G535 404G535 404G535 404G535} {404G517 404G517 404G517 404G517} {404G500 404G500 404G500 404G500} {376 www.datasheetarchive.com/download/24288047-960681ZC/plugplay.zip (PLGPLY.LCA) |
Xilinx | 20/05/1995 | 240.04 Kb | ZIP | plugplay.zip |
| ;: gate_red_dw.lca (4005PC84-5 4005PC84-5 4005PC84-5 4005PC84-5), xdelay Pre-5.2.0h, Wed May 31 09:35:29 1995 Version 2 Design 4005PC84 4005PC84 4005PC84 4005PC84 4 0 Speed -5 Addnet _cell_381/DATA1 381/DATA1 381/DATA1 381/DATA1_0 HH.Y HH.C3 Netdelay _cell_381/DATA1 381/DATA1 381/DATA1 381/DATA1_0 HH.C3 1.3 Program _cell_381/DATA1 381/DATA1 381/DATA1 381/DATA1_0 {369G395 369G395 369G395 369G395} {369G398 369G398 369G398 369G398} NProgram _cell_381/DATA1 381/DATA1 381/DATA1 381/DATA1_0 col.J.local.4:HH.C3 col.J.local.4:HH.Y Addnet _cell_383/DATA1 383/DATA1 383/DATA1 383/DATA1_0 JH.X JH.G2 Netdelay _cell_383/DATA1 383/DATA1 383/DATA1 383/DATA1_0 JH.G2 1.2 Program _cell_383/DATA1 383/DATA1 383/DATA1 383/DATA1_0 {346G319 346G319 346G319 346G319} {336G319 336G319 336G319 336G319} NProgram _cell_383/DATA1 383/DATA1 383/DATA1 383/DATA1_0 row.K.local.2:JH.G2 row.K.local.2:JH.X Addnet www.datasheetarchive.com/download/61635476-996530ZC/xsi_vhdl.tar |
Xilinx | 09/04/1997 | 12384 Kb | TAR | xsi_vhdl.tar |