PK100 PQ100 HQ160 PQ160 HQ208 PQ208 HQ240 PQ240 HQ304 MS022 BG225 BG256 BG352 - Datasheet Archive
Packages and Thermal Characteristics: High-Reliability Products R 0 5 PK100 (v1.0) June 15, 2000 Package Information Inches vs.
0 Packages and Thermal Characteristics: High-Reliability Products R 0 5 PK100 PK100 (v1.0) June 15, 2000 Package Information Inches vs. Millimeters The JEDEC standards for PLCC, CQFP, and PGA packages define package dimensions in inches. The lead spacing is specified as 25, 50, or 100 mils (0.025", 0.050" or 0.100"). The JEDEC standards for PQFP and HQFP packages define package dimensions in millimeters. These packages have a lead spacing of 0.5 mm, 0.65 mm, or 0.8 mm. Because of the potential for measurement discrepancies, this Data Book provides measurements in the controlling standard only, either inches or millimeters. (See Table 1 for package dimensions.) M ID e e e M IE b2 e l2 PK100 PK100_01_060100 Figure 1: EIA Standard Board Layout of Soldered Pads for QFP Devices Table 1: Dimensions for Xilinx Quad Flat Packs(1) Dimension PQ100 PQ100 HQ160 HQ160, PQ160 PQ160 HQ208 HQ208, PQ208 PQ208 HQ240 HQ240, PQ240 PQ240 HQ304 HQ304 MID 20.40 28.40 28.20 32.20 40.20 MIE 14.40 28.40 28.20 32.20 40.20 e 0.65 0.65 0.50 0.50 0.50 b2 0.3-0.5 0.3-0.5 0.3-0.4 0.3-0.4 0.3-0.4 I2 1.80(2) 1.80 1.60 1.60 1.60 Notes: 1. Dimensions in millimeters 2. For 3.2 mm, footprint per MS022 MS022, JEDEC Publication 95. © 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. PK100 PK100 (v1.0) June 15, 2000 www.xilinx.com 1-800-255-7778 1 R Packages and Thermal Characteristics: High-Reliability Products Suggested Board Layout of Soldered Pads for BGA, CGA and FG Packages VL VL VH VH W W D D L L M M Mask Opening Overlaps Land Mask Opening Outside of Land e e Solder Mask Defined Land Patterns are recommended for BG. Non-Solder Mask Defined Land Patterns or Land Defined land Patterns are recommended for FG. PK100 PK100_02_060100 Figure 2: Suggested Board Layout of Soldered Pads for BGA and FG Packages Table 2: Soldering Dimensions for BG and CG Packages BG225 BG225 BG256 BG256 BG352 BG352 BG432 BG432 BG560 BG560 CG560 CG560 Solder Land (L) diameter 0.89 0.79 0.79 0.79 0.79 0.79 Opening in Solder Mask (M) diameter 0.65 0.58 0.58 0.58 0.58 0.58 Solder (Ball) Land Pitch (e) 1.5 1.27 1.27 1.27 1.27 1.27 Line Width between Via and Land (W) 0.3 0.3 0.3 0.3 0.3 0.3 Distance between Via and Land (D) 1.06 0.9 0.9 0.9 0.9 0.9 Via Land (VL) diameter 0.65 0.65 0.65 0.65 0.65 0.65 Through Hole (VH) diameter 0.3 0.3 0.3 0.3 0.3 0.3 Pad Array Full - - - - - 15 x 15 20 x 20 26 x 26 31 x 31 33 x 33 33 x 33 - 4 4 4 5 5 Matrix or External Row Periphery rows 2 www.xilinx.com 1-800-255-7778 PK100 PK100 (v1.0) June 15, 2000 R Packages and Thermal Characteristics: High-Reliability Products Table 3: Soldering Dimensions for FG Packages FG256 FG256 FG456 FG456 FG556 FG556 FG676 FG676 FG680 FG680 FG860 FG860 FG900 FG900 FG1156 FG1156 Solder Land (L) diameter 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 Opening in Solder Mask (M) diameter 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 Solder (Ball) Land Pitch (e) 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Line Width between Via and Land (W) 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 Distance between Via and Land (D) 0.7 0.7 0.7 0.7 0.7 0.7 0.7 0.7 Via Land (VL) diameter 0.61 0.61 0.61 0.61 0.61 0.56 0.61 0.61 Through Hole (VH) diameter 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 Pad Array Full Full - Full - - Full Full 16 x 16 22 x 22 30 x 30 26 x 26 39 x 39 42 x 42 30 x 30 34 x 34 - - 7 - 5 6 - - Matrix or External Row Periphery rows Cavity Up or Cavity Down Most Xilinx devices attach the die against the inside bottom of the package (the side that does not carry the Xilinx logo). This is called cavity-up, and has been the standard IC assembly method for over 25 years. This method does not provide the best thermal characteristics. Pin Grid Arrays (greater than 130 pins) and Ceramic Quad Flat Packs are assembled "Cavity Down", with the die attached to the inside top of the package, for optimal heat transfer to the ambient air. For most packages this information does not affect how the package is used because the user has no choice in how the package is mounted on a board. For Ceramic Quad Flat Pack (CQFP) packages however, the leads can be formed to either side. Therefore, for best heat transfer to the surrounding air, CQFP packages should be mounted with the logo up, facing away from the PC board. Clockwise or Counterclockwise The orientation of the die in the package and the orientation of the package on the PC board affect the PC board layout. PLCC and PQFP packages specify pins in a counterclockwise direction, when viewed from the top of the package (the surface with the Xilinx logo). PLCCs have pin 1 in the center of the beveled edge while all other packages have pin 1 in one corner, with one exception: The 100-pin and 165-pin CQFPs (CB100 CB100 and CB164 CB164) for the XC3000 XC3000 devices have pin 1 in the center of one edge. CQFP packages specify pins in a clockwise direction, when viewed from the top of the package. The user can make the pins run counterclockwise by forming the leads such that the logo mounts against the PC board. However, heat flow to the surrounding air is impaired if the logo is mounted down. Thermal Management PK100 PK100 (v1.0) June 15, 2000 Modern high-speed logic devices consume an appreciable amount of electrical energy. This energy invariably turns into heat. Higher device integration drives technologies to produce smaller device geometry and interconnections. With smaller chip sizes and higher circuit densities, heat generation on a fast switching CMOS circuit can be very significant. The heat removal needs for these modern devices must be addressed. Managing heat generation in a modern CMOS logic device is an industry-wide pursuit. However, unlike the power needs of a typical Application Specific Integrated Circuit (ASIC) gate array, the power requirements for FPGAs are not determined as the device leaves the factory. Designs vary in power needs. www.xilinx.com 1-800-255-7778 3 R Packages and Thermal Characteristics: High-Reliability Products There is no way of anticipating the power needs of an FPGA device short of depending on compiled data from previous designs. For each device type, primary packages are chosen to handle "typical" designs and gate utilization requirements. For the most part the choice of a package as the primary heat removal casing works well. Occasionally designers exercise an FPGA device, particularly the high gate count variety, beyond "typical" designs. The use of the primary package without enhancement may not adequately address the device's heat removal needs. Heat removal management through external means or an alternative enhanced package should be considered. Removing heat ensures the functional and maximum design temperature limits are maintained. The device may go outside the temperature limits if heat build up becomes excessive. As a consequence, the device may fail to meet electrical performance specifications. It is also necessary to satisfy reliability objectives by operating at a lower temperature. Failure mechanisms and the failure rate of devices depend on device operating temperature. Control of the package and the device temperature ensures product reliability. Package Thermal Characterization Methods and Conditions Method and Calibration Xilinx uses the indirect electrical method for package thermal resistance characterization. The forward-voltage drop of an isolated diode residing on a special test die is calibrated at constant forcing current of 0.520 mA with respect to temperature over a correlation temperature range of 22°C to 125°C (degree Celsius). The calibrated device is then mounted in an appropriate environment (still air, forced convection, circulating FC-40 FC-40, etc.) Depending on the package, between 0.5 to 4 watts of power (Pd) is applied. Power (Pd) is applied to the device through diffused resistors on the same thermal die. The resulting rise in junction temperature is monitored with the forward-voltage drop of the precalibrated diode. Typically, three identical samples are tested at each data point. The reproducibility error in the setup is within 6%. Definition of Terms TJ TA Ambient Temperature - expressed in °C. TC The temperature of the package body taken at a defined location on the body. This is taken at the primary heat flow path on the package and represents the hottest part on the package - expressed in °C. Tl The isothermal fluid temperature when junction to case temperature is taken - expressed in °C. Pd 4 Junction Temperature - the maximum temperature on the die, expressed in °C The total device power dissipation - expressed in watts. www.xilinx.com 1-800-255-7778 PK100 PK100 (v1.0) June 15, 2000 R Packages and Thermal Characteristics: High-Reliability Products Junction-to-Reference General Setup ENVIRONMENT D Constant Current Source Resistor Supply R VF VR DUT IF IR Environment may be: Still or Forced Air - JA D = Sensing Diode R = Diffused Resistors Data Acquisition and Control Computer PK100 PK100_01_060100 Figure 3: Thermal Measurement Set-Up (Schematic for Junction to Reference) Junction-to-Case Measurement - JC JC is measured in a 3M Flourinert (FC-40 FC-40) isothermal circulating fluid stabilized at 25°C. The Device Under Test (DUT) is completely immersed in the fluid and initial stable conditions are recorded. Pd is then applied. Case temperature (TC) is measured at the primary heat-flow path of the particular package. Junction temperature (TJ) is calculated from the diode forwardvoltage drop from the initial stable condition before power was applied. JC = (TJ - TC)/Pd The junction-to-isothermal-fluid measurement (JI) is also calculated from the same data. JL = (TJ - TI)/Pd The latter data is considered as the ideal JA data for the package that can be obtained with the most efficient heat removal scheme. Other schemes such as airflow, heatsinks, use of copper clad board, or some combination of all these will tend towards this ideal figure. Since this is not a widely used parameter in the industry, and it is not very realistic for normal application of Xilinx packages, the JI data is not published. The thermal lab keeps such data for package comparisons. PK100 PK100 (v1.0) June 15, 2000 www.xilinx.com 1-800-255-7778 5 R Packages and Thermal Characteristics: High-Reliability Products Junction-to-Ambient Measurement - JA JA is measured on FR4 based PC boards measuring 4.5" x 6.0" x .0625" (114.3mm x 152.4mm x 1.6mm) with edge connectors. There are two main board types. Type I, 2L/0P board, is single layer with two signal planes (one on each surface) and no internal Power/GND planes. The trace density on this board is less than 10% per side. Type II, the 4L/2P board, has two internal copper planes (one power, one ground) and two signal trace layers on both surfaces. Data may be taken with the package mounted in a socket or with the package mounted directly on the board. Socket measurements typically use the 2L/0P boards. SMT devices may use either board. Published data always reflects the board and mount conditions used. Data is taken at the prevailing temperature and pressure conditions (22°C to 25°C ambient). The board with the DUT is mounted in a cylindrical enclosure. The power application and signal monitoring are the same as JC measurements. The enclosure (ambient) thermocouple is substituted for the fluid thermocouple and two extra thermocouples brought in to monitor room and board temperatures. The junction to ambient thermal resistance is calculated as follows: JA = (TJ - TA)/Pd The setup described herein lends itself to the application of various airflow velocities from 0-800 Linear feet per minute (LFM), i.e., 0-4.06 m/s. Since the board selection (copper trace density, absence or presence of ground planes, etc.) affects the results of the thermal resistance, the data from these tests shall always be qualified with the board mounting information. Data Acquisition and Package Thermal Database Xilinx gathers data for a package type in die sizes, power levels and cooling modes (air flow and sometimes heatsink effects) with a Data Acquisition and Control system (DAS). The DAS controls the power supplies and other ancillary equipment for hands-free data taking. Different setups within the DAS software are used to run calibration, JA, JC, fan tests, as well as the power effect characteristics of a package. A package is characterized with respect to the major variables that influence the thermal resistance. The results are stored in a database. Thermal resistance data is interpolated as typical values for the individual Xilinx devices that are assembled in the characterized package. Table 4 shows the typical values for different packages. Specific device data may not be the same as the typical data. However, the data will fall within the given minimum and maximum ranges. The more widely used packages will have a wider range. Customers may contact the Xilinx application group for specific device data. Table 4: Summary of Thermal Resistance for Packages(1,2,3) Package Code BG225 BG225 BG256 BG256 BG352 BG352 BG432 BG432 CG560 CG560 CB100 CB100 CB164 CB164 CB196 CB196 CB228 CB228 6 JA Still Air (Max) °C/Watt 37 32 14 13 10 44 29 25 19 JA Still Air (Typ) °C/Watt 30 29 12 11 9 41 26 24 18 JA Still Air (Min) °C/Watt 24 24 10 9 8 38 25 24 17 JA 250 LFM (Typ) °C/Watt 19 19 8 8 7 25 17 15 11 JA 500 LFM (Typ) °C/Watt 17 17 7 6 6 19 12 11 8 www.xilinx.com 1-800-255-7778 JA 750 LFM (Typ) °C/Watt 16 16 6 6 5 17 11 10 7 JC (Typ) °C/Watt 3.3 3.2 0.8 0.8 0.8 5.1 3.6 1.8 1.3 Comments Various 4L/2P-SMT(4) 4L/2P-SMT(4) 4L/2P-SMT(4) Estimated Socketed Socketed Socketed Socketed PK100 PK100 (v1.0) June 15, 2000 R Packages and Thermal Characteristics: High-Reliability Products Table 4: Summary of Thermal Resistance for Packages(1,2,3) (Continued) Package Code DD8 HQ160 HQ160 FG256 FG256 FG456 FG456 FG556 FG556 FG676 FG676 FG680 FG680 FG860 FG860 FG900 FG900 FG1156 FG1156 HQ208 HQ208 HQ240 HQ240 HQ304 HQ304 PC20 PC44 PC68 PC84 PD8 PG84 PG120 PG120 PG132 PG132 PG156 PG156 PG175 PG175 PG191 PG191 PG223 PG223 PG299 PG299 PG411 PG411 PG475 PG475 PG559 PG559 PQ100 PQ100 PQ160 PQ160 PQ208 PQ208 PQ240 PQ240 SO8 JA Still Air (Max) °C/Watt 114 14 27 19 14 17 11 10 14 14 15 13 11 86 51 46 41 82 37 32 32 25 25 24 24 18 16 14 35 37 35 28 147 JA Still Air (Typ) °C/Watt 109 14 25 18 14 17 11 10 14 13 14 12 11 84 46 42 33 79 34 27 28 23 23 21 20 17 15 13 12.00 33 32 32 23 147 JA Still Air (Min) °C/Watt 97 14 23 17 14 17 10 10 14 13 14 12 10 76 42 38 28 73 31 25 24 21 20 18 18 16 14 12 32 22 26 19 147 JA 250 LFM (Typ) °C/Watt 90 10 21 14 10 13 8 7 10 10 10 9 7 63 35 31 25 60 24 19 20 15 14 15 15 10 9 9 29 24 23 17 112 JA 500 LFM (Typ) °C/Watt 73 8 20 13 9 12 6 6 9 9 8 7 5 56 31 28 21 54 18 15 17 11 11 12 12 9 8 8 28 21 21 15 105 JA 750 LFM (Typ) °C/Watt 60 7 19 13 9 12 6 5 9 9 7 6 5 53 29 26 17 50 16 13 15 10 10 11 11 8 7 7 27 20 19 14 98 JC (Typ) °C/Watt 8.2 1.0 3.9 1.5 0.8 0.9 0.9 0.8 0.8 0.8 1.7 1.5 0.9 25.8 13.7 9.3 5.3 22.2 5.8 3.6 2.8 2.6 2.6 1.5 1.5 1.9 1.2 1.2 5.5 4.6 4.3 2.8 48.3 Comments Socketed 4L/2P-SMT(4) 4L/2P-SMT(4) 4L/2P-SMT(4) 4L/2P-SMT(4) 4L/2P-SMT(4) 4L/2P-SMT(4) 4L/2P-SMT(4) Estimated Estimated 4L/2P-SMT(4) 4L/2P-SMT(4) 4L/2P-SMT(4) 2L/0P-SMT(5) 2L/0P-SMT(5) 2L/0P-SMT(5) 2L/0P-SMT(5) Socketed Socketed Socketed Socketed Socketed Socketed Socketed Socketed Socketed Socketed Socketed Estimated 4L/2P-SMT(4) 2L/0P-SMT(5) 2L/0P-SMT(5) 2L/0P-SMT(5) IEEE-(Ref) Notes: 1. Maximum, typical and minimum numbers are based on numbers for all the devices in the specific package at the time of compilation. The numbers do not necessarily reflect the absolute limits of that packages. Specific device data should lie within the limits. Packages used for a broader spectrum of devices have a wider range in the table. Specific device data in a package may be obtained from the factory. 2. Package configurations and drawings can be found on the Xilinx web site: www.xilinx.com/partinfo/databook.htm 3. Air flow is given Linear Feet per Minute (LFM). 500 LFM = 2.5 Meters per second. 4. 4L/2P-SMT: the data is from a 4-layer SMT board incorporating 2 internal planes. Socketed data is taken in socket. 5. 2L/0P-SMT: the data is from a surface mount Type I board-no internal planes on the board. PK100 PK100 (v1.0) June 15, 2000 www.xilinx.com 1-800-255-7778 7 R Packages and Thermal Characteristics: High-Reliability Products Application of Thermal Resistance Data Thermal resistance data gauges the IC package thermal performance. JC measures the internal package resistance to heat conduction from the die surface, through the die mount material to the package exterior. JC strongly depends on the package's heat conductivity, architecture and geometrical considerations. JA measures the total package thermal resistance including JC. JA depends on the package material properties and such external conditions as convective efficiency and board mount conditions. For example, a package mounted on a socket may have a JA value 20% higher than the same package mounted on a 4-layer board with power and ground planes. By specifying a few constraints, devices are ensured to operate within the intended temperature range. This also ensures device reliability and functionality. The system ambient temperature needs to be specified. A maximum TJ also needs to be established for the system. The following inequality will hold. TJ(max) > JA* Pd +TA The following two examples illustrates the use of this inequality. Example 1: The manufacturer's goal is TJ (max) < 100°C A module is designed for a TA = 45°C max. A XC3042 XC3042 in a PLCC 84 has a JA = 32°C/watt. Given a XC3042 XC3042 with a logic design with a rated power Pd of 0.75watt. With this information, the maximum die temperature can be calculated as: TJ = 45 + (32 x 0.75) 69°C. The system manufacturer's goal of TJ < 100°C is met. Example 2: A module has a TA = 55°C max. The Xilinx XC4013E XC4013E is in a PQ240 PQ240 package (HQ240 HQ240 is also considered). A XC4013E XC4013E, in an example logic design, has a rated power of 2.50 watts. The module manufacturers goal is TJ (max.) < 100°C. Table 5 shows the package and thermal enhancement combinations required to meet the goal of TJ < 100°C. Table 5: Thermal Resistance for XC4013E XC4013E in PQ240 PQ240 and HQ240 HQ240 Packages Device Name Package JA Still Air JA (250 LFM) JA (500 LFM) JA (750 LFM) JC Comments XC4013E XC4013E PQ240 PQ240 23.7 17.5 15.4 14.3 2.7 Cu, SMT 2L/0P XC4013E XC4013E HQ240 HQ240 12.5 8.6 6.9 6.2 1.5 4-layer board data Notes: 1. Possible Solutions to meet the module requirements of 100°C : 2. Using the standard PQ240 PQ240; TJ = 55 + (23.7 x 2.50) 114.25°C. 3. Using standard PQ240 PQ240 with 250LFM 250LFM forced air; TJ = 55 + (17.5 x 2.50) 98.75°C 4. Using standard HQ240 HQ240, TJ = 55 + (12.5 x 2.50) 86.25°C 5. Using HQ240 HQ240 with 250 LFM forced air; TJ = 55 + (8.6 x 2.50) 76.5°C 8 www.xilinx.com 1-800-255-7778 PK100 PK100 (v1.0) June 15, 2000 R Packages and Thermal Characteristics: High-Reliability Products For all solutions, the junction temperature is calculated as: TJ = Power x JA + TA. All solutions meet the module requirement of less than 100°C, with the exception of the PQ240 PQ240 package in still air. In general, depending on ambient and board temperatures conditions, and most importantly the total power dissipation, thermal enhancements - such as forced air cooling, heat sinking, etc. may be necessary to meet the TJ(max) conditions set. Thermal Data Comparison Charts The following charts (Figures 4, 5, 6, 7, and 8) are for reference only. HQ/PQ Thermal Data Size Effect on JA 35 30 JA (°C/watt) 25 HQ208 HQ208 20 HQ240 HQ240 15 HQ304 HQ304 PQ208 PQ208 10 PQ240 PQ240 5 200 300 400 500 600 700 Die size (mils) PK100 PK100_04_060100 Figure 4: HQ/PQ Thermal Data (Size Effect on JA) HQ/PQ Thermal Data Effect of Forced Air on JA 30 JA (°C/watt) 25 XC4010E-HQ208 XC4010E-HQ208 XC4010E-PQ208 XC4010E-PQ208 20 XC4013E-HQ240 XC4013E-HQ240 XC4013E-PQ240 XC4013E-PQ240 XC4025E-HQ304 XC4025E-HQ304 15 10 5 0 0 200 400 600 800 Airflow - LFM PK100 PK100_05_060100 Figure 5: HQ/PQ Thermal Data (Effect of Forced Air on JA) PK100 PK100 (v1.0) June 15, 2000 www.xilinx.com 1-800-255-7778 9 R Packages and Thermal Characteristics: High-Reliability Products PGA Thermal Resistance Effect of Air Flow on JA 25 PG191-XC4010E PG191-XC4010E PG299-XC4025E PG299-XC4025E JA (°C/watt) 20 PG223-XC4013E PG223-XC4013E PG299-FHS PG299-FHS(XC4025E XC4025E) 15 10 5 0 0 100 200 300 400 500 600 700 Air Flow - LFM PK100 PK100_06_060100 Figure 6: PGA Thermal Data (Effect of Air Flow on JA) PGA Thermal Resistance Effects of Active and Passive Heat sinks 20 JA (°C/watt) 15 10 5 0 A B C D E F PGA - Various Enhancements A. Standard Pkg B. Pkg + Finned HS (Passive) C. Pkg +Active Fan (V=0) D. Pkg + Active Fan (V=12) E. Std Pkg + 250 LFM F. Pkg + Finned HS + 250 LFM PK100 PK100_07_060100 Figure 7: PGA Thermal Data (Effects of Active and Passive Heat Sinks) 10 www.xilinx.com 1-800-255-7778 PK100 PK100 (v1.0) June 15, 2000 R Packages and Thermal Characteristics: High-Reliability Products BGA/CGA Thermal Resistance Effect of Air Flow on JA 40 XC4010E-BG225 XC4010E-BG225 (2L) XC73108-BG225 XC73108-BG225(2L) 35 XC4013E-BG225 XC4013E-BG225(4L) XC5210-BG225 XC5210-BG225(2L) XC73144-BG225 XC73144-BG225(4L) JA (°C/watt) 30 25 20 15 10 0 200 400 600 800 Air Flow - LFM PK100 PK100_08_060100 Figure 8: BGA/CGA Thermal Data (Effect of Air Flow on JA) Some Power Management Options FPGA devices are usually not the dominating power consumers in a system, and do not have a big impact on power supply designs. There are obvious exceptions. When the actual or estimated power dissipation appears to be more than the specification of the chosen package, some options can be considered. Details on the engineering designs and analysis of some of these suggested considerations may be obtained from the references listed at the end of the section. The options include: · · · · PK100 PK100 (v1.0) June 15, 2000 Explore thermally enhanced package options available for the same device. As illustrated above, the HQ240 HQ240 package has a thermal impedance of about 50% of the equivalent PQ240 PQ240. Besides, the 240 lead, the 208 lead and the 304 lead Quad packages have equivalent heatsink enhanced versions. Typically 25% to 40% improvement in thermal performance can be expected from these heatsink enhanced packages. Most of the high gate count devices above the XC4013 XC4013 level come either exclusively in heat enhanced packages or have these packages as options. If the use of a standard PQ appears to be a handicap in this respect, a move to the equivalent HQ package if available may resolve the issue. The heat enhanced packages are pin to pin compatible and they use the same board layout. The use of forced air is an effective way to improve thermal performance. As seen on the graphs and the calculations above, forced air (200-300 LFM) can reduce junction to ambient thermal resistance by 30%. If space will allow, the use of finned external heatsinks can be effective. If implemented with forced air as well, the benefit can be a 40% to 50% reduction. The HQ304 HQ304, all cavity down PGAs, and the BG352 BG352 with exposed heatsink lend themselves to the application of external heatsinks for further heat removal efficiency. Outside the package itself, the board on which the package sits can have a significant impact. Board designs may be implemented to take advantage of this. Heat flows to the outside of a board mounted package and is sunk into the board to radiate. The effect of the board will be dependent on the size and how it conducts heat. Board size, the level of copper traces on it, the number of buried copper planes all lower the junction-to-ambient thermal resistance for a package. Some of the heatsink packages with the exposed heatsink on the board side can be glued to the board with thermal compound to enhance heat removal. www.xilinx.com 1-800-255-7778 11 R Packages and Thermal Characteristics: High-Reliability Products References Forced Air Cooling Application Engineering COMAIR ROTRON 2675 Custom House Court San Ysidro, CA 92173 1-619-661-6688 Heatsink Application Engineering The following facilities provide heatsink solutions for industry standard packages. AAVID Thermal Technologies 1 Kool Path Box 400 Laconia, NH 03247-0400 1-603-528-3400 Thermalloy, Inc. 2021 W. Valley View Lane Box 810839 Dallas, TX 75381-0839 1-214-243-4321 Wakefield Engineering, Inc. 60 Audubon Road Wakefield MA 01880-1255 1-617-245-5900 Xilinx does not endorse these vendors nor their products. They are listed here for reference only. Any materials or services received from the vendors should be evaluated for compatibility with Xilinx components. Package Electrical Characterization In high-speed systems, the effects of electrical package parasitics become very critical when optimizing for system performance. Such problems as ground bounce and crosstalk can occur due to the inductance, capacitance, and resistance of package interconnects. In digital systems, such phenomena can cause logic error, delay, and reduced system speed. A solid understanding and proper usage of package characterization data during system design simulation can help prevent such problems. Theoretical Background There are three major electrical parameters which are used to describe the package performance: resistance, capacitance, and inductance. Also known as interconnect parasitics, they can cause many serious problems in digital systems. For example, a large resistance can cause RC & RL off-chip delays, power dissipation, and edge-rate degradation. Large capacitance can cause RC delays, crosstalk, edge-rate degradation, and signal distortion. The lead inductance, perhaps the most damaging parasitic in digital circuitry, can cause such problems as ground bounce (also known as simultaneous switching noise or delta-I noise), RL delays, crosstalk, edge rate degradation, and signal distortion. Ground bounce is the voltage difference between any two grounds (typically between an IC and circuit board ground) induced by simultaneously switching current through bondwire, lead, or other interconnect inductance. When IC outputs change state, large current spikes result from charging or discharging the load capacitance. The larger the load capacitance and faster the rise/fall times, the larger the current spikes are: I = C * dv/dt. Current spikes through the IC pin and bondwire induces a voltage drop across the leads and bondwires: V = L * di/dt. The result is a momentary voltage difference between the internal IC ground and system ground, which show up as voltage spikes and unswitched outputs. 12 www.xilinx.com 1-800-255-7778 PK100 PK100 (v1.0) June 15, 2000 R Packages and Thermal Characteristics: High-Reliability Products Factors that affect ground bounce: - rise and fall times - load capacitance - package inductance - number of output drivers sharing the same ground path - device type Analytical Formulas for Lead Inductance 1. Rectangular Leadframe/Trace (straight) Lself = (no ground) 2l 1 5l ln - + - w + t 2 8h w+t Lself = 5l ln - + - w + t 4h nH nH (above ground) where: l = lead/trace length w = lead/trace width t = lead/trace thickness h = ground height unit = inches 2. Bondwire (gold wire) 2l 3 Lwire = 5l ln - - nH r 4 where: L = wire length r = wire radius unit = inches General Measurement Procedure Xilinx uses the Time-Domain Reflectometry (TDR) method for parasitic inductance and capacitance measurements. The main components of a TDR setup includes: a digitizing sampling oscilloscope, a fast rise time step generator (