PIC24HJXXXGPX06A/X08A/X10A DS70592B PICC-18 PIC32 ISO/TS-16949 PIC24H - Datasheet Archive

 

Data Sheet High-Performance, 16-bit Microcontrollers 2009 Microchip Technology Inc. Preliminary DS70592B Note the following

 

PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A Data Sheet High-Performance, 16-bit Microcontrollers 2009 Microchip Technology Inc. Preliminary DS70592B DS70592B Note the following details of the code protection feature on Microchip devices: · Microchip products meet the specification contained in their particular Microchip Data Sheet. · Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. · There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. · Microchip is willing to work with the customer who is concerned about the integrity of their code. · Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18 PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, PIC32 PIC32 logo, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949 ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS70592B-page 2 Preliminary 2009 Microchip Technology Inc. PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A High-Performance, 16-Bit Microcontrollers Operating Range: On-Chip Flash and SRAM: · Up to 40 MIPS operation (@ 3.0-3.6V): - Industrial temperature range (-40°C to +85°C) - Extended temperature range (-40°C to +125°C) · Up to 20 MIPS operation (@ 3.0-3.6V): - High temperature range (-40°C to +140°C) · Flash program memory, up to 256 Kbytes · Data SRAM, up to 16 Kbytes (includes 2 Kbytes of DMA RAM) High-Performance CPU: · Flexible clock options: - External, crystal, resonator, internal RC - Fully integrated PLL - Extremely low jitter PLL · Power-up Timer · Oscillator Start-up Timer/Stabilizer · Watchdog Timer with its own RC oscillator · Fail-Safe Clock Monitor · Reset by multiple sources · · · · · · · · · · · · · Modified Harvard architecture C compiler optimized instruction set 16-bit wide data path 24-bit wide instructions Linear program memory addressing up to 4M instruction words Linear data memory addressing up to 64 Kbytes 71 base instructions: mostly 1 word/1 cycle Sixteen 16-bit General Purpose Registers Flexible and powerful Indirect Addressing modes Software stack 16 x 16 multiply operations 32/16 and 16/16 divide operations Up to ±16-bit data shifts Direct Memory Access (DMA): · 8-channel hardware DMA · 2 Kbytes dual ported DMA buffer area (DMA RAM) to store data transferred via DMA: - Allows data transfer between RAM and a peripheral while CPU is executing code (no cycle stealing) · Most peripherals support DMA Interrupt Controller: · · · · · 5-cycle latency Up to 61 available interrupt sources Up to five external interrupts Seven programmable priority levels FIve processor exceptions System Management: Power Management: · On-chip 2.5V voltage regulator · Switch between clock sources in real time · Idle, Sleep and Doze modes with fast wake-up Timers/Capture/Compare/PWM: · Timer/Counters, up to nine 16-bit timers: - Can pair up to make four 32-bit timers - One timer runs as Real-Time Clock with external 32.768 kHz oscillator - Programmable prescaler · Input Capture (up to eight channels): - Capture on up, down or both edges - 16-bit capture input functions - 4-deep FIFO on each capture · Output Compare (up to eight channels): - Single or Dual 16-Bit Compare mode - 16-bit Glitchless PWM mode Digital I/O: · · · · · Up to 85 programmable digital I/O pins Wake-up/Interrupt-on-Change on up to 24 pins Output pins can drive from 3.0V to 3.6V All digital input pins are 5V tolerant 4 mA sink on all I/O pins 2009 Microchip Technology Inc. Preliminary DS70592B-page 3 PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A Communication Modules: Analog-to-Digital Converters: · 3-wire SPI (up to two modules): - Framing supports I/O interface to simple codecs - Supports 8-bit and 16-bit data - Supports all serial clock formats and sampling modes · I2CTM (up to two modules): - Full Multi-Master Slave mode support - 7-bit and 10-bit addressing - Bus collision detection and arbitration - Integrated signal conditioning - Slave address masking · UART (up to two modules): - Interrupt on address bit detect - Interrupt on UART error - Wake-up on Start bit from Sleep mode - 4-character TX and RX FIFO buffers - LIN bus support - IrDA® encoding and decoding in hardware - High-Speed Baud mode - Hardware Flow Control with CTS and RTS · Enhanced CAN (ECANTM module) 2.0B active (up to two modules): - Up to eight transmit and up to 32 receive buffers - 16 receive filters and 3 masks - Loopback, Listen Only and Listen All Messages modes for diagnostics and bus monitoring - Wake-up on CAN message - Automatic processing of Remote Transmission Requests - FIFO mode using DMA - DeviceNetTM addressing support · Up to two Analog-to-Digital Converter (ADC) modules in a device · 10-bit, 1.1 Msps or 12-bit, 500 ksps conversion: - Two, four, or eight simultaneous samples - Up to 32 input channels with auto-scanning - Conversion start can be manual or synchronized with one of four trigger sources - Conversion possible in Sleep mode - ±1 LSb max integral nonlinearity - ±1 LSb max differential nonlinearity DS70592B-page 4 CMOS Flash Technology: · · · · · Low-power, high-speed Flash technology Fully static design 3.3V (±10%) operating voltage Industrial and extended temperature Low-power consumption Packaging: · 100-pin TQFP (14x14x1 mm and 12x12x1 mm) · 64-pin TQFP (10x10x1 mm) · 64-pin QFN (9x9x0.9 mm) Note: Preliminary See the device variant tables for exact peripheral features per device. 2009 Microchip Technology Inc. PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A PIC24H PIC24H PRODUCT FAMILIES The PIC24H PIC24H Family of devices is ideal for a wide variety of 16-bit MCU embedded applications. The device names, pin counts, memory sizes and peripheral availability of each device are listed below, followed by their pinout diagrams. Pins Program Flash Memory (KB) RAM(1) (KB) DMA Channels Timer 16-bit Input Capture Output Compare Std. PWM Codec Interface ADC UART SPI I2CTM CAN I/O Pins (Max)(2) Packages PIC24H PIC24H Family Controllers PIC24HJ64GP206A PIC24HJ64GP206A 64 64 8 8 9 8 8 0 1 ADC, 18 ch 2 2 1 0 53 PT, MR PIC24HJ64GP210A PIC24HJ64GP210A 100 64 8 8 9 8 8 0 1 ADC, 32 ch 2 2 2 0 85 PF, PT PIC24HJ64GP506A PIC24HJ64GP506A 64 64 8 8 9 8 8 0 1 ADC, 18 ch 2 2 2 1 53 PT, MR PIC24HJ64GP510A PIC24HJ64GP510A 100 64 8 8 9 8 8 0 1 ADC, 32 ch 2 2 2 1 85 PF, PT PIC24HJ128GP206A PIC24HJ128GP206A 64 128 8 8 9 8 8 0 1 ADC, 18 ch 2 2 2 0 53 PT, MR PIC24HJ128GP210A PIC24HJ128GP210A 100 128 8 8 9 8 8 0 1 ADC, 32 ch 2 2 2 0 85 PF, PT PIC24HJ128GP506A PIC24HJ128GP506A 64 128 8 8 9 8 8 0 1 ADC, 18 ch 2 2 2 1 53 PT, MR PIC24HJ128GP510A PIC24HJ128GP510A 100 128 8 8 9 8 8 0 1 ADC, 32 ch 2 2 2 1 85 PF, PT PIC24HJ128GP306A PIC24HJ128GP306A 64 128 16 8 9 8 8 0 1 ADC, 18 ch 2 2 2 0 53 PT, MR PIC24HJ128GP310A PIC24HJ128GP310A 100 128 16 8 9 8 8 0 1 ADC, 32 ch 2 2 2 0 85 PF, PT PIC24HJ256GP206A PIC24HJ256GP206A 64 256 16 8 9 8 8 0 1 ADC, 18 ch 2 2 2 0 53 PT, MR PIC24HJ256GP210A PIC24HJ256GP210A 100 256 16 8 9 8 8 0 1 ADC, 32 ch 2 2 2 0 85 PF, PT PIC24HJ256GP610A PIC24HJ256GP610A 100 256 16 8 9 8 8 0 2 ADC, 32 ch 2 2 2 2 85 PF, PT Device Note 1: 2: RAM size is inclusive of 2 Kbytes DMA RAM. Maximum I/O pin count includes pins shared by the peripheral functions. 2009 Microchip Technology Inc. Preliminary DS70592B-page 5 PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A Pin Diagrams 64-Pin QFN(1) RG13 RG12 RG14 RG0 RG1 RF1 RF0 VDD VCAP/VDDCORE OC8/CN16/RD7 OC8/CN16/RD7 OC7/CN15/RD6 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1 = Pins are up to 5V tolerant 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RG15 AN16/T2CK/T7CK/RC1 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN17/T3CK/T6CK/RC2 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 SDO2/CN10/RG8 MCLR SS2/CN11/RG9 SS2/CN11/RG9 VSS VDD AN5/IC8/CN7/RB5 AN4/IC7/CN6/RB4 AN3/CN5/RB3 AN2/SS1/CN4/RB2 PGEC3/AN1/VREF-/CN3/RB1 PGED3/AN0/VREF+/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIC24HJ64GP206A PIC24HJ64GP206A(2) PIC24HJ128GP206A PIC24HJ128GP206A PIC24HJ256GP206A PIC24HJ256GP206A 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PGEC2/SOSCO/T1CK/CN0/RC14 PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/T4CK/CN1/RC13 PGED2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC4/INT4/RD11 IC3/INT3/RD10 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 VSS OSC2/CLKO/RC15 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 OSC1/CLKIN/RC12 VDD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 PGEC1/AN6/OCFA/RB6 PGED1/AN7/RB7 AVDD AVSS U2CTS/AN8/RB8 AN9/RB9 TMS/AN10/RB10 TMS/AN10/RB10 TDO/AN11/RB11 TDO/AN11/RB11 VSS VDD TCK/AN12/RB12 TCK/AN12/RB12 TDI/AN13/RB13 TDI/AN13/RB13 U2RTS/AN14/RB14 U2RTS/AN14/RB14 AN15/OCFB/CN12/RB15 AN15/OCFB/CN12/RB15 U2RX/SDA2/CN17/RF4 U2RX/SDA2/CN17/RF4 U2TX/SCL2/CN18/RF5 U2TX/SCL2/CN18/RF5 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Note 1: The metal plane at the bottom of the device is not connected to any pins and should be connected to VSS externally. 2: The PIC24HJ64GP206A PIC24HJ64GP206A device does not have the SCL2 and SDA2 pins. DS70592B-page 6 Preliminary 2009 Microchip Technology Inc. PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A Pin Diagrams (Continued) 64-Pin QFN(1) RG13 RG12 RG14 RG0 RG1 RF1 RF0 VDD VCAP/VDDCORE OC8/CN16/RD7 OC8/CN16/RD7 OC7/CN15/RD6 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1 = Pins are up to 5V tolerant 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RG15 AN16/T2CK/T7CK/RC1 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN17/T3CK/T6CK/RC2 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 SDO2/CN10/RG8 MCLR SS2/CN11/RG9 SS2/CN11/RG9 VSS VDD AN5/IC8/CN7/RB5 AN4/IC7/CN6/RB4 AN3/CN5/RB3 AN2/SS1/CN4/RB2 PGEC3/AN1/VREF-/CN3/RB1 PGED3/AN0/VREF+/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIC24HJ128GP306A PIC24HJ128GP306A 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PGEC2/SOSCO/T1CK/CN0/RC14 PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/T4CK/CN1/RC13 PGED2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC4/INT4/RD11 IC3/INT3/RD10 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 VSS OSC2/CLKO/RC15 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 OSC1/CLKIN/RC12 VDD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 PGEC1/AN6/OCFA/RB6 PGED1/AN7/RB7 AVDD AVSS U2CTS/AN8/RB8 AN9/RB9 TMS/AN10/RB10 TMS/AN10/RB10 TDO/AN11/RB11 TDO/AN11/RB11 VSS VDD TCK/AN12/RB12 TCK/AN12/RB12 TDI/AN13/RB13 TDI/AN13/RB13 U2RTS/AN14/RB14 U2RTS/AN14/RB14 AN15/OCFB/CN12/RB15 AN15/OCFB/CN12/RB15 U2RX/SDA2/CN17/RF4 U2RX/SDA2/CN17/RF4 U2TX/SCL2/CN18/RF5 U2TX/SCL2/CN18/RF5 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Note 1: The metal plane at the bottom of the device is not connected to any pins and should be connected to VSS externally. 2009 Microchip Technology Inc. Preliminary DS70592B-page 7 PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A Pin Diagrams (Continued) 64-Pin QFN(1) RG13 RG12 RG14 RG0 RG1 C1TX/RF1 C1RX/RF0 VDD VCAP/VDDCORE OC8/CN16/RD7 OC8/CN16/RD7 OC7/CN15/RD6 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1 = Pins are up to 5V tolerant 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RG15 AN16/T2CK/T7CK/RC1 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN17/T3CK/T6CK/RC2 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 SDO2/CN10/RG8 MCLR SS2/CN11/RG9 SS2/CN11/RG9 VSS VDD AN5/IC8/CN7/RB5 AN4/IC7/CN6/RB4 AN3/CN5/RB3 AN2/SS1/CN4/RB2 PGEC3/AN1/VREF-/CN3/RB1 PGED3/AN0/VREF+/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIC24HJ64GP506A PIC24HJ64GP506A PIC24HJ128GP506A PIC24HJ128GP506A 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PGEC2/SOSCO/T1CK/CN0/RC14 PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/T4CK/CN1/RC13 PGED2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC4/INT4/RD11 IC3/INT3/RD10 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 VSS OSC2/CLKO/RC15 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 OSC1/CLKIN/RC12 VDD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 PGEC1/AN6/OCFA/RB6 PGED1/AN7/RB7 AVDD AVSS U2CTS/AN8/RB8 AN9/RB9 TMS/AN10/RB10 TMS/AN10/RB10 TDO/AN11/RB11 TDO/AN11/RB11 VSS VDD TCK/AN12/RB12 TCK/AN12/RB12 TDI/AN13/RB13 TDI/AN13/RB13 U2RTS/AN14/RB14 U2RTS/AN14/RB14 AN15/OCFB/CN12/RB15 AN15/OCFB/CN12/RB15 U2RX/SDA2/CN17/RF4 U2RX/SDA2/CN17/RF4 U2TX/SCL2/CN18/RF5 U2TX/SCL2/CN18/RF5 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Note 1: The metal plane at the bottom of the device is not connected to any pins and should be connected to VSS externally. DS70592B-page 8 Preliminary 2009 Microchip Technology Inc. PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A Pin Diagrams (Continued) 64-Pin TQFP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RG13 RG12 RG14 RG0 RG1 RF1 RF0 VDD VCAP/VDDCORE OC8/CN16/RD7 OC8/CN16/RD7 OC7/CN15/RD6 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1 = Pins are up to 5V tolerant 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIC24HJ64GP206A PIC24HJ64GP206A PIC24HJ128GP206A PIC24HJ128GP206A PIC24HJ256GP206A PIC24HJ256GP206A 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PGEC2/SOSCO/T1CK/CN0/RC14 PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/T4CK/CN1/RC13 PGED2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC4/INT4/RD11 IC3/INT3/RD10 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 VSS OSC2/CLKO/RC15 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 OSC1/CLKIN/RC12 VDD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 PGEC1/AN6/OCFA/RB6 PGED1/AN7/RB7 AVDD AVSS U2CTS/AN8/RB8 AN9/RB9 TMS/AN10/RB10 TMS/AN10/RB10 TDO/AN11/RB11 TDO/AN11/RB11 VSS VDD TCK/AN12/RB12 TCK/AN12/RB12 TDI/AN13/RB13 TDI/AN13/RB13 U2RTS/AN14/RB14 U2RTS/AN14/RB14 AN15/OCFB/CN12/RB15 AN15/OCFB/CN12/RB15 U2RX/SDA2/CN17/RF4 U2RX/SDA2/CN17/RF4 U2TX/SCL2/CN18/RF5 U2TX/SCL2/CN18/RF5 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 RG15 AN16/T2CK/T7CK/RC1 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN17/T3CK/T6CK/RC2 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 SDO2/CN10/RG8 MCLR SS2/CN11/RG9 SS2/CN11/RG9 VSS VDD AN5/IC8/CN7/RB5 AN4/IC7/CN6/RB4 AN3/CN5/RB3 AN2/SS1/CN4/RB2 PGEC3/AN1/VREF-/CN3/RB1 PGED3/AN0/VREF+/CN2/RB0 Note: The PIC24HJ64GP206A PIC24HJ64GP206A device does not have the SCL2 and SDA2 pins. 2009 Microchip Technology Inc. Preliminary DS70592B-page 9 PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A Pin Diagrams (Continued) 64-Pin TQFP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RG13 RG12 RG14 RG0 RG1 RF1 RF0 VDD VCAP/VDDCORE OC8/CN16/RD7 OC8/CN16/RD7 OC7/CN15/RD6 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1 = Pins are up to 5V tolerant 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIC24HJ128GP306A PIC24HJ128GP306A 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PGEC2/SOSCO/T1CK/CN0/RC14 PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/T4CK/CN1/RC13 PGED2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC4/INT4/RD11 IC3/INT3/RD10 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 VSS OSC2/CLKO/RC15 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 OSC1/CLKIN/RC12 VDD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 PGEC1/AN6/OCFA/RB6 PGED1/AN7/RB7 AVDD AVSS U2CTS/AN8/RB8 AN9/RB9 TMS/AN10/RB10 TMS/AN10/RB10 TDO/AN11/RB11 TDO/AN11/RB11 VSS VDD TCK/AN12/RB12 TCK/AN12/RB12 TDI/AN13/RB13 TDI/AN13/RB13 U2RTS/AN14/RB14 U2RTS/AN14/RB14 AN15/OCFB/CN12/RB15 AN15/OCFB/CN12/RB15 U2RX/SDA2/CN17/RF4 U2RX/SDA2/CN17/RF4 U2TX/SCL2/CN18/RF5 U2TX/SCL2/CN18/RF5 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 RG15 AN16/T2CK/T7CK/RC1 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN17/T3CK/T6CK/RC2 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 SDO2/CN10/RG8 MCLR SS2/CN11/RG9 SS2/CN11/RG9 VSS VDD AN5/IC8/CN7/RB5 AN4/IC7/CN6/RB4 AN3/CN5/RB3 AN2/SS1/CN4/RB2 PGEC3/AN1/VREF-/CN3/RB1 PGED3/AN0/VREF+/CN2/RB0 DS70592B-page 10 Preliminary 2009 Microchip Technology Inc. PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A Pin Diagrams (Continued) 64-Pin TQFP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RG13 RG12 RG14 RG0 RG1 C1TX/RF1 C1RX/RF0 VDD VCAP/VDDCORE OC8/CN16/RD7 OC8/CN16/RD7 OC7/CN15/RD6 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1 = Pins are up to 5V tolerant 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIC24HJ64GP506A PIC24HJ64GP506A PIC24HJ128GP506A PIC24HJ128GP506A 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PGEC2/SOSCO/T1CK/CN0/RC14 PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/T4CK/CN1/RC13 PGED2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC4/INT4/RD11 IC3/INT3/RD10 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 VSS OSC2/CLKO/RC15 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 OSC1/CLKIN/RC12 VDD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 PGEC1/AN6/OCFA/RB6 PGED1/AN7/RB7 AVDD AVSS U2CTS/AN8/RB8 AN9/RB9 TMS/AN10/RB10 TMS/AN10/RB10 TDO/AN11/RB11 TDO/AN11/RB11 VSS VDD TCK/AN12/RB12 TCK/AN12/RB12 TDI/AN13/RB13 TDI/AN13/RB13 U2RTS/AN14/RB14 U2RTS/AN14/RB14 AN15/OCFB/CN12/RB15 AN15/OCFB/CN12/RB15 U2RX/SDA2/CN17/RF4 U2RX/SDA2/CN17/RF4 U2TX/SCL2/CN18/RF5 U2TX/SCL2/CN18/RF5 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 RG15 AN16/T2CK/T7CK/RC1 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN17/T3CK/T6CK/RC2 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 SDO2/CN10/RG8 MCLR SS2/CN11/RG9 SS2/CN11/RG9 VSS VDD AN5/IC8/CN7/RB5 AN4/IC7/CN6/RB4 AN3/CN5/RB3 AN2/SS1/CN4/RB2 PGEC3/AN1/VREF-/CN3/RB1 PGED3/AN0/VREF+/CN2/RB0 2009 Microchip Technology Inc. Preliminary DS70592B-page 11 PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A Pin Diagrams (Continued) = Pins are up to 5V tolerant 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 AN28/RE4 AN28/RE4 AN27/RE3 AN27/RE3 AN26/RE2 AN26/RE2 RG13 RG12 RG14 AN25/RE1 AN25/RE1 AN24/RE0 AN24/RE0 AN23/CN23/RA7 AN23/CN23/RA7 AN22/CN22/RA6 AN22/CN22/RA6 RG0 RG1 RF1 RF0 VDD VCAP/VDDCORE OC8/CN16/RD7 OC8/CN16/RD7 OC7/CN15/RD6 OC7/CN15/RD6 OC6/CN14/RD5 OC6/CN14/RD5 OC5/CN13/RD4 OC5/CN13/RD4 IC6/CN19/RD13 IC6/CN19/RD13 IC5/RD12 IC5/RD12 OC4/RD3 OC3/RD2 OC2/RD1 100-Pin TQFP RG15 VDD AN29/RE5 AN29/RE5 AN30/RE6 AN30/RE6 AN31/RE7 AN31/RE7 AN16/T2CK/T7CK/RC1 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN17/T3CK/T6CK/RC2 AN18/T4CK/T9CK/RC3 AN18/T4CK/T9CK/RC3 AN19/T5CK/T8CK/RC4 AN19/T5CK/T8CK/RC4 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 SDO2/CN10/RG8 MCLR SS2/CN11/RG9 SS2/CN11/RG9 VSS VDD TMS/RA0 AN20/INT1/RA12 AN20/INT1/RA12 AN21/INT2/RA13 AN21/INT2/RA13 AN5/CN7/RB5 AN4/CN6/RB4 AN3/CN5/RB3 AN2/SS1/CN4/RB2 PGEC3/AN1/CN3/RB1 75 VSS 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 74 PGEC2/SOSCO/T1CK/CN0/RC14 PGEC2/SOSCO/T1CK/CN0/RC14 73 PGED2/SOSCI/CN1/RC13 PGED2/SOSCI/CN1/RC13 OC1/RD0 IC4/RD11 IC4/RD11 72 71 70 69 68 67 66 65 64 63 62 IC3/RD10 IC3/RD10 IC2/RD9 IC1/RD8 INT4/RA15 INT4/RA15 INT3/RA14 INT3/RA14 VSS 25 59 58 SDA2/RA3 SCL2/RA2 SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 54 53 52 51 23 24 61 60 OSC2/CLKO/RC15 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 OSC1/CLKIN/RC12 VDD TDO/RA5 TDI/RA4 57 56 55 PIC24HJ64GP210A PIC24HJ64GP210A PIC24HJ128GP210A PIC24HJ128GP210A PIC24HJ128GP310A PIC24HJ128GP310A PIC24HJ256GP210A PIC24HJ256GP210A SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3 PGEC1/AN6/OCFA/RB6 26 PGED1PGED1/AN7/RB7 27 VREF-/RA9 28 VREF+/RA10 /RA10 29 30 AVDD 31 AVSS 32 AN8/RB8 33 AN9/RB9 34 AN10/RB10 AN10/RB10 35 AN11/RB11 AN11/RB11 36 VSS VDD 37 38 TCK/RA1 U2RTS/RF13 U2RTS/RF13 39 40 U2CTS/RF12 U2CTS/RF12 41 AN12/RB12 AN12/RB12 42 AN13/RB13 AN13/RB13 43 AN14/RB14 AN14/RB14 44 AN15/OCFB/CN12/RB15 AN15/OCFB/CN12/RB15 45 VSS 46 VDD 47 IC7/U1CTS/CN20/RD14 IC7/U1CTS/CN20/RD14 48 IC8/U1RTS/CN21/RD15 IC8/U1RTS/CN21/RD15 49 U2RX/CN17/RF4 U2RX/CN17/RF4 50 U2TX/CN18/RF5 U2TX/CN18/RF5 PGED3/AN0/CN2/RB0 1 DS70592B-page 12 Preliminary 2009 Microchip Technology Inc. PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A Pin Diagrams (Continued) 100-Pin TQFP 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 AN28/RE4 AN28/RE4 AN27/RE3 AN27/RE3 AN26/RE2 AN26/RE2 RG13 RG12 RG14 AN25/RE1 AN25/RE1 AN24/RE0 AN24/RE0 AN23/CN23/RA7 AN23/CN23/RA7 AN22/CN22/RA6 AN22/CN22/RA6 RG0 RG1 C1TX/RF1 C1RX/RF0 VDD VCAP/VDDCORE OC8/CN16/RD7 OC8/CN16/RD7 OC7/CN15/RD6 OC7/CN15/RD6 OC6/CN14/RD5 OC6/CN14/RD5 OC5/CN13/RD4 OC5/CN13/RD4 IC6/CN19/RD13 IC6/CN19/RD13 IC5/RD12 IC5/RD12 OC4/RD3 OC3/RD2 OC2/RD1 = Pins are up to 5V tolerant RG15 VDD AN29/RE5 AN29/RE5 AN30/RE6 AN30/RE6 AN31/RE7 AN31/RE7 AN16/T2CK/T7CK/RC1 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN17/T3CK/T6CK/RC2 AN18/T4CK/T9CK/RC3 AN18/T4CK/T9CK/RC3 AN19/T5CK/T8CK/RC4 AN19/T5CK/T8CK/RC4 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 SDO2/CN10/RG8 MCLR SS2/CN11/RG9 SS2/CN11/RG9 VSS VDD TMS/RA0 AN20/INT1/RA12 AN20/INT1/RA12 AN21/INT2/RA13 AN21/INT2/RA13 AN5/CN7/RB5 AN4/CN6/RB4 AN3/CN5/RB3 AN2/SS1/CN4/RB2 PGEC3/AN1/CN3/RB1 75 74 VSS PGEC2/SOSCO/T1CK/CN0/RC14 PGEC2/SOSCO/T1CK/CN0/RC14 73 PGED2/SOSCI/CN1/RC13 PGED2/SOSCI/CN1/RC13 OC1/RD0 5 6 7 8 9 71 70 69 68 67 66 72 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 PIC24HJ64GP510A PIC24HJ64GP510A PIC24HJ128GP510A PIC24HJ128GP510A 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 IC4/RD11 IC4/RD11 IC3/RD10 IC3/RD10 IC2/RD9 IC1/RD8 INT4/RA15 INT4/RA15 INT3/RA14 INT3/RA14 VSS OSC2/CLKO/RC15 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 OSC1/CLKIN/RC12 VDD TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3 PGEC1/AN6/OCFA/RB6 PGED1/AN7/RB7 VREF-/RA9 VREF+/RA10 /RA10 AVDD AVSS AN8/RB8 AN9/RB9 AN10/RB10 AN10/RB10 AN11/RB11 AN11/RB11 VSS VDD TCK/RA1 U2RTS/RF13 U2RTS/RF13 U2CTS/RF12 U2CTS/RF12 AN12/RB12 AN12/RB12 AN13/RB13 AN13/RB13 AN14/RB14 AN14/RB14 AN15/OCFB/CN12/RB15 AN15/OCFB/CN12/RB15 VSS VDD IC7/U1CTS/CN20/RD14 IC7/U1CTS/CN20/RD14 IC8/U1RTS/CN21/RD15 IC8/U1RTS/CN21/RD15 U2RX/CN17/RF4 U2RX/CN17/RF4 U2TX/CN18/RF5 U2TX/CN18/RF5 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PGED3/AN0/CN2/RB0 1 2 3 4 2009 Microchip Technology Inc. Preliminary DS70592B-page 13 PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A Pin Diagrams (Continued) 100-Pin TQFP 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 AN28/RE4 AN28/RE4 AN27/RE3 AN27/RE3 AN26/RE2 AN26/RE2 RG13 RG12 RG14 AN25/RE1 AN25/RE1 AN24/RE0 AN24/RE0 AN23/CN23/RA7 AN23/CN23/RA7 AN22/CN22/RA6 AN22/CN22/RA6 C2RX/RG0 C2TX/RG1 C1TX/RF1 C1RX/RF0 VDD VCAP/VDDCORE OC8/CN16/RD7 OC8/CN16/RD7 OC7/CN15/RD6 OC7/CN15/RD6 OC6/CN14/RD5 OC6/CN14/RD5 OC5/CN13/RD4 OC5/CN13/RD4 IC6/CN19/RD13 IC6/CN19/RD13 IC5/RD12 IC5/RD12 OC4/RD3 OC3/RD2 OC2/RD1 = Pins are up to 5V tolerant RG15 VDD AN29/RE5 AN29/RE5 AN30/RE6 AN30/RE6 AN31/RE7 AN31/RE7 AN16/T2CK/T7CK/RC1 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN17/T3CK/T6CK/RC2 AN18/T4CK/T9CK/RC3 AN18/T4CK/T9CK/RC3 AN19/T5CK/T8CK/RC4 AN19/T5CK/T8CK/RC4 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 SDO2/CN10/RG8 MCLR SS2/CN11/RG9 SS2/CN11/RG9 VSS VDD TMS/RA0 AN20/INT1/RA12 AN20/INT1/RA12 AN21/INT2/RA13 AN21/INT2/RA13 AN5/CN7/RB5 AN4/CN6/RB4 75 VSS 2 3 4 5 6 7 8 9 10 11 12 74 73 PGEC2/SOSCO/T1CK/CN0/RC14 PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/CN1/RC13 PGED2/SOSCI/CN1/RC13 72 OC1/RD0 71 70 69 IC4/RD11 IC4/RD11 IC3/RD10 IC3/RD10 IC2/RD9 68 67 66 IC1/RD8 INT4/RA15 INT4/RA15 PIC24HJ256GP610A PIC24HJ256GP610A 13 14 15 16 17 18 19 20 21 22 23 24 25 65 64 63 62 61 60 59 58 INT3/RA14 INT3/RA14 VSS OSC2/CLKO/RC15 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 OSC1/CLKIN/RC12 VDD TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 57 56 55 54 SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 53 52 51 SDO1/RF8 U1RX/RF2 SDI1/RF7 U1TX/RF3 PGEC1/AN6/OCFA/RB6 PGED1/AN7/RB7 VREF-/RA9 VREF+/RA10 /RA10 AVDD AVSS AN8/RB8 AN9/RB9 AN10/RB10 AN10/RB10 AN11/RB11 AN11/RB11 VSS VDD TCK/RA1 U2RTS/RF13 U2RTS/RF13 U2CTS/RF12 U2CTS/RF12 AN12/RB12 AN12/RB12 AN13/RB13 AN13/RB13 AN14/RB14 AN14/RB14 AN15/OCFB/CN12/RB15 AN15/OCFB/CN12/RB15 VSS VDD IC7/U1CTS/CN20/RD14 IC7/U1CTS/CN20/RD14 IC8/U1RTS/CN21/RD15 IC8/U1RTS/CN21/RD15 U2RX/CN17/RF4 U2RX/CN17/RF4 U2TX/CN18/RF5 U2TX/CN18/RF5 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 AN3/CN5/RB3 AN2/SS1/CN4/RB2 PGEC3/AN1/CN3/RB1 PGED3/AN0/CN2/RB0 1 DS70592B-page 14 Preliminary 2009 Microchip Technology Inc. PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A Table of Contents PIC24H PIC24H Product Families. 5 1.0 Device Overview . 17 2.0 Guidelines for Getting Started with 16-Bit Microcontrollers. 21 3.0 CPU. 25 4.0 Memory Organization . 31 5.0 Flash Program Memory. 61 6.0 Reset . 67 7.0 Interrupt Controller . 73 8.0 Direct Memory Access (DMA) . 117 9.0 Oscillator Configuration . 127 10.0 Power-Saving Features. 137 11.0 I/O Ports . 145 12.0 Timer1 . 147 13.0 Timer2/3, Timer4/5, Timer6/7 and Timer8/9 . 149 14.0 Input Capture. 155 15.0 Output Compare. 157 16.0 Serial Peripheral Interface (SPI). 161 17.0 Inter-Integrated CircuitTM (I2CTM). 167 18.0 Universal Asynchronous Receiver Transmitter (UART) . 175 19.0 Enhanced CAN (ECANTM) Module. 181 20.0 10-Bit/12-Bit Analog-to-Digital Converter (ADC) . 207 21.0 Special Features . 219 22.0 Instruction Set Summary . 227 23.0 Development Support. 235 24.0 Electrical Characteristics . 239 25.0 High Temperature Electrical Characteristics . 275 26.0 Packaging Information. 285 Appendix A: Migrating from PIC24HJXXXGPX06/X08/X10 PIC24HJXXXGPX06/X08/X10 Devices to PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A Devices . 295 Appendix B: Revision History. 296 Index . 297 The Microchip Web Site . 301 Customer Change Notification Service . 301 Customer Support . 301 Reader Response . 302 Product Identification System . 303 2009 Microchip Technology Inc. Preliminary DS70592B-page 15 PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A DS30000A is version A of document DS30000 DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: · Microchip's Worldwide Web site; http://www.microchip.com · Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS70592B-page 16 Preliminary 2009 Microchip Technology Inc. PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A 1.0 Note: DEVICE OVERVIEW This data sheet summarizes the features of the PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the latest family reference sections of the "dsPIC33F/PIC24H Family Reference Manual", which is available from the Microchip web site (www.microchip.com). This document contains device specific information for the following devices: · · · · · · · · · · · · · PIC24HJ64GP206A PIC24HJ64GP206A PIC24HJ64GP210A PIC24HJ64GP210A PIC24HJ64GP506A PIC24HJ64GP506A PIC24HJ64GP510A PIC24HJ64GP510A PIC24HJ128GP206A PIC24HJ128GP206A PIC24HJ128GP210A PIC24HJ128GP210A PIC24HJ128GP506A PIC24HJ128GP506A PIC24HJ128GP510A PIC24HJ128GP510A PIC24HJ128GP306A PIC24HJ128GP306A PIC24HJ128GP310A PIC24HJ128GP310A PIC24HJ256GP206A PIC24HJ256GP206A PIC24HJ256GP210A PIC24HJ256GP210A PIC24HJ256GP610A PIC24HJ256GP610A The PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A device family includes devices with different pin counts (64 and 100 pins), different program memory sizes (64 Kbytes, 128 Kbytes and 256 Kbytes) and different RAM sizes (8 Kbytes and 16 Kbytes). 2009 Microchip Technology Inc. This makes these families suitable for a wide variety of high-performance digital signal control applications. The devices are pin compatible with the dsPIC33F family of devices, and also share a very high degree of compatibility with the dsPIC30F family devices. This allows easy migration between device families as may be necessitated by the specific functionality, computational resource and system cost requirements of the application. The PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A device family employs a powerful 16-bit architecture, ideal for applications that rely on high-speed, repetitive computations, as well as control. The 17 x 17 multiplier, hardware support for division operations, multi-bit data shifter, a large array of 16-bit working registers and a wide variety of data addressing modes, together provide the PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A Central Processing Unit (CPU) with extensive mathematical processing capability. Flexible and deterministic interrupt handling, coupled with a powerful array of peripherals, renders the PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A devices suitable for control applications. Further, Direct Memory Access (DMA) enables overhead-free transfer of data between several peripherals and a dedicated DMA RAM. Reliable, field programmable Flash program memory ensures scalability of applications that use PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A devices. Figure 1-1 shows a general block diagram of the various core and peripheral modules in the PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A family of devices, while Table 1-1 lists the functions of the various pins shown in the pinout diagrams. Preliminary DS70592B-page 17 PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A FIGURE 1-1: PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A GENERAL BLOCK DIAGRAM PSV and Table Data Access Control Block Data Bus Interrupt Controller PORTA 16 8 16 16 DMA RAM Data Latch 23 PCU PCH PCL Program Counter Loop Stack Control Control Logic Logic 23 X RAM PORTB Address Latch DMA 23 16 Controller 16 PORTC Address Generator Units Address Latch Program Memory EA MUX Data Latch 24 Instruction Reg Control Signals to Various Blocks Timing Generation FRC/LPRC Oscillators Precision Band Gap Reference Voltage Regulator VCAP/VDDCORE Timers 1-9 IC1-8 Note: Literal Data 16 Instruction Decode and Control OSC2/CLKO OSC1/CLKI PORTD ROM Latch 16 PORTE 16 17 x 17 Multiplier Power-up Timer Divide Support 16 x 16 W Register Array 16 PORTF Oscillator Start-up Timer Power-on Reset 16-bit ALU Watchdog Timer 16 Brown-out Reset VDD, VSS ADC1,2 OC/ PWM1-8 PORTG MCLR ECAN1,2 UART1,2 CN1-23 CN1-23 SPI1,2 I2C1,2 Not all pins or features are implemented on all device pinout configurations. See pinout diagrams for the specific pins and features present on each device. DS70592B-page 18 Preliminary 2009 Microchip Technology Inc. PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Type Buffer Type AN0-AN31 AN0-AN31 I Analog AVDD P P Positive supply for analog modules. This pin must be connected at all times. AVSS P P Ground reference for analog modules. CLKI CLKO I O CN0-CN23 CN0-CN23 I ST Input change notification inputs. Can be software programmed for internal weak pull-ups on all inputs. C1RX C1TX C2RX C2TX I O I O ST - ST - ECAN1 bus receive pin. ECAN1 bus transmit pin. ECAN2 bus receive pin. ECAN2 bus transmit pin. PGED1 PGEC1 PGED2 PGEC2 PGED3 PGEC3 I/O I I/O I I/O I ST ST ST ST ST ST Data I/O pin for programming/debugging communication channel 1. Clock input pin for programming/debugging communication channel 1. Data I/O pin for programming/debugging communication channel 2. Clock input pin for programming/debugging communication channel 2. Data I/O pin for programming/debugging communication channel 3. Clock input pin for programming/debugging communication channel 3. IC1-IC8 I ST Capture inputs 1 through 8. INT0 INT1 INT2 INT3 INT4 I I I I I ST ST ST ST ST External interrupt 0. External interrupt 1. External interrupt 2. External interrupt 3. External interrupt 4. Pin Name Description Analog input channels. ST/CMOS External clock source input. Always associated with OSC1 pin function. - Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function. MCLR I/P ST Master Clear (Reset) input. This pin is an active-low Reset to the device. OCFA OCFB OC1-OC8 I I O ST ST - Compare Fault A input (for Compare Channels 1, 2, 3 and 4). Compare Fault B input (for Compare Channels 5, 6, 7 and 8). Compare outputs 1 through 8. OSC1 I OSC2 I/O RA0-RA7 RA9-RA10 RA9-RA10 RA12-RA15 RA12-RA15 I/O I/O I/O ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. - Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. ST ST ST PORTA is a bidirectional I/O port. RB0-RB15 RB0-RB15 I/O ST PORTB is a bidirectional I/O port. RC1-RC4 RC12-RC15 RC12-RC15 I/O I/O ST ST PORTC is a bidirectional I/O port. RD0-RD15 RD0-RD15 I/O ST PORTD is a bidirectional I/O port. RE0-RE7 I/O ST PORTE is a bidirectional I/O port. RF0-RF8 RF12-RF13 RF12-RF13 I/O ST PORTF is a bidirectional I/O port. RG0-RG3 RG6-RG9 RG12-RG15 RG12-RG15 I/O I/O I/O ST ST ST PORTG is a bidirectional I/O port. Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels 2009 Microchip Technology Inc. Analog = Analog input O = Output Preliminary P = Power I = Input DS70592B-page 19 PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Type Buffer Type SCK1 SDI1 SDO1 SS1 SCK2 SDI2 SDO2 SS2 I/O I O I/O I/O I O I/O ST ST - ST ST ST - ST Synchronous serial clock input/output for SPI1. SPI1 data in. SPI1 data out. SPI1 slave synchronization or frame pulse I/O. Synchronous serial clock input/output for SPI2. SPI2 data in. SPI2 data out. SPI2 slave synchronization or frame pulse I/O. SCL1 SDA1 SCL2 SDA2 I/O I/O I/O I/O ST ST ST ST Synchronous serial clock input/output for I2C1. Synchronous serial data input/output for I2C1. Synchronous serial clock input/output for I2C2. Synchronous serial data input/output for I2C2. SOSCI SOSCO I O TMS TCK TDI TDO I I I O ST ST ST - JTAG Test mode select pin. JTAG test clock input pin. JTAG test data input pin. JTAG test data output pin. T1CK T2CK T3CK T4CK T5CK T6CK T7CK T8CK T9CK I I I I I I I I I ST ST ST ST ST ST ST ST ST Timer1 external clock input. Timer2 external clock input. Timer3 external clock input. Timer4 external clock input. Timer5 external clock input. Timer6 external clock input. Timer7 external clock input. Timer8 external clock input. Timer9 external clock input. U1CTS U1RTS U1RX U1TX U2CTS U2RTS U2RX U2TX I O I O I O I O ST - ST - ST - ST - UART1 clear to send. UART1 ready to send. UART1 receive. UART1 transmit. UART2 clear to send. UART2 ready to send. UART2 receive. UART2 transmit. VDD P - Positive supply for peripheral logic and I/O pins. VCAP/VDDCORE P - CPU logic filter capacitor connection. VSS P - Ground reference for logic and I/O pins. VREF+ I Analog Analog voltage reference (high) input. VREF- I Analog Analog voltage reference (low) input. Pin Name Description ST/CMOS 32.768 kHz low-power oscillator crystal input; CMOS otherwise. - 32.768 kHz low-power oscillator crystal output. Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels DS70592B-page 20 Analog = Analog input O = Output Preliminary P = Power I = Input 2009 Microchip Technology Inc. PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A 2.0 GUIDELINES FOR GETTING STARTED WITH 16-BIT 16-BIT MICROCONTROLLERS 2.2 The use of decoupling capacitors on every pair of power supply pins, such as VDD, VSS, AVDD and AVSS is required. Note 1: This data sheet summarizes the features of the PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "dsPIC33F/PIC24H Family Reference Manual". Please see the Microchip web site (www.microchip.com) for the latest dsPIC33F/PIC24H Family Reference Manual sections. 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. 2.1 Decoupling Capacitors Basic Connection Requirements Getting started with the PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A family of 16-bit Microcontrollers (MCUs) requires attention to a minimal set of device pin connections before proceeding with development. The following is a list of pin names, which must always be connected: · All VDD and VSS pins (see Section 2.2 "Decoupling Capacitors") · All AVDD and AVSS pins (regardless if ADC module is not used) (see Section 2.2 "Decoupling Capacitors") · VCAP/VDDCORE (see Section 2.3 "Capacitor on Internal Voltage Regulator (VCAP/VDDCORE)") · MCLR pin (see Section 2.4 "Master Clear (MCLR) Pin") · PGECx/PGEDx pins used for In-Circuit Serial ProgrammingTM (ICSPTM) and debugging purposes (see Section 2.5 "ICSP Pins") · OSC1 and OSC2 pins when external oscillator source is used (see Section 2.6 "External Oscillator Pins") Consider the following criteria when using decoupling capacitors: · Value and type of capacitor: Recommendation of 0.1 µF (100 nF), 10-20V. This capacitor should be a low-ESR and have resonance frequency in the range of 20 MHz and higher. It is recommended that ceramic capacitors be used. · Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended to place the capacitors on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is within one-quarter inch (6 mm) in length. · Handling high frequency noise: If the board is experiencing high frequency noise, upward of tens of MHz, add a second ceramic-type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 µF to 0.001 µF. Place this second capacitor next to the primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible. For example, 0.1 µF in parallel with 0.001 µF. · Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum thereby reducing PCB track inductance. Additionally, the following pins may be required: · VREF+/VREF- pins used when external voltage reference for ADC module is implemented Note: The AVDD and AVSS pins must be connected independent of the ADC voltage reference source. 2009 Microchip Technology Inc. Preliminary DS70592B-page 21 PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION 0.1 µF Ceramic R1 MCLR C VSS 10 2.2.1 VDD 0.1 µF Ceramic VSS VDD AVSS VDD AVDD 0.1 µF Ceramic The MCLR pin provides for two specific device functions: During device programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values of R and C will need to be adjusted based on the application and PCB requirements. PIC24H PIC24H VSS Master Clear (MCLR) Pin · Device Reset · Device programming and debugging VSS R VDD VCAP/VDDCORE VDD 2.4 0.1 µF Ceramic 0.1 µF Ceramic For example, as shown in Figure 2-2, it is recommended that the capacitor C, be isolated from the MCLR pin during programming and debugging operations. Place the components shown in Figure 2-2 within one-quarter inch (6 mm) from the MCLR pin. FIGURE 2-2: TANK CAPACITORS On boards with power traces running longer than six inches in length, it is suggested to use a tank capacitor for integrated circuits including MCUs to supply a local power source. The value of the tank capacitor should be determined based on the trace resistance that connects the power supply source to the device, and the maximum current drawn by the device in the application. In other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. Typical values range from 4.7 µF to 47 µF. 2.3 Capacitor on Internal Voltage Regulator (VCAP/VDDCORE) EXAMPLE OF MCLR PIN CONNECTIONS VDD R R1 MCLR JP PIC24H PIC24H C Note 1: R 10 k is recommended. A suggested starting value is 10 k. Ensure that the MCLR pin VIH and VIL specifications are met. 2: R1 470 will limit any current flowing into MCLR from the external capacitor C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin VIH and VIL specifications are met. A low-ESR (< 5 Ohms) capacitor is required on the VCAP/VDDCORE pin, which is used to stabilize the voltage regulator output voltage. The VCAP/VDDCORE pin must not be connected to VDD, and must have a capacitor between 4.7 µF and 10 µF, 16V connected to ground. The type can be ceramic or tantalum. Refer to Section 24.0 "Electrical Characteristics" for additional information. The placement of this capacitor should be close to the VCAP/VDDCORE. It is recommended that the trace length not exceed one-quarter inch (6 mm). Refer to Section 21.2 "On-Chip Voltage Regulator" for details. DS70592B-page 22 Preliminary 2009 Microchip Technology Inc. PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A 2.5 ICSP Pins 2.6 The PGECx and PGEDx pins are used for In-Circuit Serial ProgrammingTM (ICSPTM) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms. Pull-up resistors, series diodes, and capacitors on the PGECx and PGEDx pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits and pin input voltage high (VIH) and input low (VIL) requirements. Ensure that the "Communication Channel Select" (i.e., PGECx/PGEDx pins) programmed into the device matches the physical connections for the ICSP to MPLAB® ICD 2, MPLAB ICD 3 or MPLAB REAL ICETM. Many MCUs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 9.0 "Oscillator Configuration" for details). The oscillator circuit should be placed on the same side of the board as the device. Also, place the oscillator circuit close to the respective oscillator pins, not exceeding one-half inch (12 mm) distance between them. The load capacitors should be placed next to the oscillator itself, on the same side of the board. Use a grounded copper pour around the oscillator circuit to isolate them from surrounding circuits. The grounded copper pour should be routed directly to the MCU ground. Do not run any signal traces or power traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. A suggested layout is shown in Figure 2-3. FIGURE 2-3: For more information on ICD 2, ICD 3 and REAL ICE connection requirements, refer to the following documents that are available on the Microchip website. · "MPLAB® ICD 2 In-Circuit Debugger User's Guide" DS51331 DS51331 · "Using MPLAB® ICD 2" (poster) DS51265 DS51265 · "MPLAB® ICD 2 Design Advisory" DS51566 DS51566 · "Using MPLAB® ICD 3 In-Circuit Debugger" (poster) DS51765 DS51765 · "MPLAB® ICD 3 Design Advisory" DS51764 DS51764 · "MPLAB® REAL ICETM In-Circuit Emulator User's Guide" DS51616 DS51616 · "Using MPLAB® REAL ICETM" (poster) DS51749 DS51749 2009 Microchip Technology Inc. External Oscillator Pins Preliminary SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT Main Oscillator 13 Guard Ring 14 15 Guard Trace Secondary Oscillator 16 17 18 19 20 DS70592B-page 23 PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A 2.7 Oscillator Value Conditions on Device Start-up If the PLL of the target device is enabled and configured for the device start-up oscillator, the maximum oscillator source frequency must be limited to 4 MHz < FIN < 8 MHz to comply with device PLL start-up conditions. This means that if the external oscillator frequency is outside this range, the application must start-up in the FRC mode first. The default PLL settings after a POR with an oscillator frequency outside this range will violate the device operating speed. Once the device powers up, the application firmware can initialize the PLL SFRs, CLKDIV and PLLDBF to a suitable value, and then perform a clock switch to the Oscillator + PLL clock source. Note that clock switching must be enabled in the device Configuration word. 2.8 Configuration of Analog and Digital Pins During ICSP Operations If MPLAB ICD 2, ICD 3 or REAL ICE is selected as a debugger, it automatically initializes all of the A/D input pins (ANx) as "digital" pins, by setting all bits in the AD1PCFGL register. The bits in this register that correspond to the A/D pins that are initialized by MPLAB ICD 2, ICD 3, or REAL ICE, must not be cleared by the user application firmware; otherwise, communication errors will result between the debugger and the device. If your application needs to use certain A/D pins as analog input pins during the debug session, the user application must clear the corresponding bits in the AD1PCFGL register during initialization of the ADC module. When MPLAB ICD 2, ICD 3 or REAL ICE is used as a programmer, the user application firmware must correctly configure the AD1PCFGL register. Automatic initialization of this register is only done during debugger operation. Failure to correctly configure the register(s) will result in all A/D pins being recognized as analog input pins, resulting in the port value being read as a logic `0', which may affect user application functionality. 2.9 Unused I/Os Unused I/O pins should be configured as outputs and driven to a logic-low state. Alternatively, connect a 1k to 10k resistor to VSS on unused pins and drive the output to logic low. DS70592B-page 24 Preliminary 2009 Microchip Technology Inc. PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A 3.0 CPU 3.1 Note 1: This data sheet summarizes the features of the PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 2. "CPU" (DS70245 DS70245) of the "dsPIC33F/PIC24H Family Reference Manual", which is available from the Microchip website (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. The PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A CPU module has a 16-bit (data) modified Harvard architecture with an enhanced instruction set and addressing modes. The CPU has a 24-bit instruction word with a variable length opcode field. The Program Counter (PC) is 23 bits wide and addresses up to 4M x 24 bits of user program memory space. The actual amount of program memory implemented varies by device. A single-cycle instruction prefetch mechanism is used to help maintain throughput and provides predictable execution. All instructions execute in a single cycle, with the exception of instructions that change the program flow, the double word move (MOV.D) instruction and the table instructions. Overhead-free, single-cycle program loop constructs are supported using the REPEAT instruction, which is interruptible at any point. Data Addressing Overview The data space can be linearly addressed as 32K words or 64 Kbytes using an Address Generation Unit (AGU). The upper 32 Kbytes of the data space memory map can optionally be mapped into program space at any 16K program word boundary defined by the 8-bit Program Space Visibility Page (PSVPAG) register. The program to data space mapping feature lets any instruction access program space as if it were data space. The data space also includes 2 Kbytes of DMA RAM, which is primarily used for DMA data transfers, but may be used as general purpose RAM. 3.2 Special MCU Features The PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A features a 17-bit by 17-bit, single-cycle multiplier. The multiplier can perform signed, unsigned and mixed-sign multiplication. Using a 17-bit by 17-bit multiplier for 16-bit by 16-bit multiplication makes mixed-sign multiplication possible. The PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A supports 16/16 and 32/16 integer divide operations. All divide instructions are iterative operations. They must be executed within a REPEAT loop, resulting in a total execution time of 19 instruction cycles. The divide operation can be interrupted during any of those 19 cycles without loss of data. A multi-bit data shifter is used to perform up to a 16-bit, left or right shift in a single cycle. The PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A devices have sixteen, 16-bit working registers in the programmer's model. Each of the working registers can serve as a data, address or address offset register. The 16th working register (W15) operates as a software Stack Pointer (SP) for interrupts and calls. The PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A instruction set includes many addressing modes and is designed for optimum C compiler efficiency. For most instructions, the PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle. As a result, three parameter instructions can be supported, allowing A + B = C operations to be executed in a single cycle. A block diagram of the CPU is shown in Figure 3-1, and the programmer's model for the PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A is shown in Figure 3-2. 2009 Microchip Technology Inc. Preliminary DS70592B-page 25 PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A FIGURE 3-1: PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A CPU CORE BLOCK DIAGRAM PSV and Table Data Access Control Block X Data Bus Interrupt Controller 8 16 16 16 Data Latch DMA 23 23 PCU PCH PCL Program Counter Loop Stack Control Control Logic Logic X RAM RAM 16 Address Latch 23 16 DMA Controller Address Generator Units Address Latch Program Memory EA MUX Data Latch ROM Latch 24 Control Signals to Various Blocks Instruction Reg Literal Data Instruction Decode and Control 16 16 16 17 x 17 Multiplier Divide Support 16 x 16 W Register Array 16 16-bit ALU 16 To Peripheral Modules DS70592B-page 26 Preliminary 2009 Microchip Technology Inc. PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A FIGURE 3-2: PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A PROGRAMMER'S MODEL D15 D0 W0/WREG PUSH.S Shadow W1 DO Shadow W2 W3 Legend W4 W5 W6 W7 Working Registers W8 W9 W10 W11 W12 W13 W14/Frame Pointer W15/Stack Pointer Stack Pointer Limit Register SPLIM PC22 PC0 Program Counter 0 0 7 Data Table Page Address TBLPAG 7 0 PSVPAG Program Space Visibility Page Address 15 0 RCOUNT REPEAT Loop Counter 15 0 Core Configuration Register CORCON - - - - - - - DC SRH 3.3 IPL2 IPL1 IPL0 RA N OV Z C STATUS Register SRL CPU Control Registers 2009 Microchip Technology Inc. Preliminary DS70592B-page 27 PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A REGISTER 3-1: SR: CPU STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 - - - - - - - DC bit 15 bit 8 R/W-0(1) R/W-0(2) R/W-0(2) R-0 R/W-0 R/W-0 R/W-0 R/W-0 RA IPL(2) N OV Z C bit 7 bit 0 Legend: C = Clear only bit R = Readable bit U = Unimplemented bit, read as `0' S = Set only bit W = Writable bit -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as `0' bit 8 DC: MCU ALU Half Carry/Borrow bit 1 = A carry-out from the 4th low-order bit (for byte sized data) or 8th low-order bit (for word sized data) of the result occurred 0 = No carry-out from the 4th low-order bit (for byte sized data) or 8th low-order bit (for word sized data) of the result occurred bit 7-5 IPL: CPU Interrupt Priority Level Status bits(2) 111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8) bit 4 RA: REPEAT Loop Active bit 1 = REPEAT loop in progress 0 = REPEAT loop not in progress bit 3 N: MCU ALU Negative bit 1 = Result was negative 0 = Result was non-negative (zero or positive) bit 2 OV: MCU ALU Overflow bit This bit is used for signed arithmetic (2's complement). It indicates an overflow of the magnitude which causes the sign bit to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred bit 1 Z: MCU ALU Zero bit 1 = An operation which affects the Z bit has set it at some time in the past 0 = The most recent operation which affects the Z bit has cleared it (i.e., a non-zero result) bit 0 C: MCU ALU Carry/Borrow bit 1 = A carry-out from the Most Significant bit (MSb) of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: The IPL bits are concatenated with the IPL bit (CORCON) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL if IPL = 1. User interrupts are disabled when IPL = 1. 2: The IPL Status bits are read only when NSTDIS = 1 (INTCON1). DS70592B-page 28 Preliminary 2009 Microchip Technology Inc. PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A REGISTER 3-2: CORCON: CORE CONTROL REGISTER U-0 - bit 15 U-0 - U-0 - U-0 - U-0 - U-0 - U-0 - U-0 - U-0 - U-0 - bit 8 U-0 - U-0 - R/C-0 IPL3(1) R/W-0 PSV U-0 - U-0 - bit 7 bit 0 Legend: R = Readable bit 0' = Bit is cleared bit 15-4 bit 3 bit 2 bit 1-0 C = Clear only bit W = Writable bit `x = Bit is unknown -n = Value at POR `1' = Bit is set U = Unimplemented bit, read as `0' Unimplemented: Read as `0' IPL3: CPU Interrupt Priority Level Status bit 3(1) 1 = CPU interrupt priority level is greater than 7 0 = CPU interrupt priority level is 7 or less PSV: Program Space Visibility in Data Space Enable bit 1 = Program space visible in data space 0 = Program space not visible in data space Unimplemented: Read as `0' Note 1: The IPL3 bit is concatenated with the IPL bits (SR) to form the CPU interrupt priority level. 2009 Microchip Technology Inc. Preliminary DS70592B-page 29 PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A 3.4 3.4.2 Arithmetic Logic Unit (ALU) The PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A ALU is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are 2's complement in nature. Depending on the operation, the ALU may affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR register. The C and DC Status bits operate as Borrow and Digit Borrow bits, respectively, for subtraction operations. The ALU can perform 8-bit or 16-bit operations, depending on the mode of the instruction that is used. Data for the ALU operation can come from the W register array, or data memory, depending on the addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location. Refer to the "dsPIC30F/33F Programmer's Reference Manual" (DS70157 DS70157) for information on the SR bits affected by each instruction. The PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A CPU incorporates hardware support for both multiplication and division. This includes a dedicated hardware multiplier and support hardware for 16-bit divisor division. 3.4.1 MULTIPLIER DIVIDER The divide block supports 32-bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operations with the following data sizes: 1. 2. 3. 4. 32-bit signed/16-bit signed divide 32-bit unsigned/16-bit unsigned divide 16-bit signed/16-bit signed divide 16-bit unsigned/16-bit unsigned divide The quotient for all divide instructions ends up in W0 and the remainder in W1. Sixteen-bit signed and unsigned DIV instructions can specify any W register for both the 16-bit divisor (Wn) and any W register (aligned) pair (W(m + 1):Wm) for the 32-bit dividend. The divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute. 3.4.3 MULTI-BIT DATA SHIFTER The multi-bit data shifter is capable of performing up to 16-bit arithmetic or logic right shifts, or up to 16-bit left shifts in a single cycle. The source can be either a working register or a memory location. The shifter requires a signed binary value to determine both the magnitude (number of bits) and direction of the shift operation. A positive value shifts the operand right. A negative value shifts the operand left. A value of `0' does not modify the operand. Using the high-speed 17-bit x 17-bit multiplier, the ALU supports unsigned, signed or mixed-sign operation in several multiplication modes: 1. 2. 3. 4. 5. 6. 7. 16-bit x 16-bit signed 16-bit x 16-bit unsigned 16-bit signed x 5-bit (literal) unsigned 16-bit unsigned x 16-bit unsigned 16-bit unsigned x 5-bit (literal) unsigned 16-bit unsigned x 16-bit signed 8-bit unsigned x 8-bit unsigned DS70592B-page 30 Preliminary 2009 Microchip Technology Inc. PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A 4.0 MEMORY ORGANIZATION Note: 4.1 This data sheet summarizes the features of the PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 3. "Data Memory" (DS70237 DS70237) of the "dsPIC33F/ PIC24H PIC24H Family Reference Manual", which is available from the Microchip website (www.microchip.com). The PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A architecture features separate program and data memory spaces and buses. This architecture also allows the direct access of program memory from the data space during code execution. FIGURE 4-1: The program address memory space of the PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A devices is 4M instructions. The space is addressable by a 24-bit value derived from either the 23-bit Program Counter (PC) during program execution, or from table operation or data space remapping as described in Section 4.4 "Interfacing Program and Data Memory Spaces". User access to the program memory space is restricted to the lower half of the address range (0x000000 to 0x7FFFFF). The exception is the use of TBLRD/TBLWT operations, which use TBLPAG to permit access to the Configuration bits and Device ID sections of the configuration memory space. Memory maps for the PIC24HJXXXGPX06A/X08A/ PIC24HJXXXGPX06A/X08A/ X10A family of devices are shown in Figure 4-1. PROGRAM MEMORY MAP FOR PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A FAMILY DEVICES PIC24HJ64XXXXXA PIC24HJ64XXXXXA GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table User Memory Space Program Address Space User Program Flash Memory (22K instructions) PIC24HJ128XXXXXA PIC24HJ128XXXXXA GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table PIC24HJ256XXXXXA PIC24HJ256XXXXXA GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table User Program Flash Memory (44K instructions) User Program Flash Memory (88K instructions) 0x000000 0x000002 0x000004 0x0000FE 0x000100 0x000104 0x0001FE 0x000200 0x00ABFE 0x00AC00 0x0157FE 0x015800 Unimplemented (Read `0's) Unimplemented (Read `0's) 0x02ABFE 0x02AC00 Unimplemented (Read `0's) 0x7FFFFE 0x800000 Reserved Reserved Device Configuration Registers Device Configuration Registers Device Configuration Registers Reserved Reserved Reserved DEVID (2) Configuration Memory Space Reserved DEVID (2) DEVID (2) 2009 Microchip Technology Inc. Preliminary 0xF7FFFE 0xF80000 0xF80017 0xF80010 0xFEFFFE 0xFF0000 0xFFFFFE DS70592B-page 31 PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A 4.1.1 PROGRAM MEMORY ORGANIZATION 4.1.2 All PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A devices reserve the addresses between 0x00000 and 0x000200 for hard-coded program execution vectors. A hardware Reset vector is provided to redirect code execution from the default value of the PC on device Reset to the actual start of code. A GOTO instruction is programmed by the user at 0x000000, with the actual address for the start of code at 0x000002. The program memory space is organized in wordaddressable blocks. Although it is treated as 24 bits wide, it is more appropriate to think of each address of the program memory as a lower and upper word, with the upper byte of the upper word being unimplemented. The lower word always has an even address, while the upper word has an odd address (Figure 4-2). PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A devices also have two interrupt vector tables, located from 0x000004 to 0x0000FF and 0x000100 to 0x0001FF. These vector tables allow each of the many device interrupt sources to be handled by separate Interrupt Service Routines (ISRs). A more detailed discussion of the interrupt vector tables is provided in Section 7.1 "Interrupt Vector Table". Program memory addresses are always word-aligned on the lower word, and addresses are incremented or decremented by two during code execution. This arrangement also provides compatibility with data memory space addressing and makes it possible to access data in the program memory space. FIGURE 4-2: msw Address PROGRAM MEMORY ORGANIZATION 16 8 PC Address (lsw Address) 0 0x000000 0x000002 0x000004 0x000006 00000000 00000000 00000000 00000000 Program Memory `Phantom' Byte (read as `0') DS70592B-page 32 least significant word most significant word 23 0x000001 0x000003 0x000005 0x000007 INTERRUPT AND TRAP VECTORS Instruction Width Preliminary 2009 Microchip Technology Inc. PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A 4.2 Data Address Space The PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A CPU has a separate 16-bit wide data memory space. The data space is accessed using separate Address Generation Units (AGUs) for read and write operations. Data memory maps of devices with different RAM sizes are shown in Figure 4-3 and Figure 4-4. All Effective Addresses (EAs) in the data memory space are 16 bits wide and point to bytes within the data space. This arrangement gives a data space address range of 64 Kbytes or 32K words. The lower half of the data memory space (that is, when EA = 0) is used for implemented memory addresses, while the upper half (EA = 1) is reserved for the Program Space Visibility area (see Section 4.4.3 "Reading Data from Program Memory Using Program Space Visibility"). PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A devices implement up to 16 Kbytes of data memory. Should an EA point to a location outside of this area, an all-zero word or byte will be returned. 4.2.1 DATA MEMORY ORGANIZATION AND ALIGNMENT To maintain backward compatibility with PIC® MCU devices and improve data space memory usage efficiency, the PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A instruction set supports both word and byte operations. As a consequence of byte accessibility, all effective address calculations are internally scaled to step through word-aligned memory. For example, the core recognizes that Post-Modified Register Indirect Addressing mode [Ws+] will result in a value of Ws + 1 for byte operations and Ws + 2 for word operations. Data byte reads will read the complete word that contains the byte, using the Least Significant bit (LSb) of any EA to determine which byte to select. The selected byte is placed onto the Least Significant Byte (LSB) of the data path. That is, data memory and registers are organized as two parallel byte-wide entities with shared (word) address decode but separate write lines. Data byte writes only write to the corresponding side of the array or register which matches the byte address. 2009 Microchip Technology Inc. All byte loads into any W register are loaded into the Least Significant Byte. The Most Significant Byte (MSB) is not modified. A sign-extend instruction (SE) is provided to allow users to translate 8-bit signed data to 16-bit signed values. Alternatively, for 16-bit unsigned data, users can clear the Most Significant Byte of any W register by executing a zero-extend (ZE) instruction on the appropriate address. 4.2.3 DATA SPACE WIDTH The data memory space is organized in byte addressable, 16-bit wide blocks. Data is aligned in data memory and registers as 16-bit words, but all data space EAs resolve to bytes. The Least Significant Bytes of each word have even addresses, while the Most Significant Bytes have odd addresses. 4.2.2 All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations, or translating from 8-bit MCU code. If a misaligned read or write is attempted, an address error trap is generated. If the error occurred on a read, the instruction underway is completed; if it occurred on a write, the instruction will be executed but the write does not occur. In either case, a trap is then executed, allowing the system and/or user to examine the machine state prior to execution of the address Fault. SFR SPACE The first 2 Kbytes of the Near Data Space, from 0x0000 to 0x07FF, is primarily occupied by Special Function Registers (SFRs). These are used by the PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A core and peripheral modules for controlling the operation of the device. SFRs are distributed among the modules that they control, and are generally grouped together by module. Much of the SFR space contains unused addresses; these are read as `0'. A complete listing of implemented SFRs, including their addresses, is shown in Table 4-1 through Table 4-33. Note: 4.2.4 The actual set of peripheral features and interrupts varies by the device. Please refer to the corresponding device tables and pinout diagrams for device-specific information. NEAR DATA SPACE The 8-Kbyte area between 0x0000 and 0x1FFF is referred to as the Near Data Space. Locations in this space are directly addressable via a 13-bit absolute address field within all memory direct instructions. Additionally, the whole data space is addressable using MOV instructions, which support Memory Direct Addressing mode with a 16-bit address field, or by using Indirect Addressing mode using a working register as an Address Pointer. Preliminary DS70592B-page 33 PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A FIGURE 4-3: DATA MEMORY MAP FOR PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A DEVICES WITH 8 KBS RAM MSB Address MSB 2 Kbyte SFR Space LSB Address 16 bits LSB 0x0000 0x0001 SFR Space 0x07FE 0x0800 0x07FF 0x0801 8 Kbyte Near Data Space X Data RAM (X) 8 Kbyte SRAM Space 0x1FFF 0x2001 0x27FF 0x2801 0x1FFE 0x2000 DMA RAM 0x8001 0x8000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFF DS70592B-page 34 0x27FE 0x2800 0xFFFE Preliminary 2009 Microchip Technology Inc. PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A FIGURE 4-4: DATA MEMORY MAP FOR PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A DEVICES WITH 16 KBS RAM MSB Address LSB Address 16 bits MSB LSB 0x0000 0x0001 2 Kbyte SFR Space SFR Space 0x07FE 0x0800 0x07FF 0x0801 0x1FFF 8 Kbyte Near Data Space 0x1FFE X Data RAM (X) 16 Kbyte SRAM Space 0x3FFF 0x4001 0x47FF 0x4801 0x3FFE 0x4000 DMA RAM 0x47FE 0x4800 0x8001 0x8000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFF 4.2.5 0xFFFE DMA RAM Every PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A device contains 2 Kbytes of dual ported DMA RAM located at the end of data space. Memory locations in the DMA RAM space are accessible simultaneously by the CPU and the DMA controller module. DMA RAM is utilized by the DMA controller to store data to be transferred to various peripherals using DMA, as well as data transferred from various peripherals using DMA. The DMA RAM can be accessed by the DMA controller without having to steal cycles from the CPU. When the CPU and the DMA controller attempt to concurrently write to the same DMA RAM location, the hardware ensures that the CPU is given precedence in accessing the DMA RAM location. Therefore, the DMA RAM provides a reliable means of transferring DMA data without ever having to stall the CPU. Note: 2009 Microchip Technology Inc. Preliminary DMA RAM can be used for general purpose data storage if the DMA function is not required in an application. DS70592B-page 35 CPU CORE REGISTERS MAP All Resets WREG0 0000 Working Register 0 0000 WREG1 0002 Working Register 1 0000 WREG2 0004 Working Register 2 0000 WREG3 0006 Working Register 3 0000 WREG4 0008 Working Register 4 0000 WREG5 000A Working Register 5 0000 WREG6 000C Working Register 6 0000 WREG7 000E Working Register 7 0000 WREG8 0010 Working Register 8 0000 WREG9 0012 Working Register 9 0000 WREG10 WREG10 0014 Working Register 10 0000 WREG11 WREG11 0016 Working Register 11 0000 WREG12 WREG12 0018 Working Register 12 0000 WREG13 WREG13 001A Working Register 13 0000 WREG14 WREG14 001C Working Register 14 0000 WREG15 WREG15 001E Working Register 15 0800 SPLIM 0020 Stack Pointer Limit Register xxxx PCL 002E Program Counter Low Word Register PCH 0030 - - - - - - - - Program Counter High Byte Register 0000 TBLPAG 0032 - - - - - - - - Table Page Address Pointer Register 0000 PSVPAG 0034 - - - - - - - - Program Memory Visibility Page Address Pointer Register 0000 RCOUNT 0036 SR 0042 - - - - - - - DC CORCON 0044 - - - - - - - - DISICNT 0052 - - BSRAM 0750 - - - - - - - - - SSRAM Preliminary SFR Name SFR Addr 0752 - - - - - - - - - 2009 Microchip Technology Inc. Legend: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0000 Repeat Loop Counter Register xxxx IPL - - RA N OV Z C 0000 - IPL3 PSV - - 0000 - - - IW_BSR IR_BSR RL_BSR 0000 - - - IW_SSR IR_SSR RL_SSR 0000 - Disable Interrupts Counter Register x = unknown value on Reset, - = unimplemented, read as `0'. Reset values are shown in hexadecimal for PinHigh devices. xxxx PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A DS70592B-page 36 TABLE 4-1: 2009 Microchip Technology Inc. TABLE 4-2: CHANGE NOTIFICATION REGISTER MAP FOR PIC24HJXXXGPX10A PIC24HJXXXGPX10A DEVICES SFR Name SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 CNEN1 0060 CN15IE CN15IE CN14IE CN14IE CN13IE CN13IE CN12IE CN12IE CN11IE CN11IE CN10IE CN10IE CN9IE CN8IE CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CNEN2 0062 - - - - - - - - CN23IE CN23IE CN22IE CN22IE CN21IE CN21IE CN20IE CN20IE CN19IE CN19IE CN18IE CN18IE CNPU1 0068 CN8PUE CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CNPU2 006A Legend: CN15PUE CN15PUE CN14PUE CN14PUE CN13PUE CN13PUE CN12PUE CN12PUE CN11PUE CN11PUE CN10PUE CN10PUE CN9PUE - - - - - - - - Bit 0 All Resets CN1IE CN0IE 0000 CN17IE CN17IE CN16IE CN16IE 0000 CN0PUE 0000 CN23PUE CN23PUE CN22PUE CN22PUE CN21PUE CN21PUE CN20PUE CN20PUE CN19PUE CN19PUE CN18PUE CN18PUE CN17PUE CN17PUE CN16PUE CN16PUE 0000 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 x = unknown value on Reset, - = unimplemented, read as `0'. Reset values are shown in hexadecimal for PinHigh devices. CHANGE NOTIFICATION REGISTER MAP FOR PIC24HJXXXGPX08A PIC24HJXXXGPX08A DEVICES SFR Name SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 CNEN1 0060 CN15IE CN15IE CN14IE CN14IE CN13IE CN13IE CN12IE CN12IE CN11IE CN11IE CN10IE CN10IE CN9IE CN8IE CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CNEN2 0062 - - - - - - - - - - CN21IE CN21IE CN20IE CN20IE CN19IE CN19IE CN18IE CN18IE CNPU1 0068 CN8PUE CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CNPU2 006A - - - Preliminary Legend: CN15PUE CN15PUE CN14PUE CN14PUE CN13PUE CN13PUE CN12PUE CN12PUE CN11PUE CN11PUE CN10PUE CN10PUE CN9PUE - - - - - - - Bit 0 All Resets CN1IE CN0IE 0000 CN17IE CN17IE CN16IE CN16IE 0000 CN0PUE 0000 CN21PUE CN21PUE CN20PUE CN20PUE CN19PUE CN19PUE CN18PUE CN18PUE CN17PUE CN17PUE CN16PUE CN16PUE 0000 Bit 5 Bit 3 Bit 2 Bit 1 x = unknown value on Reset, - = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-4: CHANGE NOTIFICATION REGISTER MAP FOR PIC24HJXXXGPX06A PIC24HJXXXGPX06A DEVICES SFR Name SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 CNEN1 0060 CN15IE CN15IE CN14IE CN14IE CN13IE CN13IE CN12IE CN12IE CN11IE CN11IE CN10IE CN10IE CN9IE CN8IE CN7IE CN6IE CNEN2 0062 - - - - - - - - - - CNPU1 0068 CN8PUE CN7PUE CN6PUE CN5PUE CNPU2 006A - - - Legend: Bit 4 CN15PUE CN15PUE CN14PUE CN14PUE CN13PUE CN13PUE CN12PUE CN12PUE CN11PUE CN11PUE CN10PUE CN10PUE CN9PUE - - - - - - - x = unknown value on Reset, - = unimplemented, read as `0'. Reset values are shown in hexadecimal. Bit 5 Bit 0 All Resets CN1IE CN0IE 0000 CN17IE CN17IE CN16IE CN16IE 0000 CN0PUE 0000 CN18PUE CN18PUE CN17PUE CN17PUE CN16PUE CN16PUE 0000 Bit 4 Bit 3 CN5IE CN4IE CN3IE CN2IE CN21IE CN21IE CN20IE CN20IE - CN18IE CN18IE CN4PUE CN3PUE CN2PUE CN1PUE CN21PUE CN21PUE CN20PUE CN20PUE - Bit 2 Bit 1 DS70592B-page 37 PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A TABLE 4-3: SFR Name INTERRUPT CONTROLLER REGISTER MAP SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets INTCON1 0080 NSTDIS - - - - - - - - OSCFAIL - 0000 INTCON2 0082 ALTIVT DISI - - - - - - - - - INT4EP INT3EP INT2EP INT1EP INT0EP 0000 IFS0 0084 - DMA1IF AD1IF U1TXIF U1RXIF T3IF T2IF OC2IF IC2IF DMA0IF T1IF OC1IF IC1IF INT0IF 0000 IFS1 0086 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF DMA2IF IC8IF IC7IF AD2IF INT1IF CNIF - MI2C1IF SI2C1IF 0000 IFS2 0088 T6IF DMA4IF - OC8IF OC7IF OC6IF OC5IF IC6IF IC5IF IC4IF IC3IF DMA3IF C1IF C1RXIF SPI2IF SPI2EIF 0000 IFS3 008A - - DMA5IF - - - - C2IF C2RXIF INT4IF INT3IF T9IF T8IF MI2C2IF SI2C2IF T7IF 0000 IFS4 008C - - - - - - - - C2TXIF C1TXIF DMA7IF DMA6IF - U2EIF U1EIF - 0000 IEC0 0094 - DMA1IE AD1IE U1TXIE U1RXIE T3IE T2IE OC2IE IC2IE DMA0IE T1IE OC1IE IC1IE INT0IE IEC1 0096 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE DMA2IE IC8IE IC7IE AD2IE INT1IE CNIE - IEC2 0098 T6IE DMA4IE - OC8IE OC7IE OC6IE OC5IE IC6IE IC5IE IC4IE IC3IE DMA3IE C1IE C1RXIE SPI2IE SPI2EIE IEC3 009A - - DMA5IE - - - - C2IE C2RXIE INT4IE INT3IE T9IE T8IE MI2C2IE SI2C2IE T7IE 0000 IEC4 009C - - - - - - - - C2TXIE C1TXIE DMA7IE DMA6IE - U2EIE U1EIE - 0000 SPI1IF SPI1EIF SPI1IE SPI1EIE DIV0ERR DMACERR MATHERR ADDRERR STKERR MI2C1IE SI2C1IE 0000 0000 0000 - T1IP - OC1IP - IC1IP - INT0IP 4444 - T2IP - OC2IP - IC2IP - DMA0IP 4444 IPC2 00A8 - U1RXIP - SPI1IP - SPI1EIP - T3IP 4444 IPC3 00AA - - DMA1IP - AD1IP - U1TXIP 0444 IPC4 00AC - CNIP - - MI2C1IP - SI2C1IP 4044 IPC5 00AE - IC8IP - IC7IP - AD2IP - INT1IP 4444 IPC6 00B0 - T4IP - OC4IP - OC3IP - DMA2IP 4444 00B2 - U2TXIP - U2RXIP - INT2IP - T5IP 4444 IPC8 00B4 - C1IP - C1RXIP - SPI2IP - SPI2EIP 4444 IPC9 00B6 - IC5IP - IC4IP - IC3IP - DMA3IP 4444 IPC10 IPC10 00B8 - OC7IP - OC6IP - OC5IP - IC6IP 4444 IPC11 IPC11 00BA - T6IP - DMA4IP - - OC8IP 4404 IPC12 IPC12 2009 Microchip Technology Inc. 00A4 00A6 IPC7 Preliminary IPC0 IPC1 00BC - T8IP - MI2C2IP - SI2C2IP - T7IP 4444 IPC13 IPC13 00BE - C2RXIP - INT4IP - INT3IP - T9IP 4444 IPC14 IPC14 00C0 - - - - - - - - - - C2IP IPC15 IPC15 00C2 - - - - - - - - - DMA5IP - - - - IPC16 IPC16 00C4 - - - - - U2EIP - U1EIP - - - - IPC17 IPC17 00C6 - - C1TXIP - DMA7IP - INTTREG 00E0 - Legend: - - - C2TXIP - - - - - ILR - - - - - - x = unknown value on Reset, - = unimplemented, read as `0'. Reset values are shown in hexadecimal for PinHigh devices. - - VECNUM DMA6IP 0004 0040 0440 4444 0000 PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A DS70592B-page 38 TABLE 4-5: 2009 Microchip Technology Inc. TABLE 4-6: SFR Name SFR Addr TIMER REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 TMR1 0100 0102 0104 TMR2 0106 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Period Register 1 T1CON Bit 5 Timer1 Register PR1 Bit 6 TON - TSIDL - - - - - - All Resets xxxx FFFF TGATE TCKPS - TSYNC TCS - 0000 Timer2 Register xxxx Timer3 Holding Register (for 32-bit timer operations only) TMR3HLD 0108 xxxx Timer3 Register xxxx PR2 010C Period Register 2 FFFF 010E Period Register 3 T2CON 0110 TON - TSIDL - - - - - - TGATE TCKPS T32 - TCS - 0000 T3CON 0112 TON - TSIDL - - - - - - TGATE TCKPS - - TCS - 0000 TMR4 0114 Timer4 Register xxxx TMR5HLD 0116 Timer5 Holding Register (for 32-bit operations only) xxxx TMR5 0118 Timer5 Register xxxx PR4 011A Period Register 4 FFFF PR5 011C Period Register 5 T4CON 011E TON - TSIDL - - - - - - TGATE TCKPS T32 - TCS - 0000 T5CON 0120 TON - TSIDL - - - - - - TGATE TCKPS - - TCS - 0000 TMR6 0122 FFFF FFFF Timer6 Register xxxx Timer7 Holding Register (for 32-bit operations only) TMR7HLD 0124 xxxx TMR7 0126 Timer7 Register xxxx PR6 0128 Period Register 6 FFFF PR7 012A Period Register 7 T6CON 012C TON - TSIDL - - - - - - TGATE TCKPS T32 - TCS - 0000 T7CON 012E TON - TSIDL - - - - - - TGATE TCKPS - - TCS - 0000 TMR8 0130 FFFF Timer8 Register TMR9HLD 0132 xxxx xxxx 0134 Timer9 Register xxxx PR8 0136 Period Register 8 FFFF PR9 DS70592B-page 39 Timer9 Holding Register (for 32-bit operations only) TMR9 0138 Period Register 9 T8CON 013A TON - TSIDL - - - - - - TGATE TCKPS T32 - TCS - 0000 T9CON 013C TON - TSIDL - - - - - - TGATE TCKPS - - TCS - 0000 Legend: FFFF x = unknown value on Reset, - = unimplemented, read as `0'. Reset values are shown in hexadecimal for PinHigh devices. PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A 010A PR3 Preliminary TMR3 IC1BUF 0142 IC2BUF 0144 0146 IC3BUF 0148 IC3CON 014A IC4BUF 014C IC4CON 014E IC5BUF 0150 IC5CON 0152 IC6BUF 0154 IC6CON 0156 IC7BUF 0158 IC7CON 015A IC8BUF 015C IC8CON 015E INPUT CAPTURE REGISTER MAP 0140 IC1CON IC2CON Preliminary SFR Name SFR Addr Legend: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 - - ICSIDL - - - - Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 ICI ICOV ICBNE ICM ICI ICOV ICBNE ICM ICI ICOV ICBNE ICM ICI ICOV ICBNE ICM ICI ICOV ICBNE ICM ICI ICOV ICBNE ICM ICI ICOV ICBNE ICM ICI ICOV ICBNE ICM Input 1 Capture Register - ICTMR - ICSIDL - - - - - ICTMR - ICSIDL - - - - - ICTMR - ICSIDL - - - - - ICTMR - ICSIDL - - - - - ICTMR - ICSIDL - - - - - ICTMR - ICSIDL - - - - - ICTMR - ICSIDL - - - - - ICTMR 0000 xxxx Input 8 Capture Register - 0000 xxxx Input 7 Capture Register - 0000 xxxx Input 6 Capture Register - 0000 xxxx Input 5 Capture Register - 0000 xxxx Input 4 Capture Register - 0000 xxxx Input 3 Capture Register - All Resets xxxx Input 2 Capture Register - Bit 0 0000 xxxx x = unknown value on Reset, - = unimplemented, read as `0'. Reset values are shown in hexadecimal for PinHigh devices. 0000 PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A DS70592B-page 40 TABLE 4-7: 2009 Microchip Technology Inc. 2009 Microchip Technology Inc. TABLE 4-8: SFR Name OUTPUT COMPARE REGISTER MAP SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 0184 OC2RS 0186 0188 Output Compare 2 Register OC2CON 018A OC3RS 018C Output Compare 3 Secondary Register 018E Output Compare 3 Register OC3CON 0190 OC4RS 0192 Output Compare 4 Secondary Register OC4R 0194 Output Compare 4 Register OC4CON 0196 OC5RS 0198 Output Compare 5 Secondary Register OC5R 019A Output Compare 5 Register OC5CON 019C OC6RS 019E Output Compare 6 Secondary Register OC6R 01A0 Output Compare 6 Register OC6CON 01A2 OC7RS 01A4 Output Compare 7 Secondary Register OC7R 01A6 Output Compare 7 Register OC7CON 01A8 OC8RS 01AA Output Compare 8 Secondary Register OC8R 01AC Output Compare 8 Register OC8CON 01AE Bit 1 Output Compare 2 Secondary Register OC2R Bit 2 Output Compare 1 Register OC1CON Bit 3 Output Compare 1 Secondary Register 0182 Bit 4 Legend: - - - - - - - - - - - - - - - - OCSIDL OCSIDL OCSIDL OCSIDL OCSIDL OCSIDL OCSIDL OCSIDL - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Bit 0 All Resets xxxx xxxx - OCFLT OCTSEL OCM 0000 xxxx xxxx - OCFLT OCTSEL OCM 0000 xxxx xxxx - OCFLT OCTSEL OCM 0000 xxxx xxxx - OCFLT OCTSEL OCM 0000 xxxx xxxx - OCFLT OCTSEL OCM 0000 xxxx xxxx - OCFLT OCTSEL OCM 0000 xxxx xxxx - OCFLT OCTSEL OCM 0000 xxxx xxxx - x = unknown value on Reset, - = unimplemented, read as `0'. Reset values are shown in hexadecimal for PinHigh devices. OCFLT OCTSEL OCM 0000 DS70592B-page 41 PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A 0180 OC1R OC3R Preliminary OC1RS Bit 5 I2C1 REGISTER MAP SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 I2C1RCV 0200 - - - - - - - - Receive Register 0000 I2C1TRN 0202 - - - - - - - - Transmit Register 00FF I2C1BRG 0204 - - - - - - - I2C1CON 0206 I2CEN - I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000 I2C1STAT 0208 ACKSTAT TRSTAT - - - BCL GCSTAT ADD10 ADD10 IWCOL I2COV D_A P S R_W RBF TBF 0000 I2C1ADD 020A - - - - - - Address Register 0000 I2C1MSK 020C - - - - - - Address Mask Register 0000 SFR Name Legend: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Baud Rate Generator Register All Resets 0000 x = unknown value on Reset, - = unimplemented, read as `0'. Reset values are shown in hexadecimal for PinHigh devices. TABLE 4-10: I2C2 REGISTER MAP SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 I2C2RCV 0210 - - - - - - - - Receive Register 0000 I2C2TRN 0212 - - - - - - - - Transmit Register 00FF I2C2BRG 0214 - - - - - - - I2C2CON 0216 I2CEN - I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000 I2C2STAT 0218 ACKSTAT TRSTAT - - - BCL GCSTAT ADD10 ADD10 IWCOL I2COV D_A P S R_W RBF TBF 0000 I2C2ADD 021A - - - - - - Address Register 0000 I2C2MSK 021C - - - - - - Address Mask Register 0000 SFR Name Preliminary Legend: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Baud Rate Generator Register All Resets 0000 x = unknown value on Reset, - = unimplemented, read as `0'. Reset values are shown in hexadecimal for PinHigh devices. TABLE 4-11: UART1 REGISTER MAP 2009 Microchip Technology Inc. SFR Name SFR Addr U1MODE 0220 UARTEN U1STA 0222 UTXISEL1 U1TXREG 0224 - - U1RXREG 0226 - - U1BRG 0228 Legend: x = unknown value on Reset, - = unimplemented, read as `0'. Reset values are shown in hexadecimal for PinHigh devices. Bit 15 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 UEN1 UEN0 WAKE LPBACK UTXBF TRMT Bit 4 Bit 3 ABAUD URXINV BRGH ADDEN RIDLE PERR Bit 1 STSEL 0000 0110 - USIDL IREN RTSMD - - UTXBRK UTXEN - - - - - UART Transmit Register xxxx - - - - - UART Receive Register 0000 Baud Rate Generator Prescaler Bit 2 URXDA Bit 12 URXISEL Bit 5 All Resets Bit 13 UTXINV UTXISEL0 Bit 11 Bit 0 Bit 14 PDSEL FERR OERR 0000 PIC24HJXXXGPX06A/X08A/X10A PIC24HJXXXGPX06A/X08A/X10A DS70592B-page 42 TABLE 4-9: 2009 Microchip Technology Inc. TABLE 4-12: SFR Name SFR Addr UART2 REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 WAKE LPBACK Bit 5 Bit 4 Bit 3 ABAUD URXINV BRGH ADDEN RIDLE PERR Bit 2 All Resets 0000 URXDA 0110 U2MODE 0230 UARTEN - USIDL IREN RTSMD - UEN1 UEN0 U2STA 0232 UTXISEL1 UTXINV UTXISEL0 - UTXBRK UTXEN UTXBF TRMT U2TXREG 0234 - - - - - - - UART Transmit Register xxxx U2RXREG 0236 - - - - - - - UART Receive Register 0000 U2BRG 0238 Legend: x = unknown value on Reset, - = unimplemented, read as `0'. Reset values are shown in hexadecimal for PinHigh devices. SFR Name FERR OERR Baud Rate Generator Prescaler 0000 SPI1 REGISTER MAP Bit 15 Bit 14 Bit 13 SPI1STAT 0240 SPIEN - SPISIDL - - - - SPI1CON1 0242 - - - DISSCK DISSDO MODE16 MODE16 SMP SPI1CON2 Preliminary SFR Addr 0244 FRMEN SPIFSD FRMPOL - - - - -